stats.txt revision 11754:c209cb86278a
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.848913 # Number of seconds simulated 4sim_ticks 2848912955000 # Number of ticks simulated 5final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 258856 # Simulator instruction rate (inst/s) 8host_op_rate 313468 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5762698171 # Simulator tick rate (ticks/s) 10host_mem_usage 627144 # Number of bytes of host memory used 11host_seconds 494.37 # Real time elapsed on the host 12sim_insts 127970828 # Number of instructions simulated 13sim_ops 154969713 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory 44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 49system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory 50system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.readReqs 201104 # Number of read requests accepted 81system.physmem.writeReqs 145983 # Number of write requests accepted 82system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue 83system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue 84system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM 85system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue 86system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM 87system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side 88system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side 89system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue 90system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 92system.physmem.perBankRdBursts::0 12429 # Per bank write bursts 93system.physmem.perBankRdBursts::1 12794 # Per bank write bursts 94system.physmem.perBankRdBursts::2 13696 # Per bank write bursts 95system.physmem.perBankRdBursts::3 13190 # Per bank write bursts 96system.physmem.perBankRdBursts::4 15337 # Per bank write bursts 97system.physmem.perBankRdBursts::5 12894 # Per bank write bursts 98system.physmem.perBankRdBursts::6 12741 # Per bank write bursts 99system.physmem.perBankRdBursts::7 13088 # Per bank write bursts 100system.physmem.perBankRdBursts::8 12333 # Per bank write bursts 101system.physmem.perBankRdBursts::9 12486 # Per bank write bursts 102system.physmem.perBankRdBursts::10 11357 # Per bank write bursts 103system.physmem.perBankRdBursts::11 10671 # Per bank write bursts 104system.physmem.perBankRdBursts::12 11888 # Per bank write bursts 105system.physmem.perBankRdBursts::13 12773 # Per bank write bursts 106system.physmem.perBankRdBursts::14 11762 # Per bank write bursts 107system.physmem.perBankRdBursts::15 11515 # Per bank write bursts 108system.physmem.perBankWrBursts::0 8987 # Per bank write bursts 109system.physmem.perBankWrBursts::1 9459 # Per bank write bursts 110system.physmem.perBankWrBursts::2 10102 # Per bank write bursts 111system.physmem.perBankWrBursts::3 9553 # Per bank write bursts 112system.physmem.perBankWrBursts::4 8641 # Per bank write bursts 113system.physmem.perBankWrBursts::5 9022 # Per bank write bursts 114system.physmem.perBankWrBursts::6 9160 # Per bank write bursts 115system.physmem.perBankWrBursts::7 9289 # Per bank write bursts 116system.physmem.perBankWrBursts::8 8726 # Per bank write bursts 117system.physmem.perBankWrBursts::9 8906 # Per bank write bursts 118system.physmem.perBankWrBursts::10 8219 # Per bank write bursts 119system.physmem.perBankWrBursts::11 7897 # Per bank write bursts 120system.physmem.perBankWrBursts::12 8731 # Per bank write bursts 121system.physmem.perBankWrBursts::13 8920 # Per bank write bursts 122system.physmem.perBankWrBursts::14 8491 # Per bank write bursts 123system.physmem.perBankWrBursts::15 7959 # Per bank write bursts 124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 125system.physmem.numWrRetry 98 # Number of times write queue was full causing retry 126system.physmem.totGap 2848912399000 # Total gap between requests 127system.physmem.readPktSize::0 0 # Read request sizes (log2) 128system.physmem.readPktSize::1 0 # Read request sizes (log2) 129system.physmem.readPktSize::2 556 # Read request sizes (log2) 130system.physmem.readPktSize::3 28 # Read request sizes (log2) 131system.physmem.readPktSize::4 0 # Read request sizes (log2) 132system.physmem.readPktSize::5 0 # Read request sizes (log2) 133system.physmem.readPktSize::6 200520 # Read request sizes (log2) 134system.physmem.writePktSize::0 0 # Write request sizes (log2) 135system.physmem.writePktSize::1 0 # Write request sizes (log2) 136system.physmem.writePktSize::2 4391 # Write request sizes (log2) 137system.physmem.writePktSize::3 0 # Write request sizes (log2) 138system.physmem.writePktSize::4 0 # Write request sizes (log2) 139system.physmem.writePktSize::5 0 # Write request sizes (log2) 140system.physmem.writePktSize::6 141592 # Write request sizes (log2) 141system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 4499 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 5027 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 6162 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 7110 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 7579 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 8612 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 8496 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 9787 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 10402 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 8601 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 9100 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 10035 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 8447 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 8229 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::33 943 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::34 593 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::35 477 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::36 428 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::37 296 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::39 236 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::40 211 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::42 248 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::43 226 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::54 262 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::57 198 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::58 156 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::59 221 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::60 217 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::61 179 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::62 143 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see 237system.physmem.bytesPerActivate::samples 89688 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::mean 244.770315 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::gmean 140.172635 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::stdev 301.083170 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::0-127 45750 51.01% 51.01% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::128-255 18787 20.95% 71.96% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::256-383 6651 7.42% 79.37% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation 251system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes 258system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads 299system.physmem.totQLat 9366475580 # Total ticks spent queuing 300system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.06 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing 315system.physmem.readRowHits 166422 # Number of row buffer hits during reads 316system.physmem.writeRowHits 86905 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes 319system.physmem.avgGap 8208064.26 # Average gap between requests 320system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined 321system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ) 322system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ) 323system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ) 324system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ) 325system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ) 326system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ) 327system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ) 328system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ) 329system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ) 330system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ) 331system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ) 332system.physmem_0.averagePower 246.980538 # Core power per rank (mW) 333system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank 334system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states 335system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states 336system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states 337system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states 338system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states 339system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states 340system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ) 341system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ) 342system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ) 343system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ) 344system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ) 345system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ) 346system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ) 347system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ) 348system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ) 349system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ) 350system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ) 351system.physmem_1.averagePower 246.743143 # Core power per rank (mW) 352system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank 353system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states 354system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states 355system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states 356system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states 357system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states 358system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states 359system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 360system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 365system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 366system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 368system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 369system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 378system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 379system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 380system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 381system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 382system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 383system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 384system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 385system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 386system.cf0.dma_write_txs 631 # Number of DMA write transactions. 387system.cpu0.branchPred.lookups 20830846 # Number of BP lookups 388system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted 389system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect 390system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups 391system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits 392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 393system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage 394system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target. 395system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions. 396system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups. 397system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits. 398system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses. 399system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches. 400system.cpu_clk_domain.clock 500 # Clock period in ticks 401system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 406system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 411system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 412system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 413system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 414system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 415system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 416system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 417system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 418system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 419system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 420system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 421system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 422system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 423system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 424system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 426system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 427system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 428system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 429system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 430system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 431system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 432system.cpu0.dtb.walker.walks 66699 # Table walker walks requested 433system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors 434system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate 435system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate 436system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated 456system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.inst_hits 0 # ITB inst hits 465system.cpu0.dtb.inst_misses 0 # ITB inst misses 466system.cpu0.dtb.read_hits 17337178 # DTB read hits 467system.cpu0.dtb.read_misses 60105 # DTB read misses 468system.cpu0.dtb.write_hits 14536732 # DTB write hits 469system.cpu0.dtb.write_misses 6594 # DTB write misses 470system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 472system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 474system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB 475system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 17397283 # DTB read accesses 480system.cpu0.dtb.write_accesses 14543326 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 31873910 # DTB hits 483system.cpu0.dtb.misses 66699 # DTB misses 484system.cpu0.dtb.accesses 31940609 # DTB accesses 485system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 486system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 495system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 496system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 497system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 498system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 499system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 501system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 502system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 503system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 504system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 505system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 506system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 507system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 508system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 509system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 510system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 511system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 512system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 513system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 514system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 515system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 516system.cpu0.itb.walker.walks 4013 # Table walker walks requested 517system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors 518system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate 519system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate 520system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution 535system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution 536system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution 537system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated 538system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated 539system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated 540system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst 547system.cpu0.itb.inst_hits 38740955 # ITB inst hits 548system.cpu0.itb.inst_misses 4013 # ITB inst misses 549system.cpu0.itb.read_hits 0 # DTB read hits 550system.cpu0.itb.read_misses 0 # DTB read misses 551system.cpu0.itb.write_hits 0 # DTB write hits 552system.cpu0.itb.write_misses 0 # DTB write misses 553system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 554system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 555system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 556system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 557system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB 558system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 559system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 560system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 561system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions 562system.cpu0.itb.read_accesses 0 # DTB read accesses 563system.cpu0.itb.write_accesses 0 # DTB write accesses 564system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses 565system.cpu0.itb.hits 38740955 # DTB hits 566system.cpu0.itb.misses 4013 # DTB misses 567system.cpu0.itb.accesses 38744968 # DTB accesses 568system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions 569system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state 570system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state 571system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state 572system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state 573system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state 574system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state 575system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 576system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 577system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 578system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state 579system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state 580system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states 581system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states 582system.cpu0.numCycles 172712897 # number of cpu cycles simulated 583system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 584system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 585system.cpu0.committedInsts 79713377 # Number of instructions committed 586system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed 587system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit 588system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching 589system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 590system.cpu0.cpi 2.166674 # CPI: cycles per instruction 591system.cpu0.ipc 0.461537 # IPC: instructions per cycle 592system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction 593system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction 594system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction 595system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction 596system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction 597system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction 598system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction 599system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction 600system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction 601system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction 602system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction 603system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction 604system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction 605system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction 606system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction 607system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction 608system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction 609system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction 610system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction 611system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction 612system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction 613system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction 614system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction 615system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction 616system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction 617system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction 618system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction 619system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction 620system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction 621system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction 622system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction 623system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction 624system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction 625system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction 626system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction 627system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction 628system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 629system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 630system.cpu0.op_class_0::total 95922535 # Class of committed instruction 631system.cpu0.kern.inst.arm 0 # number of arm instructions executed 632system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed 633system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked 634system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped 635system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 636system.cpu0.dcache.tags.replacements 716918 # number of replacements 637system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use 638system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks. 639system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks. 640system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks. 641system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. 642system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor 643system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy 644system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy 645system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 646system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 647system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 648system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 649system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 650system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses 651system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses 652system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 653system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits 654system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits 655system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits 656system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits 657system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits 658system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits 659system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits 660system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits 661system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits 662system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits 663system.cpu0.dcache.demand_hits::cpu0.data 29272712 # number of demand (read+write) hits 664system.cpu0.dcache.demand_hits::total 29272712 # number of demand (read+write) hits 665system.cpu0.dcache.overall_hits::cpu0.data 29593516 # number of overall hits 666system.cpu0.dcache.overall_hits::total 29593516 # number of overall hits 667system.cpu0.dcache.ReadReq_misses::cpu0.data 439135 # number of ReadReq misses 668system.cpu0.dcache.ReadReq_misses::total 439135 # number of ReadReq misses 669system.cpu0.dcache.WriteReq_misses::cpu0.data 581157 # number of WriteReq misses 670system.cpu0.dcache.WriteReq_misses::total 581157 # number of WriteReq misses 671system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135756 # number of SoftPFReq misses 672system.cpu0.dcache.SoftPFReq_misses::total 135756 # number of SoftPFReq misses 673system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20923 # number of LoadLockedReq misses 674system.cpu0.dcache.LoadLockedReq_misses::total 20923 # number of LoadLockedReq misses 675system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20396 # number of StoreCondReq misses 676system.cpu0.dcache.StoreCondReq_misses::total 20396 # number of StoreCondReq misses 677system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses 678system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses 679system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses 680system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses 681system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles 682system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles 683system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles 684system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles 685system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles 686system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles 687system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles 688system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles 689system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles 690system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles 691system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles 692system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles 693system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles 694system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles 695system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses) 696system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses) 697system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # number of WriteReq accesses(hits+misses) 698system.cpu0.dcache.WriteReq_accesses::total 14003365 # number of WriteReq accesses(hits+misses) 699system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456560 # number of SoftPFReq accesses(hits+misses) 700system.cpu0.dcache.SoftPFReq_accesses::total 456560 # number of SoftPFReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386428 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::total 386428 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381557 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::total 381557 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.demand_accesses::cpu0.data 30293004 # number of demand (read+write) accesses 706system.cpu0.dcache.demand_accesses::total 30293004 # number of demand (read+write) accesses 707system.cpu0.dcache.overall_accesses::cpu0.data 30749564 # number of overall (read+write) accesses 708system.cpu0.dcache.overall_accesses::total 30749564 # number of overall (read+write) accesses 709system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026958 # miss rate for ReadReq accesses 710system.cpu0.dcache.ReadReq_miss_rate::total 0.026958 # miss rate for ReadReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041501 # miss rate for WriteReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::total 0.041501 # miss rate for WriteReq accesses 713system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297345 # miss rate for SoftPFReq accesses 714system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297345 # miss rate for SoftPFReq accesses 715system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054145 # miss rate for LoadLockedReq accesses 716system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054145 # miss rate for LoadLockedReq accesses 717system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053455 # miss rate for StoreCondReq accesses 718system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053455 # miss rate for StoreCondReq accesses 719system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses 720system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses 721system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses 722system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses 723system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency 724system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency 725system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency 726system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency 727system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency 728system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency 729system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # average StoreCondReq miss latency 730system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23652.088645 # average StoreCondReq miss latency 731system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 732system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 733system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency 734system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency 735system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency 736system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency 737system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks 744system.cpu0.dcache.writebacks::total 716918 # number of writebacks 745system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits 746system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits 747system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits 748system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits 749system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits 750system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits 751system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits 752system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits 753system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits 754system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits 755system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses 756system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses 757system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses 758system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses 759system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses 760system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses 761system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses 762system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses 763system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses 764system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses 765system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses 766system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses 767system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses 768system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses 769system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable 770system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable 771system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable 772system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable 773system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses 774system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses 775system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles 776system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles 777system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles 778system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles 779system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles 780system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles 781system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles 782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles 783system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles 784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles 785system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles 786system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles 793system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles 794system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles 795system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses 796system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses 797system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses 798system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses 799system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses 800system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses 801system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses 802system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses 803system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses 804system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses 805system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses 806system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses 807system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses 808system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses 809system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency 810system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency 811system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency 812system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency 813system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency 814system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency 815system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency 816system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency 817system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency 818system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency 819system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 820system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 821system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15890.301584 # average overall mshr miss latency 822system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15890.301584 # average overall mshr miss latency 823system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15987.508421 # average overall mshr miss latency 824system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15987.508421 # average overall mshr miss latency 825system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.653467 # average ReadReq mshr uncacheable latency 826system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.653467 # average ReadReq mshr uncacheable latency 827system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115618.240446 # average overall mshr uncacheable latency 828system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115618.240446 # average overall mshr uncacheable latency 829system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 830system.cpu0.icache.tags.replacements 1966568 # number of replacements 831system.cpu0.icache.tags.tagsinuse 511.773009 # Cycle average of tags in use 832system.cpu0.icache.tags.total_refs 36766553 # Total number of references to valid blocks. 833system.cpu0.icache.tags.sampled_refs 1967080 # Sample count of references to valid blocks. 834system.cpu0.icache.tags.avg_refs 18.690929 # Average number of references to valid blocks. 835system.cpu0.icache.tags.warmup_cycle 6697446000 # Cycle when the warmup percentage was hit. 836system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773009 # Average occupied blocks per requestor 837system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy 838system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy 839system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 840system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id 841system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 842system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id 843system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 844system.cpu0.icache.tags.tag_accesses 79434387 # Number of tag accesses 845system.cpu0.icache.tags.data_accesses 79434387 # Number of data accesses 846system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 847system.cpu0.icache.ReadReq_hits::cpu0.inst 36766553 # number of ReadReq hits 848system.cpu0.icache.ReadReq_hits::total 36766553 # number of ReadReq hits 849system.cpu0.icache.demand_hits::cpu0.inst 36766553 # number of demand (read+write) hits 850system.cpu0.icache.demand_hits::total 36766553 # number of demand (read+write) hits 851system.cpu0.icache.overall_hits::cpu0.inst 36766553 # number of overall hits 852system.cpu0.icache.overall_hits::total 36766553 # number of overall hits 853system.cpu0.icache.ReadReq_misses::cpu0.inst 1967094 # number of ReadReq misses 854system.cpu0.icache.ReadReq_misses::total 1967094 # number of ReadReq misses 855system.cpu0.icache.demand_misses::cpu0.inst 1967094 # number of demand (read+write) misses 856system.cpu0.icache.demand_misses::total 1967094 # number of demand (read+write) misses 857system.cpu0.icache.overall_misses::cpu0.inst 1967094 # number of overall misses 858system.cpu0.icache.overall_misses::total 1967094 # number of overall misses 859system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19796906000 # number of ReadReq miss cycles 860system.cpu0.icache.ReadReq_miss_latency::total 19796906000 # number of ReadReq miss cycles 861system.cpu0.icache.demand_miss_latency::cpu0.inst 19796906000 # number of demand (read+write) miss cycles 862system.cpu0.icache.demand_miss_latency::total 19796906000 # number of demand (read+write) miss cycles 863system.cpu0.icache.overall_miss_latency::cpu0.inst 19796906000 # number of overall miss cycles 864system.cpu0.icache.overall_miss_latency::total 19796906000 # number of overall miss cycles 865system.cpu0.icache.ReadReq_accesses::cpu0.inst 38733647 # number of ReadReq accesses(hits+misses) 866system.cpu0.icache.ReadReq_accesses::total 38733647 # number of ReadReq accesses(hits+misses) 867system.cpu0.icache.demand_accesses::cpu0.inst 38733647 # number of demand (read+write) accesses 868system.cpu0.icache.demand_accesses::total 38733647 # number of demand (read+write) accesses 869system.cpu0.icache.overall_accesses::cpu0.inst 38733647 # number of overall (read+write) accesses 870system.cpu0.icache.overall_accesses::total 38733647 # number of overall (read+write) accesses 871system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050785 # miss rate for ReadReq accesses 872system.cpu0.icache.ReadReq_miss_rate::total 0.050785 # miss rate for ReadReq accesses 873system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050785 # miss rate for demand accesses 874system.cpu0.icache.demand_miss_rate::total 0.050785 # miss rate for demand accesses 875system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050785 # miss rate for overall accesses 876system.cpu0.icache.overall_miss_rate::total 0.050785 # miss rate for overall accesses 877system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.036594 # average ReadReq miss latency 878system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.036594 # average ReadReq miss latency 879system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency 880system.cpu0.icache.demand_avg_miss_latency::total 10064.036594 # average overall miss latency 881system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency 882system.cpu0.icache.overall_avg_miss_latency::total 10064.036594 # average overall miss latency 883system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 884system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 885system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 886system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 887system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 888system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 889system.cpu0.icache.writebacks::writebacks 1966568 # number of writebacks 890system.cpu0.icache.writebacks::total 1966568 # number of writebacks 891system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1967094 # number of ReadReq MSHR misses 892system.cpu0.icache.ReadReq_mshr_misses::total 1967094 # number of ReadReq MSHR misses 893system.cpu0.icache.demand_mshr_misses::cpu0.inst 1967094 # number of demand (read+write) MSHR misses 894system.cpu0.icache.demand_mshr_misses::total 1967094 # number of demand (read+write) MSHR misses 895system.cpu0.icache.overall_mshr_misses::cpu0.inst 1967094 # number of overall MSHR misses 896system.cpu0.icache.overall_mshr_misses::total 1967094 # number of overall MSHR misses 897system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable 898system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable 899system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses 900system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses 901system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18813359500 # number of ReadReq MSHR miss cycles 902system.cpu0.icache.ReadReq_mshr_miss_latency::total 18813359500 # number of ReadReq MSHR miss cycles 903system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18813359500 # number of demand (read+write) MSHR miss cycles 904system.cpu0.icache.demand_mshr_miss_latency::total 18813359500 # number of demand (read+write) MSHR miss cycles 905system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18813359500 # number of overall MSHR miss cycles 906system.cpu0.icache.overall_mshr_miss_latency::total 18813359500 # number of overall MSHR miss cycles 907system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles 908system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles 909system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles 910system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles 911system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for ReadReq accesses 912system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050785 # mshr miss rate for ReadReq accesses 913system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for demand accesses 914system.cpu0.icache.demand_mshr_miss_rate::total 0.050785 # mshr miss rate for demand accesses 915system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for overall accesses 916system.cpu0.icache.overall_mshr_miss_rate::total 0.050785 # mshr miss rate for overall accesses 917system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average ReadReq mshr miss latency 918system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.036848 # average ReadReq mshr miss latency 919system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency 920system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency 921system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency 922system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency 923system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency 924system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency 925system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency 926system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency 927system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 928system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845428 # number of hwpf issued 929system.cpu0.l2cache.prefetcher.pfIdentified 1845508 # number of prefetch candidates identified 930system.cpu0.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue 931system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 932system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 933system.cpu0.l2cache.prefetcher.pfSpanPage 235148 # number of prefetches not generated due to page crossing 934system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 935system.cpu0.l2cache.tags.replacements 289262 # number of replacements 936system.cpu0.l2cache.tags.tagsinuse 15626.234267 # Cycle average of tags in use 937system.cpu0.l2cache.tags.total_refs 2591525 # Total number of references to valid blocks. 938system.cpu0.l2cache.tags.sampled_refs 304855 # Sample count of references to valid blocks. 939system.cpu0.l2cache.tags.avg_refs 8.500845 # Average number of references to valid blocks. 940system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 941system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.282419 # Average occupied blocks per requestor 942system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.020594 # Average occupied blocks per requestor 943system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070348 # Average occupied blocks per requestor 944system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1045.860906 # Average occupied blocks per requestor 945system.cpu0.l2cache.tags.occ_percent::writebacks 0.885881 # Average percentage of cache occupancy 946system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy 947system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 948system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy 949system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy 950system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id 951system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 952system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id 953system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 954system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id 955system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id 956system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id 957system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id 958system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 959system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id 962system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id 966system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id 967system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 968system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id 969system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses 970system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses 971system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 972system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78219 # number of ReadReq hits 973system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5306 # number of ReadReq hits 974system.cpu0.l2cache.ReadReq_hits::total 83525 # number of ReadReq hits 975system.cpu0.l2cache.WritebackDirty_hits::writebacks 481785 # number of WritebackDirty hits 976system.cpu0.l2cache.WritebackDirty_hits::total 481785 # number of WritebackDirty hits 977system.cpu0.l2cache.WritebackClean_hits::writebacks 2159151 # number of WritebackClean hits 978system.cpu0.l2cache.WritebackClean_hits::total 2159151 # number of WritebackClean hits 979system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222970 # number of ReadExReq hits 980system.cpu0.l2cache.ReadExReq_hits::total 222970 # number of ReadExReq hits 981system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1875280 # number of ReadCleanReq hits 982system.cpu0.l2cache.ReadCleanReq_hits::total 1875280 # number of ReadCleanReq hits 983system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389002 # number of ReadSharedReq hits 984system.cpu0.l2cache.ReadSharedReq_hits::total 389002 # number of ReadSharedReq hits 985system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78219 # number of demand (read+write) hits 986system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5306 # number of demand (read+write) hits 987system.cpu0.l2cache.demand_hits::cpu0.inst 1875280 # number of demand (read+write) hits 988system.cpu0.l2cache.demand_hits::cpu0.data 611972 # number of demand (read+write) hits 989system.cpu0.l2cache.demand_hits::total 2570777 # number of demand (read+write) hits 990system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78219 # number of overall hits 991system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5306 # number of overall hits 992system.cpu0.l2cache.overall_hits::cpu0.inst 1875280 # number of overall hits 993system.cpu0.l2cache.overall_hits::cpu0.data 611972 # number of overall hits 994system.cpu0.l2cache.overall_hits::total 2570777 # number of overall hits 995system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1055 # number of ReadReq misses 996system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 176 # number of ReadReq misses 997system.cpu0.l2cache.ReadReq_misses::total 1231 # number of ReadReq misses 998system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56519 # number of UpgradeReq misses 999system.cpu0.l2cache.UpgradeReq_misses::total 56519 # number of UpgradeReq misses 1000system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20396 # number of SCUpgradeReq misses 1001system.cpu0.l2cache.SCUpgradeReq_misses::total 20396 # number of SCUpgradeReq misses 1002system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46078 # number of ReadExReq misses 1003system.cpu0.l2cache.ReadExReq_misses::total 46078 # number of ReadExReq misses 1004system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91814 # number of ReadCleanReq misses 1005system.cpu0.l2cache.ReadCleanReq_misses::total 91814 # number of ReadCleanReq misses 1006system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 114162 # number of ReadSharedReq misses 1007system.cpu0.l2cache.ReadSharedReq_misses::total 114162 # number of ReadSharedReq misses 1008system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1055 # number of demand (read+write) misses 1009system.cpu0.l2cache.demand_misses::cpu0.itb.walker 176 # number of demand (read+write) misses 1010system.cpu0.l2cache.demand_misses::cpu0.inst 91814 # number of demand (read+write) misses 1011system.cpu0.l2cache.demand_misses::cpu0.data 160240 # number of demand (read+write) misses 1012system.cpu0.l2cache.demand_misses::total 253285 # number of demand (read+write) misses 1013system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1055 # number of overall misses 1014system.cpu0.l2cache.overall_misses::cpu0.itb.walker 176 # number of overall misses 1015system.cpu0.l2cache.overall_misses::cpu0.inst 91814 # number of overall misses 1016system.cpu0.l2cache.overall_misses::cpu0.data 160240 # number of overall misses 1017system.cpu0.l2cache.overall_misses::total 253285 # number of overall misses 1018system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 45088000 # number of ReadReq miss cycles 1019system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4105500 # number of ReadReq miss cycles 1020system.cpu0.l2cache.ReadReq_miss_latency::total 49193500 # number of ReadReq miss cycles 1021system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 43638000 # number of UpgradeReq miss cycles 1022system.cpu0.l2cache.UpgradeReq_miss_latency::total 43638000 # number of UpgradeReq miss cycles 1023system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 10254000 # number of SCUpgradeReq miss cycles 1024system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 10254000 # number of SCUpgradeReq miss cycles 1025system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 591500 # number of SCUpgradeFailReq miss cycles 1026system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 591500 # number of SCUpgradeFailReq miss cycles 1027system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2907293999 # number of ReadExReq miss cycles 1028system.cpu0.l2cache.ReadExReq_miss_latency::total 2907293999 # number of ReadExReq miss cycles 1029system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4520777000 # number of ReadCleanReq miss cycles 1030system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4520777000 # number of ReadCleanReq miss cycles 1031system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3763870996 # number of ReadSharedReq miss cycles 1032system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3763870996 # number of ReadSharedReq miss cycles 1033system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 45088000 # number of demand (read+write) miss cycles 1034system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4105500 # number of demand (read+write) miss cycles 1035system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4520777000 # number of demand (read+write) miss cycles 1036system.cpu0.l2cache.demand_miss_latency::cpu0.data 6671164995 # number of demand (read+write) miss cycles 1037system.cpu0.l2cache.demand_miss_latency::total 11241135495 # number of demand (read+write) miss cycles 1038system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 45088000 # number of overall miss cycles 1039system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4105500 # number of overall miss cycles 1040system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4520777000 # number of overall miss cycles 1041system.cpu0.l2cache.overall_miss_latency::cpu0.data 6671164995 # number of overall miss cycles 1042system.cpu0.l2cache.overall_miss_latency::total 11241135495 # number of overall miss cycles 1043system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79274 # number of ReadReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5482 # number of ReadReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadReq_accesses::total 84756 # number of ReadReq accesses(hits+misses) 1046system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481785 # number of WritebackDirty accesses(hits+misses) 1047system.cpu0.l2cache.WritebackDirty_accesses::total 481785 # number of WritebackDirty accesses(hits+misses) 1048system.cpu0.l2cache.WritebackClean_accesses::writebacks 2159151 # number of WritebackClean accesses(hits+misses) 1049system.cpu0.l2cache.WritebackClean_accesses::total 2159151 # number of WritebackClean accesses(hits+misses) 1050system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56519 # number of UpgradeReq accesses(hits+misses) 1051system.cpu0.l2cache.UpgradeReq_accesses::total 56519 # number of UpgradeReq accesses(hits+misses) 1052system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20396 # number of SCUpgradeReq accesses(hits+misses) 1053system.cpu0.l2cache.SCUpgradeReq_accesses::total 20396 # number of SCUpgradeReq accesses(hits+misses) 1054system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269048 # number of ReadExReq accesses(hits+misses) 1055system.cpu0.l2cache.ReadExReq_accesses::total 269048 # number of ReadExReq accesses(hits+misses) 1056system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1967094 # number of ReadCleanReq accesses(hits+misses) 1057system.cpu0.l2cache.ReadCleanReq_accesses::total 1967094 # number of ReadCleanReq accesses(hits+misses) 1058system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 503164 # number of ReadSharedReq accesses(hits+misses) 1059system.cpu0.l2cache.ReadSharedReq_accesses::total 503164 # number of ReadSharedReq accesses(hits+misses) 1060system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79274 # number of demand (read+write) accesses 1061system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5482 # number of demand (read+write) accesses 1062system.cpu0.l2cache.demand_accesses::cpu0.inst 1967094 # number of demand (read+write) accesses 1063system.cpu0.l2cache.demand_accesses::cpu0.data 772212 # number of demand (read+write) accesses 1064system.cpu0.l2cache.demand_accesses::total 2824062 # number of demand (read+write) accesses 1065system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79274 # number of overall (read+write) accesses 1066system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5482 # number of overall (read+write) accesses 1067system.cpu0.l2cache.overall_accesses::cpu0.inst 1967094 # number of overall (read+write) accesses 1068system.cpu0.l2cache.overall_accesses::cpu0.data 772212 # number of overall (read+write) accesses 1069system.cpu0.l2cache.overall_accesses::total 2824062 # number of overall (read+write) accesses 1070system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for ReadReq accesses 1071system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032105 # miss rate for ReadReq accesses 1072system.cpu0.l2cache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses 1073system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1074system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1075system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1076system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1077system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171263 # miss rate for ReadExReq accesses 1078system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171263 # miss rate for ReadExReq accesses 1079system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046675 # miss rate for ReadCleanReq accesses 1080system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046675 # miss rate for ReadCleanReq accesses 1081system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226888 # miss rate for ReadSharedReq accesses 1082system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.226888 # miss rate for ReadSharedReq accesses 1083system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for demand accesses 1084system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032105 # miss rate for demand accesses 1085system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046675 # miss rate for demand accesses 1086system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.207508 # miss rate for demand accesses 1087system.cpu0.l2cache.demand_miss_rate::total 0.089688 # miss rate for demand accesses 1088system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for overall accesses 1089system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032105 # miss rate for overall accesses 1090system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046675 # miss rate for overall accesses 1091system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.207508 # miss rate for overall accesses 1092system.cpu0.l2cache.overall_miss_rate::total 0.089688 # miss rate for overall accesses 1093system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average ReadReq miss latency 1094system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23326.704545 # average ReadReq miss latency 1095system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39962.225833 # average ReadReq miss latency 1096system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 772.094340 # average UpgradeReq miss latency 1097system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 772.094340 # average UpgradeReq miss latency 1098system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 502.745636 # average SCUpgradeReq miss latency 1099system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 502.745636 # average SCUpgradeReq miss latency 1100system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1101system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1102system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63095.056187 # average ReadExReq miss latency 1103system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63095.056187 # average ReadExReq miss latency 1104system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49238.427691 # average ReadCleanReq miss latency 1105system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49238.427691 # average ReadCleanReq miss latency 1106system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32969.560765 # average ReadSharedReq miss latency 1107system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32969.560765 # average ReadSharedReq miss latency 1108system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency 1109system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency 1110system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency 1111system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency 1112system.cpu0.l2cache.demand_avg_miss_latency::total 44381.370768 # average overall miss latency 1113system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency 1114system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency 1115system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency 1116system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency 1117system.cpu0.l2cache.overall_avg_miss_latency::total 44381.370768 # average overall miss latency 1118system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # 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number of overall MSHR hits 1142system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits 1143system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 62 # number of overall MSHR hits 1144system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3635 # number of overall MSHR hits 1145system.cpu0.l2cache.overall_mshr_hits::total 3705 # number of overall MSHR hits 1146system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1051 # number of ReadReq MSHR misses 1147system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses 1148system.cpu0.l2cache.ReadReq_mshr_misses::total 1223 # number of ReadReq MSHR misses 1149system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of HardPFReq MSHR misses 1150system.cpu0.l2cache.HardPFReq_mshr_misses::total 265014 # number of HardPFReq MSHR misses 1151system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56519 # number of UpgradeReq MSHR misses 1152system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56519 # 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number of demand (read+write) MSHR misses 1163system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 91752 # number of demand (read+write) MSHR misses 1164system.cpu0.l2cache.demand_mshr_misses::cpu0.data 156605 # number of demand (read+write) MSHR misses 1165system.cpu0.l2cache.demand_mshr_misses::total 249580 # number of demand (read+write) MSHR misses 1166system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1051 # number of overall MSHR misses 1167system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses 1168system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 91752 # number of overall MSHR misses 1169system.cpu0.l2cache.overall_mshr_misses::cpu0.data 156605 # number of overall MSHR misses 1170system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of overall MSHR misses 1171system.cpu0.l2cache.overall_mshr_misses::total 514594 # number of overall MSHR misses 1172system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable 1173system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20581 # 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number of HardPFReq MSHR miss cycles 1184system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16721781964 # number of HardPFReq MSHR miss cycles 1185system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 978283000 # number of UpgradeReq MSHR miss cycles 1186system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 978283000 # number of UpgradeReq MSHR miss cycles 1187system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 308154500 # number of SCUpgradeReq MSHR miss cycles 1188system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 308154500 # number of SCUpgradeReq MSHR miss cycles 1189system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 483500 # number of SCUpgradeFailReq MSHR miss cycles 1190system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 483500 # number of SCUpgradeFailReq MSHR miss cycles 1191system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2153848999 # number of ReadExReq MSHR miss cycles 1192system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2153848999 # number of ReadExReq MSHR miss cycles 1193system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3967827500 # number of ReadCleanReq MSHR miss cycles 1194system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3967827500 # number of ReadCleanReq MSHR miss cycles 1195system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3058327496 # number of ReadSharedReq MSHR miss cycles 1196system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3058327496 # number of ReadSharedReq MSHR miss cycles 1197system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3003500 # number of demand (read+write) MSHR miss cycles 1199system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3967827500 # number of demand (read+write) MSHR miss cycles 1200system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5212176495 # number of demand (read+write) MSHR miss cycles 1201system.cpu0.l2cache.demand_mshr_miss_latency::total 9221681495 # number of demand (read+write) MSHR miss cycles 1202system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of overall MSHR miss cycles 1203system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3003500 # number of overall MSHR miss cycles 1204system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3967827500 # number of overall MSHR miss cycles 1205system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5212176495 # number of overall MSHR miss cycles 1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of overall MSHR miss cycles 1207system.cpu0.l2cache.overall_mshr_miss_latency::total 25943463459 # number of overall MSHR miss cycles 1208system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles 1209system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4442744500 # number of ReadReq MSHR uncacheable cycles 1210system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4740410500 # number of ReadReq MSHR uncacheable cycles 1211system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles 1212system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4442744500 # number of overall MSHR uncacheable cycles 1213system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4740410500 # number of overall MSHR uncacheable cycles 1214system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for ReadReq accesses 1215system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for ReadReq accesses 1216system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014430 # mshr miss rate for ReadReq accesses 1217system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1218system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1219system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1220system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1221system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1222system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1223system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159236 # mshr miss rate for ReadExReq accesses 1224system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159236 # mshr miss rate for ReadExReq accesses 1225system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for ReadCleanReq accesses 1226system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046643 # mshr miss rate for ReadCleanReq accesses 1227system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226095 # mshr miss rate for ReadSharedReq accesses 1228system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226095 # mshr miss rate for ReadSharedReq accesses 1229system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for demand accesses 1230system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for demand accesses 1231system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for demand accesses 1232system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for demand accesses 1233system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088376 # mshr miss rate for demand accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for overall accesses 1235system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for overall accesses 1236system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for overall accesses 1237system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for overall accesses 1238system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1239system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses 1240system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency 1241system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency 1242system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency 1243system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency 1244system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency 1245system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency 1246system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency 1247system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency 1248system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency 1249system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1250system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1251system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency 1252system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency 1253system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency 1254system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency 1255system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency 1256system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency 1257system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency 1258system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency 1259system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency 1260system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency 1261system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency 1263system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency 1264system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency 1265system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency 1266system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency 1267system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency 1268system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency 1269system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency 1270system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency 1271system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency 1272system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency 1273system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency 1274system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter. 1275system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1276system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1277system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter. 1278system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1279system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1280system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1281system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution 1290system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution 1291system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution 1295system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution 1300system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes) 1301system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes) 1302system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes) 1303system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes) 1304system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes) 1305system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes) 1306system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes) 1307system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes) 1308system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes) 1309system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes) 1310system.cpu0.toL2Bus.snoops 942421 # Total snoops (count) 1311system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes) 1312system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram 1313system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram 1314system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram 1315system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1316system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram 1317system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram 1318system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram 1319system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1320system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1321system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1322system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram 1323system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks) 1324system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1325system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks) 1326system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1327system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks) 1328system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1329system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks) 1330system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1331system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks) 1332system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1333system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks) 1334system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1335system.cpu1.branchPred.lookups 19376501 # Number of BP lookups 1336system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted 1337system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect 1338system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups 1339system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits 1340system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1341system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage 1342system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target. 1343system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions. 1344system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups. 1345system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits. 1346system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses. 1347system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches. 1348system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1349system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1350system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1351system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1352system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1353system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1356system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1357system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1358system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1359system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1360system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1361system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1362system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1363system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1364system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1365system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1366system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1367system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1368system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1369system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1370system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1371system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1372system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1373system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1374system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1375system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1376system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1377system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1378system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1379system.cpu1.dtb.walker.walks 26236 # Table walker walks requested 1380system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors 1381system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate 1382system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate 1383system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency 1384system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1385system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency 1386system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency 1387system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency 1388system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency 1389system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency 1390system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency 1391system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency 1392system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency 1393system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency 1394system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency 1395system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency 1397system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency 1398system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency 1399system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution 1401system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution 1402system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution 1403system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated 1404system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated 1405system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated 1406system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst 1407system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1408system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst 1409system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst 1410system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1411system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst 1412system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst 1413system.cpu1.dtb.inst_hits 0 # ITB inst hits 1414system.cpu1.dtb.inst_misses 0 # ITB inst misses 1415system.cpu1.dtb.read_hits 11335471 # DTB read hits 1416system.cpu1.dtb.read_misses 23997 # DTB read misses 1417system.cpu1.dtb.write_hits 7067505 # DTB write hits 1418system.cpu1.dtb.write_misses 2239 # DTB write misses 1419system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1420system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1421system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1422system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1423system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB 1424system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions 1425system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch 1426system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1427system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions 1428system.cpu1.dtb.read_accesses 11359468 # DTB read accesses 1429system.cpu1.dtb.write_accesses 7069744 # DTB write accesses 1430system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1431system.cpu1.dtb.hits 18402976 # DTB hits 1432system.cpu1.dtb.misses 26236 # DTB misses 1433system.cpu1.dtb.accesses 18429212 # DTB accesses 1434system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1435system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1436system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1437system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1438system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1439system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1440system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1441system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1442system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1443system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1444system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1445system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1446system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1447system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1448system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1449system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1450system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1451system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1452system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1453system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1454system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1455system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1456system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1457system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1458system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1459system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1460system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1461system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1462system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1463system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1464system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1465system.cpu1.itb.walker.walks 2445 # Table walker walks requested 1466system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors 1467system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate 1468system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate 1469system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency 1470system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1471system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency 1472system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency 1476system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency 1477system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency 1478system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency 1479system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency 1480system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency 1481system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency 1484system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency 1485system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution 1489system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution 1490system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution 1491system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated 1492system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated 1493system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated 1494system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1495system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst 1496system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst 1497system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1498system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst 1499system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst 1500system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst 1501system.cpu1.itb.inst_hits 39707544 # ITB inst hits 1502system.cpu1.itb.inst_misses 2445 # ITB inst misses 1503system.cpu1.itb.read_hits 0 # DTB read hits 1504system.cpu1.itb.read_misses 0 # DTB read misses 1505system.cpu1.itb.write_hits 0 # DTB write hits 1506system.cpu1.itb.write_misses 0 # DTB write misses 1507system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1508system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1509system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1510system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1511system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB 1512system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1513system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1514system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1515system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions 1516system.cpu1.itb.read_accesses 0 # DTB read accesses 1517system.cpu1.itb.write_accesses 0 # DTB write accesses 1518system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses 1519system.cpu1.itb.hits 39707544 # DTB hits 1520system.cpu1.itb.misses 2445 # DTB misses 1521system.cpu1.itb.accesses 39709989 # DTB accesses 1522system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions 1523system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state 1524system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state 1525system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state 1526system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state 1527system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state 1528system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1529system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1530system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1531system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1532system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1533system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state 1534system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state 1535system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states 1536system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states 1537system.cpu1.numCycles 117416330 # number of cpu cycles simulated 1538system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1539system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1540system.cpu1.committedInsts 48257451 # Number of instructions committed 1541system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed 1542system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit 1543system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching 1544system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1545system.cpu1.cpi 2.433123 # CPI: cycles per instruction 1546system.cpu1.ipc 0.410994 # IPC: instructions per cycle 1547system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction 1548system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction 1549system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction 1550system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction 1551system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction 1552system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction 1553system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction 1554system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction 1555system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction 1556system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction 1557system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction 1558system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction 1559system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction 1560system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction 1561system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction 1562system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction 1563system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction 1564system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction 1565system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction 1566system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction 1567system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction 1568system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction 1569system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction 1570system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction 1571system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction 1572system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction 1573system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction 1574system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction 1575system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction 1576system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction 1577system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction 1578system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction 1579system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction 1580system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction 1581system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction 1582system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction 1583system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1584system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1585system.cpu1.op_class_0::total 59047178 # Class of committed instruction 1586system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1587system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed 1588system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked 1589system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped 1590system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1591system.cpu1.dcache.tags.replacements 197406 # number of replacements 1592system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use 1593system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks. 1594system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks. 1595system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks. 1596system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit. 1597system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor 1598system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy 1599system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy 1600system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id 1601system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id 1602system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id 1603system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id 1604system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses 1605system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses 1606system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1607system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits 1608system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits 1609system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits 1610system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits 1611system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits 1612system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits 1613system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits 1614system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits 1615system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits 1616system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits 1617system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits 1618system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits 1619system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits 1620system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits 1621system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses 1622system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses 1623system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses 1624system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses 1625system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses 1626system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses 1627system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses 1628system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses 1629system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses 1630system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses 1631system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses 1632system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses 1633system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses 1634system.cpu1.dcache.overall_misses::total 326977 # number of overall misses 1635system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles 1636system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles 1637system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles 1638system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles 1639system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles 1640system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles 1641system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles 1642system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles 1643system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles 1644system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles 1645system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles 1646system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles 1647system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles 1648system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles 1649system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses) 1650system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses) 1651system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses) 1652system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses) 1653system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses) 1654system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses) 1655system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses) 1656system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses) 1657system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses) 1658system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses) 1659system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses 1660system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses 1661system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses 1662system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses 1663system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses 1664system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses 1665system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses 1666system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses 1667system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses 1668system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses 1669system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses 1670system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses 1671system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses 1672system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses 1673system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses 1674system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses 1675system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses 1676system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses 1677system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency 1678system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency 1679system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency 1680system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency 1681system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency 1682system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency 1683system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency 1684system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency 1685system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1686system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1687system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency 1688system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency 1689system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency 1690system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency 1691system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1692system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1693system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1694system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1695system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1696system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1697system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks 1698system.cpu1.dcache.writebacks::total 197406 # number of writebacks 1699system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits 1700system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits 1701system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits 1702system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits 1703system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits 1704system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits 1705system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits 1706system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits 1707system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits 1708system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits 1709system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses 1710system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses 1711system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses 1712system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses 1713system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses 1714system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses 1715system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses 1716system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses 1717system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses 1718system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses 1719system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses 1720system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses 1721system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses 1722system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses 1723system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable 1724system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable 1725system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable 1726system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable 1727system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses 1728system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses 1729system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles 1730system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles 1731system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles 1732system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles 1733system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles 1734system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles 1735system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles 1736system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles 1737system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles 1738system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles 1739system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles 1740system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles 1741system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles 1742system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles 1743system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles 1744system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles 1745system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles 1746system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles 1747system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles 1748system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles 1749system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses 1750system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses 1751system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses 1752system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses 1753system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses 1754system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses 1755system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses 1756system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses 1757system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses 1758system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses 1759system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses 1760system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses 1761system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses 1762system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses 1763system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency 1764system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency 1765system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency 1766system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency 1767system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency 1768system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency 1770system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency 1771system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency 1772system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency 1773system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1774system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1775system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency 1776system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency 1777system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency 1778system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency 1779system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency 1780system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # average ReadReq mshr uncacheable latency 1781system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95221.591994 # average overall mshr uncacheable latency 1782system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95221.591994 # average overall mshr uncacheable latency 1783system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1784system.cpu1.icache.tags.replacements 951563 # number of replacements 1785system.cpu1.icache.tags.tagsinuse 499.187738 # Cycle average of tags in use 1786system.cpu1.icache.tags.total_refs 38753540 # Total number of references to valid blocks. 1787system.cpu1.icache.tags.sampled_refs 952075 # Sample count of references to valid blocks. 1788system.cpu1.icache.tags.avg_refs 40.704293 # Average number of references to valid blocks. 1789system.cpu1.icache.tags.warmup_cycle 73017738000 # Cycle when the warmup percentage was hit. 1790system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.187738 # Average occupied blocks per requestor 1791system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974976 # Average percentage of cache occupancy 1792system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy 1793system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1794system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id 1795system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 1796system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1797system.cpu1.icache.tags.tag_accesses 80363305 # Number of tag accesses 1798system.cpu1.icache.tags.data_accesses 80363305 # Number of data accesses 1799system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1800system.cpu1.icache.ReadReq_hits::cpu1.inst 38753540 # number of ReadReq hits 1801system.cpu1.icache.ReadReq_hits::total 38753540 # number of ReadReq hits 1802system.cpu1.icache.demand_hits::cpu1.inst 38753540 # number of demand (read+write) hits 1803system.cpu1.icache.demand_hits::total 38753540 # number of demand (read+write) hits 1804system.cpu1.icache.overall_hits::cpu1.inst 38753540 # number of overall hits 1805system.cpu1.icache.overall_hits::total 38753540 # number of overall hits 1806system.cpu1.icache.ReadReq_misses::cpu1.inst 952075 # number of ReadReq misses 1807system.cpu1.icache.ReadReq_misses::total 952075 # number of ReadReq misses 1808system.cpu1.icache.demand_misses::cpu1.inst 952075 # number of demand (read+write) misses 1809system.cpu1.icache.demand_misses::total 952075 # number of demand (read+write) misses 1810system.cpu1.icache.overall_misses::cpu1.inst 952075 # number of overall misses 1811system.cpu1.icache.overall_misses::total 952075 # number of overall misses 1812system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8812564500 # number of ReadReq miss cycles 1813system.cpu1.icache.ReadReq_miss_latency::total 8812564500 # number of ReadReq miss cycles 1814system.cpu1.icache.demand_miss_latency::cpu1.inst 8812564500 # number of demand (read+write) miss cycles 1815system.cpu1.icache.demand_miss_latency::total 8812564500 # number of demand (read+write) miss cycles 1816system.cpu1.icache.overall_miss_latency::cpu1.inst 8812564500 # number of overall miss cycles 1817system.cpu1.icache.overall_miss_latency::total 8812564500 # number of overall miss cycles 1818system.cpu1.icache.ReadReq_accesses::cpu1.inst 39705615 # number of ReadReq accesses(hits+misses) 1819system.cpu1.icache.ReadReq_accesses::total 39705615 # number of ReadReq accesses(hits+misses) 1820system.cpu1.icache.demand_accesses::cpu1.inst 39705615 # number of demand (read+write) accesses 1821system.cpu1.icache.demand_accesses::total 39705615 # number of demand (read+write) accesses 1822system.cpu1.icache.overall_accesses::cpu1.inst 39705615 # number of overall (read+write) accesses 1823system.cpu1.icache.overall_accesses::total 39705615 # number of overall (read+write) accesses 1824system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023978 # miss rate for ReadReq accesses 1825system.cpu1.icache.ReadReq_miss_rate::total 0.023978 # miss rate for ReadReq accesses 1826system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023978 # miss rate for demand accesses 1827system.cpu1.icache.demand_miss_rate::total 0.023978 # miss rate for demand accesses 1828system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023978 # miss rate for overall accesses 1829system.cpu1.icache.overall_miss_rate::total 0.023978 # miss rate for overall accesses 1830system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.166268 # average ReadReq miss latency 1831system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.166268 # average ReadReq miss latency 1832system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency 1833system.cpu1.icache.demand_avg_miss_latency::total 9256.166268 # average overall miss latency 1834system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency 1835system.cpu1.icache.overall_avg_miss_latency::total 9256.166268 # average overall miss latency 1836system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1837system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1838system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1839system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1840system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1841system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1842system.cpu1.icache.writebacks::writebacks 951563 # number of writebacks 1843system.cpu1.icache.writebacks::total 951563 # number of writebacks 1844system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952075 # number of ReadReq MSHR misses 1845system.cpu1.icache.ReadReq_mshr_misses::total 952075 # number of ReadReq MSHR misses 1846system.cpu1.icache.demand_mshr_misses::cpu1.inst 952075 # number of demand (read+write) MSHR misses 1847system.cpu1.icache.demand_mshr_misses::total 952075 # number of demand (read+write) MSHR misses 1848system.cpu1.icache.overall_mshr_misses::cpu1.inst 952075 # number of overall MSHR misses 1849system.cpu1.icache.overall_mshr_misses::total 952075 # number of overall MSHR misses 1850system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1851system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1852system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1853system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1854system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8336527000 # number of ReadReq MSHR miss cycles 1855system.cpu1.icache.ReadReq_mshr_miss_latency::total 8336527000 # number of ReadReq MSHR miss cycles 1856system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8336527000 # number of demand (read+write) MSHR miss cycles 1857system.cpu1.icache.demand_mshr_miss_latency::total 8336527000 # number of demand (read+write) MSHR miss cycles 1858system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8336527000 # number of overall MSHR miss cycles 1859system.cpu1.icache.overall_mshr_miss_latency::total 8336527000 # number of overall MSHR miss cycles 1860system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10996500 # number of ReadReq MSHR uncacheable cycles 1861system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10996500 # number of ReadReq MSHR uncacheable cycles 1862system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10996500 # number of overall MSHR uncacheable cycles 1863system.cpu1.icache.overall_mshr_uncacheable_latency::total 10996500 # number of overall MSHR uncacheable cycles 1864system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for ReadReq accesses 1865system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023978 # mshr miss rate for ReadReq accesses 1866system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for demand accesses 1867system.cpu1.icache.demand_mshr_miss_rate::total 0.023978 # mshr miss rate for demand accesses 1868system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for overall accesses 1869system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses 1870system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency 1871system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency 1872system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency 1873system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency 1874system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency 1875system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency 1876system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency 1877system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency 1878system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency 1879system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency 1880system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1881system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued 1882system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified 1883system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 1884system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1885system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1886system.cpu1.l2cache.prefetcher.pfSpanPage 58314 # number of prefetches not generated due to page crossing 1887system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1888system.cpu1.l2cache.tags.replacements 53261 # number of replacements 1889system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use 1890system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks. 1891system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks. 1892system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks. 1893system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1894system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor 1895system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor 1896system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor 1897system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor 1898system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy 1899system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy 1900system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1901system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy 1902system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy 1903system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id 1904system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id 1905system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id 1906system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id 1907system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id 1908system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1909system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 1910system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 1911system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1287 # Occupied blocks per task id 1912system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7824 # Occupied blocks per task id 1913system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4795 # Occupied blocks per task id 1914system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015320 # Percentage of cache occupancy per task id 1915system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id 1916system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.848755 # Percentage of cache occupancy per task id 1917system.cpu1.l2cache.tags.tag_accesses 39696628 # Number of tag accesses 1918system.cpu1.l2cache.tags.data_accesses 39696628 # Number of data accesses 1919system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 1920system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28743 # number of ReadReq hits 1921system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3180 # number of ReadReq hits 1922system.cpu1.l2cache.ReadReq_hits::total 31923 # number of ReadReq hits 1923system.cpu1.l2cache.WritebackDirty_hits::writebacks 117832 # number of WritebackDirty hits 1924system.cpu1.l2cache.WritebackDirty_hits::total 117832 # number of WritebackDirty hits 1925system.cpu1.l2cache.WritebackClean_hits::writebacks 1010940 # number of WritebackClean hits 1926system.cpu1.l2cache.WritebackClean_hits::total 1010940 # number of WritebackClean hits 1927system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28052 # number of ReadExReq hits 1928system.cpu1.l2cache.ReadExReq_hits::total 28052 # number of ReadExReq hits 1929system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916446 # number of ReadCleanReq hits 1930system.cpu1.l2cache.ReadCleanReq_hits::total 916446 # number of ReadCleanReq hits 1931system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103629 # number of ReadSharedReq hits 1932system.cpu1.l2cache.ReadSharedReq_hits::total 103629 # number of ReadSharedReq hits 1933system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28743 # number of demand (read+write) hits 1934system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3180 # number of demand (read+write) hits 1935system.cpu1.l2cache.demand_hits::cpu1.inst 916446 # number of demand (read+write) hits 1936system.cpu1.l2cache.demand_hits::cpu1.data 131681 # number of demand (read+write) hits 1937system.cpu1.l2cache.demand_hits::total 1080050 # number of demand (read+write) hits 1938system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28743 # number of overall hits 1939system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3180 # number of overall hits 1940system.cpu1.l2cache.overall_hits::cpu1.inst 916446 # number of overall hits 1941system.cpu1.l2cache.overall_hits::cpu1.data 131681 # number of overall hits 1942system.cpu1.l2cache.overall_hits::total 1080050 # number of overall hits 1943system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses 1944system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses 1945system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses 1946system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30054 # number of UpgradeReq misses 1947system.cpu1.l2cache.UpgradeReq_misses::total 30054 # number of UpgradeReq misses 1948system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23668 # number of SCUpgradeReq misses 1949system.cpu1.l2cache.SCUpgradeReq_misses::total 23668 # number of SCUpgradeReq misses 1950system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 1951system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1952system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34968 # number of ReadExReq misses 1953system.cpu1.l2cache.ReadExReq_misses::total 34968 # number of ReadExReq misses 1954system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35629 # number of ReadCleanReq misses 1955system.cpu1.l2cache.ReadCleanReq_misses::total 35629 # number of ReadCleanReq misses 1956system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75478 # number of ReadSharedReq misses 1957system.cpu1.l2cache.ReadSharedReq_misses::total 75478 # number of ReadSharedReq misses 1958system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses 1959system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses 1960system.cpu1.l2cache.demand_misses::cpu1.inst 35629 # number of demand (read+write) misses 1961system.cpu1.l2cache.demand_misses::cpu1.data 110446 # number of demand (read+write) misses 1962system.cpu1.l2cache.demand_misses::total 147023 # number of demand (read+write) misses 1963system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses 1964system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses 1965system.cpu1.l2cache.overall_misses::cpu1.inst 35629 # number of overall misses 1966system.cpu1.l2cache.overall_misses::cpu1.data 110446 # number of overall misses 1967system.cpu1.l2cache.overall_misses::total 147023 # number of overall misses 1968system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15962500 # number of ReadReq miss cycles 1969system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5289000 # number of ReadReq miss cycles 1970system.cpu1.l2cache.ReadReq_miss_latency::total 21251500 # number of ReadReq miss cycles 1971system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13859000 # number of UpgradeReq miss cycles 1972system.cpu1.l2cache.UpgradeReq_miss_latency::total 13859000 # number of UpgradeReq miss cycles 1973system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17603500 # number of SCUpgradeReq miss cycles 1974system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17603500 # number of SCUpgradeReq miss cycles 1975system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 622000 # number of SCUpgradeFailReq miss cycles 1976system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 622000 # number of SCUpgradeFailReq miss cycles 1977system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1509066000 # number of ReadExReq miss cycles 1978system.cpu1.l2cache.ReadExReq_miss_latency::total 1509066000 # number of ReadExReq miss cycles 1979system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359934000 # number of ReadCleanReq miss cycles 1980system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359934000 # number of ReadCleanReq miss cycles 1981system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1890312995 # number of ReadSharedReq miss cycles 1982system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1890312995 # number of ReadSharedReq miss cycles 1983system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15962500 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5289000 # number of demand (read+write) miss cycles 1985system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359934000 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.demand_miss_latency::cpu1.data 3399378995 # number of demand (read+write) miss cycles 1987system.cpu1.l2cache.demand_miss_latency::total 4780564495 # number of demand (read+write) miss cycles 1988system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15962500 # number of overall miss cycles 1989system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5289000 # number of overall miss cycles 1990system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359934000 # number of overall miss cycles 1991system.cpu1.l2cache.overall_miss_latency::cpu1.data 3399378995 # number of overall miss cycles 1992system.cpu1.l2cache.overall_miss_latency::total 4780564495 # number of overall miss cycles 1993system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29425 # number of ReadReq accesses(hits+misses) 1994system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3446 # number of ReadReq accesses(hits+misses) 1995system.cpu1.l2cache.ReadReq_accesses::total 32871 # number of ReadReq accesses(hits+misses) 1996system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117832 # number of WritebackDirty accesses(hits+misses) 1997system.cpu1.l2cache.WritebackDirty_accesses::total 117832 # number of WritebackDirty accesses(hits+misses) 1998system.cpu1.l2cache.WritebackClean_accesses::writebacks 1010940 # number of WritebackClean accesses(hits+misses) 1999system.cpu1.l2cache.WritebackClean_accesses::total 1010940 # number of WritebackClean accesses(hits+misses) 2000system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30054 # number of UpgradeReq accesses(hits+misses) 2001system.cpu1.l2cache.UpgradeReq_accesses::total 30054 # number of UpgradeReq accesses(hits+misses) 2002system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses) 2003system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses) 2004system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2005system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2006system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63020 # number of ReadExReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadExReq_accesses::total 63020 # number of ReadExReq accesses(hits+misses) 2008system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952075 # number of ReadCleanReq accesses(hits+misses) 2009system.cpu1.l2cache.ReadCleanReq_accesses::total 952075 # number of ReadCleanReq accesses(hits+misses) 2010system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179107 # number of ReadSharedReq accesses(hits+misses) 2011system.cpu1.l2cache.ReadSharedReq_accesses::total 179107 # number of ReadSharedReq accesses(hits+misses) 2012system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29425 # number of demand (read+write) accesses 2013system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3446 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::cpu1.inst 952075 # number of demand (read+write) accesses 2015system.cpu1.l2cache.demand_accesses::cpu1.data 242127 # number of demand (read+write) accesses 2016system.cpu1.l2cache.demand_accesses::total 1227073 # number of demand (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29425 # number of overall (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3446 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::cpu1.inst 952075 # number of overall (read+write) accesses 2020system.cpu1.l2cache.overall_accesses::cpu1.data 242127 # number of overall (read+write) accesses 2021system.cpu1.l2cache.overall_accesses::total 1227073 # number of overall (read+write) accesses 2022system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for ReadReq accesses 2023system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077191 # miss rate for ReadReq accesses 2024system.cpu1.l2cache.ReadReq_miss_rate::total 0.028840 # miss rate for ReadReq accesses 2025system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2026system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2028system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2029system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2031system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554871 # miss rate for ReadExReq accesses 2032system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554871 # miss rate for ReadExReq accesses 2033system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.037422 # miss rate for ReadCleanReq accesses 2034system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.037422 # miss rate for ReadCleanReq accesses 2035system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421413 # miss rate for ReadSharedReq accesses 2036system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421413 # miss rate for ReadSharedReq accesses 2037system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for demand accesses 2038system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077191 # miss rate for demand accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.037422 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456149 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::total 0.119816 # miss rate for demand accesses 2042system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for overall accesses 2043system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077191 # miss rate for overall accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.037422 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456149 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::total 0.119816 # miss rate for overall accesses 2047system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average ReadReq miss latency 2048system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19883.458647 # average ReadReq miss latency 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22417.194093 # average ReadReq miss latency 2050system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 461.136621 # average UpgradeReq miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 461.136621 # average UpgradeReq miss latency 2052system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 743.767957 # average SCUpgradeReq miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 743.767957 # average SCUpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622000 # average SCUpgradeFailReq miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622000 # average SCUpgradeFailReq miss latency 2056system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43155.628003 # average ReadExReq miss latency 2057system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43155.628003 # average ReadExReq miss latency 2058system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38169.300289 # average ReadCleanReq miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38169.300289 # average ReadCleanReq miss latency 2060system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25044.555963 # average ReadSharedReq miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25044.555963 # average ReadSharedReq miss latency 2062system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency 2063system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency 2064system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency 2065system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::total 32515.759405 # average overall miss latency 2067system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency 2068system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency 2069system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency 2070system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::total 32515.759405 # average overall miss latency 2072system.cpu1.l2cache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked 2073system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2074system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 2075system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2076system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked 2077system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2078system.cpu1.l2cache.unused_prefetches 862 # number of HardPF blocks evicted w/o reference 2079system.cpu1.l2cache.writebacks::writebacks 36438 # number of writebacks 2080system.cpu1.l2cache.writebacks::total 36438 # number of writebacks 2081system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2082system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2083system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 196 # number of ReadExReq MSHR hits 2084system.cpu1.l2cache.ReadExReq_mshr_hits::total 196 # number of ReadExReq MSHR hits 2085system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits 2086system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 2087system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 87 # number of ReadSharedReq MSHR hits 2088system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 87 # number of ReadSharedReq MSHR hits 2089system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2090system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits 2091system.cpu1.l2cache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits 2092system.cpu1.l2cache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits 2093system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2094system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits 2095system.cpu1.l2cache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits 2096system.cpu1.l2cache.overall_mshr_hits::total 302 # number of overall MSHR hits 2097system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 681 # number of ReadReq MSHR misses 2098system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 266 # number of ReadReq MSHR misses 2099system.cpu1.l2cache.ReadReq_mshr_misses::total 947 # number of ReadReq MSHR misses 2100system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of HardPFReq MSHR misses 2101system.cpu1.l2cache.HardPFReq_mshr_misses::total 26287 # number of HardPFReq MSHR misses 2102system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30054 # number of UpgradeReq MSHR misses 2103system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30054 # number of UpgradeReq MSHR misses 2104system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23668 # number of SCUpgradeReq MSHR misses 2105system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23668 # number of SCUpgradeReq MSHR misses 2106system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2107system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2108system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34772 # number of ReadExReq MSHR misses 2109system.cpu1.l2cache.ReadExReq_mshr_misses::total 34772 # number of ReadExReq MSHR misses 2110system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 35611 # number of ReadCleanReq MSHR misses 2111system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 35611 # number of ReadCleanReq MSHR misses 2112system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 75391 # number of ReadSharedReq MSHR misses 2113system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 75391 # number of ReadSharedReq MSHR misses 2114system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 681 # number of demand (read+write) MSHR misses 2115system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 266 # number of demand (read+write) MSHR misses 2116system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 35611 # number of demand (read+write) MSHR misses 2117system.cpu1.l2cache.demand_mshr_misses::cpu1.data 110163 # number of demand (read+write) MSHR misses 2118system.cpu1.l2cache.demand_mshr_misses::total 146721 # number of demand (read+write) MSHR misses 2119system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 681 # number of overall MSHR misses 2120system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 266 # number of overall MSHR misses 2121system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 35611 # number of overall MSHR misses 2122system.cpu1.l2cache.overall_mshr_misses::cpu1.data 110163 # number of overall MSHR misses 2123system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of overall MSHR misses 2124system.cpu1.l2cache.overall_mshr_misses::total 173008 # number of overall MSHR misses 2125system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2126system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable 2127system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14536 # number of ReadReq MSHR uncacheable 2128system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable 2129system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable 2130system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2131system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses 2132system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26293 # number of overall MSHR uncacheable misses 2133system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of ReadReq MSHR miss cycles 2134system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3693000 # number of ReadReq MSHR miss cycles 2135system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles 2136system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of HardPFReq MSHR miss cycles 2137system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 965321170 # number of HardPFReq MSHR miss cycles 2138system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 461957500 # number of UpgradeReq MSHR miss cycles 2139system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 461957500 # number of UpgradeReq MSHR miss cycles 2140system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354728500 # number of SCUpgradeReq MSHR miss cycles 2141system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354728500 # number of SCUpgradeReq MSHR miss cycles 2142system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 526000 # number of SCUpgradeFailReq MSHR miss cycles 2143system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 526000 # number of SCUpgradeFailReq MSHR miss cycles 2144system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1277222000 # number of ReadExReq MSHR miss cycles 2145system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1277222000 # number of ReadExReq MSHR miss cycles 2146system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1145765500 # number of ReadCleanReq MSHR miss cycles 2147system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1145765500 # number of ReadCleanReq MSHR miss cycles 2148system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1434909495 # number of ReadSharedReq MSHR miss cycles 2149system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1434909495 # number of ReadSharedReq MSHR miss cycles 2150system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of demand (read+write) MSHR miss cycles 2151system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3693000 # number of demand (read+write) MSHR miss cycles 2152system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1145765500 # number of demand (read+write) MSHR miss cycles 2153system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2712131495 # number of demand (read+write) MSHR miss cycles 2154system.cpu1.l2cache.demand_mshr_miss_latency::total 3873447495 # number of demand (read+write) MSHR miss cycles 2155system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of overall MSHR miss cycles 2156system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3693000 # number of overall MSHR miss cycles 2157system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1145765500 # number of overall MSHR miss cycles 2158system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712131495 # number of overall MSHR miss cycles 2159system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of overall MSHR miss cycles 2160system.cpu1.l2cache.overall_mshr_miss_latency::total 4838768665 # number of overall MSHR miss cycles 2161system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10100500 # number of ReadReq MSHR uncacheable cycles 2162system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377583500 # number of ReadReq MSHR uncacheable cycles 2163system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2387684000 # number of ReadReq MSHR uncacheable cycles 2164system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10100500 # number of overall MSHR uncacheable cycles 2165system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377583500 # number of overall MSHR uncacheable cycles 2166system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2387684000 # number of overall MSHR uncacheable cycles 2167system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for ReadReq accesses 2168system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for ReadReq accesses 2169system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028810 # mshr miss rate for ReadReq accesses 2170system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2171system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2172system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2173system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2174system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2175system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2176system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2177system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2178system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551761 # mshr miss rate for ReadExReq accesses 2179system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551761 # mshr miss rate for ReadExReq accesses 2180system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for ReadCleanReq accesses 2181system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037404 # mshr miss rate for ReadCleanReq accesses 2182system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420927 # mshr miss rate for ReadSharedReq accesses 2183system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420927 # mshr miss rate for ReadSharedReq accesses 2184system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for demand accesses 2185system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for demand accesses 2186system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for demand accesses 2187system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for demand accesses 2188system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119570 # mshr miss rate for demand accesses 2189system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for overall accesses 2190system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for overall accesses 2191system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for overall accesses 2192system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for overall accesses 2193system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2194system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140992 # mshr miss rate for overall accesses 2195system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency 2196system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency 2197system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency 2198system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency 2199system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency 2200system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency 2201system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency 2202system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency 2203system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency 2204system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency 2205system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency 2206system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency 2207system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency 2208system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency 2209system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency 2210system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency 2211system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency 2212system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency 2213system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency 2214system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency 2215system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency 2216system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency 2217system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency 2218system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency 2219system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency 2220system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency 2221system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency 2222system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency 2223system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency 2224system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency 2225system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency 2226system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency 2227system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency 2228system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency 2229system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter. 2230system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2231system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2232system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter. 2233system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2234system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2235system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2236system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution 2237system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution 2238system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution 2239system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution 2240system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution 2241system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution 2242system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution 2243system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution 2244system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution 2245system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution 2246system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution 2247system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 2248system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution 2249system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution 2250system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution 2251system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution 2252system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution 2253system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution 2254system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes) 2255system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes) 2256system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes) 2257system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes) 2258system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes) 2259system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes) 2260system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes) 2261system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes) 2262system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes) 2263system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes) 2264system.cpu1.toL2Bus.snoops 370911 # Total snoops (count) 2265system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes) 2266system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram 2267system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram 2268system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram 2269system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2270system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram 2271system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram 2272system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram 2273system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2274system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2275system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2276system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram 2277system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks) 2278system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2279system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks) 2280system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2281system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks) 2282system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2283system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks) 2284system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2285system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks) 2286system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2287system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks) 2288system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2289system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2290system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2291system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2292system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2293system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2294system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2298system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2299system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2300system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2301system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2302system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2303system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2304system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2305system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2306system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2307system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2308system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2309system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2310system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2311system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2312system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2313system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2314system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2315system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2316system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2317system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2321system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2322system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2323system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2324system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2325system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2326system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2327system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2328system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2329system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2330system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2331system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2332system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2333system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2334system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2335system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks) 2341system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2342system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) 2343system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2344system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) 2345system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2346system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) 2347system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2348system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) 2349system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2350system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) 2351system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks) 2353system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 2355system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) 2357system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2359system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 2361system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) 2363system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 2365system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) 2367system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2369system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2370system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2371system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2372system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 2373system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2374system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks) 2375system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2376system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks) 2377system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2378system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks) 2379system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2380system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2381system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2382system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2383system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2384system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2385system.iocache.tags.replacements 36461 # number of replacements 2386system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use 2387system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2388system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. 2389system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2390system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit. 2391system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor 2392system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy 2393system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy 2394system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2395system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2396system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2397system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2398system.iocache.tags.data_accesses 328311 # Number of data accesses 2399system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2400system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2401system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2402system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2403system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2404system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2405system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2406system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2407system.iocache.overall_misses::total 36479 # number of overall misses 2408system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles 2409system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles 2410system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles 2411system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles 2412system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles 2413system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles 2414system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles 2415system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles 2416system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2417system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2418system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2419system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2420system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2421system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2422system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2423system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2424system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2425system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2426system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2427system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2428system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2429system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2430system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2431system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2432system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency 2433system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency 2434system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency 2435system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency 2436system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency 2437system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency 2438system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency 2439system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency 2440system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked 2441system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2442system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked 2443system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2444system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked 2445system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2446system.iocache.writebacks::writebacks 36206 # number of writebacks 2447system.iocache.writebacks::total 36206 # number of writebacks 2448system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2449system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2450system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2451system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2452system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2453system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2454system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2455system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2456system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles 2457system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles 2458system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles 2459system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles 2460system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles 2461system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles 2462system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles 2463system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles 2464system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2465system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2466system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2467system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2468system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2469system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2470system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2471system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2472system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency 2473system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency 2474system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency 2475system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency 2476system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency 2477system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency 2478system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency 2479system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency 2480system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2481system.l2c.tags.replacements 144965 # number of replacements 2482system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use 2483system.l2c.tags.total_refs 609190 # Total number of references to valid blocks. 2484system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks. 2485system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks. 2486system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit. 2487system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor 2488system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor 2489system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor 2490system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor 2491system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor 2492system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor 2493system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor 2494system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor 2495system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor 2496system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor 2497system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy 2498system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy 2499system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2500system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy 2501system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy 2502system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy 2503system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy 2504system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy 2505system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy 2506system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy 2507system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy 2508system.l2c.tags.occ_task_id_blocks::1022 31624 # Occupied blocks per task id 2509system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 2510system.l2c.tags.occ_task_id_blocks::1024 33792 # Occupied blocks per task id 2511system.l2c.tags.age_task_id_blocks_1022::2 150 # Occupied blocks per task id 2512system.l2c.tags.age_task_id_blocks_1022::3 4711 # Occupied blocks per task id 2513system.l2c.tags.age_task_id_blocks_1022::4 26763 # Occupied blocks per task id 2514system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id 2515system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2516system.l2c.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id 2517system.l2c.tags.age_task_id_blocks_1024::3 1870 # Occupied blocks per task id 2518system.l2c.tags.age_task_id_blocks_1024::4 31828 # Occupied blocks per task id 2519system.l2c.tags.occ_task_id_percent::1022 0.482544 # Percentage of cache occupancy per task id 2520system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 2521system.l2c.tags.occ_task_id_percent::1024 0.515625 # Percentage of cache occupancy per task id 2522system.l2c.tags.tag_accesses 6850011 # Number of tag accesses 2523system.l2c.tags.data_accesses 6850011 # Number of data accesses 2524system.l2c.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2525system.l2c.WritebackDirty_hits::writebacks 269158 # number of WritebackDirty hits 2526system.l2c.WritebackDirty_hits::total 269158 # number of WritebackDirty hits 2527system.l2c.UpgradeReq_hits::cpu0.data 42928 # number of UpgradeReq hits 2528system.l2c.UpgradeReq_hits::cpu1.data 5622 # number of UpgradeReq hits 2529system.l2c.UpgradeReq_hits::total 48550 # number of UpgradeReq hits 2530system.l2c.SCUpgradeReq_hits::cpu0.data 2743 # number of SCUpgradeReq hits 2531system.l2c.SCUpgradeReq_hits::cpu1.data 2305 # number of SCUpgradeReq hits 2532system.l2c.SCUpgradeReq_hits::total 5048 # number of SCUpgradeReq hits 2533system.l2c.ReadExReq_hits::cpu0.data 4279 # number of ReadExReq hits 2534system.l2c.ReadExReq_hits::cpu1.data 1522 # number of ReadExReq hits 2535system.l2c.ReadExReq_hits::total 5801 # number of ReadExReq hits 2536system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 596 # number of ReadSharedReq hits 2537system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits 2538system.l2c.ReadSharedReq_hits::cpu0.inst 68829 # number of ReadSharedReq hits 2539system.l2c.ReadSharedReq_hits::cpu0.data 63546 # number of ReadSharedReq hits 2540system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47286 # number of ReadSharedReq hits 2541system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 133 # number of ReadSharedReq hits 2542system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits 2543system.l2c.ReadSharedReq_hits::cpu1.inst 32119 # number of ReadSharedReq hits 2544system.l2c.ReadSharedReq_hits::cpu1.data 13663 # number of ReadSharedReq hits 2545system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5831 # number of ReadSharedReq hits 2546system.l2c.ReadSharedReq_hits::total 232111 # number of ReadSharedReq hits 2547system.l2c.demand_hits::cpu0.dtb.walker 596 # number of demand (read+write) hits 2548system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits 2549system.l2c.demand_hits::cpu0.inst 68829 # number of demand (read+write) hits 2550system.l2c.demand_hits::cpu0.data 67825 # number of demand (read+write) hits 2551system.l2c.demand_hits::cpu0.l2cache.prefetcher 47286 # number of demand (read+write) hits 2552system.l2c.demand_hits::cpu1.dtb.walker 133 # number of demand (read+write) hits 2553system.l2c.demand_hits::cpu1.itb.walker 12 # number of demand (read+write) hits 2554system.l2c.demand_hits::cpu1.inst 32119 # number of demand (read+write) hits 2555system.l2c.demand_hits::cpu1.data 15185 # number of demand (read+write) hits 2556system.l2c.demand_hits::cpu1.l2cache.prefetcher 5831 # number of demand (read+write) hits 2557system.l2c.demand_hits::total 237912 # number of demand (read+write) hits 2558system.l2c.overall_hits::cpu0.dtb.walker 596 # number of overall hits 2559system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits 2560system.l2c.overall_hits::cpu0.inst 68829 # number of overall hits 2561system.l2c.overall_hits::cpu0.data 67825 # number of overall hits 2562system.l2c.overall_hits::cpu0.l2cache.prefetcher 47286 # number of overall hits 2563system.l2c.overall_hits::cpu1.dtb.walker 133 # number of overall hits 2564system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits 2565system.l2c.overall_hits::cpu1.inst 32119 # number of overall hits 2566system.l2c.overall_hits::cpu1.data 15185 # number of overall hits 2567system.l2c.overall_hits::cpu1.l2cache.prefetcher 5831 # number of overall hits 2568system.l2c.overall_hits::total 237912 # number of overall hits 2569system.l2c.UpgradeReq_misses::cpu0.data 404 # number of UpgradeReq misses 2570system.l2c.UpgradeReq_misses::cpu1.data 229 # number of UpgradeReq misses 2571system.l2c.UpgradeReq_misses::total 633 # number of UpgradeReq misses 2572system.l2c.SCUpgradeReq_misses::cpu0.data 106 # number of SCUpgradeReq misses 2573system.l2c.SCUpgradeReq_misses::cpu1.data 82 # number of SCUpgradeReq misses 2574system.l2c.SCUpgradeReq_misses::total 188 # number of SCUpgradeReq misses 2575system.l2c.ReadExReq_misses::cpu0.data 11300 # number of ReadExReq misses 2576system.l2c.ReadExReq_misses::cpu1.data 8634 # number of ReadExReq misses 2577system.l2c.ReadExReq_misses::total 19934 # number of ReadExReq misses 2578system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 147 # number of ReadSharedReq misses 2579system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2580system.l2c.ReadSharedReq_misses::cpu0.inst 22922 # number of ReadSharedReq misses 2581system.l2c.ReadSharedReq_misses::cpu0.data 9947 # number of ReadSharedReq misses 2582system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq misses 2583system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 19 # number of ReadSharedReq misses 2584system.l2c.ReadSharedReq_misses::cpu1.inst 3492 # number of ReadSharedReq misses 2585system.l2c.ReadSharedReq_misses::cpu1.data 1704 # number of ReadSharedReq misses 2586system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq misses 2587system.l2c.ReadSharedReq_misses::total 177568 # number of ReadSharedReq misses 2588system.l2c.demand_misses::cpu0.dtb.walker 147 # number of demand (read+write) misses 2589system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2590system.l2c.demand_misses::cpu0.inst 22922 # number of demand (read+write) misses 2591system.l2c.demand_misses::cpu0.data 21247 # number of demand (read+write) misses 2592system.l2c.demand_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) misses 2593system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses 2594system.l2c.demand_misses::cpu1.inst 3492 # number of demand (read+write) misses 2595system.l2c.demand_misses::cpu1.data 10338 # number of demand (read+write) misses 2596system.l2c.demand_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) misses 2597system.l2c.demand_misses::total 197502 # number of demand (read+write) misses 2598system.l2c.overall_misses::cpu0.dtb.walker 147 # number of overall misses 2599system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2600system.l2c.overall_misses::cpu0.inst 22922 # number of overall misses 2601system.l2c.overall_misses::cpu0.data 21247 # number of overall misses 2602system.l2c.overall_misses::cpu0.l2cache.prefetcher 132993 # number of overall misses 2603system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses 2604system.l2c.overall_misses::cpu1.inst 3492 # number of overall misses 2605system.l2c.overall_misses::cpu1.data 10338 # number of overall misses 2606system.l2c.overall_misses::cpu1.l2cache.prefetcher 6343 # number of overall misses 2607system.l2c.overall_misses::total 197502 # number of overall misses 2608system.l2c.UpgradeReq_miss_latency::cpu0.data 7730000 # number of UpgradeReq miss cycles 2609system.l2c.UpgradeReq_miss_latency::cpu1.data 962500 # number of UpgradeReq miss cycles 2610system.l2c.UpgradeReq_miss_latency::total 8692500 # number of UpgradeReq miss cycles 2611system.l2c.SCUpgradeReq_miss_latency::cpu0.data 689500 # number of SCUpgradeReq miss cycles 2612system.l2c.SCUpgradeReq_miss_latency::cpu1.data 165500 # number of SCUpgradeReq miss cycles 2613system.l2c.SCUpgradeReq_miss_latency::total 855000 # number of SCUpgradeReq miss cycles 2614system.l2c.ReadExReq_miss_latency::cpu0.data 1562017000 # number of ReadExReq miss cycles 2615system.l2c.ReadExReq_miss_latency::cpu1.data 830214000 # number of ReadExReq miss cycles 2616system.l2c.ReadExReq_miss_latency::total 2392231000 # number of ReadExReq miss cycles 2617system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 21395500 # number of ReadSharedReq miss cycles 2618system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles 2619system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2310573000 # number of ReadSharedReq miss cycles 2620system.l2c.ReadSharedReq_miss_latency::cpu0.data 1198855000 # number of ReadSharedReq miss cycles 2621system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of ReadSharedReq miss cycles 2622system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1721000 # number of ReadSharedReq miss cycles 2623system.l2c.ReadSharedReq_miss_latency::cpu1.inst 383378500 # number of ReadSharedReq miss cycles 2624system.l2c.ReadSharedReq_miss_latency::cpu1.data 272430000 # number of ReadSharedReq miss cycles 2625system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of ReadSharedReq miss cycles 2626system.l2c.ReadSharedReq_miss_latency::total 20918670107 # number of ReadSharedReq miss cycles 2627system.l2c.demand_miss_latency::cpu0.dtb.walker 21395500 # number of demand (read+write) miss cycles 2628system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles 2629system.l2c.demand_miss_latency::cpu0.inst 2310573000 # number of demand (read+write) miss cycles 2630system.l2c.demand_miss_latency::cpu0.data 2760872000 # number of demand (read+write) miss cycles 2631system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of demand (read+write) miss cycles 2632system.l2c.demand_miss_latency::cpu1.dtb.walker 1721000 # number of demand (read+write) miss cycles 2633system.l2c.demand_miss_latency::cpu1.inst 383378500 # number of demand (read+write) miss cycles 2634system.l2c.demand_miss_latency::cpu1.data 1102644000 # number of demand (read+write) miss cycles 2635system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of demand (read+write) miss cycles 2636system.l2c.demand_miss_latency::total 23310901107 # number of demand (read+write) miss cycles 2637system.l2c.overall_miss_latency::cpu0.dtb.walker 21395500 # number of overall miss cycles 2638system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles 2639system.l2c.overall_miss_latency::cpu0.inst 2310573000 # number of overall miss cycles 2640system.l2c.overall_miss_latency::cpu0.data 2760872000 # number of overall miss cycles 2641system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of overall miss cycles 2642system.l2c.overall_miss_latency::cpu1.dtb.walker 1721000 # number of overall miss cycles 2643system.l2c.overall_miss_latency::cpu1.inst 383378500 # number of overall miss cycles 2644system.l2c.overall_miss_latency::cpu1.data 1102644000 # number of overall miss cycles 2645system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of overall miss cycles 2646system.l2c.overall_miss_latency::total 23310901107 # number of overall miss cycles 2647system.l2c.WritebackDirty_accesses::writebacks 269158 # number of WritebackDirty accesses(hits+misses) 2648system.l2c.WritebackDirty_accesses::total 269158 # number of WritebackDirty accesses(hits+misses) 2649system.l2c.UpgradeReq_accesses::cpu0.data 43332 # number of UpgradeReq accesses(hits+misses) 2650system.l2c.UpgradeReq_accesses::cpu1.data 5851 # number of UpgradeReq accesses(hits+misses) 2651system.l2c.UpgradeReq_accesses::total 49183 # number of UpgradeReq accesses(hits+misses) 2652system.l2c.SCUpgradeReq_accesses::cpu0.data 2849 # number of SCUpgradeReq accesses(hits+misses) 2653system.l2c.SCUpgradeReq_accesses::cpu1.data 2387 # number of SCUpgradeReq accesses(hits+misses) 2654system.l2c.SCUpgradeReq_accesses::total 5236 # number of SCUpgradeReq accesses(hits+misses) 2655system.l2c.ReadExReq_accesses::cpu0.data 15579 # number of ReadExReq accesses(hits+misses) 2656system.l2c.ReadExReq_accesses::cpu1.data 10156 # number of ReadExReq accesses(hits+misses) 2657system.l2c.ReadExReq_accesses::total 25735 # number of ReadExReq accesses(hits+misses) 2658system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 743 # number of ReadSharedReq accesses(hits+misses) 2659system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 97 # number of ReadSharedReq accesses(hits+misses) 2660system.l2c.ReadSharedReq_accesses::cpu0.inst 91751 # number of ReadSharedReq accesses(hits+misses) 2661system.l2c.ReadSharedReq_accesses::cpu0.data 73493 # number of ReadSharedReq accesses(hits+misses) 2662system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180279 # number of ReadSharedReq accesses(hits+misses) 2663system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 152 # number of ReadSharedReq accesses(hits+misses) 2664system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses) 2665system.l2c.ReadSharedReq_accesses::cpu1.inst 35611 # number of ReadSharedReq accesses(hits+misses) 2666system.l2c.ReadSharedReq_accesses::cpu1.data 15367 # number of ReadSharedReq accesses(hits+misses) 2667system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12174 # number of ReadSharedReq accesses(hits+misses) 2668system.l2c.ReadSharedReq_accesses::total 409679 # number of ReadSharedReq accesses(hits+misses) 2669system.l2c.demand_accesses::cpu0.dtb.walker 743 # number of demand (read+write) accesses 2670system.l2c.demand_accesses::cpu0.itb.walker 97 # number of demand (read+write) accesses 2671system.l2c.demand_accesses::cpu0.inst 91751 # number of demand (read+write) accesses 2672system.l2c.demand_accesses::cpu0.data 89072 # number of demand (read+write) accesses 2673system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180279 # number of demand (read+write) accesses 2674system.l2c.demand_accesses::cpu1.dtb.walker 152 # number of demand (read+write) accesses 2675system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses 2676system.l2c.demand_accesses::cpu1.inst 35611 # number of demand (read+write) accesses 2677system.l2c.demand_accesses::cpu1.data 25523 # number of demand (read+write) accesses 2678system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12174 # number of demand (read+write) accesses 2679system.l2c.demand_accesses::total 435414 # number of demand (read+write) accesses 2680system.l2c.overall_accesses::cpu0.dtb.walker 743 # number of overall (read+write) accesses 2681system.l2c.overall_accesses::cpu0.itb.walker 97 # number of overall (read+write) accesses 2682system.l2c.overall_accesses::cpu0.inst 91751 # number of overall (read+write) accesses 2683system.l2c.overall_accesses::cpu0.data 89072 # number of overall (read+write) accesses 2684system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180279 # number of overall (read+write) accesses 2685system.l2c.overall_accesses::cpu1.dtb.walker 152 # number of overall (read+write) accesses 2686system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses 2687system.l2c.overall_accesses::cpu1.inst 35611 # number of overall (read+write) accesses 2688system.l2c.overall_accesses::cpu1.data 25523 # number of overall (read+write) accesses 2689system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12174 # number of overall (read+write) accesses 2690system.l2c.overall_accesses::total 435414 # number of overall (read+write) accesses 2691system.l2c.UpgradeReq_miss_rate::cpu0.data 0.009323 # miss rate for UpgradeReq accesses 2692system.l2c.UpgradeReq_miss_rate::cpu1.data 0.039139 # miss rate for UpgradeReq accesses 2693system.l2c.UpgradeReq_miss_rate::total 0.012870 # miss rate for UpgradeReq accesses 2694system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037206 # miss rate for SCUpgradeReq accesses 2695system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034353 # miss rate for SCUpgradeReq accesses 2696system.l2c.SCUpgradeReq_miss_rate::total 0.035905 # miss rate for SCUpgradeReq accesses 2697system.l2c.ReadExReq_miss_rate::cpu0.data 0.725335 # miss rate for ReadExReq accesses 2698system.l2c.ReadExReq_miss_rate::cpu1.data 0.850138 # miss rate for ReadExReq accesses 2699system.l2c.ReadExReq_miss_rate::total 0.774587 # miss rate for ReadExReq accesses 2700system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for ReadSharedReq accesses 2701system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010309 # miss rate for ReadSharedReq accesses 2702system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.249828 # miss rate for ReadSharedReq accesses 2703system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.135346 # miss rate for ReadSharedReq accesses 2704system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for ReadSharedReq accesses 2705system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses 2706system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098060 # miss rate for ReadSharedReq accesses 2707system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110887 # miss rate for ReadSharedReq accesses 2708system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for ReadSharedReq accesses 2709system.l2c.ReadSharedReq_miss_rate::total 0.433432 # miss rate for ReadSharedReq accesses 2710system.l2c.demand_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for demand accesses 2711system.l2c.demand_miss_rate::cpu0.itb.walker 0.010309 # miss rate for demand accesses 2712system.l2c.demand_miss_rate::cpu0.inst 0.249828 # miss rate for demand accesses 2713system.l2c.demand_miss_rate::cpu0.data 0.238537 # miss rate for demand accesses 2714system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for demand accesses 2715system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses 2716system.l2c.demand_miss_rate::cpu1.inst 0.098060 # miss rate for demand accesses 2717system.l2c.demand_miss_rate::cpu1.data 0.405046 # miss rate for demand accesses 2718system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for demand accesses 2719system.l2c.demand_miss_rate::total 0.453596 # miss rate for demand accesses 2720system.l2c.overall_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for overall accesses 2721system.l2c.overall_miss_rate::cpu0.itb.walker 0.010309 # miss rate for overall accesses 2722system.l2c.overall_miss_rate::cpu0.inst 0.249828 # miss rate for overall accesses 2723system.l2c.overall_miss_rate::cpu0.data 0.238537 # miss rate for overall accesses 2724system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for overall accesses 2725system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses 2726system.l2c.overall_miss_rate::cpu1.inst 0.098060 # miss rate for overall accesses 2727system.l2c.overall_miss_rate::cpu1.data 0.405046 # miss rate for overall accesses 2728system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for overall accesses 2729system.l2c.overall_miss_rate::total 0.453596 # miss rate for overall accesses 2730system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19133.663366 # average UpgradeReq miss latency 2731system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4203.056769 # average UpgradeReq miss latency 2732system.l2c.UpgradeReq_avg_miss_latency::total 13732.227488 # average UpgradeReq miss latency 2733system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6504.716981 # average SCUpgradeReq miss latency 2734system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2018.292683 # average SCUpgradeReq miss latency 2735system.l2c.SCUpgradeReq_avg_miss_latency::total 4547.872340 # average SCUpgradeReq miss latency 2736system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138231.592920 # average ReadExReq miss latency 2737system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96156.358582 # average ReadExReq miss latency 2738system.l2c.ReadExReq_avg_miss_latency::total 120007.574997 # average ReadExReq miss latency 2739system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average ReadSharedReq miss latency 2740system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency 2741system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 100801.544368 # average ReadSharedReq miss latency 2742system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 120524.278677 # average ReadSharedReq miss latency 2743system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average ReadSharedReq miss latency 2744system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average ReadSharedReq miss latency 2745system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109787.657503 # average ReadSharedReq miss latency 2746system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 159876.760563 # average ReadSharedReq miss latency 2747system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average ReadSharedReq miss latency 2748system.l2c.ReadSharedReq_avg_miss_latency::total 117806.531059 # average ReadSharedReq miss latency 2749system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency 2750system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2751system.l2c.demand_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency 2752system.l2c.demand_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency 2753system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency 2754system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency 2755system.l2c.demand_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency 2756system.l2c.demand_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency 2757system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency 2758system.l2c.demand_avg_miss_latency::total 118028.683796 # average overall miss latency 2759system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency 2760system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2761system.l2c.overall_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency 2762system.l2c.overall_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency 2763system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency 2764system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency 2765system.l2c.overall_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency 2766system.l2c.overall_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency 2767system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency 2768system.l2c.overall_avg_miss_latency::total 118028.683796 # average overall miss latency 2769system.l2c.blocked_cycles::no_mshrs 151 # number of cycles access was blocked 2770system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2771system.l2c.blocked::no_mshrs 4 # number of cycles access was blocked 2772system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2773system.l2c.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked 2774system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2775system.l2c.writebacks::writebacks 105386 # number of writebacks 2776system.l2c.writebacks::total 105386 # number of writebacks 2777system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits 2778system.l2c.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits 2779system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 2780system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 2781system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 2782system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits 2783system.l2c.CleanEvict_mshr_misses::writebacks 4794 # number of CleanEvict MSHR misses 2784system.l2c.CleanEvict_mshr_misses::total 4794 # number of CleanEvict MSHR misses 2785system.l2c.UpgradeReq_mshr_misses::cpu0.data 404 # number of UpgradeReq MSHR misses 2786system.l2c.UpgradeReq_mshr_misses::cpu1.data 229 # number of UpgradeReq MSHR misses 2787system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses 2788system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 106 # number of SCUpgradeReq MSHR misses 2789system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 82 # number of SCUpgradeReq MSHR misses 2790system.l2c.SCUpgradeReq_mshr_misses::total 188 # number of SCUpgradeReq MSHR misses 2791system.l2c.ReadExReq_mshr_misses::cpu0.data 11300 # number of ReadExReq MSHR misses 2792system.l2c.ReadExReq_mshr_misses::cpu1.data 8634 # number of ReadExReq MSHR misses 2793system.l2c.ReadExReq_mshr_misses::total 19934 # number of ReadExReq MSHR misses 2794system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 147 # number of ReadSharedReq MSHR misses 2795system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2796system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22919 # number of ReadSharedReq MSHR misses 2797system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9947 # number of ReadSharedReq MSHR misses 2798system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq MSHR misses 2799system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 19 # 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number of demand (read+write) MSHR misses 2811system.l2c.demand_mshr_misses::cpu1.data 10338 # number of demand (read+write) MSHR misses 2812system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) MSHR misses 2813system.l2c.demand_mshr_misses::total 197499 # number of demand (read+write) MSHR misses 2814system.l2c.overall_mshr_misses::cpu0.dtb.walker 147 # number of overall MSHR misses 2815system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2816system.l2c.overall_mshr_misses::cpu0.inst 22919 # number of overall MSHR misses 2817system.l2c.overall_mshr_misses::cpu0.data 21247 # number of overall MSHR misses 2818system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of overall MSHR misses 2819system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses 2820system.l2c.overall_mshr_misses::cpu1.inst 3492 # number of overall MSHR misses 2821system.l2c.overall_mshr_misses::cpu1.data 10338 # number of overall MSHR misses 2822system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of overall MSHR misses 2823system.l2c.overall_mshr_misses::total 197499 # number of overall MSHR misses 2824system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable 2825system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable 2826system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2827system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14421 # number of ReadReq MSHR uncacheable 2828system.l2c.ReadReq_mshr_uncacheable::total 38391 # number of ReadReq MSHR uncacheable 2829system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable 2830system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable 2831system.l2c.WriteReq_mshr_uncacheable::total 31027 # number of WriteReq MSHR uncacheable 2832system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses 2833system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses 2834system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2835system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26178 # number of overall MSHR uncacheable misses 2836system.l2c.overall_mshr_uncacheable_misses::total 69418 # number of overall MSHR uncacheable misses 2837system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 8946500 # number of UpgradeReq MSHR miss cycles 2838system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5034000 # number of UpgradeReq MSHR miss cycles 2839system.l2c.UpgradeReq_mshr_miss_latency::total 13980500 # number of UpgradeReq MSHR miss cycles 2840system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2786000 # number of SCUpgradeReq MSHR miss cycles 2841system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1998500 # number of SCUpgradeReq MSHR miss cycles 2842system.l2c.SCUpgradeReq_mshr_miss_latency::total 4784500 # number of SCUpgradeReq MSHR miss cycles 2843system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1449017000 # number of ReadExReq MSHR miss cycles 2844system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 743874000 # number of ReadExReq MSHR miss cycles 2845system.l2c.ReadExReq_mshr_miss_latency::total 2192891000 # number of ReadExReq MSHR miss cycles 2846system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of ReadSharedReq MSHR miss cycles 2847system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles 2848system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2081229000 # number of ReadSharedReq MSHR miss cycles 2849system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1099385000 # number of ReadSharedReq MSHR miss cycles 2850system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of ReadSharedReq MSHR miss cycles 2851system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of ReadSharedReq MSHR miss cycles 2852system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 348458500 # number of ReadSharedReq MSHR miss cycles 2853system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 255390000 # number of ReadSharedReq MSHR miss cycles 2854system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of ReadSharedReq MSHR miss cycles 2855system.l2c.ReadSharedReq_mshr_miss_latency::total 19142863612 # number of ReadSharedReq MSHR miss cycles 2856system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of demand (read+write) MSHR miss cycles 2857system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 2858system.l2c.demand_mshr_miss_latency::cpu0.inst 2081229000 # number of demand (read+write) MSHR miss cycles 2859system.l2c.demand_mshr_miss_latency::cpu0.data 2548402000 # number of demand (read+write) MSHR miss cycles 2860system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of demand (read+write) MSHR miss cycles 2861system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of demand (read+write) MSHR miss cycles 2862system.l2c.demand_mshr_miss_latency::cpu1.inst 348458500 # number of demand (read+write) MSHR miss cycles 2863system.l2c.demand_mshr_miss_latency::cpu1.data 999264000 # number of demand (read+write) MSHR miss cycles 2864system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of demand (read+write) MSHR miss cycles 2865system.l2c.demand_mshr_miss_latency::total 21335754612 # number of demand (read+write) MSHR miss cycles 2866system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of overall MSHR miss cycles 2867system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles 2868system.l2c.overall_mshr_miss_latency::cpu0.inst 2081229000 # number of overall MSHR miss cycles 2869system.l2c.overall_mshr_miss_latency::cpu0.data 2548402000 # number of overall MSHR miss cycles 2870system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of overall MSHR miss cycles 2871system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of overall MSHR miss cycles 2872system.l2c.overall_mshr_miss_latency::cpu1.inst 348458500 # number of overall MSHR miss cycles 2873system.l2c.overall_mshr_miss_latency::cpu1.data 999264000 # number of overall MSHR miss cycles 2874system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of overall MSHR miss cycles 2875system.l2c.overall_mshr_miss_latency::total 21335754612 # number of overall MSHR miss cycles 2876system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles 2877system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4072237500 # number of ReadReq MSHR uncacheable cycles 2878system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7748500 # number of ReadReq MSHR uncacheable cycles 2879system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2117933000 # number of ReadReq MSHR uncacheable cycles 2880system.l2c.ReadReq_mshr_uncacheable_latency::total 6426767500 # number of ReadReq MSHR uncacheable cycles 2881system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles 2882system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4072237500 # number of overall MSHR uncacheable cycles 2883system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7748500 # number of overall MSHR uncacheable cycles 2884system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2117933000 # number of overall MSHR uncacheable cycles 2885system.l2c.overall_mshr_uncacheable_latency::total 6426767500 # number of overall MSHR uncacheable cycles 2886system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2887system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2888system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.009323 # mshr miss rate for UpgradeReq accesses 2889system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.039139 # mshr miss rate for UpgradeReq accesses 2890system.l2c.UpgradeReq_mshr_miss_rate::total 0.012870 # mshr miss rate for UpgradeReq accesses 2891system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for SCUpgradeReq accesses 2892system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034353 # mshr miss rate for SCUpgradeReq accesses 2893system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035905 # mshr miss rate for SCUpgradeReq accesses 2894system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725335 # mshr miss rate for ReadExReq accesses 2895system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850138 # mshr miss rate for ReadExReq accesses 2896system.l2c.ReadExReq_mshr_miss_rate::total 0.774587 # mshr miss rate for ReadExReq accesses 2897system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for ReadSharedReq accesses 2898system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses 2899system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for ReadSharedReq accesses 2900system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.135346 # mshr miss rate for ReadSharedReq accesses 2901system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for ReadSharedReq accesses 2902system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses 2903system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for ReadSharedReq accesses 2904system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110887 # mshr miss rate for ReadSharedReq accesses 2905system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for ReadSharedReq accesses 2906system.l2c.ReadSharedReq_mshr_miss_rate::total 0.433425 # mshr miss rate for ReadSharedReq accesses 2907system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for demand accesses 2908system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses 2909system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for demand accesses 2910system.l2c.demand_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for demand accesses 2911system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for demand accesses 2912system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses 2913system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for demand accesses 2914system.l2c.demand_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for demand accesses 2915system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for demand accesses 2916system.l2c.demand_mshr_miss_rate::total 0.453589 # mshr miss rate for demand accesses 2917system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for overall accesses 2918system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses 2919system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for overall accesses 2920system.l2c.overall_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for overall accesses 2921system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for overall accesses 2922system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses 2923system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for overall accesses 2924system.l2c.overall_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for overall accesses 2925system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for overall accesses 2926system.l2c.overall_mshr_miss_rate::total 0.453589 # mshr miss rate for overall accesses 2927system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22144.801980 # average UpgradeReq mshr miss latency 2928system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21982.532751 # average UpgradeReq mshr miss latency 2929system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22086.097946 # average UpgradeReq mshr miss latency 2930system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26283.018868 # average SCUpgradeReq mshr miss latency 2931system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24371.951220 # average SCUpgradeReq mshr miss latency 2932system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25449.468085 # average SCUpgradeReq mshr miss latency 2933system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128231.592920 # average ReadExReq mshr miss latency 2934system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86156.358582 # average ReadExReq mshr miss latency 2935system.l2c.ReadExReq_avg_mshr_miss_latency::total 110007.574997 # average ReadExReq mshr miss latency 2936system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average ReadSharedReq mshr miss latency 2937system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency 2938system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average ReadSharedReq mshr miss latency 2939system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 110524.278677 # average ReadSharedReq mshr miss latency 2940system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average ReadSharedReq mshr miss latency 2941system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average ReadSharedReq mshr miss latency 2942system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average ReadSharedReq mshr miss latency 2943system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 149876.760563 # average ReadSharedReq mshr miss latency 2944system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average ReadSharedReq mshr miss latency 2945system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 107807.640087 # average ReadSharedReq mshr miss latency 2946system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency 2947system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2948system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency 2949system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency 2950system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency 2951system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency 2952system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency 2953system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency 2954system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency 2955system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency 2956system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency 2957system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2958system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency 2959system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency 2960system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency 2961system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency 2962system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency 2963system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency 2964system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency 2965system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency 2966system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency 2967system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency 2968system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency 2969system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency 2970system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency 2971system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency 2972system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency 2973system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency 2974system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency 2975system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency 2976system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter. 2977system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2978system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2979system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2980system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2981system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2982system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 2983system.membus.trans_dist::ReadReq 38391 # Transaction distribution 2984system.membus.trans_dist::ReadResp 216211 # Transaction distribution 2985system.membus.trans_dist::WriteReq 31027 # Transaction distribution 2986system.membus.trans_dist::WriteResp 31027 # Transaction distribution 2987system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution 2988system.membus.trans_dist::CleanEvict 19995 # Transaction distribution 2989system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution 2990system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution 2991system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2992system.membus.trans_dist::ReadExReq 40431 # Transaction distribution 2993system.membus.trans_dist::ReadExResp 19912 # Transaction distribution 2994system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution 2995system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2996system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution 2997system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2998system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2999system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) 3000system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes) 3001system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes) 3002system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) 3003system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) 3004system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes) 3005system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 3006system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 3007system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) 3008system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes) 3009system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes) 3010system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3011system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3012system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes) 3013system.membus.snoops 127509 # Total snoops (count) 3014system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) 3015system.membus.snoop_fanout::samples 426843 # Request fanout histogram 3016system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram 3017system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram 3018system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3019system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram 3020system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram 3021system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3022system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3023system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3024system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3025system.membus.snoop_fanout::total 426843 # Request fanout histogram 3026system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks) 3027system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3028system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) 3029system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3030system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks) 3031system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3032system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks) 3033system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3034system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks) 3035system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3036system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks) 3037system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3038system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3039system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3040system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3041system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3042system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3043system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3044system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3045system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3046system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3047system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3048system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3049system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3050system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3051system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3052system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3053system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3054system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3055system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3056system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3057system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3058system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3059system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3060system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3061system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3062system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3063system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3064system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3065system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3066system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3067system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3068system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3069system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3070system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3071system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3072system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3073system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3074system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3075system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3076system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3077system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3078system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3079system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3080system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3081system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3082system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3083system.realview.ethernet.droppedPackets 0 # number of packets dropped 3084system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3085system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3086system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3087system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3088system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3089system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3090system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3091system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3092system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3093system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3094system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3095system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3096system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3097system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3098system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3099system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3100system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3101system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3102system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3103system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3104system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3105system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3106system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3107system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter. 3108system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3109system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3110system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. 3111system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3112system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3113system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states 3114system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution 3115system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution 3116system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution 3117system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution 3118system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution 3119system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution 3120system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution 3121system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution 3122system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution 3123system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution 3124system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution 3125system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution 3126system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution 3127system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution 3128system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution 3129system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution 3130system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes) 3131system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes) 3132system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes) 3133system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes) 3134system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes) 3135system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes) 3136system.toL2Bus.snoops 402215 # Total snoops (count) 3137system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes) 3138system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram 3139system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram 3140system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram 3141system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3142system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram 3143system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram 3144system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram 3145system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3146system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3147system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3148system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram 3149system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks) 3150system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3151system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks) 3152system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3153system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks) 3154system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3155system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks) 3156system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3157 3158---------- End Simulation Statistics ---------- 3159