stats.txt revision 11374:c1525cc9ec7f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.649116 # Number of seconds simulated 4sim_ticks 2649116242500 # Number of ticks simulated 5final_tick 2649116242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 120147 # Simulator instruction rate (inst/s) 8host_op_rate 145490 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2497044812 # Simulator tick rate (ticks/s) 10host_mem_usage 602856 # Number of bytes of host memory used 11host_seconds 1060.90 # Real time elapsed on the host 12sim_insts 127464482 # Number of instructions simulated 13sim_ops 154350851 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1526336 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1246188 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8224576 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 394816 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 723292 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 617536 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12744072 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1526336 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 394816 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1921152 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8953600 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8971164 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 23849 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 19993 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 128509 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 6169 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 11324 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 9649 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 199670 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 139900 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 144291 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 576168 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 470417 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 3104649 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 966 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 149037 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 273031 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 233110 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 362 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4810688 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 576168 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 149037 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 725205 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3379844 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6615 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 3386474 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3379844 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 576168 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 477032 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 3104649 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 966 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 149037 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 273047 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 233110 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 362 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 8197162 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199670 # Number of read requests accepted 80system.physmem.writeReqs 144291 # Number of write requests accepted 81system.physmem.readBursts 199670 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 144291 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12768704 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8984192 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12744072 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8971164 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12456 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12907 # Per bank write bursts 93system.physmem.perBankRdBursts::2 13452 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12663 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15992 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12602 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12853 # Per bank write bursts 98system.physmem.perBankRdBursts::7 13005 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12164 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12306 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11290 # Per bank write bursts 102system.physmem.perBankRdBursts::11 10778 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11668 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12164 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11811 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11400 # Per bank write bursts 107system.physmem.perBankWrBursts::0 8970 # Per bank write bursts 108system.physmem.perBankWrBursts::1 9418 # Per bank write bursts 109system.physmem.perBankWrBursts::2 9818 # Per bank write bursts 110system.physmem.perBankWrBursts::3 9016 # Per bank write bursts 111system.physmem.perBankWrBursts::4 8619 # Per bank write bursts 112system.physmem.perBankWrBursts::5 8911 # Per bank write bursts 113system.physmem.perBankWrBursts::6 9199 # Per bank write bursts 114system.physmem.perBankWrBursts::7 9114 # Per bank write bursts 115system.physmem.perBankWrBursts::8 8718 # Per bank write bursts 116system.physmem.perBankWrBursts::9 8852 # Per bank write bursts 117system.physmem.perBankWrBursts::10 8120 # Per bank write bursts 118system.physmem.perBankWrBursts::11 7867 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8570 # Per bank write bursts 120system.physmem.perBankWrBursts::13 8570 # Per bank write bursts 121system.physmem.perBankWrBursts::14 8685 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7931 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 32 # Number of times write queue was full causing retry 125system.physmem.totGap 2649115714000 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 554 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 199088 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 139900 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 88665 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 60851 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 11657 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9446 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5185 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4622 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3733 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 673 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2858 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3859 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 5326 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 5137 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 6360 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6284 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6761 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7386 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8198 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 8241 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 8939 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 10034 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8912 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 9656 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 11650 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 9193 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8389 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 8138 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 1203 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 417 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 311 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 213 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 183 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 201 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 138 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 131 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 74 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 93964 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 231.501767 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 131.710526 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 295.455834 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 51656 54.97% 54.97% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 18156 19.32% 74.30% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6272 6.67% 80.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3449 3.67% 84.64% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2927 3.12% 87.76% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1465 1.56% 89.32% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 883 0.94% 90.26% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 950 1.01% 91.27% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8206 8.73% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 93964 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6826 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 29.227952 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 564.671734 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6825 99.99% 99.99% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::total 6826 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6826 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 20.565192 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 18.817384 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 13.562313 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-19 5689 83.34% 83.34% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20-23 486 7.12% 90.46% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::24-27 93 1.36% 91.83% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::28-31 54 0.79% 92.62% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::32-35 43 0.63% 93.25% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::36-39 24 0.35% 93.60% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::40-43 57 0.84% 94.43% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::44-47 8 0.12% 94.55% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::48-51 116 1.70% 96.25% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::52-55 16 0.23% 96.48% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::56-59 10 0.15% 96.63% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::60-63 12 0.18% 96.81% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-67 73 1.07% 97.88% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::68-71 7 0.10% 97.98% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::72-75 4 0.06% 98.04% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::76-79 20 0.29% 98.33% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::80-83 80 1.17% 99.50% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::88-91 3 0.04% 99.56% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::92-95 1 0.01% 99.58% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::96-99 2 0.03% 99.60% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::104-107 3 0.04% 99.65% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::108-111 1 0.01% 99.66% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::128-131 9 0.13% 99.79% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::136-139 1 0.01% 99.81% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::140-143 1 0.01% 99.82% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::144-147 3 0.04% 99.87% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::152-155 1 0.01% 99.88% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::total 6826 # Writes before turning the bus around for reads 294system.physmem.totQLat 5414962245 # Total ticks spent queuing 295system.physmem.totMemAccLat 9155793495 # Total ticks spent from burst creation until serviced by the DRAM 296system.physmem.totBusLat 997555000 # Total ticks spent in databus transfers 297system.physmem.avgQLat 27141.17 # Average queueing delay per DRAM burst 298system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 299system.physmem.avgMemAccLat 45891.17 # Average memory access latency per DRAM burst 300system.physmem.avgRdBW 4.82 # Average DRAM read bandwidth in MiByte/s 301system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s 302system.physmem.avgRdBWSys 4.81 # Average system read bandwidth in MiByte/s 303system.physmem.avgWrBWSys 3.39 # Average system write bandwidth in MiByte/s 304system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 305system.physmem.busUtil 0.06 # Data bus utilization in percentage 306system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 307system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 308system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 309system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing 310system.physmem.readRowHits 165357 # Number of row buffer hits during reads 311system.physmem.writeRowHits 80567 # Number of row buffer hits during writes 312system.physmem.readRowHitRate 82.88 # Row buffer hit rate for reads 313system.physmem.writeRowHitRate 57.39 # Row buffer hit rate for writes 314system.physmem.avgGap 7701790.94 # Average gap between requests 315system.physmem.pageHitRate 72.35 # Row buffer hit rate, read and write combined 316system.physmem_0.actEnergy 377130600 # Energy for activate commands per rank (pJ) 317system.physmem_0.preEnergy 205775625 # Energy for precharge commands per rank (pJ) 318system.physmem_0.readEnergy 826254000 # Energy for read commands per rank (pJ) 319system.physmem_0.writeEnergy 473461200 # Energy for write commands per rank (pJ) 320system.physmem_0.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ) 321system.physmem_0.actBackEnergy 81211791960 # Energy for active background per rank (pJ) 322system.physmem_0.preBackEnergy 1518231236250 # Energy for precharge background per rank (pJ) 323system.physmem_0.totalEnergy 1774353018435 # Total energy per rank (pJ) 324system.physmem_0.averagePower 669.790588 # Core power per rank (mW) 325system.physmem_0.memoryStateTime::IDLE 2525572951341 # Time in different power states 326system.physmem_0.memoryStateTime::REF 88459800000 # Time in different power states 327system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 328system.physmem_0.memoryStateTime::ACT 35083346159 # Time in different power states 329system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 330system.physmem_1.actEnergy 333237240 # Energy for activate commands per rank (pJ) 331system.physmem_1.preEnergy 181825875 # Energy for precharge commands per rank (pJ) 332system.physmem_1.readEnergy 729924000 # Energy for read commands per rank (pJ) 333system.physmem_1.writeEnergy 436188240 # Energy for write commands per rank (pJ) 334system.physmem_1.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ) 335system.physmem_1.actBackEnergy 79517209320 # Energy for active background per rank (pJ) 336system.physmem_1.preBackEnergy 1519717712250 # Energy for precharge background per rank (pJ) 337system.physmem_1.totalEnergy 1773943465725 # Total energy per rank (pJ) 338system.physmem_1.averagePower 669.635988 # Core power per rank (mW) 339system.physmem_1.memoryStateTime::IDLE 2528054644365 # Time in different power states 340system.physmem_1.memoryStateTime::REF 88459800000 # Time in different power states 341system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 342system.physmem_1.memoryStateTime::ACT 32601653135 # Time in different power states 343system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 344system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 350system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 353system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::total 507 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::total 507 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 507 # Total bandwidth to/from this memory (bytes/s) 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. 368system.cpu0.branchPred.lookups 19632721 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 12741106 # Number of conditional branches predicted 370system.cpu0.branchPred.condIncorrect 957809 # Number of conditional branches incorrect 371system.cpu0.branchPred.BTBLookups 12414007 # Number of BTB lookups 372system.cpu0.branchPred.BTBHits 8826841 # Number of BTB hits 373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 374system.cpu0.branchPred.BTBHitPct 71.103883 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 3283973 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 196273 # Number of incorrect RAS predictions. 377system.cpu_clk_domain.clock 500 # Clock period in ticks 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 387system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 388system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 389system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 390system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 391system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 392system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 393system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 396system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 397system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 398system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 399system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 401system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 402system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 403system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 404system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 405system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 406system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 407system.cpu0.dtb.walker.walks 67362 # Table walker walks requested 408system.cpu0.dtb.walker.walksShort 67362 # Table walker walks initiated with short descriptors 409system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44747 # Level at which table walker walks with short descriptors terminate 410system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22615 # Level at which table walker walks with short descriptors terminate 411system.cpu0.dtb.walker.walkWaitTime::samples 67362 # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::0 67362 100.00% 100.00% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::total 67362 # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkCompletionTime::samples 6703 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::mean 11941.220349 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::gmean 10822.969980 # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::stdev 8452.619900 # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::0-32767 6653 99.25% 99.25% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::32768-65535 41 0.61% 99.87% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::131072-163839 8 0.12% 99.99% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::total 6703 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution 424system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution 425system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution 426system.cpu0.dtb.walker.walkPageSizes::4K 5190 77.43% 77.43% # Table walker page sizes translated 427system.cpu0.dtb.walker.walkPageSizes::1M 1513 22.57% 100.00% # Table walker page sizes translated 428system.cpu0.dtb.walker.walkPageSizes::total 6703 # Table walker page sizes translated 429system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67362 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67362 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6703 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 434system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6703 # Table walker requests started/completed, data/inst 435system.cpu0.dtb.walker.walkRequestOrigin::total 74065 # Table walker requests started/completed, data/inst 436system.cpu0.dtb.inst_hits 0 # ITB inst hits 437system.cpu0.dtb.inst_misses 0 # ITB inst misses 438system.cpu0.dtb.read_hits 16471465 # DTB read hits 439system.cpu0.dtb.read_misses 61259 # DTB read misses 440system.cpu0.dtb.write_hits 13861421 # DTB write hits 441system.cpu0.dtb.write_misses 6103 # DTB write misses 442system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 443system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 444system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 445system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 446system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 447system.cpu0.dtb.align_faults 1118 # Number of TLB faults due to alignment restrictions 448system.cpu0.dtb.prefetch_faults 1582 # Number of TLB faults due to prefetch 449system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 450system.cpu0.dtb.perms_faults 565 # Number of TLB faults due to permissions restrictions 451system.cpu0.dtb.read_accesses 16532724 # DTB read accesses 452system.cpu0.dtb.write_accesses 13867524 # DTB write accesses 453system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 454system.cpu0.dtb.hits 30332886 # DTB hits 455system.cpu0.dtb.misses 67362 # DTB misses 456system.cpu0.dtb.accesses 30400248 # DTB accesses 457system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 466system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 467system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 468system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 469system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 470system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 471system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 472system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 473system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 474system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 475system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 476system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 477system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 478system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 479system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 480system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 481system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 482system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 483system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 484system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 485system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 486system.cpu0.itb.walker.walks 3870 # Table walker walks requested 487system.cpu0.itb.walker.walksShort 3870 # Table walker walks initiated with short descriptors 488system.cpu0.itb.walker.walksShortTerminationLevel::Level1 303 # Level at which table walker walks with short descriptors terminate 489system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3567 # Level at which table walker walks with short descriptors terminate 490system.cpu0.itb.walker.walkWaitTime::samples 3870 # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::0 3870 100.00% 100.00% # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkWaitTime::total 3870 # Table walker wait (enqueue to first request) latency 493system.cpu0.itb.walker.walkCompletionTime::samples 2416 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::mean 12175.289735 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::gmean 11303.436072 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::stdev 5287.236665 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::0-16383 2213 91.60% 91.60% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::16384-32767 183 7.57% 99.17% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.79% 99.96% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::total 2416 # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution 503system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution 504system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution 505system.cpu0.itb.walker.walkPageSizes::4K 2118 87.67% 87.67% # Table walker page sizes translated 506system.cpu0.itb.walker.walkPageSizes::1M 298 12.33% 100.00% # Table walker page sizes translated 507system.cpu0.itb.walker.walkPageSizes::total 2416 # Table walker page sizes translated 508system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3870 # Table walker requests started/completed, data/inst 510system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3870 # Table walker requests started/completed, data/inst 511system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2416 # Table walker requests started/completed, data/inst 513system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2416 # Table walker requests started/completed, data/inst 514system.cpu0.itb.walker.walkRequestOrigin::total 6286 # Table walker requests started/completed, data/inst 515system.cpu0.itb.inst_hits 36732226 # ITB inst hits 516system.cpu0.itb.inst_misses 3870 # ITB inst misses 517system.cpu0.itb.read_hits 0 # DTB read hits 518system.cpu0.itb.read_misses 0 # DTB read misses 519system.cpu0.itb.write_hits 0 # DTB write hits 520system.cpu0.itb.write_misses 0 # DTB write misses 521system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 522system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 523system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 524system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 525system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB 526system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 527system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 528system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 529system.cpu0.itb.perms_faults 7242 # Number of TLB faults due to permissions restrictions 530system.cpu0.itb.read_accesses 0 # DTB read accesses 531system.cpu0.itb.write_accesses 0 # DTB write accesses 532system.cpu0.itb.inst_accesses 36736096 # ITB inst accesses 533system.cpu0.itb.hits 36732226 # DTB hits 534system.cpu0.itb.misses 3870 # DTB misses 535system.cpu0.itb.accesses 36736096 # DTB accesses 536system.cpu0.numCycles 162382442 # number of cpu cycles simulated 537system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 538system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 539system.cpu0.committedInsts 75583432 # Number of instructions committed 540system.cpu0.committedOps 90974289 # Number of ops (including micro ops) committed 541system.cpu0.discardedOps 5013155 # Number of ops (including micro ops) which were discarded before commit 542system.cpu0.numFetchSuspends 2059 # Number of times Execute suspended instruction fetching 543system.cpu0.quiesceCycles 5135888904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 544system.cpu0.cpi 2.148387 # CPI: cycles per instruction 545system.cpu0.ipc 0.465466 # IPC: instructions per cycle 546system.cpu0.kern.inst.arm 0 # number of arm instructions executed 547system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed 548system.cpu0.tickCycles 121978989 # Number of cycles that the object actually ticked 549system.cpu0.idleCycles 40403453 # Total number of cycles that the object has spent stopped 550system.cpu0.dcache.tags.replacements 680701 # number of replacements 551system.cpu0.dcache.tags.tagsinuse 486.682235 # Cycle average of tags in use 552system.cpu0.dcache.tags.total_refs 28901777 # Total number of references to valid blocks. 553system.cpu0.dcache.tags.sampled_refs 681213 # Sample count of references to valid blocks. 554system.cpu0.dcache.tags.avg_refs 42.426931 # Average number of references to valid blocks. 555system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. 556system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.682235 # Average occupied blocks per requestor 557system.cpu0.dcache.tags.occ_percent::cpu0.data 0.950551 # Average percentage of cache occupancy 558system.cpu0.dcache.tags.occ_percent::total 0.950551 # Average percentage of cache occupancy 559system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 560system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 561system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id 562system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 563system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 564system.cpu0.dcache.tags.tag_accesses 60666006 # Number of tag accesses 565system.cpu0.dcache.tags.data_accesses 60666006 # Number of data accesses 566system.cpu0.dcache.ReadReq_hits::cpu0.data 14995152 # number of ReadReq hits 567system.cpu0.dcache.ReadReq_hits::total 14995152 # number of ReadReq hits 568system.cpu0.dcache.WriteReq_hits::cpu0.data 12778726 # number of WriteReq hits 569system.cpu0.dcache.WriteReq_hits::total 12778726 # number of WriteReq hits 570system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305913 # number of SoftPFReq hits 571system.cpu0.dcache.SoftPFReq_hits::total 305913 # number of SoftPFReq hits 572system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356785 # number of LoadLockedReq hits 573system.cpu0.dcache.LoadLockedReq_hits::total 356785 # number of LoadLockedReq hits 574system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351877 # number of StoreCondReq hits 575system.cpu0.dcache.StoreCondReq_hits::total 351877 # number of StoreCondReq hits 576system.cpu0.dcache.demand_hits::cpu0.data 27773878 # number of demand (read+write) hits 577system.cpu0.dcache.demand_hits::total 27773878 # number of demand (read+write) hits 578system.cpu0.dcache.overall_hits::cpu0.data 28079791 # number of overall hits 579system.cpu0.dcache.overall_hits::total 28079791 # number of overall hits 580system.cpu0.dcache.ReadReq_misses::cpu0.data 443645 # number of ReadReq misses 581system.cpu0.dcache.ReadReq_misses::total 443645 # number of ReadReq misses 582system.cpu0.dcache.WriteReq_misses::cpu0.data 558771 # number of WriteReq misses 583system.cpu0.dcache.WriteReq_misses::total 558771 # number of WriteReq misses 584system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131921 # number of SoftPFReq misses 585system.cpu0.dcache.SoftPFReq_misses::total 131921 # number of SoftPFReq misses 586system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20933 # number of LoadLockedReq misses 587system.cpu0.dcache.LoadLockedReq_misses::total 20933 # number of LoadLockedReq misses 588system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21449 # number of StoreCondReq misses 589system.cpu0.dcache.StoreCondReq_misses::total 21449 # number of StoreCondReq misses 590system.cpu0.dcache.demand_misses::cpu0.data 1002416 # number of demand (read+write) misses 591system.cpu0.dcache.demand_misses::total 1002416 # number of demand (read+write) misses 592system.cpu0.dcache.overall_misses::cpu0.data 1134337 # number of overall misses 593system.cpu0.dcache.overall_misses::total 1134337 # number of overall misses 594system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6380347500 # number of ReadReq miss cycles 595system.cpu0.dcache.ReadReq_miss_latency::total 6380347500 # number of ReadReq miss cycles 596system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11838491500 # number of WriteReq miss cycles 597system.cpu0.dcache.WriteReq_miss_latency::total 11838491500 # number of WriteReq miss cycles 598system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330148000 # number of LoadLockedReq miss cycles 599system.cpu0.dcache.LoadLockedReq_miss_latency::total 330148000 # number of LoadLockedReq miss cycles 600system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 572278500 # number of StoreCondReq miss cycles 601system.cpu0.dcache.StoreCondReq_miss_latency::total 572278500 # number of StoreCondReq miss cycles 602system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 490000 # number of StoreCondFailReq miss cycles 603system.cpu0.dcache.StoreCondFailReq_miss_latency::total 490000 # number of StoreCondFailReq miss cycles 604system.cpu0.dcache.demand_miss_latency::cpu0.data 18218839000 # number of demand (read+write) miss cycles 605system.cpu0.dcache.demand_miss_latency::total 18218839000 # number of demand (read+write) miss cycles 606system.cpu0.dcache.overall_miss_latency::cpu0.data 18218839000 # number of overall miss cycles 607system.cpu0.dcache.overall_miss_latency::total 18218839000 # number of overall miss cycles 608system.cpu0.dcache.ReadReq_accesses::cpu0.data 15438797 # number of ReadReq accesses(hits+misses) 609system.cpu0.dcache.ReadReq_accesses::total 15438797 # number of ReadReq accesses(hits+misses) 610system.cpu0.dcache.WriteReq_accesses::cpu0.data 13337497 # number of WriteReq accesses(hits+misses) 611system.cpu0.dcache.WriteReq_accesses::total 13337497 # number of WriteReq accesses(hits+misses) 612system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437834 # number of SoftPFReq accesses(hits+misses) 613system.cpu0.dcache.SoftPFReq_accesses::total 437834 # number of SoftPFReq accesses(hits+misses) 614system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377718 # number of LoadLockedReq accesses(hits+misses) 615system.cpu0.dcache.LoadLockedReq_accesses::total 377718 # number of LoadLockedReq accesses(hits+misses) 616system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373326 # number of StoreCondReq accesses(hits+misses) 617system.cpu0.dcache.StoreCondReq_accesses::total 373326 # number of StoreCondReq accesses(hits+misses) 618system.cpu0.dcache.demand_accesses::cpu0.data 28776294 # number of demand (read+write) accesses 619system.cpu0.dcache.demand_accesses::total 28776294 # number of demand (read+write) accesses 620system.cpu0.dcache.overall_accesses::cpu0.data 29214128 # number of overall (read+write) accesses 621system.cpu0.dcache.overall_accesses::total 29214128 # number of overall (read+write) accesses 622system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028736 # miss rate for ReadReq accesses 623system.cpu0.dcache.ReadReq_miss_rate::total 0.028736 # miss rate for ReadReq accesses 624system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041895 # miss rate for WriteReq accesses 625system.cpu0.dcache.WriteReq_miss_rate::total 0.041895 # miss rate for WriteReq accesses 626system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301304 # miss rate for SoftPFReq accesses 627system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301304 # miss rate for SoftPFReq accesses 628system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055420 # miss rate for LoadLockedReq accesses 629system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055420 # miss rate for LoadLockedReq accesses 630system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057454 # miss rate for StoreCondReq accesses 631system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057454 # miss rate for StoreCondReq accesses 632system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034835 # miss rate for demand accesses 633system.cpu0.dcache.demand_miss_rate::total 0.034835 # miss rate for demand accesses 634system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038828 # miss rate for overall accesses 635system.cpu0.dcache.overall_miss_rate::total 0.038828 # miss rate for overall accesses 636system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14381.650870 # average ReadReq miss latency 637system.cpu0.dcache.ReadReq_avg_miss_latency::total 14381.650870 # average ReadReq miss latency 638system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21186.660546 # average WriteReq miss latency 639system.cpu0.dcache.WriteReq_avg_miss_latency::total 21186.660546 # average WriteReq miss latency 640system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.652415 # average LoadLockedReq miss latency 641system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.652415 # average LoadLockedReq miss latency 642system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26680.894214 # average StoreCondReq miss latency 643system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26680.894214 # average StoreCondReq miss latency 644system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 645system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 646system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18174.928373 # average overall miss latency 647system.cpu0.dcache.demand_avg_miss_latency::total 18174.928373 # average overall miss latency 648system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16061.222547 # average overall miss latency 649system.cpu0.dcache.overall_avg_miss_latency::total 16061.222547 # average overall miss latency 650system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu0.dcache.fast_writes 0 # number of fast writes performed 657system.cpu0.dcache.cache_copies 0 # number of cache copies performed 658system.cpu0.dcache.writebacks::writebacks 680701 # number of writebacks 659system.cpu0.dcache.writebacks::total 680701 # number of writebacks 660system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 70219 # number of ReadReq MSHR hits 661system.cpu0.dcache.ReadReq_mshr_hits::total 70219 # number of ReadReq MSHR hits 662system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244921 # number of WriteReq MSHR hits 663system.cpu0.dcache.WriteReq_mshr_hits::total 244921 # number of WriteReq MSHR hits 664system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14844 # number of LoadLockedReq MSHR hits 665system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14844 # number of LoadLockedReq MSHR hits 666system.cpu0.dcache.demand_mshr_hits::cpu0.data 315140 # number of demand (read+write) MSHR hits 667system.cpu0.dcache.demand_mshr_hits::total 315140 # number of demand (read+write) MSHR hits 668system.cpu0.dcache.overall_mshr_hits::cpu0.data 315140 # number of overall MSHR hits 669system.cpu0.dcache.overall_mshr_hits::total 315140 # number of overall MSHR hits 670system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373426 # number of ReadReq MSHR misses 671system.cpu0.dcache.ReadReq_mshr_misses::total 373426 # number of ReadReq MSHR misses 672system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 313850 # number of WriteReq MSHR misses 673system.cpu0.dcache.WriteReq_mshr_misses::total 313850 # number of WriteReq MSHR misses 674system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99342 # number of SoftPFReq MSHR misses 675system.cpu0.dcache.SoftPFReq_mshr_misses::total 99342 # number of SoftPFReq MSHR misses 676system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6089 # number of LoadLockedReq MSHR misses 677system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6089 # number of LoadLockedReq MSHR misses 678system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21449 # number of StoreCondReq MSHR misses 679system.cpu0.dcache.StoreCondReq_mshr_misses::total 21449 # number of StoreCondReq MSHR misses 680system.cpu0.dcache.demand_mshr_misses::cpu0.data 687276 # number of demand (read+write) MSHR misses 681system.cpu0.dcache.demand_mshr_misses::total 687276 # number of demand (read+write) MSHR misses 682system.cpu0.dcache.overall_mshr_misses::cpu0.data 786618 # number of overall MSHR misses 683system.cpu0.dcache.overall_mshr_misses::total 786618 # number of overall MSHR misses 684system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17966 # number of ReadReq MSHR uncacheable 685system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17966 # number of ReadReq MSHR uncacheable 686system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16715 # number of WriteReq MSHR uncacheable 687system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16715 # number of WriteReq MSHR uncacheable 688system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34681 # number of overall MSHR uncacheable misses 689system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34681 # number of overall MSHR uncacheable misses 690system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4799499000 # number of ReadReq MSHR miss cycles 691system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4799499000 # number of ReadReq MSHR miss cycles 692system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6708842500 # number of WriteReq MSHR miss cycles 693system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6708842500 # number of WriteReq MSHR miss cycles 694system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1708183000 # number of SoftPFReq MSHR miss cycles 695system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1708183000 # number of SoftPFReq MSHR miss cycles 696system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97000000 # number of LoadLockedReq MSHR miss cycles 697system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97000000 # number of LoadLockedReq MSHR miss cycles 698system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 550839500 # number of StoreCondReq MSHR miss cycles 699system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 550839500 # number of StoreCondReq MSHR miss cycles 700system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480000 # number of StoreCondFailReq MSHR miss cycles 701system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480000 # number of StoreCondFailReq MSHR miss cycles 702system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11508341500 # number of demand (read+write) MSHR miss cycles 703system.cpu0.dcache.demand_mshr_miss_latency::total 11508341500 # number of demand (read+write) MSHR miss cycles 704system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13216524500 # number of overall MSHR miss cycles 705system.cpu0.dcache.overall_mshr_miss_latency::total 13216524500 # number of overall MSHR miss cycles 706system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3964655000 # number of ReadReq MSHR uncacheable cycles 707system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3964655000 # number of ReadReq MSHR uncacheable cycles 708system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3079216000 # number of WriteReq MSHR uncacheable cycles 709system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3079216000 # number of WriteReq MSHR uncacheable cycles 710system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7043871000 # number of overall MSHR uncacheable cycles 711system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7043871000 # number of overall MSHR uncacheable cycles 712system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024188 # mshr miss rate for ReadReq accesses 713system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024188 # mshr miss rate for ReadReq accesses 714system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023531 # mshr miss rate for WriteReq accesses 715system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023531 # mshr miss rate for WriteReq accesses 716system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226894 # mshr miss rate for SoftPFReq accesses 717system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226894 # mshr miss rate for SoftPFReq accesses 718system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016120 # mshr miss rate for LoadLockedReq accesses 719system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016120 # mshr miss rate for LoadLockedReq accesses 720system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057454 # mshr miss rate for StoreCondReq accesses 721system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057454 # mshr miss rate for StoreCondReq accesses 722system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023883 # mshr miss rate for demand accesses 723system.cpu0.dcache.demand_mshr_miss_rate::total 0.023883 # mshr miss rate for demand accesses 724system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026926 # mshr miss rate for overall accesses 725system.cpu0.dcache.overall_mshr_miss_rate::total 0.026926 # mshr miss rate for overall accesses 726system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12852.610691 # average ReadReq mshr miss latency 727system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12852.610691 # average ReadReq mshr miss latency 728system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21375.951888 # average WriteReq mshr miss latency 729system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21375.951888 # average WriteReq mshr miss latency 730system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17194.972922 # average SoftPFReq mshr miss latency 731system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17194.972922 # average SoftPFReq mshr miss latency 732system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15930.366234 # average LoadLockedReq mshr miss latency 733system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15930.366234 # average LoadLockedReq mshr miss latency 734system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25681.360436 # average StoreCondReq mshr miss latency 735system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25681.360436 # average StoreCondReq mshr miss latency 736system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 737system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 738system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16744.861599 # average overall mshr miss latency 739system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16744.861599 # average overall mshr miss latency 740system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16801.706165 # average overall mshr miss latency 741system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16801.706165 # average overall mshr miss latency 742system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 220675.442503 # average ReadReq mshr uncacheable latency 743system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220675.442503 # average ReadReq mshr uncacheable latency 744system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 184218.725695 # average WriteReq mshr uncacheable latency 745system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184218.725695 # average WriteReq mshr uncacheable latency 746system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 203104.610594 # average overall mshr uncacheable latency 747system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 203104.610594 # average overall mshr uncacheable latency 748system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 749system.cpu0.icache.tags.replacements 1875262 # number of replacements 750system.cpu0.icache.tags.tagsinuse 511.707229 # Cycle average of tags in use 751system.cpu0.icache.tags.total_refs 34848846 # Total number of references to valid blocks. 752system.cpu0.icache.tags.sampled_refs 1875774 # Sample count of references to valid blocks. 753system.cpu0.icache.tags.avg_refs 18.578382 # Average number of references to valid blocks. 754system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit. 755system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.707229 # Average occupied blocks per requestor 756system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999428 # Average percentage of cache occupancy 757system.cpu0.icache.tags.occ_percent::total 0.999428 # Average percentage of cache occupancy 758system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 759system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 760system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id 761system.cpu0.icache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id 762system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 763system.cpu0.icache.tags.tag_accesses 75325070 # Number of tag accesses 764system.cpu0.icache.tags.data_accesses 75325070 # Number of data accesses 765system.cpu0.icache.ReadReq_hits::cpu0.inst 34848846 # number of ReadReq hits 766system.cpu0.icache.ReadReq_hits::total 34848846 # number of ReadReq hits 767system.cpu0.icache.demand_hits::cpu0.inst 34848846 # number of demand (read+write) hits 768system.cpu0.icache.demand_hits::total 34848846 # number of demand (read+write) hits 769system.cpu0.icache.overall_hits::cpu0.inst 34848846 # number of overall hits 770system.cpu0.icache.overall_hits::total 34848846 # number of overall hits 771system.cpu0.icache.ReadReq_misses::cpu0.inst 1875793 # number of ReadReq misses 772system.cpu0.icache.ReadReq_misses::total 1875793 # number of ReadReq misses 773system.cpu0.icache.demand_misses::cpu0.inst 1875793 # number of demand (read+write) misses 774system.cpu0.icache.demand_misses::total 1875793 # number of demand (read+write) misses 775system.cpu0.icache.overall_misses::cpu0.inst 1875793 # number of overall misses 776system.cpu0.icache.overall_misses::total 1875793 # number of overall misses 777system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18730135500 # number of ReadReq miss cycles 778system.cpu0.icache.ReadReq_miss_latency::total 18730135500 # number of ReadReq miss cycles 779system.cpu0.icache.demand_miss_latency::cpu0.inst 18730135500 # number of demand (read+write) miss cycles 780system.cpu0.icache.demand_miss_latency::total 18730135500 # number of demand (read+write) miss cycles 781system.cpu0.icache.overall_miss_latency::cpu0.inst 18730135500 # number of overall miss cycles 782system.cpu0.icache.overall_miss_latency::total 18730135500 # number of overall miss cycles 783system.cpu0.icache.ReadReq_accesses::cpu0.inst 36724639 # number of ReadReq accesses(hits+misses) 784system.cpu0.icache.ReadReq_accesses::total 36724639 # number of ReadReq accesses(hits+misses) 785system.cpu0.icache.demand_accesses::cpu0.inst 36724639 # number of demand (read+write) accesses 786system.cpu0.icache.demand_accesses::total 36724639 # number of demand (read+write) accesses 787system.cpu0.icache.overall_accesses::cpu0.inst 36724639 # number of overall (read+write) accesses 788system.cpu0.icache.overall_accesses::total 36724639 # number of overall (read+write) accesses 789system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051077 # miss rate for ReadReq accesses 790system.cpu0.icache.ReadReq_miss_rate::total 0.051077 # miss rate for ReadReq accesses 791system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051077 # miss rate for demand accesses 792system.cpu0.icache.demand_miss_rate::total 0.051077 # miss rate for demand accesses 793system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051077 # miss rate for overall accesses 794system.cpu0.icache.overall_miss_rate::total 0.051077 # miss rate for overall accesses 795system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9985.182533 # average ReadReq miss latency 796system.cpu0.icache.ReadReq_avg_miss_latency::total 9985.182533 # average ReadReq miss latency 797system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9985.182533 # average overall miss latency 798system.cpu0.icache.demand_avg_miss_latency::total 9985.182533 # average overall miss latency 799system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9985.182533 # average overall miss latency 800system.cpu0.icache.overall_avg_miss_latency::total 9985.182533 # average overall miss latency 801system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu0.icache.fast_writes 0 # number of fast writes performed 808system.cpu0.icache.cache_copies 0 # number of cache copies performed 809system.cpu0.icache.writebacks::writebacks 1875262 # number of writebacks 810system.cpu0.icache.writebacks::total 1875262 # number of writebacks 811system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1875793 # number of ReadReq MSHR misses 812system.cpu0.icache.ReadReq_mshr_misses::total 1875793 # number of ReadReq MSHR misses 813system.cpu0.icache.demand_mshr_misses::cpu0.inst 1875793 # number of demand (read+write) MSHR misses 814system.cpu0.icache.demand_mshr_misses::total 1875793 # number of demand (read+write) MSHR misses 815system.cpu0.icache.overall_mshr_misses::cpu0.inst 1875793 # number of overall MSHR misses 816system.cpu0.icache.overall_mshr_misses::total 1875793 # number of overall MSHR misses 817system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 818system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable 819system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 820system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses 821system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17792239500 # number of ReadReq MSHR miss cycles 822system.cpu0.icache.ReadReq_mshr_miss_latency::total 17792239500 # number of ReadReq MSHR miss cycles 823system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17792239500 # number of demand (read+write) MSHR miss cycles 824system.cpu0.icache.demand_mshr_miss_latency::total 17792239500 # number of demand (read+write) MSHR miss cycles 825system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17792239500 # number of overall MSHR miss cycles 826system.cpu0.icache.overall_mshr_miss_latency::total 17792239500 # number of overall MSHR miss cycles 827system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles 828system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles 830system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles 831system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for ReadReq accesses 832system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051077 # mshr miss rate for ReadReq accesses 833system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for demand accesses 834system.cpu0.icache.demand_mshr_miss_rate::total 0.051077 # mshr miss rate for demand accesses 835system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for overall accesses 836system.cpu0.icache.overall_mshr_miss_rate::total 0.051077 # mshr miss rate for overall accesses 837system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average ReadReq mshr miss latency 838system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9485.182800 # average ReadReq mshr miss latency 839system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency 840system.cpu0.icache.demand_avg_mshr_miss_latency::total 9485.182800 # average overall mshr miss latency 841system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency 842system.cpu0.icache.overall_avg_mshr_miss_latency::total 9485.182800 # average overall mshr miss latency 843system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency 844system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency 845system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency 846system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency 847system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 848system.cpu0.l2cache.prefetcher.num_hwpf_issued 1759572 # number of hwpf issued 849system.cpu0.l2cache.prefetcher.pfIdentified 1759695 # number of prefetch candidates identified 850system.cpu0.l2cache.prefetcher.pfBufferHit 108 # number of redundant prefetches already in prefetch queue 851system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 852system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 853system.cpu0.l2cache.prefetcher.pfSpanPage 223393 # number of prefetches not generated due to page crossing 854system.cpu0.l2cache.tags.replacements 281012 # number of replacements 855system.cpu0.l2cache.tags.tagsinuse 16001.828165 # Cycle average of tags in use 856system.cpu0.l2cache.tags.total_refs 4472083 # Total number of references to valid blocks. 857system.cpu0.l2cache.tags.sampled_refs 297133 # Sample count of references to valid blocks. 858system.cpu0.l2cache.tags.avg_refs 15.050779 # Average number of references to valid blocks. 859system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 860system.cpu0.l2cache.tags.occ_blocks::writebacks 15118.800161 # Average occupied blocks per requestor 861system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.428887 # Average occupied blocks per requestor 862system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070691 # Average occupied blocks per requestor 863system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 838.528425 # Average occupied blocks per requestor 864system.cpu0.l2cache.tags.occ_percent::writebacks 0.922778 # Average percentage of cache occupancy 865system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002712 # Average percentage of cache occupancy 866system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 867system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051180 # Average percentage of cache occupancy 868system.cpu0.l2cache.tags.occ_percent::total 0.976674 # Average percentage of cache occupancy 869system.cpu0.l2cache.tags.occ_task_id_blocks::1022 954 # Occupied blocks per task id 870system.cpu0.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id 871system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15150 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id 874system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 395 # Occupied blocks per task id 875system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 262 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id 881system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4006 # Occupied blocks per task id 882system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8013 # Occupied blocks per task id 883system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2701 # Occupied blocks per task id 884system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058228 # Percentage of cache occupancy per task id 885system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 886system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924683 # Percentage of cache occupancy per task id 887system.cpu0.l2cache.tags.tag_accesses 85407529 # Number of tag accesses 888system.cpu0.l2cache.tags.data_accesses 85407529 # Number of data accesses 889system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81193 # number of ReadReq hits 890system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4894 # number of ReadReq hits 891system.cpu0.l2cache.ReadReq_hits::total 86087 # number of ReadReq hits 892system.cpu0.l2cache.WritebackDirty_hits::writebacks 464150 # number of WritebackDirty hits 893system.cpu0.l2cache.WritebackDirty_hits::total 464150 # number of WritebackDirty hits 894system.cpu0.l2cache.WritebackClean_hits::writebacks 2050484 # number of WritebackClean hits 895system.cpu0.l2cache.WritebackClean_hits::total 2050484 # number of WritebackClean hits 896system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210006 # number of ReadExReq hits 897system.cpu0.l2cache.ReadExReq_hits::total 210006 # number of ReadExReq hits 898system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1815550 # number of ReadCleanReq hits 899system.cpu0.l2cache.ReadCleanReq_hits::total 1815550 # number of ReadCleanReq hits 900system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 378161 # number of ReadSharedReq hits 901system.cpu0.l2cache.ReadSharedReq_hits::total 378161 # number of ReadSharedReq hits 902system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 81193 # number of demand (read+write) hits 903system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4894 # number of demand (read+write) hits 904system.cpu0.l2cache.demand_hits::cpu0.inst 1815550 # number of demand (read+write) hits 905system.cpu0.l2cache.demand_hits::cpu0.data 588167 # number of demand (read+write) hits 906system.cpu0.l2cache.demand_hits::total 2489804 # number of demand (read+write) hits 907system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 81193 # number of overall hits 908system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4894 # number of overall hits 909system.cpu0.l2cache.overall_hits::cpu0.inst 1815550 # number of overall hits 910system.cpu0.l2cache.overall_hits::cpu0.data 588167 # number of overall hits 911system.cpu0.l2cache.overall_hits::total 2489804 # number of overall hits 912system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 786 # number of ReadReq misses 913system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 116 # number of ReadReq misses 914system.cpu0.l2cache.ReadReq_misses::total 902 # number of ReadReq misses 915system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57057 # number of UpgradeReq misses 916system.cpu0.l2cache.UpgradeReq_misses::total 57057 # number of UpgradeReq misses 917system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 21447 # number of SCUpgradeReq misses 918system.cpu0.l2cache.SCUpgradeReq_misses::total 21447 # number of SCUpgradeReq misses 919system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 920system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 921system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46792 # number of ReadExReq misses 922system.cpu0.l2cache.ReadExReq_misses::total 46792 # number of ReadExReq misses 923system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 60243 # number of ReadCleanReq misses 924system.cpu0.l2cache.ReadCleanReq_misses::total 60243 # number of ReadCleanReq misses 925system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100692 # number of ReadSharedReq misses 926system.cpu0.l2cache.ReadSharedReq_misses::total 100692 # number of ReadSharedReq misses 927system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 786 # number of demand (read+write) misses 928system.cpu0.l2cache.demand_misses::cpu0.itb.walker 116 # number of demand (read+write) misses 929system.cpu0.l2cache.demand_misses::cpu0.inst 60243 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::cpu0.data 147484 # number of demand (read+write) misses 931system.cpu0.l2cache.demand_misses::total 208629 # number of demand (read+write) misses 932system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 786 # number of overall misses 933system.cpu0.l2cache.overall_misses::cpu0.itb.walker 116 # number of overall misses 934system.cpu0.l2cache.overall_misses::cpu0.inst 60243 # number of overall misses 935system.cpu0.l2cache.overall_misses::cpu0.data 147484 # number of overall misses 936system.cpu0.l2cache.overall_misses::total 208629 # number of overall misses 937system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 33583500 # number of ReadReq miss cycles 938system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2701500 # number of ReadReq miss cycles 939system.cpu0.l2cache.ReadReq_miss_latency::total 36285000 # number of ReadReq miss cycles 940system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 167791500 # number of UpgradeReq miss cycles 941system.cpu0.l2cache.UpgradeReq_miss_latency::total 167791500 # number of UpgradeReq miss cycles 942system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 54595000 # number of SCUpgradeReq miss cycles 943system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 54595000 # number of SCUpgradeReq miss cycles 944system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 461999 # number of SCUpgradeFailReq miss cycles 945system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 461999 # number of SCUpgradeFailReq miss cycles 946system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3075348000 # number of ReadExReq miss cycles 947system.cpu0.l2cache.ReadExReq_miss_latency::total 3075348000 # number of ReadExReq miss cycles 948system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3960975500 # number of ReadCleanReq miss cycles 949system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3960975500 # number of ReadCleanReq miss cycles 950system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3384347998 # number of ReadSharedReq miss cycles 951system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3384347998 # number of ReadSharedReq miss cycles 952system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 33583500 # number of demand (read+write) miss cycles 953system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2701500 # number of demand (read+write) miss cycles 954system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3960975500 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.demand_miss_latency::cpu0.data 6459695998 # number of demand (read+write) miss cycles 956system.cpu0.l2cache.demand_miss_latency::total 10456956498 # number of demand (read+write) miss cycles 957system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 33583500 # number of overall miss cycles 958system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2701500 # number of overall miss cycles 959system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3960975500 # number of overall miss cycles 960system.cpu0.l2cache.overall_miss_latency::cpu0.data 6459695998 # number of overall miss cycles 961system.cpu0.l2cache.overall_miss_latency::total 10456956498 # number of overall miss cycles 962system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81979 # number of ReadReq accesses(hits+misses) 963system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5010 # number of ReadReq accesses(hits+misses) 964system.cpu0.l2cache.ReadReq_accesses::total 86989 # number of ReadReq accesses(hits+misses) 965system.cpu0.l2cache.WritebackDirty_accesses::writebacks 464150 # number of WritebackDirty accesses(hits+misses) 966system.cpu0.l2cache.WritebackDirty_accesses::total 464150 # number of WritebackDirty accesses(hits+misses) 967system.cpu0.l2cache.WritebackClean_accesses::writebacks 2050484 # number of WritebackClean accesses(hits+misses) 968system.cpu0.l2cache.WritebackClean_accesses::total 2050484 # number of WritebackClean accesses(hits+misses) 969system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 57057 # number of UpgradeReq accesses(hits+misses) 970system.cpu0.l2cache.UpgradeReq_accesses::total 57057 # number of UpgradeReq accesses(hits+misses) 971system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21447 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu0.l2cache.SCUpgradeReq_accesses::total 21447 # number of SCUpgradeReq accesses(hits+misses) 973system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 974system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 975system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256798 # number of ReadExReq accesses(hits+misses) 976system.cpu0.l2cache.ReadExReq_accesses::total 256798 # number of ReadExReq accesses(hits+misses) 977system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1875793 # number of ReadCleanReq accesses(hits+misses) 978system.cpu0.l2cache.ReadCleanReq_accesses::total 1875793 # number of ReadCleanReq accesses(hits+misses) 979system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 478853 # number of ReadSharedReq accesses(hits+misses) 980system.cpu0.l2cache.ReadSharedReq_accesses::total 478853 # number of ReadSharedReq accesses(hits+misses) 981system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81979 # number of demand (read+write) accesses 982system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5010 # number of demand (read+write) accesses 983system.cpu0.l2cache.demand_accesses::cpu0.inst 1875793 # number of demand (read+write) accesses 984system.cpu0.l2cache.demand_accesses::cpu0.data 735651 # number of demand (read+write) accesses 985system.cpu0.l2cache.demand_accesses::total 2698433 # number of demand (read+write) accesses 986system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81979 # number of overall (read+write) accesses 987system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5010 # number of overall (read+write) accesses 988system.cpu0.l2cache.overall_accesses::cpu0.inst 1875793 # number of overall (read+write) accesses 989system.cpu0.l2cache.overall_accesses::cpu0.data 735651 # number of overall (read+write) accesses 990system.cpu0.l2cache.overall_accesses::total 2698433 # number of overall (read+write) accesses 991system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009588 # miss rate for ReadReq accesses 992system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.023154 # miss rate for ReadReq accesses 993system.cpu0.l2cache.ReadReq_miss_rate::total 0.010369 # miss rate for ReadReq accesses 994system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 995system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 996system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 997system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 998system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 999system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1000system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.182213 # miss rate for ReadExReq accesses 1001system.cpu0.l2cache.ReadExReq_miss_rate::total 0.182213 # miss rate for ReadExReq accesses 1002system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.032116 # miss rate for ReadCleanReq accesses 1003system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.032116 # miss rate for ReadCleanReq accesses 1004system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.210277 # miss rate for ReadSharedReq accesses 1005system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.210277 # miss rate for ReadSharedReq accesses 1006system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009588 # miss rate for demand accesses 1007system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.023154 # miss rate for demand accesses 1008system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.032116 # miss rate for demand accesses 1009system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.200481 # miss rate for demand accesses 1010system.cpu0.l2cache.demand_miss_rate::total 0.077315 # miss rate for demand accesses 1011system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009588 # miss rate for overall accesses 1012system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.023154 # miss rate for overall accesses 1013system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.032116 # miss rate for overall accesses 1014system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.200481 # miss rate for overall accesses 1015system.cpu0.l2cache.overall_miss_rate::total 0.077315 # miss rate for overall accesses 1016system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42727.099237 # average ReadReq miss latency 1017system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23288.793103 # average ReadReq miss latency 1018system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40227.272727 # average ReadReq miss latency 1019system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2940.769757 # average UpgradeReq miss latency 1020system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2940.769757 # average UpgradeReq miss latency 1021system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2545.577470 # average SCUpgradeReq miss latency 1022system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2545.577470 # average SCUpgradeReq miss latency 1023system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 230999.500000 # average SCUpgradeFailReq miss latency 1024system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 230999.500000 # average SCUpgradeFailReq miss latency 1025system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65723.798940 # average ReadExReq miss latency 1026system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65723.798940 # average ReadExReq miss latency 1027system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 65749.970951 # average ReadCleanReq miss latency 1028system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 65749.970951 # average ReadCleanReq miss latency 1029system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33610.892603 # average ReadSharedReq miss latency 1030system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33610.892603 # average ReadSharedReq miss latency 1031system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42727.099237 # average overall miss latency 1032system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23288.793103 # average overall miss latency 1033system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 65749.970951 # average overall miss latency 1034system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43799.300250 # average overall miss latency 1035system.cpu0.l2cache.demand_avg_miss_latency::total 50122.257682 # average overall miss latency 1036system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42727.099237 # average overall miss latency 1037system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23288.793103 # average overall miss latency 1038system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 65749.970951 # average overall miss latency 1039system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43799.300250 # average overall miss latency 1040system.cpu0.l2cache.overall_avg_miss_latency::total 50122.257682 # average overall miss latency 1041system.cpu0.l2cache.blocked_cycles::no_mshrs 37 # number of cycles access was blocked 1042system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1043system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1044system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1045system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 18.500000 # average number of cycles each access was blocked 1046system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1047system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1048system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1049system.cpu0.l2cache.writebacks::writebacks 227499 # number of writebacks 1050system.cpu0.l2cache.writebacks::total 227499 # number of writebacks 1051system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4987 # number of ReadExReq MSHR hits 1052system.cpu0.l2cache.ReadExReq_mshr_hits::total 4987 # number of ReadExReq MSHR hits 1053system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 68 # number of ReadCleanReq MSHR hits 1054system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 68 # number of ReadCleanReq MSHR hits 1055system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 538 # number of ReadSharedReq MSHR hits 1056system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 538 # number of ReadSharedReq MSHR hits 1057system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 68 # number of demand (read+write) MSHR hits 1058system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5525 # number of demand (read+write) MSHR hits 1059system.cpu0.l2cache.demand_mshr_hits::total 5593 # number of demand (read+write) MSHR hits 1060system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 68 # number of overall MSHR hits 1061system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5525 # number of overall MSHR hits 1062system.cpu0.l2cache.overall_mshr_hits::total 5593 # number of overall MSHR hits 1063system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 786 # number of ReadReq MSHR misses 1064system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 116 # number of ReadReq MSHR misses 1065system.cpu0.l2cache.ReadReq_mshr_misses::total 902 # number of ReadReq MSHR misses 1066system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246380 # number of HardPFReq MSHR misses 1067system.cpu0.l2cache.HardPFReq_mshr_misses::total 246380 # number of HardPFReq MSHR misses 1068system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 57057 # number of UpgradeReq MSHR misses 1069system.cpu0.l2cache.UpgradeReq_mshr_misses::total 57057 # number of UpgradeReq MSHR misses 1070system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 21447 # number of SCUpgradeReq MSHR misses 1071system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 21447 # number of SCUpgradeReq MSHR misses 1072system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1073system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1074system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41805 # number of ReadExReq MSHR misses 1075system.cpu0.l2cache.ReadExReq_mshr_misses::total 41805 # number of ReadExReq MSHR misses 1076system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 60175 # number of ReadCleanReq MSHR misses 1077system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 60175 # number of ReadCleanReq MSHR misses 1078system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100154 # number of ReadSharedReq MSHR misses 1079system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100154 # number of ReadSharedReq MSHR misses 1080system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 786 # number of demand (read+write) MSHR misses 1081system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 116 # number of demand (read+write) MSHR misses 1082system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 60175 # number of demand (read+write) MSHR misses 1083system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141959 # number of demand (read+write) MSHR misses 1084system.cpu0.l2cache.demand_mshr_misses::total 203036 # number of demand (read+write) MSHR misses 1085system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 786 # number of overall MSHR misses 1086system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 116 # number of overall MSHR misses 1087system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 60175 # number of overall MSHR misses 1088system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141959 # number of overall MSHR misses 1089system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246380 # number of overall MSHR misses 1090system.cpu0.l2cache.overall_mshr_misses::total 449416 # number of overall MSHR misses 1091system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 1092system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17966 # number of ReadReq MSHR uncacheable 1093system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21883 # number of ReadReq MSHR uncacheable 1094system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16715 # number of WriteReq MSHR uncacheable 1095system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16715 # number of WriteReq MSHR uncacheable 1096system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 1097system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34681 # number of overall MSHR uncacheable misses 1098system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38598 # number of overall MSHR uncacheable misses 1099system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 28867500 # number of ReadReq MSHR miss cycles 1100system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2005500 # number of ReadReq MSHR miss cycles 1101system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 30873000 # number of ReadReq MSHR miss cycles 1102system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20196086911 # number of HardPFReq MSHR miss cycles 1103system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20196086911 # number of HardPFReq MSHR miss cycles 1104system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1443990500 # number of UpgradeReq MSHR miss cycles 1105system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1443990500 # number of UpgradeReq MSHR miss cycles 1106system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 389167000 # number of SCUpgradeReq MSHR miss cycles 1107system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 389167000 # number of SCUpgradeReq MSHR miss cycles 1108system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 401999 # number of SCUpgradeFailReq MSHR miss cycles 1109system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 401999 # number of SCUpgradeFailReq MSHR miss cycles 1110system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2354970000 # number of ReadExReq MSHR miss cycles 1111system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2354970000 # number of ReadExReq MSHR miss cycles 1112system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3597641500 # number of ReadCleanReq MSHR miss cycles 1113system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3597641500 # number of ReadCleanReq MSHR miss cycles 1114system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2754037498 # number of ReadSharedReq MSHR miss cycles 1115system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2754037498 # number of ReadSharedReq MSHR miss cycles 1116system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 28867500 # number of demand (read+write) MSHR miss cycles 1117system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2005500 # number of demand (read+write) MSHR miss cycles 1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3597641500 # number of demand (read+write) MSHR miss cycles 1119system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5109007498 # number of demand (read+write) MSHR miss cycles 1120system.cpu0.l2cache.demand_mshr_miss_latency::total 8737521998 # number of demand (read+write) MSHR miss cycles 1121system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 28867500 # number of overall MSHR miss cycles 1122system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2005500 # number of overall MSHR miss cycles 1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3597641500 # number of overall MSHR miss cycles 1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5109007498 # number of overall MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20196086911 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.overall_mshr_miss_latency::total 28933608909 # number of overall MSHR miss cycles 1127system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles 1128system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3820755500 # number of ReadReq MSHR uncacheable cycles 1129system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4346775500 # number of ReadReq MSHR uncacheable cycles 1130system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2953338000 # number of WriteReq MSHR uncacheable cycles 1131system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2953338000 # number of WriteReq MSHR uncacheable cycles 1132system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles 1133system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6774093500 # number of overall MSHR uncacheable cycles 1134system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7300113500 # number of overall MSHR uncacheable cycles 1135system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for ReadReq accesses 1136system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for ReadReq accesses 1137system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010369 # mshr miss rate for ReadReq accesses 1138system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1139system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1140system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1141system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1142system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1143system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1144system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1145system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1146system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162793 # mshr miss rate for ReadExReq accesses 1147system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162793 # mshr miss rate for ReadExReq accesses 1148system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for ReadCleanReq accesses 1149system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032080 # mshr miss rate for ReadCleanReq accesses 1150system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209154 # mshr miss rate for ReadSharedReq accesses 1151system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209154 # mshr miss rate for ReadSharedReq accesses 1152system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for demand accesses 1153system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for demand accesses 1154system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for demand accesses 1155system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for demand accesses 1156system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075242 # mshr miss rate for demand accesses 1157system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for overall accesses 1158system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for overall accesses 1159system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for overall accesses 1160system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for overall accesses 1161system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1162system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166547 # mshr miss rate for overall accesses 1163system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average ReadReq mshr miss latency 1164system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average ReadReq mshr miss latency 1165system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34227.272727 # average ReadReq mshr miss latency 1166system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average HardPFReq mshr miss latency 1167system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 81971.291951 # average HardPFReq mshr miss latency 1168system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25307.858808 # average UpgradeReq mshr miss latency 1169system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25307.858808 # average UpgradeReq mshr miss latency 1170system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18145.521518 # average SCUpgradeReq mshr miss latency 1171system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18145.521518 # average SCUpgradeReq mshr miss latency 1172system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 200999.500000 # average SCUpgradeFailReq mshr miss latency 1173system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 200999.500000 # average SCUpgradeFailReq mshr miss latency 1174system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56332.256907 # average ReadExReq mshr miss latency 1175system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56332.256907 # average ReadExReq mshr miss latency 1176system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average ReadCleanReq mshr miss latency 1177system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 59786.314915 # average ReadCleanReq mshr miss latency 1178system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27498.028017 # average ReadSharedReq mshr miss latency 1179system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27498.028017 # average ReadSharedReq mshr miss latency 1180system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency 1181system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency 1182system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency 1183system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency 1184system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43034.348579 # average overall mshr miss latency 1185system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency 1186system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency 1187system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency 1188system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency 1189system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average overall mshr miss latency 1190system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64380.460217 # average overall mshr miss latency 1191system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency 1192system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212665.896694 # average ReadReq mshr uncacheable latency 1193system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198637.092720 # average ReadReq mshr uncacheable latency 1194system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176687.885133 # average WriteReq mshr uncacheable latency 1195system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176687.885133 # average WriteReq mshr uncacheable latency 1196system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency 1197system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 195325.783570 # average overall mshr uncacheable latency 1198system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 189131.910980 # average overall mshr uncacheable latency 1199system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1200system.cpu0.toL2Bus.snoop_filter.tot_requests 5267322 # Total number of requests made to the snoop filter. 1201system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2655927 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1202system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 41328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1203system.cpu0.toL2Bus.snoop_filter.tot_snoops 334158 # Total number of snoops made to the snoop filter. 1204system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 329304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1205system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4854 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1206system.cpu0.toL2Bus.trans_dist::ReadReq 119336 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::ReadResp 2522924 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::WriteReq 16715 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::WriteResp 16715 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::WritebackDirty 692222 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::WritebackClean 2091812 # Transaction distribution 1212system.cpu0.toL2Bus.trans_dist::CleanEvict 222834 # Transaction distribution 1213system.cpu0.toL2Bus.trans_dist::HardPFReq 309300 # Transaction distribution 1214system.cpu0.toL2Bus.trans_dist::UpgradeReq 91686 # Transaction distribution 1215system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43805 # Transaction distribution 1216system.cpu0.toL2Bus.trans_dist::UpgradeResp 115698 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::ReadExReq 274549 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::ReadExResp 271267 # Transaction distribution 1221system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1875793 # Transaction distribution 1222system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569005 # Transaction distribution 1223system.cpu0.toL2Bus.trans_dist::InvalidateReq 3104 # Transaction distribution 1224system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5634681 # Packet count per connected master and slave (bytes) 1225system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2479031 # Packet count per connected master and slave (bytes) 1226system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12447 # Packet count per connected master and slave (bytes) 1227system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171956 # Packet count per connected master and slave (bytes) 1228system.cpu0.toL2Bus.pkt_count::total 8298115 # Packet count per connected master and slave (bytes) 1229system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 240318144 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94807159 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20040 # Cumulative packet size per connected master and slave (bytes) 1232system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327916 # Cumulative packet size per connected master and slave (bytes) 1233system.cpu0.toL2Bus.pkt_size::total 335473259 # Cumulative packet size per connected master and slave (bytes) 1234system.cpu0.toL2Bus.snoops 1039321 # Total snoops (count) 1235system.cpu0.toL2Bus.snoop_fanout::samples 3754204 # Request fanout histogram 1236system.cpu0.toL2Bus.snoop_fanout::mean 0.107024 # Request fanout histogram 1237system.cpu0.toL2Bus.snoop_fanout::stdev 0.313298 # Request fanout histogram 1238system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1239system.cpu0.toL2Bus.snoop_fanout::0 3357269 89.43% 89.43% # Request fanout histogram 1240system.cpu0.toL2Bus.snoop_fanout::1 392081 10.44% 99.87% # Request fanout histogram 1241system.cpu0.toL2Bus.snoop_fanout::2 4854 0.13% 100.00% # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1243system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1244system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1245system.cpu0.toL2Bus.snoop_fanout::total 3754204 # Request fanout histogram 1246system.cpu0.toL2Bus.reqLayer0.occupancy 5255285493 # Layer occupancy (ticks) 1247system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1248system.cpu0.toL2Bus.snoopLayer0.occupancy 113846370 # Layer occupancy (ticks) 1249system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1250system.cpu0.toL2Bus.respLayer0.occupancy 2820178266 # Layer occupancy (ticks) 1251system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1252system.cpu0.toL2Bus.respLayer1.occupancy 1169961199 # Layer occupancy (ticks) 1253system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1254system.cpu0.toL2Bus.respLayer2.occupancy 7446481 # Layer occupancy (ticks) 1255system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1256system.cpu0.toL2Bus.respLayer3.occupancy 90008437 # Layer occupancy (ticks) 1257system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1258system.cpu1.branchPred.lookups 20449244 # Number of BP lookups 1259system.cpu1.branchPred.condPredicted 7039055 # Number of conditional branches predicted 1260system.cpu1.branchPred.condIncorrect 963225 # Number of conditional branches incorrect 1261system.cpu1.branchPred.BTBLookups 10410340 # Number of BTB lookups 1262system.cpu1.branchPred.BTBHits 7679577 # Number of BTB hits 1263system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1264system.cpu1.branchPred.BTBHitPct 73.768743 # BTB Hit Percentage 1265system.cpu1.branchPred.usedRAS 8836366 # Number of times the RAS was used to get a target. 1266system.cpu1.branchPred.RASInCorrect 692168 # Number of incorrect RAS predictions. 1267system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1274system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1275system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1276system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1277system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1278system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1279system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1280system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1281system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1282system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1283system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1284system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1285system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1286system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1287system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1288system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1289system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1290system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1291system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1292system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1293system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1294system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1295system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1296system.cpu1.dtb.walker.walks 30868 # Table walker walks requested 1297system.cpu1.dtb.walker.walksShort 30868 # Table walker walks initiated with short descriptors 1298system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23108 # Level at which table walker walks with short descriptors terminate 1299system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7760 # Level at which table walker walks with short descriptors terminate 1300system.cpu1.dtb.walker.walkWaitTime::samples 30868 # Table walker wait (enqueue to first request) latency 1301system.cpu1.dtb.walker.walkWaitTime::0 30868 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1302system.cpu1.dtb.walker.walkWaitTime::total 30868 # Table walker wait (enqueue to first request) latency 1303system.cpu1.dtb.walker.walkCompletionTime::samples 2696 # Table walker service (enqueue to completion) latency 1304system.cpu1.dtb.walker.walkCompletionTime::mean 11992.210682 # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::gmean 10915.827455 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::stdev 8355.113227 # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::0-16383 2479 91.95% 91.95% # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::16384-32767 196 7.27% 99.22% # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::32768-49151 12 0.45% 99.67% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.11% 99.78% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.11% 99.89% # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.11% 100.00% # Table walker service (enqueue to completion) latency 1313system.cpu1.dtb.walker.walkCompletionTime::total 2696 # Table walker service (enqueue to completion) latency 1314system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution 1315system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution 1316system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution 1317system.cpu1.dtb.walker.walkPageSizes::4K 1974 73.22% 73.22% # Table walker page sizes translated 1318system.cpu1.dtb.walker.walkPageSizes::1M 722 26.78% 100.00% # Table walker page sizes translated 1319system.cpu1.dtb.walker.walkPageSizes::total 2696 # Table walker page sizes translated 1320system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30868 # Table walker requests started/completed, data/inst 1321system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1322system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30868 # Table walker requests started/completed, data/inst 1323system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2696 # Table walker requests started/completed, data/inst 1324system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2696 # Table walker requests started/completed, data/inst 1326system.cpu1.dtb.walker.walkRequestOrigin::total 33564 # Table walker requests started/completed, data/inst 1327system.cpu1.dtb.inst_hits 0 # ITB inst hits 1328system.cpu1.dtb.inst_misses 0 # ITB inst misses 1329system.cpu1.dtb.read_hits 12117944 # DTB read hits 1330system.cpu1.dtb.read_misses 28100 # DTB read misses 1331system.cpu1.dtb.write_hits 7719144 # DTB write hits 1332system.cpu1.dtb.write_misses 2768 # DTB write misses 1333system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1334system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1335system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1336system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1337system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB 1338system.cpu1.dtb.align_faults 330 # Number of TLB faults due to alignment restrictions 1339system.cpu1.dtb.prefetch_faults 545 # Number of TLB faults due to prefetch 1340system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1341system.cpu1.dtb.perms_faults 280 # Number of TLB faults due to permissions restrictions 1342system.cpu1.dtb.read_accesses 12146044 # DTB read accesses 1343system.cpu1.dtb.write_accesses 7721912 # DTB write accesses 1344system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1345system.cpu1.dtb.hits 19837088 # DTB hits 1346system.cpu1.dtb.misses 30868 # DTB misses 1347system.cpu1.dtb.accesses 19867956 # DTB accesses 1348system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1349system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1355system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1356system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1357system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1358system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1359system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1360system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1361system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1362system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1363system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1364system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1365system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1366system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1367system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1368system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1369system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1370system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1371system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1372system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1373system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1374system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1375system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1376system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1377system.cpu1.itb.walker.walks 2320 # Table walker walks requested 1378system.cpu1.itb.walker.walksShort 2320 # Table walker walks initiated with short descriptors 1379system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate 1380system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2136 # Level at which table walker walks with short descriptors terminate 1381system.cpu1.itb.walker.walkWaitTime::samples 2320 # Table walker wait (enqueue to first request) latency 1382system.cpu1.itb.walker.walkWaitTime::0 2320 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1383system.cpu1.itb.walker.walkWaitTime::total 2320 # Table walker wait (enqueue to first request) latency 1384system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency 1385system.cpu1.itb.walker.walkCompletionTime::mean 12081.032947 # Table walker service (enqueue to completion) latency 1386system.cpu1.itb.walker.walkCompletionTime::gmean 11456.275098 # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::stdev 4603.593303 # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::4096-8191 188 16.74% 16.74% # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::8192-12287 645 57.44% 74.18% # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::12288-16383 209 18.61% 92.79% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.36% 97.15% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 97.24% # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.58% # Table walker service (enqueue to completion) latency 1394system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.27% 98.84% # Table walker service (enqueue to completion) latency 1395system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 98.93% # Table walker service (enqueue to completion) latency 1396system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.89% 99.82% # Table walker service (enqueue to completion) latency 1397system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1398system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1399system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency 1400system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution 1401system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution 1402system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution 1403system.cpu1.itb.walker.walkPageSizes::4K 953 84.86% 84.86% # Table walker page sizes translated 1404system.cpu1.itb.walker.walkPageSizes::1M 170 15.14% 100.00% # Table walker page sizes translated 1405system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated 1406system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1407system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2320 # Table walker requests started/completed, data/inst 1408system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2320 # Table walker requests started/completed, data/inst 1409system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1410system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst 1411system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst 1412system.cpu1.itb.walker.walkRequestOrigin::total 3443 # Table walker requests started/completed, data/inst 1413system.cpu1.itb.inst_hits 41835871 # ITB inst hits 1414system.cpu1.itb.inst_misses 2320 # ITB inst misses 1415system.cpu1.itb.read_hits 0 # DTB read hits 1416system.cpu1.itb.read_misses 0 # DTB read misses 1417system.cpu1.itb.write_hits 0 # DTB write hits 1418system.cpu1.itb.write_misses 0 # DTB write misses 1419system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1420system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1421system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1422system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1423system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB 1424system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1425system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1426system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1427system.cpu1.itb.perms_faults 1837 # Number of TLB faults due to permissions restrictions 1428system.cpu1.itb.read_accesses 0 # DTB read accesses 1429system.cpu1.itb.write_accesses 0 # DTB write accesses 1430system.cpu1.itb.inst_accesses 41838191 # ITB inst accesses 1431system.cpu1.itb.hits 41835871 # DTB hits 1432system.cpu1.itb.misses 2320 # DTB misses 1433system.cpu1.itb.accesses 41838191 # DTB accesses 1434system.cpu1.numCycles 128464441 # number of cpu cycles simulated 1435system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1436system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1437system.cpu1.committedInsts 51881050 # Number of instructions committed 1438system.cpu1.committedOps 63376562 # Number of ops (including micro ops) committed 1439system.cpu1.discardedOps 5336781 # Number of ops (including micro ops) which were discarded before commit 1440system.cpu1.numFetchSuspends 2726 # Number of times Execute suspended instruction fetching 1441system.cpu1.quiesceCycles 5169132523 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1442system.cpu1.cpi 2.476134 # CPI: cycles per instruction 1443system.cpu1.ipc 0.403855 # IPC: instructions per cycle 1444system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1445system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed 1446system.cpu1.tickCycles 105981069 # Number of cycles that the object actually ticked 1447system.cpu1.idleCycles 22483372 # Total number of cycles that the object has spent stopped 1448system.cpu1.dcache.tags.replacements 234073 # number of replacements 1449system.cpu1.dcache.tags.tagsinuse 481.612157 # Cycle average of tags in use 1450system.cpu1.dcache.tags.total_refs 19315800 # Total number of references to valid blocks. 1451system.cpu1.dcache.tags.sampled_refs 234411 # Sample count of references to valid blocks. 1452system.cpu1.dcache.tags.avg_refs 82.401423 # Average number of references to valid blocks. 1453system.cpu1.dcache.tags.warmup_cycle 91649523000 # Cycle when the warmup percentage was hit. 1454system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.612157 # Average occupied blocks per requestor 1455system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940649 # Average percentage of cache occupancy 1456system.cpu1.dcache.tags.occ_percent::total 0.940649 # Average percentage of cache occupancy 1457system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id 1458system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id 1459system.cpu1.dcache.tags.age_task_id_blocks_1024::3 43 # Occupied blocks per task id 1460system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id 1461system.cpu1.dcache.tags.tag_accesses 39692249 # Number of tag accesses 1462system.cpu1.dcache.tags.data_accesses 39692249 # Number of data accesses 1463system.cpu1.dcache.ReadReq_hits::cpu1.data 11657958 # number of ReadReq hits 1464system.cpu1.dcache.ReadReq_hits::total 11657958 # number of ReadReq hits 1465system.cpu1.dcache.WriteReq_hits::cpu1.data 7379701 # number of WriteReq hits 1466system.cpu1.dcache.WriteReq_hits::total 7379701 # number of WriteReq hits 1467system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66326 # number of SoftPFReq hits 1468system.cpu1.dcache.SoftPFReq_hits::total 66326 # number of SoftPFReq hits 1469system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88715 # number of LoadLockedReq hits 1470system.cpu1.dcache.LoadLockedReq_hits::total 88715 # number of LoadLockedReq hits 1471system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80616 # number of StoreCondReq hits 1472system.cpu1.dcache.StoreCondReq_hits::total 80616 # number of StoreCondReq hits 1473system.cpu1.dcache.demand_hits::cpu1.data 19037659 # number of demand (read+write) hits 1474system.cpu1.dcache.demand_hits::total 19037659 # number of demand (read+write) hits 1475system.cpu1.dcache.overall_hits::cpu1.data 19103985 # number of overall hits 1476system.cpu1.dcache.overall_hits::total 19103985 # number of overall hits 1477system.cpu1.dcache.ReadReq_misses::cpu1.data 186675 # number of ReadReq misses 1478system.cpu1.dcache.ReadReq_misses::total 186675 # number of ReadReq misses 1479system.cpu1.dcache.WriteReq_misses::cpu1.data 168872 # number of WriteReq misses 1480system.cpu1.dcache.WriteReq_misses::total 168872 # number of WriteReq misses 1481system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35031 # number of SoftPFReq misses 1482system.cpu1.dcache.SoftPFReq_misses::total 35031 # number of SoftPFReq misses 1483system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17765 # number of LoadLockedReq misses 1484system.cpu1.dcache.LoadLockedReq_misses::total 17765 # number of LoadLockedReq misses 1485system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23562 # number of StoreCondReq misses 1486system.cpu1.dcache.StoreCondReq_misses::total 23562 # number of StoreCondReq misses 1487system.cpu1.dcache.demand_misses::cpu1.data 355547 # number of demand (read+write) misses 1488system.cpu1.dcache.demand_misses::total 355547 # number of demand (read+write) misses 1489system.cpu1.dcache.overall_misses::cpu1.data 390578 # number of overall misses 1490system.cpu1.dcache.overall_misses::total 390578 # number of overall misses 1491system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2934466500 # number of ReadReq miss cycles 1492system.cpu1.dcache.ReadReq_miss_latency::total 2934466500 # number of ReadReq miss cycles 1493system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5329870000 # number of WriteReq miss cycles 1494system.cpu1.dcache.WriteReq_miss_latency::total 5329870000 # number of WriteReq miss cycles 1495system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 334697000 # number of LoadLockedReq miss cycles 1496system.cpu1.dcache.LoadLockedReq_miss_latency::total 334697000 # number of LoadLockedReq miss cycles 1497system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633629500 # number of StoreCondReq miss cycles 1498system.cpu1.dcache.StoreCondReq_miss_latency::total 633629500 # number of StoreCondReq miss cycles 1499system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 219500 # number of StoreCondFailReq miss cycles 1500system.cpu1.dcache.StoreCondFailReq_miss_latency::total 219500 # number of StoreCondFailReq miss cycles 1501system.cpu1.dcache.demand_miss_latency::cpu1.data 8264336500 # number of demand (read+write) miss cycles 1502system.cpu1.dcache.demand_miss_latency::total 8264336500 # number of demand (read+write) miss cycles 1503system.cpu1.dcache.overall_miss_latency::cpu1.data 8264336500 # number of overall miss cycles 1504system.cpu1.dcache.overall_miss_latency::total 8264336500 # number of overall miss cycles 1505system.cpu1.dcache.ReadReq_accesses::cpu1.data 11844633 # number of ReadReq accesses(hits+misses) 1506system.cpu1.dcache.ReadReq_accesses::total 11844633 # number of ReadReq accesses(hits+misses) 1507system.cpu1.dcache.WriteReq_accesses::cpu1.data 7548573 # number of WriteReq accesses(hits+misses) 1508system.cpu1.dcache.WriteReq_accesses::total 7548573 # number of WriteReq accesses(hits+misses) 1509system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101357 # number of SoftPFReq accesses(hits+misses) 1510system.cpu1.dcache.SoftPFReq_accesses::total 101357 # number of SoftPFReq accesses(hits+misses) 1511system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106480 # number of LoadLockedReq accesses(hits+misses) 1512system.cpu1.dcache.LoadLockedReq_accesses::total 106480 # number of LoadLockedReq accesses(hits+misses) 1513system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104178 # number of StoreCondReq accesses(hits+misses) 1514system.cpu1.dcache.StoreCondReq_accesses::total 104178 # number of StoreCondReq accesses(hits+misses) 1515system.cpu1.dcache.demand_accesses::cpu1.data 19393206 # number of demand (read+write) accesses 1516system.cpu1.dcache.demand_accesses::total 19393206 # number of demand (read+write) accesses 1517system.cpu1.dcache.overall_accesses::cpu1.data 19494563 # number of overall (read+write) accesses 1518system.cpu1.dcache.overall_accesses::total 19494563 # number of overall (read+write) accesses 1519system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015760 # miss rate for ReadReq accesses 1520system.cpu1.dcache.ReadReq_miss_rate::total 0.015760 # miss rate for ReadReq accesses 1521system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022371 # miss rate for WriteReq accesses 1522system.cpu1.dcache.WriteReq_miss_rate::total 0.022371 # miss rate for WriteReq accesses 1523system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.345620 # miss rate for SoftPFReq accesses 1524system.cpu1.dcache.SoftPFReq_miss_rate::total 0.345620 # miss rate for SoftPFReq accesses 1525system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166839 # miss rate for LoadLockedReq accesses 1526system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166839 # miss rate for LoadLockedReq accesses 1527system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226171 # miss rate for StoreCondReq accesses 1528system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226171 # miss rate for StoreCondReq accesses 1529system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018334 # miss rate for demand accesses 1530system.cpu1.dcache.demand_miss_rate::total 0.018334 # miss rate for demand accesses 1531system.cpu1.dcache.overall_miss_rate::cpu1.data 0.020035 # miss rate for overall accesses 1532system.cpu1.dcache.overall_miss_rate::total 0.020035 # miss rate for overall accesses 1533system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15719.654480 # average ReadReq miss latency 1534system.cpu1.dcache.ReadReq_avg_miss_latency::total 15719.654480 # average ReadReq miss latency 1535system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31561.596949 # average WriteReq miss latency 1536system.cpu1.dcache.WriteReq_avg_miss_latency::total 31561.596949 # average WriteReq miss latency 1537system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18840.247678 # average LoadLockedReq miss latency 1538system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18840.247678 # average LoadLockedReq miss latency 1539system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26892.008318 # average StoreCondReq miss latency 1540system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26892.008318 # average StoreCondReq miss latency 1541system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1542system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1543system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23244.005715 # average overall miss latency 1544system.cpu1.dcache.demand_avg_miss_latency::total 23244.005715 # average overall miss latency 1545system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21159.247321 # average overall miss latency 1546system.cpu1.dcache.overall_avg_miss_latency::total 21159.247321 # average overall miss latency 1547system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1548system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1549system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1550system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1551system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1552system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1553system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1554system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1555system.cpu1.dcache.writebacks::writebacks 234075 # number of writebacks 1556system.cpu1.dcache.writebacks::total 234075 # number of writebacks 1557system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18534 # number of ReadReq MSHR hits 1558system.cpu1.dcache.ReadReq_mshr_hits::total 18534 # number of ReadReq MSHR hits 1559system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62653 # number of WriteReq MSHR hits 1560system.cpu1.dcache.WriteReq_mshr_hits::total 62653 # number of WriteReq MSHR hits 1561system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12294 # number of LoadLockedReq MSHR hits 1562system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12294 # number of LoadLockedReq MSHR hits 1563system.cpu1.dcache.demand_mshr_hits::cpu1.data 81187 # number of demand (read+write) MSHR hits 1564system.cpu1.dcache.demand_mshr_hits::total 81187 # number of demand (read+write) MSHR hits 1565system.cpu1.dcache.overall_mshr_hits::cpu1.data 81187 # number of overall MSHR hits 1566system.cpu1.dcache.overall_mshr_hits::total 81187 # number of overall MSHR hits 1567system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 168141 # number of ReadReq MSHR misses 1568system.cpu1.dcache.ReadReq_mshr_misses::total 168141 # number of ReadReq MSHR misses 1569system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106219 # number of WriteReq MSHR misses 1570system.cpu1.dcache.WriteReq_mshr_misses::total 106219 # number of WriteReq MSHR misses 1571system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33570 # number of SoftPFReq MSHR misses 1572system.cpu1.dcache.SoftPFReq_mshr_misses::total 33570 # number of SoftPFReq MSHR misses 1573system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5471 # number of LoadLockedReq MSHR misses 1574system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5471 # number of LoadLockedReq MSHR misses 1575system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23562 # number of StoreCondReq MSHR misses 1576system.cpu1.dcache.StoreCondReq_mshr_misses::total 23562 # number of StoreCondReq MSHR misses 1577system.cpu1.dcache.demand_mshr_misses::cpu1.data 274360 # number of demand (read+write) MSHR misses 1578system.cpu1.dcache.demand_mshr_misses::total 274360 # number of demand (read+write) MSHR misses 1579system.cpu1.dcache.overall_mshr_misses::cpu1.data 307930 # number of overall MSHR misses 1580system.cpu1.dcache.overall_mshr_misses::total 307930 # number of overall MSHR misses 1581system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17170 # number of ReadReq MSHR uncacheable 1582system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17170 # number of ReadReq MSHR uncacheable 1583system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14450 # number of WriteReq MSHR uncacheable 1584system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14450 # number of WriteReq MSHR uncacheable 1585system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31620 # number of overall MSHR uncacheable misses 1586system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31620 # number of overall MSHR uncacheable misses 1587system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2472737500 # number of ReadReq MSHR miss cycles 1588system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2472737500 # number of ReadReq MSHR miss cycles 1589system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3237291000 # number of WriteReq MSHR miss cycles 1590system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3237291000 # number of WriteReq MSHR miss cycles 1591system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 585199000 # number of SoftPFReq MSHR miss cycles 1592system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 585199000 # number of SoftPFReq MSHR miss cycles 1593system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99091500 # number of LoadLockedReq MSHR miss cycles 1594system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99091500 # number of LoadLockedReq MSHR miss cycles 1595system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610069500 # number of StoreCondReq MSHR miss cycles 1596system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610069500 # number of StoreCondReq MSHR miss cycles 1597system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 217500 # number of StoreCondFailReq MSHR miss cycles 1598system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 217500 # number of StoreCondFailReq MSHR miss cycles 1599system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5710028500 # number of demand (read+write) MSHR miss cycles 1600system.cpu1.dcache.demand_mshr_miss_latency::total 5710028500 # number of demand (read+write) MSHR miss cycles 1601system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6295227500 # number of overall MSHR miss cycles 1602system.cpu1.dcache.overall_mshr_miss_latency::total 6295227500 # number of overall MSHR miss cycles 1603system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3132437500 # number of ReadReq MSHR uncacheable cycles 1604system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3132437500 # number of ReadReq MSHR uncacheable cycles 1605system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2631383000 # number of WriteReq MSHR uncacheable cycles 1606system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2631383000 # number of WriteReq MSHR uncacheable cycles 1607system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5763820500 # number of overall MSHR uncacheable cycles 1608system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5763820500 # number of overall MSHR uncacheable cycles 1609system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014196 # mshr miss rate for ReadReq accesses 1610system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014196 # mshr miss rate for ReadReq accesses 1611system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014071 # mshr miss rate for WriteReq accesses 1612system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014071 # mshr miss rate for WriteReq accesses 1613system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331206 # mshr miss rate for SoftPFReq accesses 1614system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331206 # mshr miss rate for SoftPFReq accesses 1615system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051381 # mshr miss rate for LoadLockedReq accesses 1616system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051381 # mshr miss rate for LoadLockedReq accesses 1617system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226171 # mshr miss rate for StoreCondReq accesses 1618system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226171 # mshr miss rate for StoreCondReq accesses 1619system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014147 # mshr miss rate for demand accesses 1620system.cpu1.dcache.demand_mshr_miss_rate::total 0.014147 # mshr miss rate for demand accesses 1621system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015796 # mshr miss rate for overall accesses 1622system.cpu1.dcache.overall_mshr_miss_rate::total 0.015796 # mshr miss rate for overall accesses 1623system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14706.332780 # average ReadReq mshr miss latency 1624system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14706.332780 # average ReadReq mshr miss latency 1625system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30477.513439 # average WriteReq mshr miss latency 1626system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30477.513439 # average WriteReq mshr miss latency 1627system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17432.201370 # average SoftPFReq mshr miss latency 1628system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17432.201370 # average SoftPFReq mshr miss latency 1629system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18112.136721 # average LoadLockedReq mshr miss latency 1630system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18112.136721 # average LoadLockedReq mshr miss latency 1631system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25892.093201 # average StoreCondReq mshr miss latency 1632system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25892.093201 # average StoreCondReq mshr miss latency 1633system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1634system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1635system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20812.175609 # average overall mshr miss latency 1636system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20812.175609 # average overall mshr miss latency 1637system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20443.696619 # average overall mshr miss latency 1638system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20443.696619 # average overall mshr miss latency 1639system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182436.662784 # average ReadReq mshr uncacheable latency 1640system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182436.662784 # average ReadReq mshr uncacheable latency 1641system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182102.629758 # average WriteReq mshr uncacheable latency 1642system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182102.629758 # average WriteReq mshr uncacheable latency 1643system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182284.013283 # average overall mshr uncacheable latency 1644system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182284.013283 # average overall mshr uncacheable latency 1645system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1646system.cpu1.icache.tags.replacements 1045294 # number of replacements 1647system.cpu1.icache.tags.tagsinuse 498.164820 # Cycle average of tags in use 1648system.cpu1.icache.tags.total_refs 40788041 # Total number of references to valid blocks. 1649system.cpu1.icache.tags.sampled_refs 1045806 # Sample count of references to valid blocks. 1650system.cpu1.icache.tags.avg_refs 39.001537 # Average number of references to valid blocks. 1651system.cpu1.icache.tags.warmup_cycle 73317918000 # Cycle when the warmup percentage was hit. 1652system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.164820 # Average occupied blocks per requestor 1653system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972978 # Average percentage of cache occupancy 1654system.cpu1.icache.tags.occ_percent::total 0.972978 # Average percentage of cache occupancy 1655system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1656system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 1657system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id 1658system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1659system.cpu1.icache.tags.tag_accesses 84713500 # Number of tag accesses 1660system.cpu1.icache.tags.data_accesses 84713500 # Number of data accesses 1661system.cpu1.icache.ReadReq_hits::cpu1.inst 40788041 # number of ReadReq hits 1662system.cpu1.icache.ReadReq_hits::total 40788041 # number of ReadReq hits 1663system.cpu1.icache.demand_hits::cpu1.inst 40788041 # number of demand (read+write) hits 1664system.cpu1.icache.demand_hits::total 40788041 # number of demand (read+write) hits 1665system.cpu1.icache.overall_hits::cpu1.inst 40788041 # number of overall hits 1666system.cpu1.icache.overall_hits::total 40788041 # number of overall hits 1667system.cpu1.icache.ReadReq_misses::cpu1.inst 1045806 # number of ReadReq misses 1668system.cpu1.icache.ReadReq_misses::total 1045806 # number of ReadReq misses 1669system.cpu1.icache.demand_misses::cpu1.inst 1045806 # number of demand (read+write) misses 1670system.cpu1.icache.demand_misses::total 1045806 # number of demand (read+write) misses 1671system.cpu1.icache.overall_misses::cpu1.inst 1045806 # number of overall misses 1672system.cpu1.icache.overall_misses::total 1045806 # number of overall misses 1673system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9756409000 # number of ReadReq miss cycles 1674system.cpu1.icache.ReadReq_miss_latency::total 9756409000 # number of ReadReq miss cycles 1675system.cpu1.icache.demand_miss_latency::cpu1.inst 9756409000 # number of demand (read+write) miss cycles 1676system.cpu1.icache.demand_miss_latency::total 9756409000 # number of demand (read+write) miss cycles 1677system.cpu1.icache.overall_miss_latency::cpu1.inst 9756409000 # number of overall miss cycles 1678system.cpu1.icache.overall_miss_latency::total 9756409000 # number of overall miss cycles 1679system.cpu1.icache.ReadReq_accesses::cpu1.inst 41833847 # number of ReadReq accesses(hits+misses) 1680system.cpu1.icache.ReadReq_accesses::total 41833847 # number of ReadReq accesses(hits+misses) 1681system.cpu1.icache.demand_accesses::cpu1.inst 41833847 # number of demand (read+write) accesses 1682system.cpu1.icache.demand_accesses::total 41833847 # number of demand (read+write) accesses 1683system.cpu1.icache.overall_accesses::cpu1.inst 41833847 # number of overall (read+write) accesses 1684system.cpu1.icache.overall_accesses::total 41833847 # number of overall (read+write) accesses 1685system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024999 # miss rate for ReadReq accesses 1686system.cpu1.icache.ReadReq_miss_rate::total 0.024999 # miss rate for ReadReq accesses 1687system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024999 # miss rate for demand accesses 1688system.cpu1.icache.demand_miss_rate::total 0.024999 # miss rate for demand accesses 1689system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024999 # miss rate for overall accesses 1690system.cpu1.icache.overall_miss_rate::total 0.024999 # miss rate for overall accesses 1691system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9329.081111 # average ReadReq miss latency 1692system.cpu1.icache.ReadReq_avg_miss_latency::total 9329.081111 # average ReadReq miss latency 1693system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency 1694system.cpu1.icache.demand_avg_miss_latency::total 9329.081111 # average overall miss latency 1695system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency 1696system.cpu1.icache.overall_avg_miss_latency::total 9329.081111 # average overall miss latency 1697system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1698system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1699system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1700system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1701system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1702system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1703system.cpu1.icache.fast_writes 0 # number of fast writes performed 1704system.cpu1.icache.cache_copies 0 # number of cache copies performed 1705system.cpu1.icache.writebacks::writebacks 1045294 # number of writebacks 1706system.cpu1.icache.writebacks::total 1045294 # number of writebacks 1707system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1045806 # number of ReadReq MSHR misses 1708system.cpu1.icache.ReadReq_mshr_misses::total 1045806 # number of ReadReq MSHR misses 1709system.cpu1.icache.demand_mshr_misses::cpu1.inst 1045806 # number of demand (read+write) MSHR misses 1710system.cpu1.icache.demand_mshr_misses::total 1045806 # number of demand (read+write) MSHR misses 1711system.cpu1.icache.overall_mshr_misses::cpu1.inst 1045806 # number of overall MSHR misses 1712system.cpu1.icache.overall_mshr_misses::total 1045806 # number of overall MSHR misses 1713system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1714system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1715system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1716system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1717system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9233506000 # number of ReadReq MSHR miss cycles 1718system.cpu1.icache.ReadReq_mshr_miss_latency::total 9233506000 # number of ReadReq MSHR miss cycles 1719system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9233506000 # number of demand (read+write) MSHR miss cycles 1720system.cpu1.icache.demand_mshr_miss_latency::total 9233506000 # number of demand (read+write) MSHR miss cycles 1721system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9233506000 # number of overall MSHR miss cycles 1722system.cpu1.icache.overall_mshr_miss_latency::total 9233506000 # number of overall MSHR miss cycles 1723system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles 1724system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles 1725system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles 1726system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles 1727system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for ReadReq accesses 1728system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024999 # mshr miss rate for ReadReq accesses 1729system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for demand accesses 1730system.cpu1.icache.demand_mshr_miss_rate::total 0.024999 # mshr miss rate for demand accesses 1731system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for overall accesses 1732system.cpu1.icache.overall_mshr_miss_rate::total 0.024999 # mshr miss rate for overall accesses 1733system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average ReadReq mshr miss latency 1734system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.081111 # average ReadReq mshr miss latency 1735system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average overall mshr miss latency 1736system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.081111 # average overall mshr miss latency 1737system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average overall mshr miss latency 1738system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.081111 # average overall mshr miss latency 1739system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average ReadReq mshr uncacheable latency 1740system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency 1741system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency 1742system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency 1743system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1744system.cpu1.l2cache.prefetcher.num_hwpf_issued 274967 # number of hwpf issued 1745system.cpu1.l2cache.prefetcher.pfIdentified 275055 # number of prefetch candidates identified 1746system.cpu1.l2cache.prefetcher.pfBufferHit 76 # number of redundant prefetches already in prefetch queue 1747system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1748system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1749system.cpu1.l2cache.prefetcher.pfSpanPage 69809 # number of prefetches not generated due to page crossing 1750system.cpu1.l2cache.tags.replacements 70327 # number of replacements 1751system.cpu1.l2cache.tags.tagsinuse 15561.407713 # Cycle average of tags in use 1752system.cpu1.l2cache.tags.total_refs 2301234 # Total number of references to valid blocks. 1753system.cpu1.l2cache.tags.sampled_refs 85126 # Sample count of references to valid blocks. 1754system.cpu1.l2cache.tags.avg_refs 27.033268 # Average number of references to valid blocks. 1755system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1756system.cpu1.l2cache.tags.occ_blocks::writebacks 14349.457044 # Average occupied blocks per requestor 1757system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.253461 # Average occupied blocks per requestor 1758system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.124525 # Average occupied blocks per requestor 1759system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1150.572683 # Average occupied blocks per requestor 1760system.cpu1.l2cache.tags.occ_percent::writebacks 0.875821 # Average percentage of cache occupancy 1761system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003739 # Average percentage of cache occupancy 1762system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000008 # Average percentage of cache occupancy 1763system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.070225 # Average percentage of cache occupancy 1764system.cpu1.l2cache.tags.occ_percent::total 0.949793 # Average percentage of cache occupancy 1765system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1105 # Occupied blocks per task id 1766system.cpu1.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id 1767system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13629 # Occupied blocks per task id 1768system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 1769system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 296 # Occupied blocks per task id 1770system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 805 # Occupied blocks per task id 1771system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1772system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 1773system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id 1774system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id 1775system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5169 # Occupied blocks per task id 1776system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 8158 # Occupied blocks per task id 1777system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067444 # Percentage of cache occupancy per task id 1778system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id 1779system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.831848 # Percentage of cache occupancy per task id 1780system.cpu1.l2cache.tags.tag_accesses 43062781 # Number of tag accesses 1781system.cpu1.l2cache.tags.data_accesses 43062781 # Number of data accesses 1782system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 34599 # number of ReadReq hits 1783system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2926 # number of ReadReq hits 1784system.cpu1.l2cache.ReadReq_hits::total 37525 # number of ReadReq hits 1785system.cpu1.l2cache.WritebackDirty_hits::writebacks 136064 # number of WritebackDirty hits 1786system.cpu1.l2cache.WritebackDirty_hits::total 136064 # number of WritebackDirty hits 1787system.cpu1.l2cache.WritebackClean_hits::writebacks 1121093 # number of WritebackClean hits 1788system.cpu1.l2cache.WritebackClean_hits::total 1121093 # number of WritebackClean hits 1789system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38465 # number of ReadExReq hits 1790system.cpu1.l2cache.ReadExReq_hits::total 38465 # number of ReadExReq hits 1791system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1018818 # number of ReadCleanReq hits 1792system.cpu1.l2cache.ReadCleanReq_hits::total 1018818 # number of ReadCleanReq hits 1793system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 132902 # number of ReadSharedReq hits 1794system.cpu1.l2cache.ReadSharedReq_hits::total 132902 # number of ReadSharedReq hits 1795system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 34599 # number of demand (read+write) hits 1796system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2926 # number of demand (read+write) hits 1797system.cpu1.l2cache.demand_hits::cpu1.inst 1018818 # number of demand (read+write) hits 1798system.cpu1.l2cache.demand_hits::cpu1.data 171367 # number of demand (read+write) hits 1799system.cpu1.l2cache.demand_hits::total 1227710 # number of demand (read+write) hits 1800system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 34599 # number of overall hits 1801system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2926 # number of overall hits 1802system.cpu1.l2cache.overall_hits::cpu1.inst 1018818 # number of overall hits 1803system.cpu1.l2cache.overall_hits::cpu1.data 171367 # number of overall hits 1804system.cpu1.l2cache.overall_hits::total 1227710 # number of overall hits 1805system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 726 # number of ReadReq misses 1806system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 215 # number of ReadReq misses 1807system.cpu1.l2cache.ReadReq_misses::total 941 # number of ReadReq misses 1808system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 31594 # number of UpgradeReq misses 1809system.cpu1.l2cache.UpgradeReq_misses::total 31594 # number of UpgradeReq misses 1810system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23562 # number of SCUpgradeReq misses 1811system.cpu1.l2cache.SCUpgradeReq_misses::total 23562 # number of SCUpgradeReq misses 1812system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36163 # number of ReadExReq misses 1813system.cpu1.l2cache.ReadExReq_misses::total 36163 # number of ReadExReq misses 1814system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 26988 # number of ReadCleanReq misses 1815system.cpu1.l2cache.ReadCleanReq_misses::total 26988 # number of ReadCleanReq misses 1816system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74277 # number of ReadSharedReq misses 1817system.cpu1.l2cache.ReadSharedReq_misses::total 74277 # number of ReadSharedReq misses 1818system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 726 # number of demand (read+write) misses 1819system.cpu1.l2cache.demand_misses::cpu1.itb.walker 215 # number of demand (read+write) misses 1820system.cpu1.l2cache.demand_misses::cpu1.inst 26988 # number of demand (read+write) misses 1821system.cpu1.l2cache.demand_misses::cpu1.data 110440 # number of demand (read+write) misses 1822system.cpu1.l2cache.demand_misses::total 138369 # number of demand (read+write) misses 1823system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 726 # number of overall misses 1824system.cpu1.l2cache.overall_misses::cpu1.itb.walker 215 # number of overall misses 1825system.cpu1.l2cache.overall_misses::cpu1.inst 26988 # number of overall misses 1826system.cpu1.l2cache.overall_misses::cpu1.data 110440 # number of overall misses 1827system.cpu1.l2cache.overall_misses::total 138369 # number of overall misses 1828system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 20719000 # number of ReadReq miss cycles 1829system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4400000 # number of ReadReq miss cycles 1830system.cpu1.l2cache.ReadReq_miss_latency::total 25119000 # number of ReadReq miss cycles 1831system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 113192500 # number of UpgradeReq miss cycles 1832system.cpu1.l2cache.UpgradeReq_miss_latency::total 113192500 # number of UpgradeReq miss cycles 1833system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 49095500 # number of SCUpgradeReq miss cycles 1834system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 49095500 # number of SCUpgradeReq miss cycles 1835system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 214500 # number of SCUpgradeFailReq miss cycles 1836system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 214500 # number of SCUpgradeFailReq miss cycles 1837system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1899326500 # number of ReadExReq miss cycles 1838system.cpu1.l2cache.ReadExReq_miss_latency::total 1899326500 # number of ReadExReq miss cycles 1839system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1476600500 # number of ReadCleanReq miss cycles 1840system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1476600500 # number of ReadCleanReq miss cycles 1841system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1961237991 # number of ReadSharedReq miss cycles 1842system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1961237991 # number of ReadSharedReq miss cycles 1843system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 20719000 # number of demand (read+write) miss cycles 1844system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4400000 # number of demand (read+write) miss cycles 1845system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1476600500 # number of demand (read+write) miss cycles 1846system.cpu1.l2cache.demand_miss_latency::cpu1.data 3860564491 # number of demand (read+write) miss cycles 1847system.cpu1.l2cache.demand_miss_latency::total 5362283991 # number of demand (read+write) miss cycles 1848system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 20719000 # number of overall miss cycles 1849system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4400000 # number of overall miss cycles 1850system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1476600500 # number of overall miss cycles 1851system.cpu1.l2cache.overall_miss_latency::cpu1.data 3860564491 # number of overall miss cycles 1852system.cpu1.l2cache.overall_miss_latency::total 5362283991 # number of overall miss cycles 1853system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 35325 # number of ReadReq accesses(hits+misses) 1854system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3141 # number of ReadReq accesses(hits+misses) 1855system.cpu1.l2cache.ReadReq_accesses::total 38466 # number of ReadReq accesses(hits+misses) 1856system.cpu1.l2cache.WritebackDirty_accesses::writebacks 136064 # number of WritebackDirty accesses(hits+misses) 1857system.cpu1.l2cache.WritebackDirty_accesses::total 136064 # number of WritebackDirty accesses(hits+misses) 1858system.cpu1.l2cache.WritebackClean_accesses::writebacks 1121093 # number of WritebackClean accesses(hits+misses) 1859system.cpu1.l2cache.WritebackClean_accesses::total 1121093 # number of WritebackClean accesses(hits+misses) 1860system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31594 # number of UpgradeReq accesses(hits+misses) 1861system.cpu1.l2cache.UpgradeReq_accesses::total 31594 # number of UpgradeReq accesses(hits+misses) 1862system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23562 # number of SCUpgradeReq accesses(hits+misses) 1863system.cpu1.l2cache.SCUpgradeReq_accesses::total 23562 # number of SCUpgradeReq accesses(hits+misses) 1864system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74628 # number of ReadExReq accesses(hits+misses) 1865system.cpu1.l2cache.ReadExReq_accesses::total 74628 # number of ReadExReq accesses(hits+misses) 1866system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1045806 # number of ReadCleanReq accesses(hits+misses) 1867system.cpu1.l2cache.ReadCleanReq_accesses::total 1045806 # number of ReadCleanReq accesses(hits+misses) 1868system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 207179 # number of ReadSharedReq accesses(hits+misses) 1869system.cpu1.l2cache.ReadSharedReq_accesses::total 207179 # number of ReadSharedReq accesses(hits+misses) 1870system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 35325 # number of demand (read+write) accesses 1871system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3141 # number of demand (read+write) accesses 1872system.cpu1.l2cache.demand_accesses::cpu1.inst 1045806 # number of demand (read+write) accesses 1873system.cpu1.l2cache.demand_accesses::cpu1.data 281807 # number of demand (read+write) accesses 1874system.cpu1.l2cache.demand_accesses::total 1366079 # number of demand (read+write) accesses 1875system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 35325 # number of overall (read+write) accesses 1876system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3141 # number of overall (read+write) accesses 1877system.cpu1.l2cache.overall_accesses::cpu1.inst 1045806 # number of overall (read+write) accesses 1878system.cpu1.l2cache.overall_accesses::cpu1.data 281807 # number of overall (read+write) accesses 1879system.cpu1.l2cache.overall_accesses::total 1366079 # number of overall (read+write) accesses 1880system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020552 # miss rate for ReadReq accesses 1881system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068450 # miss rate for ReadReq accesses 1882system.cpu1.l2cache.ReadReq_miss_rate::total 0.024463 # miss rate for ReadReq accesses 1883system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1884system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1885system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1886system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1887system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484577 # miss rate for ReadExReq accesses 1888system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484577 # miss rate for ReadExReq accesses 1889system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025806 # miss rate for ReadCleanReq accesses 1890system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025806 # miss rate for ReadCleanReq accesses 1891system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.358516 # miss rate for ReadSharedReq accesses 1892system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.358516 # miss rate for ReadSharedReq accesses 1893system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020552 # miss rate for demand accesses 1894system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068450 # miss rate for demand accesses 1895system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025806 # miss rate for demand accesses 1896system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.391899 # miss rate for demand accesses 1897system.cpu1.l2cache.demand_miss_rate::total 0.101289 # miss rate for demand accesses 1898system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020552 # miss rate for overall accesses 1899system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068450 # miss rate for overall accesses 1900system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025806 # miss rate for overall accesses 1901system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.391899 # miss rate for overall accesses 1902system.cpu1.l2cache.overall_miss_rate::total 0.101289 # miss rate for overall accesses 1903system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 28538.567493 # average ReadReq miss latency 1904system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20465.116279 # average ReadReq miss latency 1905system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26693.942614 # average ReadReq miss latency 1906system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 3582.721403 # average UpgradeReq miss latency 1907system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 3582.721403 # average UpgradeReq miss latency 1908system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2083.672863 # average SCUpgradeReq miss latency 1909system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2083.672863 # average SCUpgradeReq miss latency 1910system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1911system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1912system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52521.264829 # average ReadExReq miss latency 1913system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52521.264829 # average ReadExReq miss latency 1914system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 54713.224396 # average ReadCleanReq miss latency 1915system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 54713.224396 # average ReadCleanReq miss latency 1916system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 26404.378085 # average ReadSharedReq miss latency 1917system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 26404.378085 # average ReadSharedReq miss latency 1918system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 28538.567493 # average overall miss latency 1919system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20465.116279 # average overall miss latency 1920system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 54713.224396 # average overall miss latency 1921system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34956.215963 # average overall miss latency 1922system.cpu1.l2cache.demand_avg_miss_latency::total 38753.506862 # average overall miss latency 1923system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 28538.567493 # average overall miss latency 1924system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20465.116279 # average overall miss latency 1925system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 54713.224396 # average overall miss latency 1926system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34956.215963 # average overall miss latency 1927system.cpu1.l2cache.overall_avg_miss_latency::total 38753.506862 # average overall miss latency 1928system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1929system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1930system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1931system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1932system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1933system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1934system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1935system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1936system.cpu1.l2cache.writebacks::writebacks 42165 # number of writebacks 1937system.cpu1.l2cache.writebacks::total 42165 # number of writebacks 1938system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 460 # number of ReadExReq MSHR hits 1939system.cpu1.l2cache.ReadExReq_mshr_hits::total 460 # number of ReadExReq MSHR hits 1940system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 30 # number of ReadCleanReq MSHR hits 1941system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits 1942system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 139 # number of ReadSharedReq MSHR hits 1943system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 139 # number of ReadSharedReq MSHR hits 1944system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 30 # number of demand (read+write) MSHR hits 1945system.cpu1.l2cache.demand_mshr_hits::cpu1.data 599 # number of demand (read+write) MSHR hits 1946system.cpu1.l2cache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits 1947system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 30 # number of overall MSHR hits 1948system.cpu1.l2cache.overall_mshr_hits::cpu1.data 599 # number of overall MSHR hits 1949system.cpu1.l2cache.overall_mshr_hits::total 629 # number of overall MSHR hits 1950system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 726 # number of ReadReq MSHR misses 1951system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 215 # number of ReadReq MSHR misses 1952system.cpu1.l2cache.ReadReq_mshr_misses::total 941 # number of ReadReq MSHR misses 1953system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 38702 # number of HardPFReq MSHR misses 1954system.cpu1.l2cache.HardPFReq_mshr_misses::total 38702 # number of HardPFReq MSHR misses 1955system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 31594 # number of UpgradeReq MSHR misses 1956system.cpu1.l2cache.UpgradeReq_mshr_misses::total 31594 # number of UpgradeReq MSHR misses 1957system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23562 # number of SCUpgradeReq MSHR misses 1958system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23562 # number of SCUpgradeReq MSHR misses 1959system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35703 # number of ReadExReq MSHR misses 1960system.cpu1.l2cache.ReadExReq_mshr_misses::total 35703 # number of ReadExReq MSHR misses 1961system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 26958 # number of ReadCleanReq MSHR misses 1962system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 26958 # number of ReadCleanReq MSHR misses 1963system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 74138 # number of ReadSharedReq MSHR misses 1964system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 74138 # number of ReadSharedReq MSHR misses 1965system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 726 # number of demand (read+write) MSHR misses 1966system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 215 # number of demand (read+write) MSHR misses 1967system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 26958 # number of demand (read+write) MSHR misses 1968system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109841 # number of demand (read+write) MSHR misses 1969system.cpu1.l2cache.demand_mshr_misses::total 137740 # number of demand (read+write) MSHR misses 1970system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 726 # number of overall MSHR misses 1971system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 215 # number of overall MSHR misses 1972system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 26958 # number of overall MSHR misses 1973system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109841 # number of overall MSHR misses 1974system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 38702 # number of overall MSHR misses 1975system.cpu1.l2cache.overall_mshr_misses::total 176442 # number of overall MSHR misses 1976system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1977system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17170 # number of ReadReq MSHR uncacheable 1978system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17282 # number of ReadReq MSHR uncacheable 1979system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14450 # number of WriteReq MSHR uncacheable 1980system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14450 # number of WriteReq MSHR uncacheable 1981system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1982system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31620 # number of overall MSHR uncacheable misses 1983system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31732 # number of overall MSHR uncacheable misses 1984system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 16363000 # number of ReadReq MSHR miss cycles 1985system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3110000 # number of ReadReq MSHR miss cycles 1986system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 19473000 # number of ReadReq MSHR miss cycles 1987system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1784487366 # number of HardPFReq MSHR miss cycles 1988system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1784487366 # number of HardPFReq MSHR miss cycles 1989system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 731407500 # number of UpgradeReq MSHR miss cycles 1990system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 731407500 # number of UpgradeReq MSHR miss cycles 1991system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 431778000 # number of SCUpgradeReq MSHR miss cycles 1992system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 431778000 # number of SCUpgradeReq MSHR miss cycles 1993system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 202500 # number of SCUpgradeFailReq MSHR miss cycles 1994system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 202500 # number of SCUpgradeFailReq MSHR miss cycles 1995system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1638685500 # number of ReadExReq MSHR miss cycles 1996system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1638685500 # number of ReadExReq MSHR miss cycles 1997system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1313778000 # number of ReadCleanReq MSHR miss cycles 1998system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1313778000 # number of ReadCleanReq MSHR miss cycles 1999system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1509035491 # number of ReadSharedReq MSHR miss cycles 2000system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1509035491 # number of ReadSharedReq MSHR miss cycles 2001system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 16363000 # number of demand (read+write) MSHR miss cycles 2002system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3110000 # number of demand (read+write) MSHR miss cycles 2003system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1313778000 # number of demand (read+write) MSHR miss cycles 2004system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 3147720991 # number of demand (read+write) MSHR miss cycles 2005system.cpu1.l2cache.demand_mshr_miss_latency::total 4480971991 # number of demand (read+write) MSHR miss cycles 2006system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 16363000 # number of overall MSHR miss cycles 2007system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3110000 # number of overall MSHR miss cycles 2008system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1313778000 # number of overall MSHR miss cycles 2009system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 3147720991 # number of overall MSHR miss cycles 2010system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1784487366 # number of overall MSHR miss cycles 2011system.cpu1.l2cache.overall_mshr_miss_latency::total 6265459357 # number of overall MSHR miss cycles 2012system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14454500 # number of ReadReq MSHR uncacheable cycles 2013system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2994980000 # number of ReadReq MSHR uncacheable cycles 2014system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3009434500 # number of ReadReq MSHR uncacheable cycles 2015system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2522882500 # number of WriteReq MSHR uncacheable cycles 2016system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2522882500 # number of WriteReq MSHR uncacheable cycles 2017system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14454500 # number of overall MSHR uncacheable cycles 2018system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5517862500 # number of overall MSHR uncacheable cycles 2019system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5532317000 # number of overall MSHR uncacheable cycles 2020system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020552 # mshr miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068450 # mshr miss rate for ReadReq accesses 2022system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024463 # mshr miss rate for ReadReq accesses 2023system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2024system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2025system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2026system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2028system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2029system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.478413 # mshr miss rate for ReadExReq accesses 2030system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.478413 # mshr miss rate for ReadExReq accesses 2031system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025777 # mshr miss rate for ReadCleanReq accesses 2032system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025777 # mshr miss rate for ReadCleanReq accesses 2033system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.357845 # mshr miss rate for ReadSharedReq accesses 2034system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.357845 # mshr miss rate for ReadSharedReq accesses 2035system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020552 # mshr miss rate for demand accesses 2036system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068450 # mshr miss rate for demand accesses 2037system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025777 # mshr miss rate for demand accesses 2038system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389774 # mshr miss rate for demand accesses 2039system.cpu1.l2cache.demand_mshr_miss_rate::total 0.100829 # mshr miss rate for demand accesses 2040system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020552 # mshr miss rate for overall accesses 2041system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068450 # mshr miss rate for overall accesses 2042system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025777 # mshr miss rate for overall accesses 2043system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389774 # mshr miss rate for overall accesses 2044system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2045system.cpu1.l2cache.overall_mshr_miss_rate::total 0.129159 # mshr miss rate for overall accesses 2046system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average ReadReq mshr miss latency 2047system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average ReadReq mshr miss latency 2048system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20693.942614 # average ReadReq mshr miss latency 2049system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788 # average HardPFReq mshr miss latency 2050system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46108.401788 # average HardPFReq mshr miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23150.202570 # average UpgradeReq mshr miss latency 2052system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23150.202570 # average UpgradeReq mshr miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18325.184619 # average SCUpgradeReq mshr miss latency 2054system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18325.184619 # average SCUpgradeReq mshr miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2056system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2057system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45897.697672 # average ReadExReq mshr miss latency 2058system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45897.697672 # average ReadExReq mshr miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average ReadCleanReq mshr miss latency 2060system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48734.253283 # average ReadCleanReq mshr miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 20354.413270 # average ReadSharedReq mshr miss latency 2062system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 20354.413270 # average ReadSharedReq mshr miss latency 2063system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency 2064system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency 2065system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency 2066system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency 2067system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32532.103899 # average overall mshr miss latency 2068system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency 2069system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency 2070system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency 2071system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency 2072system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788 # average overall mshr miss latency 2073system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35510.022313 # average overall mshr miss latency 2074system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency 2075system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174430.984275 # average ReadReq mshr uncacheable latency 2076system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174136.934383 # average ReadReq mshr uncacheable latency 2077system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174593.944637 # average WriteReq mshr uncacheable latency 2078system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 174593.944637 # average WriteReq mshr uncacheable latency 2079system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency 2080system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174505.455408 # average overall mshr uncacheable latency 2081system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174345.046010 # average overall mshr uncacheable latency 2082system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2083system.cpu1.toL2Bus.snoop_filter.tot_requests 2671947 # Total number of requests made to the snoop filter. 2084system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1344357 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2085system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 22211 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2086system.cpu1.toL2Bus.snoop_filter.tot_snoops 212012 # Total number of snoops made to the snoop filter. 2087system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 209828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2088system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2089system.cpu1.toL2Bus.trans_dist::ReadReq 60366 # Transaction distribution 2090system.cpu1.toL2Bus.trans_dist::ReadResp 1353600 # Transaction distribution 2091system.cpu1.toL2Bus.trans_dist::WriteReq 14450 # Transaction distribution 2092system.cpu1.toL2Bus.trans_dist::WriteResp 14450 # Transaction distribution 2093system.cpu1.toL2Bus.trans_dist::WritebackDirty 179270 # Transaction distribution 2094system.cpu1.toL2Bus.trans_dist::WritebackClean 1143304 # Transaction distribution 2095system.cpu1.toL2Bus.trans_dist::CleanEvict 137947 # Transaction distribution 2096system.cpu1.toL2Bus.trans_dist::HardPFReq 47540 # Transaction distribution 2097system.cpu1.toL2Bus.trans_dist::UpgradeReq 74191 # Transaction distribution 2098system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43096 # Transaction distribution 2099system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution 2100system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 2101system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::ReadExReq 82906 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::ReadExResp 80697 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1045806 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295809 # Transaction distribution 2106system.cpu1.toL2Bus.trans_dist::InvalidateReq 50 # Transaction distribution 2107system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3137130 # Packet count per connected master and slave (bytes) 2108system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1052074 # Packet count per connected master and slave (bytes) 2109system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7597 # Packet count per connected master and slave (bytes) 2110system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 73953 # Packet count per connected master and slave (bytes) 2111system.cpu1.toL2Bus.pkt_count::total 4270754 # Packet count per connected master and slave (bytes) 2112system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 133837568 # Cumulative packet size per connected master and slave (bytes) 2113system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36094549 # Cumulative packet size per connected master and slave (bytes) 2114system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12564 # Cumulative packet size per connected master and slave (bytes) 2115system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 141300 # Cumulative packet size per connected master and slave (bytes) 2116system.cpu1.toL2Bus.pkt_size::total 170085981 # Cumulative packet size per connected master and slave (bytes) 2117system.cpu1.toL2Bus.snoops 473244 # Total snoops (count) 2118system.cpu1.toL2Bus.snoop_fanout::samples 1845377 # Request fanout histogram 2119system.cpu1.toL2Bus.snoop_fanout::mean 0.133426 # Request fanout histogram 2120system.cpu1.toL2Bus.snoop_fanout::stdev 0.343498 # Request fanout histogram 2121system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2122system.cpu1.toL2Bus.snoop_fanout::0 1601339 86.78% 86.78% # Request fanout histogram 2123system.cpu1.toL2Bus.snoop_fanout::1 241854 13.11% 99.88% # Request fanout histogram 2124system.cpu1.toL2Bus.snoop_fanout::2 2184 0.12% 100.00% # Request fanout histogram 2125system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2126system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2127system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2128system.cpu1.toL2Bus.snoop_fanout::total 1845377 # Request fanout histogram 2129system.cpu1.toL2Bus.reqLayer0.occupancy 2655073991 # Layer occupancy (ticks) 2130system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2131system.cpu1.toL2Bus.snoopLayer0.occupancy 86773438 # Layer occupancy (ticks) 2132system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2133system.cpu1.toL2Bus.respLayer0.occupancy 1569094564 # Layer occupancy (ticks) 2134system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2135system.cpu1.toL2Bus.respLayer1.occupancy 476141581 # Layer occupancy (ticks) 2136system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2137system.cpu1.toL2Bus.respLayer2.occupancy 4456000 # Layer occupancy (ticks) 2138system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2139system.cpu1.toL2Bus.respLayer3.occupancy 38655445 # Layer occupancy (ticks) 2140system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2141system.iobus.trans_dist::ReadReq 31014 # Transaction distribution 2142system.iobus.trans_dist::ReadResp 31014 # Transaction distribution 2143system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2144system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2145system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2146system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2147system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2148system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2149system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2150system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2151system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) 2152system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2153system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2154system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2157system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2162system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2163system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2164system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) 2165system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) 2166system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) 2168system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) 2169system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2170system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2171system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2172system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2173system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2174system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) 2175system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2176system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2177system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2179system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2187system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes) 2188system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) 2189system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) 2190system.iobus.pkt_size::total 2484072 # Cumulative packet size per connected master and slave (bytes) 2191system.iobus.reqLayer0.occupancy 51031501 # Layer occupancy (ticks) 2192system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2193system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) 2194system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2195system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) 2196system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2197system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) 2198system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2199system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) 2200system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2201system.iobus.reqLayer7.occupancy 85000 # Layer occupancy (ticks) 2202system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2203system.iobus.reqLayer8.occupancy 565500 # Layer occupancy (ticks) 2204system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2205system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks) 2206system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2207system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 2208system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2209system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2210system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2211system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2212system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2213system.iobus.reqLayer16.occupancy 46000 # Layer occupancy (ticks) 2214system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2215system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 2216system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2217system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2218system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2219system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2220system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2221system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 2222system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2223system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) 2224system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2225system.iobus.reqLayer23.occupancy 6103500 # Layer occupancy (ticks) 2226system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2227system.iobus.reqLayer24.occupancy 32838000 # Layer occupancy (ticks) 2228system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2229system.iobus.reqLayer25.occupancy 187160706 # Layer occupancy (ticks) 2230system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2231system.iobus.respLayer0.occupancy 84713000 # Layer occupancy (ticks) 2232system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2233system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) 2234system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2235system.iocache.tags.replacements 36462 # number of replacements 2236system.iocache.tags.tagsinuse 14.353695 # Cycle average of tags in use 2237system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2238system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. 2239system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2240system.iocache.tags.warmup_cycle 272566004000 # Cycle when the warmup percentage was hit. 2241system.iocache.tags.occ_blocks::realview.ide 14.353695 # Average occupied blocks per requestor 2242system.iocache.tags.occ_percent::realview.ide 0.897106 # Average percentage of cache occupancy 2243system.iocache.tags.occ_percent::total 0.897106 # Average percentage of cache occupancy 2244system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2245system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2246system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2247system.iocache.tags.tag_accesses 328320 # Number of tag accesses 2248system.iocache.tags.data_accesses 328320 # Number of data accesses 2249system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses 2250system.iocache.ReadReq_misses::total 256 # number of ReadReq misses 2251system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2252system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2253system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses 2254system.iocache.demand_misses::total 256 # number of demand (read+write) misses 2255system.iocache.overall_misses::realview.ide 256 # number of overall misses 2256system.iocache.overall_misses::total 256 # number of overall misses 2257system.iocache.ReadReq_miss_latency::realview.ide 33038877 # number of ReadReq miss cycles 2258system.iocache.ReadReq_miss_latency::total 33038877 # number of ReadReq miss cycles 2259system.iocache.WriteLineReq_miss_latency::realview.ide 4577477829 # number of WriteLineReq miss cycles 2260system.iocache.WriteLineReq_miss_latency::total 4577477829 # number of WriteLineReq miss cycles 2261system.iocache.demand_miss_latency::realview.ide 33038877 # number of demand (read+write) miss cycles 2262system.iocache.demand_miss_latency::total 33038877 # number of demand (read+write) miss cycles 2263system.iocache.overall_miss_latency::realview.ide 33038877 # number of overall miss cycles 2264system.iocache.overall_miss_latency::total 33038877 # number of overall miss cycles 2265system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) 2266system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) 2267system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2268system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2269system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses 2270system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses 2271system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses 2272system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses 2273system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2274system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2275system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2276system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2277system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2278system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2279system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2280system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2281system.iocache.ReadReq_avg_miss_latency::realview.ide 129058.113281 # average ReadReq miss latency 2282system.iocache.ReadReq_avg_miss_latency::total 129058.113281 # average ReadReq miss latency 2283system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126365.885297 # average WriteLineReq miss latency 2284system.iocache.WriteLineReq_avg_miss_latency::total 126365.885297 # average WriteLineReq miss latency 2285system.iocache.demand_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency 2286system.iocache.demand_avg_miss_latency::total 129058.113281 # average overall miss latency 2287system.iocache.overall_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency 2288system.iocache.overall_avg_miss_latency::total 129058.113281 # average overall miss latency 2289system.iocache.blocked_cycles::no_mshrs 12 # number of cycles access was blocked 2290system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2291system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 2292system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2293system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked 2294system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2295system.iocache.fast_writes 0 # number of fast writes performed 2296system.iocache.cache_copies 0 # number of cache copies performed 2297system.iocache.writebacks::writebacks 36206 # number of writebacks 2298system.iocache.writebacks::total 36206 # number of writebacks 2299system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses 2300system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses 2301system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2302system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2303system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses 2304system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses 2305system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses 2306system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses 2307system.iocache.ReadReq_mshr_miss_latency::realview.ide 20238877 # number of ReadReq MSHR miss cycles 2308system.iocache.ReadReq_mshr_miss_latency::total 20238877 # number of ReadReq MSHR miss cycles 2309system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764566568 # number of WriteLineReq MSHR miss cycles 2310system.iocache.WriteLineReq_mshr_miss_latency::total 2764566568 # number of WriteLineReq MSHR miss cycles 2311system.iocache.demand_mshr_miss_latency::realview.ide 20238877 # number of demand (read+write) MSHR miss cycles 2312system.iocache.demand_mshr_miss_latency::total 20238877 # number of demand (read+write) MSHR miss cycles 2313system.iocache.overall_mshr_miss_latency::realview.ide 20238877 # number of overall MSHR miss cycles 2314system.iocache.overall_mshr_miss_latency::total 20238877 # number of overall MSHR miss cycles 2315system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2316system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2317system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2318system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2319system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2320system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2321system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2322system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2323system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79058.113281 # average ReadReq mshr miss latency 2324system.iocache.ReadReq_avg_mshr_miss_latency::total 79058.113281 # average ReadReq mshr miss latency 2325system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76318.644214 # average WriteLineReq mshr miss latency 2326system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76318.644214 # average WriteLineReq mshr miss latency 2327system.iocache.demand_avg_mshr_miss_latency::realview.ide 79058.113281 # average overall mshr miss latency 2328system.iocache.demand_avg_mshr_miss_latency::total 79058.113281 # average overall mshr miss latency 2329system.iocache.overall_avg_mshr_miss_latency::realview.ide 79058.113281 # average overall mshr miss latency 2330system.iocache.overall_avg_mshr_miss_latency::total 79058.113281 # average overall mshr miss latency 2331system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2332system.l2c.tags.replacements 134245 # number of replacements 2333system.l2c.tags.tagsinuse 63310.759075 # Cycle average of tags in use 2334system.l2c.tags.total_refs 474981 # Total number of references to valid blocks. 2335system.l2c.tags.sampled_refs 198059 # Sample count of references to valid blocks. 2336system.l2c.tags.avg_refs 2.398179 # Average number of references to valid blocks. 2337system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2338system.l2c.tags.occ_blocks::writebacks 14231.075006 # Average occupied blocks per requestor 2339system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.949164 # Average occupied blocks per requestor 2340system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999781 # Average occupied blocks per requestor 2341system.l2c.tags.occ_blocks::cpu0.inst 7026.716381 # Average occupied blocks per requestor 2342system.l2c.tags.occ_blocks::cpu0.data 2024.667607 # Average occupied blocks per requestor 2343system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 30360.457538 # Average occupied blocks per requestor 2344system.l2c.tags.occ_blocks::cpu1.dtb.walker 27.102838 # Average occupied blocks per requestor 2345system.l2c.tags.occ_blocks::cpu1.inst 4106.821272 # Average occupied blocks per requestor 2346system.l2c.tags.occ_blocks::cpu1.data 1547.963396 # Average occupied blocks per requestor 2347system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3916.006093 # Average occupied blocks per requestor 2348system.l2c.tags.occ_percent::writebacks 0.217149 # Average percentage of cache occupancy 2349system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001052 # Average percentage of cache occupancy 2350system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 2351system.l2c.tags.occ_percent::cpu0.inst 0.107219 # Average percentage of cache occupancy 2352system.l2c.tags.occ_percent::cpu0.data 0.030894 # Average percentage of cache occupancy 2353system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.463264 # Average percentage of cache occupancy 2354system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000414 # Average percentage of cache occupancy 2355system.l2c.tags.occ_percent::cpu1.inst 0.062665 # Average percentage of cache occupancy 2356system.l2c.tags.occ_percent::cpu1.data 0.023620 # Average percentage of cache occupancy 2357system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.059754 # Average percentage of cache occupancy 2358system.l2c.tags.occ_percent::total 0.966046 # Average percentage of cache occupancy 2359system.l2c.tags.occ_task_id_blocks::1022 27725 # Occupied blocks per task id 2360system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 2361system.l2c.tags.occ_task_id_blocks::1024 35997 # Occupied blocks per task id 2362system.l2c.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id 2363system.l2c.tags.age_task_id_blocks_1022::3 4285 # Occupied blocks per task id 2364system.l2c.tags.age_task_id_blocks_1022::4 23307 # Occupied blocks per task id 2365system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2366system.l2c.tags.age_task_id_blocks_1023::4 91 # Occupied blocks per task id 2367system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2368system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 2369system.l2c.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id 2370system.l2c.tags.age_task_id_blocks_1024::3 3332 # Occupied blocks per task id 2371system.l2c.tags.age_task_id_blocks_1024::4 32208 # Occupied blocks per task id 2372system.l2c.tags.occ_task_id_percent::1022 0.423050 # Percentage of cache occupancy per task id 2373system.l2c.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id 2374system.l2c.tags.occ_task_id_percent::1024 0.549271 # Percentage of cache occupancy per task id 2375system.l2c.tags.tag_accesses 6430843 # Number of tag accesses 2376system.l2c.tags.data_accesses 6430843 # Number of data accesses 2377system.l2c.WritebackDirty_hits::writebacks 269664 # number of WritebackDirty hits 2378system.l2c.WritebackDirty_hits::total 269664 # number of WritebackDirty hits 2379system.l2c.UpgradeReq_hits::cpu0.data 32870 # number of UpgradeReq hits 2380system.l2c.UpgradeReq_hits::cpu1.data 3603 # number of UpgradeReq hits 2381system.l2c.UpgradeReq_hits::total 36473 # number of UpgradeReq hits 2382system.l2c.SCUpgradeReq_hits::cpu0.data 1969 # number of SCUpgradeReq hits 2383system.l2c.SCUpgradeReq_hits::cpu1.data 1232 # number of SCUpgradeReq hits 2384system.l2c.SCUpgradeReq_hits::total 3201 # number of SCUpgradeReq hits 2385system.l2c.ReadExReq_hits::cpu0.data 4063 # number of ReadExReq hits 2386system.l2c.ReadExReq_hits::cpu1.data 2251 # number of ReadExReq hits 2387system.l2c.ReadExReq_hits::total 6314 # number of ReadExReq hits 2388system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 366 # number of ReadSharedReq hits 2389system.l2c.ReadSharedReq_hits::cpu0.itb.walker 61 # number of ReadSharedReq hits 2390system.l2c.ReadSharedReq_hits::cpu0.inst 40218 # number of ReadSharedReq hits 2391system.l2c.ReadSharedReq_hits::cpu0.data 47314 # number of ReadSharedReq hits 2392system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45570 # number of ReadSharedReq hits 2393system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 178 # number of ReadSharedReq hits 2394system.l2c.ReadSharedReq_hits::cpu1.itb.walker 25 # number of ReadSharedReq hits 2395system.l2c.ReadSharedReq_hits::cpu1.inst 20885 # number of ReadSharedReq hits 2396system.l2c.ReadSharedReq_hits::cpu1.data 12402 # number of ReadSharedReq hits 2397system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8121 # number of ReadSharedReq hits 2398system.l2c.ReadSharedReq_hits::total 175140 # number of ReadSharedReq hits 2399system.l2c.demand_hits::cpu0.dtb.walker 366 # number of demand (read+write) hits 2400system.l2c.demand_hits::cpu0.itb.walker 61 # number of demand (read+write) hits 2401system.l2c.demand_hits::cpu0.inst 40218 # number of demand (read+write) hits 2402system.l2c.demand_hits::cpu0.data 51377 # number of demand (read+write) hits 2403system.l2c.demand_hits::cpu0.l2cache.prefetcher 45570 # number of demand (read+write) hits 2404system.l2c.demand_hits::cpu1.dtb.walker 178 # number of demand (read+write) hits 2405system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits 2406system.l2c.demand_hits::cpu1.inst 20885 # number of demand (read+write) hits 2407system.l2c.demand_hits::cpu1.data 14653 # number of demand (read+write) hits 2408system.l2c.demand_hits::cpu1.l2cache.prefetcher 8121 # number of demand (read+write) hits 2409system.l2c.demand_hits::total 181454 # number of demand (read+write) hits 2410system.l2c.overall_hits::cpu0.dtb.walker 366 # number of overall hits 2411system.l2c.overall_hits::cpu0.itb.walker 61 # number of overall hits 2412system.l2c.overall_hits::cpu0.inst 40218 # number of overall hits 2413system.l2c.overall_hits::cpu0.data 51377 # number of overall hits 2414system.l2c.overall_hits::cpu0.l2cache.prefetcher 45570 # number of overall hits 2415system.l2c.overall_hits::cpu1.dtb.walker 178 # number of overall hits 2416system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits 2417system.l2c.overall_hits::cpu1.inst 20885 # number of overall hits 2418system.l2c.overall_hits::cpu1.data 14653 # number of overall hits 2419system.l2c.overall_hits::cpu1.l2cache.prefetcher 8121 # number of overall hits 2420system.l2c.overall_hits::total 181454 # number of overall hits 2421system.l2c.UpgradeReq_misses::cpu0.data 9292 # number of UpgradeReq misses 2422system.l2c.UpgradeReq_misses::cpu1.data 4200 # number of UpgradeReq misses 2423system.l2c.UpgradeReq_misses::total 13492 # number of UpgradeReq misses 2424system.l2c.SCUpgradeReq_misses::cpu0.data 991 # number of SCUpgradeReq misses 2425system.l2c.SCUpgradeReq_misses::cpu1.data 1195 # number of SCUpgradeReq misses 2426system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses 2427system.l2c.ReadExReq_misses::cpu0.data 11020 # number of ReadExReq misses 2428system.l2c.ReadExReq_misses::cpu1.data 8511 # number of ReadExReq misses 2429system.l2c.ReadExReq_misses::total 19531 # number of ReadExReq misses 2430system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 121 # number of ReadSharedReq misses 2431system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2432system.l2c.ReadSharedReq_misses::cpu0.inst 19956 # number of ReadSharedReq misses 2433system.l2c.ReadSharedReq_misses::cpu0.data 8680 # number of ReadSharedReq misses 2434system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128666 # number of ReadSharedReq misses 2435system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 40 # number of ReadSharedReq misses 2436system.l2c.ReadSharedReq_misses::cpu1.inst 6073 # number of ReadSharedReq misses 2437system.l2c.ReadSharedReq_misses::cpu1.data 2829 # number of ReadSharedReq misses 2438system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9649 # number of ReadSharedReq misses 2439system.l2c.ReadSharedReq_misses::total 176015 # number of ReadSharedReq misses 2440system.l2c.demand_misses::cpu0.dtb.walker 121 # number of demand (read+write) misses 2441system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2442system.l2c.demand_misses::cpu0.inst 19956 # number of demand (read+write) misses 2443system.l2c.demand_misses::cpu0.data 19700 # number of demand (read+write) misses 2444system.l2c.demand_misses::cpu0.l2cache.prefetcher 128666 # number of demand (read+write) misses 2445system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses 2446system.l2c.demand_misses::cpu1.inst 6073 # number of demand (read+write) misses 2447system.l2c.demand_misses::cpu1.data 11340 # number of demand (read+write) misses 2448system.l2c.demand_misses::cpu1.l2cache.prefetcher 9649 # number of demand (read+write) misses 2449system.l2c.demand_misses::total 195546 # number of demand (read+write) misses 2450system.l2c.overall_misses::cpu0.dtb.walker 121 # number of overall misses 2451system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2452system.l2c.overall_misses::cpu0.inst 19956 # number of overall misses 2453system.l2c.overall_misses::cpu0.data 19700 # number of overall misses 2454system.l2c.overall_misses::cpu0.l2cache.prefetcher 128666 # number of overall misses 2455system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses 2456system.l2c.overall_misses::cpu1.inst 6073 # number of overall misses 2457system.l2c.overall_misses::cpu1.data 11340 # number of overall misses 2458system.l2c.overall_misses::cpu1.l2cache.prefetcher 9649 # number of overall misses 2459system.l2c.overall_misses::total 195546 # number of overall misses 2460system.l2c.UpgradeReq_miss_latency::cpu0.data 21675000 # number of UpgradeReq miss cycles 2461system.l2c.UpgradeReq_miss_latency::cpu1.data 14363500 # number of UpgradeReq miss cycles 2462system.l2c.UpgradeReq_miss_latency::total 36038500 # number of UpgradeReq miss cycles 2463system.l2c.SCUpgradeReq_miss_latency::cpu0.data 6149500 # number of SCUpgradeReq miss cycles 2464system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3079000 # number of SCUpgradeReq miss cycles 2465system.l2c.SCUpgradeReq_miss_latency::total 9228500 # number of SCUpgradeReq miss cycles 2466system.l2c.ReadExReq_miss_latency::cpu0.data 1630299500 # number of ReadExReq miss cycles 2467system.l2c.ReadExReq_miss_latency::cpu1.data 1130442500 # number of ReadExReq miss cycles 2468system.l2c.ReadExReq_miss_latency::total 2760742000 # number of ReadExReq miss cycles 2469system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 16835500 # number of ReadSharedReq miss cycles 2470system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles 2471system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2614410000 # number of ReadSharedReq miss cycles 2472system.l2c.ReadSharedReq_miss_latency::cpu0.data 1193067000 # number of ReadSharedReq miss cycles 2473system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19387965903 # number of ReadSharedReq miss cycles 2474system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 5576500 # number of ReadSharedReq miss cycles 2475system.l2c.ReadSharedReq_miss_latency::cpu1.inst 804383000 # number of ReadSharedReq miss cycles 2476system.l2c.ReadSharedReq_miss_latency::cpu1.data 390467000 # number of ReadSharedReq miss cycles 2477system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1608252495 # number of ReadSharedReq miss cycles 2478system.l2c.ReadSharedReq_miss_latency::total 26021090398 # number of ReadSharedReq miss cycles 2479system.l2c.demand_miss_latency::cpu0.dtb.walker 16835500 # number of demand (read+write) miss cycles 2480system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles 2481system.l2c.demand_miss_latency::cpu0.inst 2614410000 # number of demand (read+write) miss cycles 2482system.l2c.demand_miss_latency::cpu0.data 2823366500 # number of demand (read+write) miss cycles 2483system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19387965903 # number of demand (read+write) miss cycles 2484system.l2c.demand_miss_latency::cpu1.dtb.walker 5576500 # number of demand (read+write) miss cycles 2485system.l2c.demand_miss_latency::cpu1.inst 804383000 # number of demand (read+write) miss cycles 2486system.l2c.demand_miss_latency::cpu1.data 1520909500 # number of demand (read+write) miss cycles 2487system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1608252495 # number of demand (read+write) miss cycles 2488system.l2c.demand_miss_latency::total 28781832398 # number of demand (read+write) miss cycles 2489system.l2c.overall_miss_latency::cpu0.dtb.walker 16835500 # number of overall miss cycles 2490system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles 2491system.l2c.overall_miss_latency::cpu0.inst 2614410000 # number of overall miss cycles 2492system.l2c.overall_miss_latency::cpu0.data 2823366500 # number of overall miss cycles 2493system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19387965903 # number of overall miss cycles 2494system.l2c.overall_miss_latency::cpu1.dtb.walker 5576500 # number of overall miss cycles 2495system.l2c.overall_miss_latency::cpu1.inst 804383000 # number of overall miss cycles 2496system.l2c.overall_miss_latency::cpu1.data 1520909500 # number of overall miss cycles 2497system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1608252495 # number of overall miss cycles 2498system.l2c.overall_miss_latency::total 28781832398 # number of overall miss cycles 2499system.l2c.WritebackDirty_accesses::writebacks 269664 # number of WritebackDirty accesses(hits+misses) 2500system.l2c.WritebackDirty_accesses::total 269664 # number of WritebackDirty accesses(hits+misses) 2501system.l2c.UpgradeReq_accesses::cpu0.data 42162 # number of UpgradeReq accesses(hits+misses) 2502system.l2c.UpgradeReq_accesses::cpu1.data 7803 # number of UpgradeReq accesses(hits+misses) 2503system.l2c.UpgradeReq_accesses::total 49965 # number of UpgradeReq accesses(hits+misses) 2504system.l2c.SCUpgradeReq_accesses::cpu0.data 2960 # number of SCUpgradeReq accesses(hits+misses) 2505system.l2c.SCUpgradeReq_accesses::cpu1.data 2427 # number of SCUpgradeReq accesses(hits+misses) 2506system.l2c.SCUpgradeReq_accesses::total 5387 # number of SCUpgradeReq accesses(hits+misses) 2507system.l2c.ReadExReq_accesses::cpu0.data 15083 # number of ReadExReq accesses(hits+misses) 2508system.l2c.ReadExReq_accesses::cpu1.data 10762 # number of ReadExReq accesses(hits+misses) 2509system.l2c.ReadExReq_accesses::total 25845 # number of ReadExReq accesses(hits+misses) 2510system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 487 # number of ReadSharedReq accesses(hits+misses) 2511system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 62 # number of ReadSharedReq accesses(hits+misses) 2512system.l2c.ReadSharedReq_accesses::cpu0.inst 60174 # number of ReadSharedReq accesses(hits+misses) 2513system.l2c.ReadSharedReq_accesses::cpu0.data 55994 # number of ReadSharedReq accesses(hits+misses) 2514system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 174236 # number of ReadSharedReq accesses(hits+misses) 2515system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 218 # number of ReadSharedReq accesses(hits+misses) 2516system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 25 # number of ReadSharedReq accesses(hits+misses) 2517system.l2c.ReadSharedReq_accesses::cpu1.inst 26958 # number of ReadSharedReq accesses(hits+misses) 2518system.l2c.ReadSharedReq_accesses::cpu1.data 15231 # number of ReadSharedReq accesses(hits+misses) 2519system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17770 # number of ReadSharedReq accesses(hits+misses) 2520system.l2c.ReadSharedReq_accesses::total 351155 # number of ReadSharedReq accesses(hits+misses) 2521system.l2c.demand_accesses::cpu0.dtb.walker 487 # number of demand (read+write) accesses 2522system.l2c.demand_accesses::cpu0.itb.walker 62 # number of demand (read+write) accesses 2523system.l2c.demand_accesses::cpu0.inst 60174 # number of demand (read+write) accesses 2524system.l2c.demand_accesses::cpu0.data 71077 # number of demand (read+write) accesses 2525system.l2c.demand_accesses::cpu0.l2cache.prefetcher 174236 # number of demand (read+write) accesses 2526system.l2c.demand_accesses::cpu1.dtb.walker 218 # number of demand (read+write) accesses 2527system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses 2528system.l2c.demand_accesses::cpu1.inst 26958 # number of demand (read+write) accesses 2529system.l2c.demand_accesses::cpu1.data 25993 # number of demand (read+write) accesses 2530system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17770 # number of demand (read+write) accesses 2531system.l2c.demand_accesses::total 377000 # number of demand (read+write) accesses 2532system.l2c.overall_accesses::cpu0.dtb.walker 487 # number of overall (read+write) accesses 2533system.l2c.overall_accesses::cpu0.itb.walker 62 # number of overall (read+write) accesses 2534system.l2c.overall_accesses::cpu0.inst 60174 # number of overall (read+write) accesses 2535system.l2c.overall_accesses::cpu0.data 71077 # number of overall (read+write) accesses 2536system.l2c.overall_accesses::cpu0.l2cache.prefetcher 174236 # number of overall (read+write) accesses 2537system.l2c.overall_accesses::cpu1.dtb.walker 218 # number of overall (read+write) accesses 2538system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses 2539system.l2c.overall_accesses::cpu1.inst 26958 # number of overall (read+write) accesses 2540system.l2c.overall_accesses::cpu1.data 25993 # number of overall (read+write) accesses 2541system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17770 # number of overall (read+write) accesses 2542system.l2c.overall_accesses::total 377000 # number of overall (read+write) accesses 2543system.l2c.UpgradeReq_miss_rate::cpu0.data 0.220388 # miss rate for UpgradeReq accesses 2544system.l2c.UpgradeReq_miss_rate::cpu1.data 0.538255 # miss rate for UpgradeReq accesses 2545system.l2c.UpgradeReq_miss_rate::total 0.270029 # miss rate for UpgradeReq accesses 2546system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.334797 # miss rate for SCUpgradeReq accesses 2547system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.492377 # miss rate for SCUpgradeReq accesses 2548system.l2c.SCUpgradeReq_miss_rate::total 0.405792 # miss rate for SCUpgradeReq accesses 2549system.l2c.ReadExReq_miss_rate::cpu0.data 0.730624 # miss rate for ReadExReq accesses 2550system.l2c.ReadExReq_miss_rate::cpu1.data 0.790838 # miss rate for ReadExReq accesses 2551system.l2c.ReadExReq_miss_rate::total 0.755697 # miss rate for ReadExReq accesses 2552system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.248460 # miss rate for ReadSharedReq accesses 2553system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.016129 # miss rate for ReadSharedReq accesses 2554system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.331638 # miss rate for ReadSharedReq accesses 2555system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.155017 # miss rate for ReadSharedReq accesses 2556system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738458 # miss rate for ReadSharedReq accesses 2557system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.183486 # miss rate for ReadSharedReq accesses 2558system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.225276 # miss rate for ReadSharedReq accesses 2559system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.185740 # miss rate for ReadSharedReq accesses 2560system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542994 # miss rate for ReadSharedReq accesses 2561system.l2c.ReadSharedReq_miss_rate::total 0.501246 # miss rate for ReadSharedReq accesses 2562system.l2c.demand_miss_rate::cpu0.dtb.walker 0.248460 # miss rate for demand accesses 2563system.l2c.demand_miss_rate::cpu0.itb.walker 0.016129 # miss rate for demand accesses 2564system.l2c.demand_miss_rate::cpu0.inst 0.331638 # miss rate for demand accesses 2565system.l2c.demand_miss_rate::cpu0.data 0.277164 # miss rate for demand accesses 2566system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738458 # miss rate for demand accesses 2567system.l2c.demand_miss_rate::cpu1.dtb.walker 0.183486 # miss rate for demand accesses 2568system.l2c.demand_miss_rate::cpu1.inst 0.225276 # miss rate for demand accesses 2569system.l2c.demand_miss_rate::cpu1.data 0.436271 # miss rate for demand accesses 2570system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542994 # miss rate for demand accesses 2571system.l2c.demand_miss_rate::total 0.518690 # miss rate for demand accesses 2572system.l2c.overall_miss_rate::cpu0.dtb.walker 0.248460 # miss rate for overall accesses 2573system.l2c.overall_miss_rate::cpu0.itb.walker 0.016129 # miss rate for overall accesses 2574system.l2c.overall_miss_rate::cpu0.inst 0.331638 # miss rate for overall accesses 2575system.l2c.overall_miss_rate::cpu0.data 0.277164 # miss rate for overall accesses 2576system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738458 # miss rate for overall accesses 2577system.l2c.overall_miss_rate::cpu1.dtb.walker 0.183486 # miss rate for overall accesses 2578system.l2c.overall_miss_rate::cpu1.inst 0.225276 # miss rate for overall accesses 2579system.l2c.overall_miss_rate::cpu1.data 0.436271 # miss rate for overall accesses 2580system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542994 # miss rate for overall accesses 2581system.l2c.overall_miss_rate::total 0.518690 # miss rate for overall accesses 2582system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2332.651743 # average UpgradeReq miss latency 2583system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3419.880952 # average UpgradeReq miss latency 2584system.l2c.UpgradeReq_avg_miss_latency::total 2671.101393 # average UpgradeReq miss latency 2585system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6205.348133 # average SCUpgradeReq miss latency 2586system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2576.569038 # average SCUpgradeReq miss latency 2587system.l2c.SCUpgradeReq_avg_miss_latency::total 4221.637694 # average SCUpgradeReq miss latency 2588system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147940.063521 # average ReadExReq miss latency 2589system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132821.348843 # average ReadExReq miss latency 2590system.l2c.ReadExReq_avg_miss_latency::total 141351.799703 # average ReadExReq miss latency 2591system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 139136.363636 # average ReadSharedReq miss latency 2592system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency 2593system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131008.719182 # average ReadSharedReq miss latency 2594system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137450.115207 # average ReadSharedReq miss latency 2595system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150684.453570 # average ReadSharedReq miss latency 2596system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139412.500000 # average ReadSharedReq miss latency 2597system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132452.329985 # average ReadSharedReq miss latency 2598system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138022.976317 # average ReadSharedReq miss latency 2599system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 166675.561716 # average ReadSharedReq miss latency 2600system.l2c.ReadSharedReq_avg_miss_latency::total 147834.505002 # average ReadSharedReq miss latency 2601system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 139136.363636 # average overall miss latency 2602system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2603system.l2c.demand_avg_miss_latency::cpu0.inst 131008.719182 # average overall miss latency 2604system.l2c.demand_avg_miss_latency::cpu0.data 143318.096447 # average overall miss latency 2605system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150684.453570 # average overall miss latency 2606system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139412.500000 # average overall miss latency 2607system.l2c.demand_avg_miss_latency::cpu1.inst 132452.329985 # average overall miss latency 2608system.l2c.demand_avg_miss_latency::cpu1.data 134119.003527 # average overall miss latency 2609system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 166675.561716 # average overall miss latency 2610system.l2c.demand_avg_miss_latency::total 147187.016855 # average overall miss latency 2611system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 139136.363636 # average overall miss latency 2612system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2613system.l2c.overall_avg_miss_latency::cpu0.inst 131008.719182 # average overall miss latency 2614system.l2c.overall_avg_miss_latency::cpu0.data 143318.096447 # average overall miss latency 2615system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150684.453570 # average overall miss latency 2616system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139412.500000 # average overall miss latency 2617system.l2c.overall_avg_miss_latency::cpu1.inst 132452.329985 # average overall miss latency 2618system.l2c.overall_avg_miss_latency::cpu1.data 134119.003527 # average overall miss latency 2619system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 166675.561716 # average overall miss latency 2620system.l2c.overall_avg_miss_latency::total 147187.016855 # average overall miss latency 2621system.l2c.blocked_cycles::no_mshrs 4 # number of cycles access was blocked 2622system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2623system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked 2624system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2625system.l2c.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked 2626system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2627system.l2c.fast_writes 0 # number of fast writes performed 2628system.l2c.cache_copies 0 # number of cache copies performed 2629system.l2c.writebacks::writebacks 103694 # number of writebacks 2630system.l2c.writebacks::total 103694 # number of writebacks 2631system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 13 # number of ReadSharedReq MSHR hits 2632system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 3 # number of ReadSharedReq MSHR hits 2633system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits 2634system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits 2635system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2636system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 2637system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits 2638system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2639system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits 2640system.l2c.CleanEvict_mshr_misses::writebacks 4308 # number of CleanEvict MSHR misses 2641system.l2c.CleanEvict_mshr_misses::total 4308 # number of CleanEvict MSHR misses 2642system.l2c.UpgradeReq_mshr_misses::cpu0.data 9292 # number of UpgradeReq MSHR misses 2643system.l2c.UpgradeReq_mshr_misses::cpu1.data 4200 # number of UpgradeReq MSHR misses 2644system.l2c.UpgradeReq_mshr_misses::total 13492 # number of UpgradeReq MSHR misses 2645system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 991 # number of SCUpgradeReq MSHR misses 2646system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1195 # number of SCUpgradeReq MSHR misses 2647system.l2c.SCUpgradeReq_mshr_misses::total 2186 # number of SCUpgradeReq MSHR misses 2648system.l2c.ReadExReq_mshr_misses::cpu0.data 11020 # number of ReadExReq MSHR misses 2649system.l2c.ReadExReq_mshr_misses::cpu1.data 8511 # number of ReadExReq MSHR misses 2650system.l2c.ReadExReq_mshr_misses::total 19531 # number of ReadExReq MSHR misses 2651system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 121 # number of ReadSharedReq MSHR misses 2652system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2653system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19943 # number of ReadSharedReq MSHR misses 2654system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8680 # number of ReadSharedReq MSHR misses 2655system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 128666 # number of ReadSharedReq MSHR misses 2656system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 40 # number of ReadSharedReq MSHR misses 2657system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 6070 # number of ReadSharedReq MSHR misses 2658system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2829 # number of ReadSharedReq MSHR misses 2659system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 9649 # number of ReadSharedReq MSHR misses 2660system.l2c.ReadSharedReq_mshr_misses::total 175999 # number of ReadSharedReq MSHR misses 2661system.l2c.demand_mshr_misses::cpu0.dtb.walker 121 # number of demand (read+write) MSHR misses 2662system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2663system.l2c.demand_mshr_misses::cpu0.inst 19943 # number of demand (read+write) MSHR misses 2664system.l2c.demand_mshr_misses::cpu0.data 19700 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128666 # number of demand (read+write) MSHR misses 2666system.l2c.demand_mshr_misses::cpu1.dtb.walker 40 # number of demand (read+write) MSHR misses 2667system.l2c.demand_mshr_misses::cpu1.inst 6070 # number of demand (read+write) MSHR misses 2668system.l2c.demand_mshr_misses::cpu1.data 11340 # number of demand (read+write) MSHR misses 2669system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9649 # number of demand (read+write) MSHR misses 2670system.l2c.demand_mshr_misses::total 195530 # number of demand (read+write) MSHR misses 2671system.l2c.overall_mshr_misses::cpu0.dtb.walker 121 # number of overall MSHR misses 2672system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2673system.l2c.overall_mshr_misses::cpu0.inst 19943 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::cpu0.data 19700 # number of overall MSHR misses 2675system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128666 # number of overall MSHR misses 2676system.l2c.overall_mshr_misses::cpu1.dtb.walker 40 # number of overall MSHR misses 2677system.l2c.overall_mshr_misses::cpu1.inst 6070 # number of overall MSHR misses 2678system.l2c.overall_mshr_misses::cpu1.data 11340 # number of overall MSHR misses 2679system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9649 # number of overall MSHR misses 2680system.l2c.overall_mshr_misses::total 195530 # number of overall MSHR misses 2681system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 2682system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17966 # number of ReadReq MSHR uncacheable 2683system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2684system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17167 # number of ReadReq MSHR uncacheable 2685system.l2c.ReadReq_mshr_uncacheable::total 39162 # number of ReadReq MSHR uncacheable 2686system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16715 # number of WriteReq MSHR uncacheable 2687system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14450 # number of WriteReq MSHR uncacheable 2688system.l2c.WriteReq_mshr_uncacheable::total 31165 # number of WriteReq MSHR uncacheable 2689system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 2690system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34681 # number of overall MSHR uncacheable misses 2691system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2692system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31617 # number of overall MSHR uncacheable misses 2693system.l2c.overall_mshr_uncacheable_misses::total 70327 # number of overall MSHR uncacheable misses 2694system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 676307000 # number of UpgradeReq MSHR miss cycles 2695system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 304978000 # number of UpgradeReq MSHR miss cycles 2696system.l2c.UpgradeReq_mshr_miss_latency::total 981285000 # number of UpgradeReq MSHR miss cycles 2697system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 73607500 # number of SCUpgradeReq MSHR miss cycles 2698system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 88595500 # number of SCUpgradeReq MSHR miss cycles 2699system.l2c.SCUpgradeReq_mshr_miss_latency::total 162203000 # number of SCUpgradeReq MSHR miss cycles 2700system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1520092024 # number of ReadExReq MSHR miss cycles 2701system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1045326512 # number of ReadExReq MSHR miss cycles 2702system.l2c.ReadExReq_mshr_miss_latency::total 2565418536 # number of ReadExReq MSHR miss cycles 2703system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 15625500 # number of ReadSharedReq MSHR miss cycles 2704system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles 2705system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2413902530 # number of ReadSharedReq MSHR miss cycles 2706system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1106263507 # number of ReadSharedReq MSHR miss cycles 2707system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18101270566 # number of ReadSharedReq MSHR miss cycles 2708system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 5176500 # number of ReadSharedReq MSHR miss cycles 2709system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 743387513 # number of ReadSharedReq MSHR miss cycles 2710system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 362172509 # number of ReadSharedReq MSHR miss cycles 2711system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1511742589 # number of ReadSharedReq MSHR miss cycles 2712system.l2c.ReadSharedReq_mshr_miss_latency::total 24259664214 # number of ReadSharedReq MSHR miss cycles 2713system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 15625500 # number of demand (read+write) MSHR miss cycles 2714system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles 2715system.l2c.demand_mshr_miss_latency::cpu0.inst 2413902530 # number of demand (read+write) MSHR miss cycles 2716system.l2c.demand_mshr_miss_latency::cpu0.data 2626355531 # number of demand (read+write) MSHR miss cycles 2717system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18101270566 # number of demand (read+write) MSHR miss cycles 2718system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 5176500 # number of demand (read+write) MSHR miss cycles 2719system.l2c.demand_mshr_miss_latency::cpu1.inst 743387513 # number of demand (read+write) MSHR miss cycles 2720system.l2c.demand_mshr_miss_latency::cpu1.data 1407499021 # number of demand (read+write) MSHR miss cycles 2721system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1511742589 # number of demand (read+write) MSHR miss cycles 2722system.l2c.demand_mshr_miss_latency::total 26825082750 # number of demand (read+write) MSHR miss cycles 2723system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 15625500 # number of overall MSHR miss cycles 2724system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles 2725system.l2c.overall_mshr_miss_latency::cpu0.inst 2413902530 # number of overall MSHR miss cycles 2726system.l2c.overall_mshr_miss_latency::cpu0.data 2626355531 # number of overall MSHR miss cycles 2727system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18101270566 # number of overall MSHR miss cycles 2728system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 5176500 # number of overall MSHR miss cycles 2729system.l2c.overall_mshr_miss_latency::cpu1.inst 743387513 # number of overall MSHR miss cycles 2730system.l2c.overall_mshr_miss_latency::cpu1.data 1407499021 # number of overall MSHR miss cycles 2731system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1511742589 # number of overall MSHR miss cycles 2732system.l2c.overall_mshr_miss_latency::total 26825082750 # number of overall MSHR miss cycles 2733system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles 2734system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3497343514 # number of ReadReq MSHR uncacheable cycles 2735system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12102000 # number of ReadReq MSHR uncacheable cycles 2736system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2685911506 # number of ReadReq MSHR uncacheable cycles 2737system.l2c.ReadReq_mshr_uncacheable_latency::total 6639120020 # number of ReadReq MSHR uncacheable cycles 2738system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2669056502 # number of WriteReq MSHR uncacheable cycles 2739system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2277223001 # number of WriteReq MSHR uncacheable cycles 2740system.l2c.WriteReq_mshr_uncacheable_latency::total 4946279503 # number of WriteReq MSHR uncacheable cycles 2741system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles 2742system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6166400016 # number of overall MSHR uncacheable cycles 2743system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12102000 # number of overall MSHR uncacheable cycles 2744system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4963134507 # number of overall MSHR uncacheable cycles 2745system.l2c.overall_mshr_uncacheable_latency::total 11585399523 # number of overall MSHR uncacheable cycles 2746system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2747system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2748system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.220388 # mshr miss rate for UpgradeReq accesses 2749system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.538255 # mshr miss rate for UpgradeReq accesses 2750system.l2c.UpgradeReq_mshr_miss_rate::total 0.270029 # mshr miss rate for UpgradeReq accesses 2751system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.334797 # mshr miss rate for SCUpgradeReq accesses 2752system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.492377 # mshr miss rate for SCUpgradeReq accesses 2753system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.405792 # mshr miss rate for SCUpgradeReq accesses 2754system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.730624 # mshr miss rate for ReadExReq accesses 2755system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.790838 # mshr miss rate for ReadExReq accesses 2756system.l2c.ReadExReq_mshr_miss_rate::total 0.755697 # mshr miss rate for ReadExReq accesses 2757system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.248460 # mshr miss rate for ReadSharedReq accesses 2758system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.016129 # mshr miss rate for ReadSharedReq accesses 2759system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.331422 # mshr miss rate for ReadSharedReq accesses 2760system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.155017 # mshr miss rate for ReadSharedReq accesses 2761system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738458 # mshr miss rate for ReadSharedReq accesses 2762system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.183486 # mshr miss rate for ReadSharedReq accesses 2763system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.225165 # mshr miss rate for ReadSharedReq accesses 2764system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.185740 # mshr miss rate for ReadSharedReq accesses 2765system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542994 # mshr miss rate for ReadSharedReq accesses 2766system.l2c.ReadSharedReq_mshr_miss_rate::total 0.501200 # mshr miss rate for ReadSharedReq accesses 2767system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.248460 # mshr miss rate for demand accesses 2768system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.016129 # mshr miss rate for demand accesses 2769system.l2c.demand_mshr_miss_rate::cpu0.inst 0.331422 # mshr miss rate for demand accesses 2770system.l2c.demand_mshr_miss_rate::cpu0.data 0.277164 # mshr miss rate for demand accesses 2771system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738458 # mshr miss rate for demand accesses 2772system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.183486 # mshr miss rate for demand accesses 2773system.l2c.demand_mshr_miss_rate::cpu1.inst 0.225165 # mshr miss rate for demand accesses 2774system.l2c.demand_mshr_miss_rate::cpu1.data 0.436271 # mshr miss rate for demand accesses 2775system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542994 # mshr miss rate for demand accesses 2776system.l2c.demand_mshr_miss_rate::total 0.518647 # mshr miss rate for demand accesses 2777system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.248460 # mshr miss rate for overall accesses 2778system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.016129 # mshr miss rate for overall accesses 2779system.l2c.overall_mshr_miss_rate::cpu0.inst 0.331422 # mshr miss rate for overall accesses 2780system.l2c.overall_mshr_miss_rate::cpu0.data 0.277164 # mshr miss rate for overall accesses 2781system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738458 # mshr miss rate for overall accesses 2782system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.183486 # mshr miss rate for overall accesses 2783system.l2c.overall_mshr_miss_rate::cpu1.inst 0.225165 # mshr miss rate for overall accesses 2784system.l2c.overall_mshr_miss_rate::cpu1.data 0.436271 # mshr miss rate for overall accesses 2785system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542994 # mshr miss rate for overall accesses 2786system.l2c.overall_mshr_miss_rate::total 0.518647 # mshr miss rate for overall accesses 2787system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72783.792510 # average UpgradeReq mshr miss latency 2788system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72613.809524 # average UpgradeReq mshr miss latency 2789system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72730.877557 # average UpgradeReq mshr miss latency 2790system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74275.983855 # average SCUpgradeReq mshr miss latency 2791system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 74138.493724 # average SCUpgradeReq mshr miss latency 2792system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74200.823422 # average SCUpgradeReq mshr miss latency 2793system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137939.385118 # average ReadExReq mshr miss latency 2794system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122820.645283 # average ReadExReq mshr miss latency 2795system.l2c.ReadExReq_avg_mshr_miss_latency::total 131351.110337 # average ReadExReq mshr miss latency 2796system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636 # average ReadSharedReq mshr miss latency 2797system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency 2798system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121040.090759 # average ReadSharedReq mshr miss latency 2799system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127449.712788 # average ReadSharedReq mshr miss latency 2800system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928 # average ReadSharedReq mshr miss latency 2801system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average ReadSharedReq mshr miss latency 2802system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average ReadSharedReq mshr miss latency 2803system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128021.388830 # average ReadSharedReq mshr miss latency 2804system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average ReadSharedReq mshr miss latency 2805system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137839.784397 # average ReadSharedReq mshr miss latency 2806system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636 # average overall mshr miss latency 2807system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2808system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121040.090759 # average overall mshr miss latency 2809system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133317.539645 # average overall mshr miss latency 2810system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928 # average overall mshr miss latency 2811system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average overall mshr miss latency 2812system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average overall mshr miss latency 2813system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124118.079453 # average overall mshr miss latency 2814system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average overall mshr miss latency 2815system.l2c.demand_avg_mshr_miss_latency::total 137191.647062 # average overall mshr miss latency 2816system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636 # average overall mshr miss latency 2817system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2818system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121040.090759 # average overall mshr miss latency 2819system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133317.539645 # average overall mshr miss latency 2820system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928 # average overall mshr miss latency 2821system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average overall mshr miss latency 2822system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average overall mshr miss latency 2823system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124118.079453 # average overall mshr miss latency 2824system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average overall mshr miss latency 2825system.l2c.overall_avg_mshr_miss_latency::total 137191.647062 # average overall mshr miss latency 2826system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency 2827system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194664.561616 # average ReadReq mshr uncacheable latency 2828system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency 2829system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156457.826411 # average ReadReq mshr uncacheable latency 2830system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169529.646596 # average ReadReq mshr uncacheable latency 2831system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159680.317200 # average WriteReq mshr uncacheable latency 2832system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157593.287266 # average WriteReq mshr uncacheable latency 2833system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158712.642484 # average WriteReq mshr uncacheable latency 2834system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency 2835system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177803.408668 # average overall mshr uncacheable latency 2836system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency 2837system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 156976.769048 # average overall mshr uncacheable latency 2838system.l2c.overall_avg_mshr_uncacheable_latency::total 164736.154294 # average overall mshr uncacheable latency 2839system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2840system.membus.trans_dist::ReadReq 39162 # Transaction distribution 2841system.membus.trans_dist::ReadResp 215417 # Transaction distribution 2842system.membus.trans_dist::WriteReq 31165 # Transaction distribution 2843system.membus.trans_dist::WriteResp 31165 # Transaction distribution 2844system.membus.trans_dist::WritebackDirty 139900 # Transaction distribution 2845system.membus.trans_dist::CleanEvict 18801 # Transaction distribution 2846system.membus.trans_dist::UpgradeReq 78213 # Transaction distribution 2847system.membus.trans_dist::SCUpgradeReq 41798 # Transaction distribution 2848system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2849system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2850system.membus.trans_dist::ReadExReq 40189 # Transaction distribution 2851system.membus.trans_dist::ReadExResp 19404 # Transaction distribution 2852system.membus.trans_dist::ReadSharedReq 176255 # Transaction distribution 2853system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2854system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) 2855system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2856system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14740 # Packet count per connected master and slave (bytes) 2857system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 671466 # Packet count per connected master and slave (bytes) 2858system.membus.pkt_count_system.l2c.mem_side::total 794158 # Packet count per connected master and slave (bytes) 2859system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) 2860system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) 2861system.membus.pkt_count::total 867115 # Packet count per connected master and slave (bytes) 2862system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) 2863system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2864system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29480 # Cumulative packet size per connected master and slave (bytes) 2865system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19397092 # Cumulative packet size per connected master and slave (bytes) 2866system.membus.pkt_size_system.l2c.mem_side::total 19590708 # Cumulative packet size per connected master and slave (bytes) 2867system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2868system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2869system.membus.pkt_size::total 21908852 # Cumulative packet size per connected master and slave (bytes) 2870system.membus.snoops 125573 # Total snoops (count) 2871system.membus.snoop_fanout::samples 601741 # Request fanout histogram 2872system.membus.snoop_fanout::mean 1 # Request fanout histogram 2873system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2874system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2875system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2876system.membus.snoop_fanout::1 601741 100.00% 100.00% # Request fanout histogram 2877system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2878system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2879system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2880system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2881system.membus.snoop_fanout::total 601741 # Request fanout histogram 2882system.membus.reqLayer0.occupancy 91242999 # Layer occupancy (ticks) 2883system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2884system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) 2885system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2886system.membus.reqLayer2.occupancy 12732000 # Layer occupancy (ticks) 2887system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2888system.membus.reqLayer5.occupancy 1019564727 # Layer occupancy (ticks) 2889system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2890system.membus.respLayer2.occupancy 1144074788 # Layer occupancy (ticks) 2891system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2892system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) 2893system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2894system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2895system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2896system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2897system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2898system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2899system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2900system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2901system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2902system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2903system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2904system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2905system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2906system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2907system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2908system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2909system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2910system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2911system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2912system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2913system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2914system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2915system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2916system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2917system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2918system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2919system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2920system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2921system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2922system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2923system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2924system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2925system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2926system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2927system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2928system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2929system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2930system.realview.ethernet.droppedPackets 0 # number of packets dropped 2931system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 2932system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 2933system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 2934system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 2935system.toL2Bus.snoop_filter.tot_requests 1069309 # Total number of requests made to the snoop filter. 2936system.toL2Bus.snoop_filter.hit_single_requests 577929 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2937system.toL2Bus.snoop_filter.hit_multi_requests 171835 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2938system.toL2Bus.snoop_filter.tot_snoops 21548 # Total number of snoops made to the snoop filter. 2939system.toL2Bus.snoop_filter.hit_single_snoops 20404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2940system.toL2Bus.snoop_filter.hit_multi_snoops 1144 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2941system.toL2Bus.trans_dist::ReadReq 39165 # Transaction distribution 2942system.toL2Bus.trans_dist::ReadResp 514340 # Transaction distribution 2943system.toL2Bus.trans_dist::WriteReq 31165 # Transaction distribution 2944system.toL2Bus.trans_dist::WriteResp 31165 # Transaction distribution 2945system.toL2Bus.trans_dist::WritebackDirty 409596 # Transaction distribution 2946system.toL2Bus.trans_dist::CleanEvict 144328 # Transaction distribution 2947system.toL2Bus.trans_dist::UpgradeReq 114559 # Transaction distribution 2948system.toL2Bus.trans_dist::SCUpgradeReq 44999 # Transaction distribution 2949system.toL2Bus.trans_dist::UpgradeResp 159558 # Transaction distribution 2950system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2951system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 2952system.toL2Bus.trans_dist::ReadExReq 51602 # Transaction distribution 2953system.toL2Bus.trans_dist::ReadExResp 51602 # Transaction distribution 2954system.toL2Bus.trans_dist::ReadSharedReq 475191 # Transaction distribution 2955system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2956system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1207299 # Packet count per connected master and slave (bytes) 2957system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 435215 # Packet count per connected master and slave (bytes) 2958system.toL2Bus.pkt_count::total 1642514 # Packet count per connected master and slave (bytes) 2959system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34510571 # Cumulative packet size per connected master and slave (bytes) 2960system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7361417 # Cumulative packet size per connected master and slave (bytes) 2961system.toL2Bus.pkt_size::total 41871988 # Cumulative packet size per connected master and slave (bytes) 2962system.toL2Bus.snoops 461244 # Total snoops (count) 2963system.toL2Bus.snoop_fanout::samples 963683 # Request fanout histogram 2964system.toL2Bus.snoop_fanout::mean 0.359503 # Request fanout histogram 2965system.toL2Bus.snoop_fanout::stdev 0.482323 # Request fanout histogram 2966system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2967system.toL2Bus.snoop_fanout::0 618380 64.17% 64.17% # Request fanout histogram 2968system.toL2Bus.snoop_fanout::1 344159 35.71% 99.88% # Request fanout histogram 2969system.toL2Bus.snoop_fanout::2 1144 0.12% 100.00% # Request fanout histogram 2970system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2971system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2972system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2973system.toL2Bus.snoop_fanout::total 963683 # Request fanout histogram 2974system.toL2Bus.reqLayer0.occupancy 919452336 # Layer occupancy (ticks) 2975system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2976system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) 2977system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2978system.toL2Bus.respLayer0.occupancy 640437781 # Layer occupancy (ticks) 2979system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2980system.toL2Bus.respLayer1.occupancy 288270065 # Layer occupancy (ticks) 2981system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2982 2983---------- End Simulation Statistics ---------- 2984