stats.txt revision 11336:b318499f676c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.848869 # Number of seconds simulated 4sim_ticks 2848869082500 # Number of ticks simulated 5final_tick 2848869082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 198569 # Simulator instruction rate (inst/s) 8host_op_rate 240456 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4442491449 # Simulator tick rate (ticks/s) 10host_mem_usage 621364 # Number of bytes of host memory used 11host_seconds 641.28 # Real time elapsed on the host 12sim_insts 127338052 # Number of instructions simulated 13sim_ops 154199103 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 8704 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1697856 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1350060 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8564736 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 206784 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 630484 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 333888 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12794304 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1697856 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 206784 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1904640 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8859904 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8877468 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 136 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26529 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 21616 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133824 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3231 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9872 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5217 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 200453 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 138436 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 142827 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 3055 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 595975 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 473893 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 3006363 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 72585 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 221310 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 117200 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4491012 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 595975 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 72585 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 668560 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3109972 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 3116138 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3109972 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 3055 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 595975 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 480045 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 3006363 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 72585 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 221324 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 117200 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7607149 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 200453 # Number of read requests accepted 80system.physmem.writeReqs 142827 # Number of write requests accepted 81system.physmem.readBursts 200453 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 142827 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12818368 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8890624 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12794304 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8877468 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12269 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12614 # Per bank write bursts 93system.physmem.perBankRdBursts::2 13475 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12831 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15664 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12720 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12662 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12956 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12071 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12246 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11615 # Per bank write bursts 102system.physmem.perBankRdBursts::11 10653 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11883 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12836 # Per bank write bursts 105system.physmem.perBankRdBursts::14 12055 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11737 # Per bank write bursts 107system.physmem.perBankWrBursts::0 8758 # Per bank write bursts 108system.physmem.perBankWrBursts::1 9183 # Per bank write bursts 109system.physmem.perBankWrBursts::2 9791 # Per bank write bursts 110system.physmem.perBankWrBursts::3 9102 # Per bank write bursts 111system.physmem.perBankWrBursts::4 8279 # Per bank write bursts 112system.physmem.perBankWrBursts::5 8882 # Per bank write bursts 113system.physmem.perBankWrBursts::6 8907 # Per bank write bursts 114system.physmem.perBankWrBursts::7 8993 # Per bank write bursts 115system.physmem.perBankWrBursts::8 8509 # Per bank write bursts 116system.physmem.perBankWrBursts::9 8693 # Per bank write bursts 117system.physmem.perBankWrBursts::10 8248 # Per bank write bursts 118system.physmem.perBankWrBursts::11 7749 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8519 # Per bank write bursts 120system.physmem.perBankWrBursts::13 8825 # Per bank write bursts 121system.physmem.perBankWrBursts::14 8545 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7933 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 22 # Number of times write queue was full causing retry 125system.physmem.totGap 2848868537000 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 552 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 199873 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 138436 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 88840 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 61310 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 11776 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9520 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7786 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6277 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4618 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3736 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 196 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 132 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2746 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3761 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 5044 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 6227 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6320 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6684 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7381 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8081 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 8106 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 8854 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 9840 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 9037 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 9314 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 11658 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 9319 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8372 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 8119 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 1314 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 323 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 109 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 122 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 108 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 84 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 92557 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 234.543816 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 133.254652 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 297.662523 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 50344 54.39% 54.39% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17979 19.42% 73.82% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6295 6.80% 80.62% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3544 3.83% 84.45% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2825 3.05% 87.50% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1428 1.54% 89.04% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 907 0.98% 90.02% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1020 1.10% 91.12% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8215 8.88% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 92557 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6759 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 29.632490 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 567.452985 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6758 99.99% 99.99% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::total 6759 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6759 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 20.552744 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 18.790179 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 13.439026 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-19 5671 83.90% 83.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20-23 455 6.73% 90.63% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::24-27 79 1.17% 91.80% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::28-31 48 0.71% 92.51% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::32-35 32 0.47% 92.99% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::36-39 21 0.31% 93.30% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::40-43 53 0.78% 94.08% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::44-47 14 0.21% 94.29% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::48-51 132 1.95% 96.24% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::52-55 15 0.22% 96.46% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::56-59 4 0.06% 96.52% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::60-63 13 0.19% 96.72% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-67 74 1.09% 97.81% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::68-71 5 0.07% 97.88% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::72-75 3 0.04% 97.93% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::76-79 26 0.38% 98.31% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::80-83 85 1.26% 99.57% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::92-95 1 0.01% 99.62% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::96-99 3 0.04% 99.66% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::104-107 2 0.03% 99.69% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::120-123 1 0.01% 99.70% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::128-131 6 0.09% 99.79% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::136-139 2 0.03% 99.82% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::176-179 4 0.06% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::total 6759 # Writes before turning the bus around for reads 290system.physmem.totQLat 5409044047 # Total ticks spent queuing 291system.physmem.totMemAccLat 9164425297 # Total ticks spent from burst creation until serviced by the DRAM 292system.physmem.totBusLat 1001435000 # Total ticks spent in databus transfers 293system.physmem.avgQLat 27006.47 # Average queueing delay per DRAM burst 294system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 295system.physmem.avgMemAccLat 45756.47 # Average memory access latency per DRAM burst 296system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s 297system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s 298system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s 299system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 301system.physmem.busUtil 0.06 # Data bus utilization in percentage 302system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 303system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 304system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 305system.physmem.avgWrQLen 25.87 # Average write queue length when enqueuing 306system.physmem.readRowHits 166261 # Number of row buffer hits during reads 307system.physmem.writeRowHits 80380 # Number of row buffer hits during writes 308system.physmem.readRowHitRate 83.01 # Row buffer hit rate for reads 309system.physmem.writeRowHitRate 57.86 # Row buffer hit rate for writes 310system.physmem.avgGap 8298964.51 # Average gap between requests 311system.physmem.pageHitRate 72.71 # Row buffer hit rate, read and write combined 312system.physmem_0.actEnergy 368829720 # Energy for activate commands per rank (pJ) 313system.physmem_0.preEnergy 201246375 # Energy for precharge commands per rank (pJ) 314system.physmem_0.readEnergy 820489800 # Energy for read commands per rank (pJ) 315system.physmem_0.writeEnergy 465801840 # Energy for write commands per rank (pJ) 316system.physmem_0.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) 317system.physmem_0.actBackEnergy 85113851220 # Energy for active background per rank (pJ) 318system.physmem_0.preBackEnergy 1634657451750 # Energy for precharge background per rank (pJ) 319system.physmem_0.totalEnergy 1907701637745 # Total energy per rank (pJ) 320system.physmem_0.averagePower 669.635783 # Core power per rank (mW) 321system.physmem_0.memoryStateTime::IDLE 2719265528725 # Time in different power states 322system.physmem_0.memoryStateTime::REF 95129840000 # Time in different power states 323system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 324system.physmem_0.memoryStateTime::ACT 34469380775 # Time in different power states 325system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 326system.physmem_1.actEnergy 330840720 # Energy for activate commands per rank (pJ) 327system.physmem_1.preEnergy 180518250 # Energy for precharge commands per rank (pJ) 328system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) 329system.physmem_1.writeEnergy 434257200 # Energy for write commands per rank (pJ) 330system.physmem_1.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) 331system.physmem_1.actBackEnergy 83792356380 # Energy for active background per rank (pJ) 332system.physmem_1.preBackEnergy 1635816657750 # Energy for precharge background per rank (pJ) 333system.physmem_1.totalEnergy 1907370338340 # Total energy per rank (pJ) 334system.physmem_1.averagePower 669.519491 # Core power per rank (mW) 335system.physmem_1.memoryStateTime::IDLE 2721199868682 # Time in different power states 336system.physmem_1.memoryStateTime::REF 95129840000 # Time in different power states 337system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 338system.physmem_1.memoryStateTime::ACT 32535082068 # Time in different power states 339system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 340system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 346system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 349system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 358system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 359system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 360system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 361system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 362system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 363system.cf0.dma_write_txs 631 # Number of DMA write transactions. 364system.cpu0.branchPred.lookups 36420174 # Number of BP lookups 365system.cpu0.branchPred.condPredicted 17682232 # Number of conditional branches predicted 366system.cpu0.branchPred.condIncorrect 1669191 # Number of conditional branches incorrect 367system.cpu0.branchPred.BTBLookups 20721489 # Number of BTB lookups 368system.cpu0.branchPred.BTBHits 15026104 # Number of BTB hits 369system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 370system.cpu0.branchPred.BTBHitPct 72.514596 # BTB Hit Percentage 371system.cpu0.branchPred.usedRAS 11397312 # Number of times the RAS was used to get a target. 372system.cpu0.branchPred.RASInCorrect 800928 # Number of incorrect RAS predictions. 373system.cpu_clk_domain.clock 500 # Clock period in ticks 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 383system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 384system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 385system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 386system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 387system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 388system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 389system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 390system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 391system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 392system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 393system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 394system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 395system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 398system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 399system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 400system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 401system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 402system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 403system.cpu0.dtb.walker.walks 73306 # Table walker walks requested 404system.cpu0.dtb.walker.walksShort 73306 # Table walker walks initiated with short descriptors 405system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47488 # Level at which table walker walks with short descriptors terminate 406system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25818 # Level at which table walker walks with short descriptors terminate 407system.cpu0.dtb.walker.walkWaitTime::samples 73306 # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::0 73306 100.00% 100.00% # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::total 73306 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkCompletionTime::samples 7529 # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::mean 12317.505645 # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.047410 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::stdev 7148.063589 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::0-32767 7474 99.27% 99.27% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::32768-65535 46 0.61% 99.88% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.97% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::total 7529 # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution 421system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution 422system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution 423system.cpu0.dtb.walker.walkPageSizes::4K 5847 77.66% 77.66% # Table walker page sizes translated 424system.cpu0.dtb.walker.walkPageSizes::1M 1682 22.34% 100.00% # Table walker page sizes translated 425system.cpu0.dtb.walker.walkPageSizes::total 7529 # Table walker page sizes translated 426system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73306 # Table walker requests started/completed, data/inst 427system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73306 # Table walker requests started/completed, data/inst 429system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7529 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7529 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin::total 80835 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.inst_hits 0 # ITB inst hits 434system.cpu0.dtb.inst_misses 0 # ITB inst misses 435system.cpu0.dtb.read_hits 24946697 # DTB read hits 436system.cpu0.dtb.read_misses 66576 # DTB read misses 437system.cpu0.dtb.write_hits 18555175 # DTB write hits 438system.cpu0.dtb.write_misses 6730 # DTB write misses 439system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 440system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 441system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 443system.cpu0.dtb.flush_entries 3812 # Number of entries that have been flushed from TLB 444system.cpu0.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions 445system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch 446system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions 448system.cpu0.dtb.read_accesses 25013273 # DTB read accesses 449system.cpu0.dtb.write_accesses 18561905 # DTB write accesses 450system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu0.dtb.hits 43501872 # DTB hits 452system.cpu0.dtb.misses 73306 # DTB misses 453system.cpu0.dtb.accesses 43575178 # DTB accesses 454system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 455system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 463system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 464system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 465system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 466system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 467system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 468system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 469system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 470system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 471system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 472system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 473system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 474system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 475system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 476system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 477system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 478system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 479system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 480system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 481system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 482system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 483system.cpu0.itb.walker.walks 4169 # Table walker walks requested 484system.cpu0.itb.walker.walksShort 4169 # Table walker walks initiated with short descriptors 485system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate 486system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3845 # Level at which table walker walks with short descriptors terminate 487system.cpu0.itb.walker.walkWaitTime::samples 4169 # Table walker wait (enqueue to first request) latency 488system.cpu0.itb.walker.walkWaitTime::0 4169 100.00% 100.00% # Table walker wait (enqueue to first request) latency 489system.cpu0.itb.walker.walkWaitTime::total 4169 # Table walker wait (enqueue to first request) latency 490system.cpu0.itb.walker.walkCompletionTime::samples 2671 # Table walker service (enqueue to completion) latency 491system.cpu0.itb.walker.walkCompletionTime::mean 12688.506177 # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::gmean 11997.245115 # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::stdev 5018.704234 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::0-16383 2423 90.72% 90.72% # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::16384-32767 228 8.54% 99.25% # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::32768-49151 18 0.67% 99.93% # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::total 2671 # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution 501system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution 502system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution 503system.cpu0.itb.walker.walkPageSizes::4K 2352 88.06% 88.06% # Table walker page sizes translated 504system.cpu0.itb.walker.walkPageSizes::1M 319 11.94% 100.00% # Table walker page sizes translated 505system.cpu0.itb.walker.walkPageSizes::total 2671 # Table walker page sizes translated 506system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 507system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4169 # Table walker requests started/completed, data/inst 508system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4169 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 510system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2671 # Table walker requests started/completed, data/inst 511system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2671 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin::total 6840 # Table walker requests started/completed, data/inst 513system.cpu0.itb.inst_hits 71444406 # ITB inst hits 514system.cpu0.itb.inst_misses 4169 # ITB inst misses 515system.cpu0.itb.read_hits 0 # DTB read hits 516system.cpu0.itb.read_misses 0 # DTB read misses 517system.cpu0.itb.write_hits 0 # DTB write hits 518system.cpu0.itb.write_misses 0 # DTB write misses 519system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 520system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 521system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 522system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 523system.cpu0.itb.flush_entries 2449 # Number of entries that have been flushed from TLB 524system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu0.itb.perms_faults 8126 # Number of TLB faults due to permissions restrictions 528system.cpu0.itb.read_accesses 0 # DTB read accesses 529system.cpu0.itb.write_accesses 0 # DTB write accesses 530system.cpu0.itb.inst_accesses 71448575 # ITB inst accesses 531system.cpu0.itb.hits 71444406 # DTB hits 532system.cpu0.itb.misses 4169 # DTB misses 533system.cpu0.itb.accesses 71448575 # DTB accesses 534system.cpu0.numCycles 248815256 # number of cpu cycles simulated 535system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 536system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 537system.cpu0.committedInsts 113230333 # Number of instructions committed 538system.cpu0.committedOps 136910947 # Number of ops (including micro ops) committed 539system.cpu0.discardedOps 8928789 # Number of ops (including micro ops) which were discarded before commit 540system.cpu0.numFetchSuspends 1886 # Number of times Execute suspended instruction fetching 541system.cpu0.quiesceCycles 5448949721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 542system.cpu0.cpi 2.197426 # CPI: cycles per instruction 543system.cpu0.ipc 0.455078 # IPC: instructions per cycle 544system.cpu0.kern.inst.arm 0 # number of arm instructions executed 545system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed 546system.cpu0.tickCycles 199822657 # Number of cycles that the object actually ticked 547system.cpu0.idleCycles 48992599 # Total number of cycles that the object has spent stopped 548system.cpu0.dcache.tags.replacements 758548 # number of replacements 549system.cpu0.dcache.tags.tagsinuse 499.039628 # Cycle average of tags in use 550system.cpu0.dcache.tags.total_refs 41909246 # Total number of references to valid blocks. 551system.cpu0.dcache.tags.sampled_refs 759060 # Sample count of references to valid blocks. 552system.cpu0.dcache.tags.avg_refs 55.212033 # Average number of references to valid blocks. 553system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. 554system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.039628 # Average occupied blocks per requestor 555system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974687 # Average percentage of cache occupancy 556system.cpu0.dcache.tags.occ_percent::total 0.974687 # Average percentage of cache occupancy 557system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 558system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 559system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 560system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 561system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 562system.cpu0.dcache.tags.tag_accesses 86968977 # Number of tag accesses 563system.cpu0.dcache.tags.data_accesses 86968977 # Number of data accesses 564system.cpu0.dcache.ReadReq_hits::cpu0.data 23338731 # number of ReadReq hits 565system.cpu0.dcache.ReadReq_hits::total 23338731 # number of ReadReq hits 566system.cpu0.dcache.WriteReq_hits::cpu0.data 17382396 # number of WriteReq hits 567system.cpu0.dcache.WriteReq_hits::total 17382396 # number of WriteReq hits 568system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329314 # number of SoftPFReq hits 569system.cpu0.dcache.SoftPFReq_hits::total 329314 # number of SoftPFReq hits 570system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374886 # number of LoadLockedReq hits 571system.cpu0.dcache.LoadLockedReq_hits::total 374886 # number of LoadLockedReq hits 572system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370842 # number of StoreCondReq hits 573system.cpu0.dcache.StoreCondReq_hits::total 370842 # number of StoreCondReq hits 574system.cpu0.dcache.demand_hits::cpu0.data 40721127 # number of demand (read+write) hits 575system.cpu0.dcache.demand_hits::total 40721127 # number of demand (read+write) hits 576system.cpu0.dcache.overall_hits::cpu0.data 41050441 # number of overall hits 577system.cpu0.dcache.overall_hits::total 41050441 # number of overall hits 578system.cpu0.dcache.ReadReq_misses::cpu0.data 492920 # number of ReadReq misses 579system.cpu0.dcache.ReadReq_misses::total 492920 # number of ReadReq misses 580system.cpu0.dcache.WriteReq_misses::cpu0.data 604804 # number of WriteReq misses 581system.cpu0.dcache.WriteReq_misses::total 604804 # number of WriteReq misses 582system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141961 # number of SoftPFReq misses 583system.cpu0.dcache.SoftPFReq_misses::total 141961 # number of SoftPFReq misses 584system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21406 # number of LoadLockedReq misses 585system.cpu0.dcache.LoadLockedReq_misses::total 21406 # number of LoadLockedReq misses 586system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20501 # number of StoreCondReq misses 587system.cpu0.dcache.StoreCondReq_misses::total 20501 # number of StoreCondReq misses 588system.cpu0.dcache.demand_misses::cpu0.data 1097724 # number of demand (read+write) misses 589system.cpu0.dcache.demand_misses::total 1097724 # number of demand (read+write) misses 590system.cpu0.dcache.overall_misses::cpu0.data 1239685 # number of overall misses 591system.cpu0.dcache.overall_misses::total 1239685 # number of overall misses 592system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6985498500 # number of ReadReq miss cycles 593system.cpu0.dcache.ReadReq_miss_latency::total 6985498500 # number of ReadReq miss cycles 594system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12567334500 # number of WriteReq miss cycles 595system.cpu0.dcache.WriteReq_miss_latency::total 12567334500 # number of WriteReq miss cycles 596system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329657000 # number of LoadLockedReq miss cycles 597system.cpu0.dcache.LoadLockedReq_miss_latency::total 329657000 # number of LoadLockedReq miss cycles 598system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 538169500 # number of StoreCondReq miss cycles 599system.cpu0.dcache.StoreCondReq_miss_latency::total 538169500 # number of StoreCondReq miss cycles 600system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1008000 # number of StoreCondFailReq miss cycles 601system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1008000 # number of StoreCondFailReq miss cycles 602system.cpu0.dcache.demand_miss_latency::cpu0.data 19552833000 # number of demand (read+write) miss cycles 603system.cpu0.dcache.demand_miss_latency::total 19552833000 # number of demand (read+write) miss cycles 604system.cpu0.dcache.overall_miss_latency::cpu0.data 19552833000 # number of overall miss cycles 605system.cpu0.dcache.overall_miss_latency::total 19552833000 # number of overall miss cycles 606system.cpu0.dcache.ReadReq_accesses::cpu0.data 23831651 # number of ReadReq accesses(hits+misses) 607system.cpu0.dcache.ReadReq_accesses::total 23831651 # number of ReadReq accesses(hits+misses) 608system.cpu0.dcache.WriteReq_accesses::cpu0.data 17987200 # number of WriteReq accesses(hits+misses) 609system.cpu0.dcache.WriteReq_accesses::total 17987200 # number of WriteReq accesses(hits+misses) 610system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471275 # number of SoftPFReq accesses(hits+misses) 611system.cpu0.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses) 612system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396292 # number of LoadLockedReq accesses(hits+misses) 613system.cpu0.dcache.LoadLockedReq_accesses::total 396292 # number of LoadLockedReq accesses(hits+misses) 614system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391343 # number of StoreCondReq accesses(hits+misses) 615system.cpu0.dcache.StoreCondReq_accesses::total 391343 # number of StoreCondReq accesses(hits+misses) 616system.cpu0.dcache.demand_accesses::cpu0.data 41818851 # number of demand (read+write) accesses 617system.cpu0.dcache.demand_accesses::total 41818851 # number of demand (read+write) accesses 618system.cpu0.dcache.overall_accesses::cpu0.data 42290126 # number of overall (read+write) accesses 619system.cpu0.dcache.overall_accesses::total 42290126 # number of overall (read+write) accesses 620system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020683 # miss rate for ReadReq accesses 621system.cpu0.dcache.ReadReq_miss_rate::total 0.020683 # miss rate for ReadReq accesses 622system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033624 # miss rate for WriteReq accesses 623system.cpu0.dcache.WriteReq_miss_rate::total 0.033624 # miss rate for WriteReq accesses 624system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301228 # miss rate for SoftPFReq accesses 625system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301228 # miss rate for SoftPFReq accesses 626system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054016 # miss rate for LoadLockedReq accesses 627system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054016 # miss rate for LoadLockedReq accesses 628system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052386 # miss rate for StoreCondReq accesses 629system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052386 # miss rate for StoreCondReq accesses 630system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026250 # miss rate for demand accesses 631system.cpu0.dcache.demand_miss_rate::total 0.026250 # miss rate for demand accesses 632system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029314 # miss rate for overall accesses 633system.cpu0.dcache.overall_miss_rate::total 0.029314 # miss rate for overall accesses 634system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14171.667816 # average ReadReq miss latency 635system.cpu0.dcache.ReadReq_avg_miss_latency::total 14171.667816 # average ReadReq miss latency 636system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20779.185488 # average WriteReq miss latency 637system.cpu0.dcache.WriteReq_avg_miss_latency::total 20779.185488 # average WriteReq miss latency 638system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15400.214893 # average LoadLockedReq miss latency 639system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15400.214893 # average LoadLockedReq miss latency 640system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26250.890200 # average StoreCondReq miss latency 641system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26250.890200 # average StoreCondReq miss latency 642system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 643system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 644system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17812.157701 # average overall miss latency 645system.cpu0.dcache.demand_avg_miss_latency::total 17812.157701 # average overall miss latency 646system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15772.420413 # average overall miss latency 647system.cpu0.dcache.overall_avg_miss_latency::total 15772.420413 # average overall miss latency 648system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 649system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 651system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 653system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 654system.cpu0.dcache.fast_writes 0 # number of fast writes performed 655system.cpu0.dcache.cache_copies 0 # number of cache copies performed 656system.cpu0.dcache.writebacks::writebacks 758548 # number of writebacks 657system.cpu0.dcache.writebacks::total 758548 # number of writebacks 658system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75935 # number of ReadReq MSHR hits 659system.cpu0.dcache.ReadReq_mshr_hits::total 75935 # number of ReadReq MSHR hits 660system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266250 # number of WriteReq MSHR hits 661system.cpu0.dcache.WriteReq_mshr_hits::total 266250 # number of WriteReq MSHR hits 662system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14874 # number of LoadLockedReq MSHR hits 663system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14874 # number of LoadLockedReq MSHR hits 664system.cpu0.dcache.demand_mshr_hits::cpu0.data 342185 # number of demand (read+write) MSHR hits 665system.cpu0.dcache.demand_mshr_hits::total 342185 # number of demand (read+write) MSHR hits 666system.cpu0.dcache.overall_mshr_hits::cpu0.data 342185 # number of overall MSHR hits 667system.cpu0.dcache.overall_mshr_hits::total 342185 # number of overall MSHR hits 668system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416985 # number of ReadReq MSHR misses 669system.cpu0.dcache.ReadReq_mshr_misses::total 416985 # number of ReadReq MSHR misses 670system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 338554 # number of WriteReq MSHR misses 671system.cpu0.dcache.WriteReq_mshr_misses::total 338554 # number of WriteReq MSHR misses 672system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108405 # number of SoftPFReq MSHR misses 673system.cpu0.dcache.SoftPFReq_mshr_misses::total 108405 # number of SoftPFReq MSHR misses 674system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6532 # number of LoadLockedReq MSHR misses 675system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6532 # number of LoadLockedReq MSHR misses 676system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20501 # number of StoreCondReq MSHR misses 677system.cpu0.dcache.StoreCondReq_mshr_misses::total 20501 # number of StoreCondReq MSHR misses 678system.cpu0.dcache.demand_mshr_misses::cpu0.data 755539 # number of demand (read+write) MSHR misses 679system.cpu0.dcache.demand_mshr_misses::total 755539 # number of demand (read+write) MSHR misses 680system.cpu0.dcache.overall_mshr_misses::cpu0.data 863944 # number of overall MSHR misses 681system.cpu0.dcache.overall_mshr_misses::total 863944 # number of overall MSHR misses 682system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32039 # number of ReadReq MSHR uncacheable 683system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32039 # number of ReadReq MSHR uncacheable 684system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable 685system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable 686system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60761 # number of overall MSHR uncacheable misses 687system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60761 # number of overall MSHR uncacheable misses 688system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289891000 # number of ReadReq MSHR miss cycles 689system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289891000 # number of ReadReq MSHR miss cycles 690system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7113543500 # number of WriteReq MSHR miss cycles 691system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7113543500 # number of WriteReq MSHR miss cycles 692system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1810098500 # number of SoftPFReq MSHR miss cycles 693system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810098500 # number of SoftPFReq MSHR miss cycles 694system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104404500 # number of LoadLockedReq MSHR miss cycles 695system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104404500 # number of LoadLockedReq MSHR miss cycles 696system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 517681500 # number of StoreCondReq MSHR miss cycles 697system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 517681500 # number of StoreCondReq MSHR miss cycles 698system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 995000 # number of StoreCondFailReq MSHR miss cycles 699system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 995000 # number of StoreCondFailReq MSHR miss cycles 700system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403434500 # number of demand (read+write) MSHR miss cycles 701system.cpu0.dcache.demand_mshr_miss_latency::total 12403434500 # number of demand (read+write) MSHR miss cycles 702system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14213533000 # number of overall MSHR miss cycles 703system.cpu0.dcache.overall_mshr_miss_latency::total 14213533000 # number of overall MSHR miss cycles 704system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6701732000 # number of ReadReq MSHR uncacheable cycles 705system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6701732000 # number of ReadReq MSHR uncacheable cycles 706system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452636000 # number of WriteReq MSHR uncacheable cycles 707system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452636000 # number of WriteReq MSHR uncacheable cycles 708system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12154368000 # number of overall MSHR uncacheable cycles 709system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12154368000 # number of overall MSHR uncacheable cycles 710system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017497 # mshr miss rate for ReadReq accesses 711system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017497 # mshr miss rate for ReadReq accesses 712system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses 713system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses 714system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230025 # mshr miss rate for SoftPFReq accesses 715system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230025 # mshr miss rate for SoftPFReq accesses 716system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016483 # mshr miss rate for LoadLockedReq accesses 717system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016483 # mshr miss rate for LoadLockedReq accesses 718system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052386 # mshr miss rate for StoreCondReq accesses 719system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052386 # mshr miss rate for StoreCondReq accesses 720system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018067 # mshr miss rate for demand accesses 721system.cpu0.dcache.demand_mshr_miss_rate::total 0.018067 # mshr miss rate for demand accesses 722system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020429 # mshr miss rate for overall accesses 723system.cpu0.dcache.overall_mshr_miss_rate::total 0.020429 # mshr miss rate for overall accesses 724system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12686.046261 # average ReadReq mshr miss latency 725system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12686.046261 # average ReadReq mshr miss latency 726system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21011.547641 # average WriteReq mshr miss latency 727system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21011.547641 # average WriteReq mshr miss latency 728system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16697.555463 # average SoftPFReq mshr miss latency 729system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16697.555463 # average SoftPFReq mshr miss latency 730system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.542560 # average LoadLockedReq mshr miss latency 731system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.542560 # average LoadLockedReq mshr miss latency 732system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25251.524316 # average StoreCondReq mshr miss latency 733system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25251.524316 # average StoreCondReq mshr miss latency 734system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 735system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 736system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16416.670086 # average overall mshr miss latency 737system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16416.670086 # average overall mshr miss latency 738system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16451.914707 # average overall mshr miss latency 739system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16451.914707 # average overall mshr miss latency 740system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.193951 # average ReadReq mshr uncacheable latency 741system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.193951 # average ReadReq mshr uncacheable latency 742system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189841.793747 # average WriteReq mshr uncacheable latency 743system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189841.793747 # average WriteReq mshr uncacheable latency 744system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200035.680782 # average overall mshr uncacheable latency 745system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200035.680782 # average overall mshr uncacheable latency 746system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 747system.cpu0.icache.tags.replacements 2044571 # number of replacements 748system.cpu0.icache.tags.tagsinuse 511.728044 # Cycle average of tags in use 749system.cpu0.icache.tags.total_refs 69390799 # Total number of references to valid blocks. 750system.cpu0.icache.tags.sampled_refs 2045083 # Sample count of references to valid blocks. 751system.cpu0.icache.tags.avg_refs 33.930554 # Average number of references to valid blocks. 752system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit. 753system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728044 # Average occupied blocks per requestor 754system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999469 # Average percentage of cache occupancy 755system.cpu0.icache.tags.occ_percent::total 0.999469 # Average percentage of cache occupancy 756system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 757system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 758system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 759system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id 760system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 761system.cpu0.icache.tags.tag_accesses 144916894 # Number of tag accesses 762system.cpu0.icache.tags.data_accesses 144916894 # Number of data accesses 763system.cpu0.icache.ReadReq_hits::cpu0.inst 69390799 # number of ReadReq hits 764system.cpu0.icache.ReadReq_hits::total 69390799 # number of ReadReq hits 765system.cpu0.icache.demand_hits::cpu0.inst 69390799 # number of demand (read+write) hits 766system.cpu0.icache.demand_hits::total 69390799 # number of demand (read+write) hits 767system.cpu0.icache.overall_hits::cpu0.inst 69390799 # number of overall hits 768system.cpu0.icache.overall_hits::total 69390799 # number of overall hits 769system.cpu0.icache.ReadReq_misses::cpu0.inst 2045099 # number of ReadReq misses 770system.cpu0.icache.ReadReq_misses::total 2045099 # number of ReadReq misses 771system.cpu0.icache.demand_misses::cpu0.inst 2045099 # number of demand (read+write) misses 772system.cpu0.icache.demand_misses::total 2045099 # number of demand (read+write) misses 773system.cpu0.icache.overall_misses::cpu0.inst 2045099 # number of overall misses 774system.cpu0.icache.overall_misses::total 2045099 # number of overall misses 775system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20582559000 # number of ReadReq miss cycles 776system.cpu0.icache.ReadReq_miss_latency::total 20582559000 # number of ReadReq miss cycles 777system.cpu0.icache.demand_miss_latency::cpu0.inst 20582559000 # number of demand (read+write) miss cycles 778system.cpu0.icache.demand_miss_latency::total 20582559000 # number of demand (read+write) miss cycles 779system.cpu0.icache.overall_miss_latency::cpu0.inst 20582559000 # number of overall miss cycles 780system.cpu0.icache.overall_miss_latency::total 20582559000 # number of overall miss cycles 781system.cpu0.icache.ReadReq_accesses::cpu0.inst 71435898 # number of ReadReq accesses(hits+misses) 782system.cpu0.icache.ReadReq_accesses::total 71435898 # number of ReadReq accesses(hits+misses) 783system.cpu0.icache.demand_accesses::cpu0.inst 71435898 # number of demand (read+write) accesses 784system.cpu0.icache.demand_accesses::total 71435898 # number of demand (read+write) accesses 785system.cpu0.icache.overall_accesses::cpu0.inst 71435898 # number of overall (read+write) accesses 786system.cpu0.icache.overall_accesses::total 71435898 # number of overall (read+write) accesses 787system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028628 # miss rate for ReadReq accesses 788system.cpu0.icache.ReadReq_miss_rate::total 0.028628 # miss rate for ReadReq accesses 789system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028628 # miss rate for demand accesses 790system.cpu0.icache.demand_miss_rate::total 0.028628 # miss rate for demand accesses 791system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028628 # miss rate for overall accesses 792system.cpu0.icache.overall_miss_rate::total 0.028628 # miss rate for overall accesses 793system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.333805 # average ReadReq miss latency 794system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.333805 # average ReadReq miss latency 795system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency 796system.cpu0.icache.demand_avg_miss_latency::total 10064.333805 # average overall miss latency 797system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency 798system.cpu0.icache.overall_avg_miss_latency::total 10064.333805 # average overall miss latency 799system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu0.icache.fast_writes 0 # number of fast writes performed 806system.cpu0.icache.cache_copies 0 # number of cache copies performed 807system.cpu0.icache.writebacks::writebacks 2044571 # number of writebacks 808system.cpu0.icache.writebacks::total 2044571 # number of writebacks 809system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2045099 # number of ReadReq MSHR misses 810system.cpu0.icache.ReadReq_mshr_misses::total 2045099 # number of ReadReq MSHR misses 811system.cpu0.icache.demand_mshr_misses::cpu0.inst 2045099 # number of demand (read+write) MSHR misses 812system.cpu0.icache.demand_mshr_misses::total 2045099 # number of demand (read+write) MSHR misses 813system.cpu0.icache.overall_mshr_misses::cpu0.inst 2045099 # number of overall MSHR misses 814system.cpu0.icache.overall_mshr_misses::total 2045099 # number of overall MSHR misses 815system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 816system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable 817system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 818system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses 819system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19560010000 # number of ReadReq MSHR miss cycles 820system.cpu0.icache.ReadReq_mshr_miss_latency::total 19560010000 # number of ReadReq MSHR miss cycles 821system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19560010000 # number of demand (read+write) MSHR miss cycles 822system.cpu0.icache.demand_mshr_miss_latency::total 19560010000 # number of demand (read+write) MSHR miss cycles 823system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19560010000 # number of overall MSHR miss cycles 824system.cpu0.icache.overall_mshr_miss_latency::total 19560010000 # number of overall MSHR miss cycles 825system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles 826system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles 827system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles 828system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles 829system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for ReadReq accesses 830system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028628 # mshr miss rate for ReadReq accesses 831system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for demand accesses 832system.cpu0.icache.demand_mshr_miss_rate::total 0.028628 # mshr miss rate for demand accesses 833system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for overall accesses 834system.cpu0.icache.overall_mshr_miss_rate::total 0.028628 # mshr miss rate for overall accesses 835system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average ReadReq mshr miss latency 836system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.334049 # average ReadReq mshr miss latency 837system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency 838system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency 839system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency 840system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency 841system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency 842system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency 843system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency 844system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency 845system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 846system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927519 # number of hwpf issued 847system.cpu0.l2cache.prefetcher.pfIdentified 1927689 # number of prefetch candidates identified 848system.cpu0.l2cache.prefetcher.pfBufferHit 149 # number of redundant prefetches already in prefetch queue 849system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 850system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 851system.cpu0.l2cache.prefetcher.pfSpanPage 245495 # number of prefetches not generated due to page crossing 852system.cpu0.l2cache.tags.replacements 305066 # number of replacements 853system.cpu0.l2cache.tags.tagsinuse 16110.532476 # Cycle average of tags in use 854system.cpu0.l2cache.tags.total_refs 4906564 # Total number of references to valid blocks. 855system.cpu0.l2cache.tags.sampled_refs 321213 # Sample count of references to valid blocks. 856system.cpu0.l2cache.tags.avg_refs 15.275110 # Average number of references to valid blocks. 857system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 858system.cpu0.l2cache.tags.occ_blocks::writebacks 14727.121799 # Average occupied blocks per requestor 859system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.543151 # Average occupied blocks per requestor 860system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067969 # Average occupied blocks per requestor 861system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1324.799556 # Average occupied blocks per requestor 862system.cpu0.l2cache.tags.occ_percent::writebacks 0.898872 # Average percentage of cache occupancy 863system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003573 # Average percentage of cache occupancy 864system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 865system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.080859 # Average percentage of cache occupancy 866system.cpu0.l2cache.tags.occ_percent::total 0.983309 # Average percentage of cache occupancy 867system.cpu0.l2cache.tags.occ_task_id_blocks::1022 972 # Occupied blocks per task id 868system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 869system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15166 # Occupied blocks per task id 870system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 871system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 324 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 411 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 226 # Occupied blocks per task id 874system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 875system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4092 # Occupied blocks per task id 881system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8366 # Occupied blocks per task id 882system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2250 # Occupied blocks per task id 883system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059326 # Percentage of cache occupancy per task id 884system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 885system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925659 # Percentage of cache occupancy per task id 886system.cpu0.l2cache.tags.tag_accesses 93458654 # Number of tag accesses 887system.cpu0.l2cache.tags.data_accesses 93458654 # Number of data accesses 888system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 89935 # number of ReadReq hits 889system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5689 # number of ReadReq hits 890system.cpu0.l2cache.ReadReq_hits::total 95624 # number of ReadReq hits 891system.cpu0.l2cache.WritebackDirty_hits::writebacks 507120 # number of WritebackDirty hits 892system.cpu0.l2cache.WritebackDirty_hits::total 507120 # number of WritebackDirty hits 893system.cpu0.l2cache.WritebackClean_hits::writebacks 2250930 # number of WritebackClean hits 894system.cpu0.l2cache.WritebackClean_hits::total 2250930 # number of WritebackClean hits 895system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233801 # number of ReadExReq hits 896system.cpu0.l2cache.ReadExReq_hits::total 233801 # number of ReadExReq hits 897system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1975273 # number of ReadCleanReq hits 898system.cpu0.l2cache.ReadCleanReq_hits::total 1975273 # number of ReadCleanReq hits 899system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 431015 # number of ReadSharedReq hits 900system.cpu0.l2cache.ReadSharedReq_hits::total 431015 # number of ReadSharedReq hits 901system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 89935 # number of demand (read+write) hits 902system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5689 # number of demand (read+write) hits 903system.cpu0.l2cache.demand_hits::cpu0.inst 1975273 # number of demand (read+write) hits 904system.cpu0.l2cache.demand_hits::cpu0.data 664816 # number of demand (read+write) hits 905system.cpu0.l2cache.demand_hits::total 2735713 # number of demand (read+write) hits 906system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 89935 # number of overall hits 907system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5689 # number of overall hits 908system.cpu0.l2cache.overall_hits::cpu0.inst 1975273 # number of overall hits 909system.cpu0.l2cache.overall_hits::cpu0.data 664816 # number of overall hits 910system.cpu0.l2cache.overall_hits::total 2735713 # number of overall hits 911system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 724 # number of ReadReq misses 912system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 99 # number of ReadReq misses 913system.cpu0.l2cache.ReadReq_misses::total 823 # number of ReadReq misses 914system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57038 # number of UpgradeReq misses 915system.cpu0.l2cache.UpgradeReq_misses::total 57038 # number of UpgradeReq misses 916system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20500 # number of SCUpgradeReq misses 917system.cpu0.l2cache.SCUpgradeReq_misses::total 20500 # number of SCUpgradeReq misses 918system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 919system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 920system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47726 # number of ReadExReq misses 921system.cpu0.l2cache.ReadExReq_misses::total 47726 # number of ReadExReq misses 922system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 69826 # number of ReadCleanReq misses 923system.cpu0.l2cache.ReadCleanReq_misses::total 69826 # number of ReadCleanReq misses 924system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100899 # number of ReadSharedReq misses 925system.cpu0.l2cache.ReadSharedReq_misses::total 100899 # number of ReadSharedReq misses 926system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 724 # number of demand (read+write) misses 927system.cpu0.l2cache.demand_misses::cpu0.itb.walker 99 # number of demand (read+write) misses 928system.cpu0.l2cache.demand_misses::cpu0.inst 69826 # number of demand (read+write) misses 929system.cpu0.l2cache.demand_misses::cpu0.data 148625 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::total 219274 # number of demand (read+write) misses 931system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 724 # number of overall misses 932system.cpu0.l2cache.overall_misses::cpu0.itb.walker 99 # number of overall misses 933system.cpu0.l2cache.overall_misses::cpu0.inst 69826 # number of overall misses 934system.cpu0.l2cache.overall_misses::cpu0.data 148625 # number of overall misses 935system.cpu0.l2cache.overall_misses::total 219274 # number of overall misses 936system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 34296000 # number of ReadReq miss cycles 937system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2472000 # number of ReadReq miss cycles 938system.cpu0.l2cache.ReadReq_miss_latency::total 36768000 # number of ReadReq miss cycles 939system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 207057500 # number of UpgradeReq miss cycles 940system.cpu0.l2cache.UpgradeReq_miss_latency::total 207057500 # number of UpgradeReq miss cycles 941system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 45305000 # number of SCUpgradeReq miss cycles 942system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 45305000 # number of SCUpgradeReq miss cycles 943system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 975500 # number of SCUpgradeFailReq miss cycles 944system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 975500 # number of SCUpgradeFailReq miss cycles 945system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3206304999 # number of ReadExReq miss cycles 946system.cpu0.l2cache.ReadExReq_miss_latency::total 3206304999 # number of ReadExReq miss cycles 947system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4508075000 # number of ReadCleanReq miss cycles 948system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4508075000 # number of ReadCleanReq miss cycles 949system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3555400496 # number of ReadSharedReq miss cycles 950system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3555400496 # number of ReadSharedReq miss cycles 951system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 34296000 # number of demand (read+write) miss cycles 952system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2472000 # number of demand (read+write) miss cycles 953system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4508075000 # number of demand (read+write) miss cycles 954system.cpu0.l2cache.demand_miss_latency::cpu0.data 6761705495 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.demand_miss_latency::total 11306548495 # number of demand (read+write) miss cycles 956system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 34296000 # number of overall miss cycles 957system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2472000 # number of overall miss cycles 958system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4508075000 # number of overall miss cycles 959system.cpu0.l2cache.overall_miss_latency::cpu0.data 6761705495 # number of overall miss cycles 960system.cpu0.l2cache.overall_miss_latency::total 11306548495 # number of overall miss cycles 961system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 90659 # number of ReadReq accesses(hits+misses) 962system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5788 # number of ReadReq accesses(hits+misses) 963system.cpu0.l2cache.ReadReq_accesses::total 96447 # number of ReadReq accesses(hits+misses) 964system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507120 # number of WritebackDirty accesses(hits+misses) 965system.cpu0.l2cache.WritebackDirty_accesses::total 507120 # number of WritebackDirty accesses(hits+misses) 966system.cpu0.l2cache.WritebackClean_accesses::writebacks 2250930 # number of WritebackClean accesses(hits+misses) 967system.cpu0.l2cache.WritebackClean_accesses::total 2250930 # number of WritebackClean accesses(hits+misses) 968system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 57038 # number of UpgradeReq accesses(hits+misses) 969system.cpu0.l2cache.UpgradeReq_accesses::total 57038 # number of UpgradeReq accesses(hits+misses) 970system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20500 # number of SCUpgradeReq accesses(hits+misses) 971system.cpu0.l2cache.SCUpgradeReq_accesses::total 20500 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 973system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 974system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 281527 # number of ReadExReq accesses(hits+misses) 975system.cpu0.l2cache.ReadExReq_accesses::total 281527 # number of ReadExReq accesses(hits+misses) 976system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2045099 # number of ReadCleanReq accesses(hits+misses) 977system.cpu0.l2cache.ReadCleanReq_accesses::total 2045099 # number of ReadCleanReq accesses(hits+misses) 978system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 531914 # number of ReadSharedReq accesses(hits+misses) 979system.cpu0.l2cache.ReadSharedReq_accesses::total 531914 # number of ReadSharedReq accesses(hits+misses) 980system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 90659 # number of demand (read+write) accesses 981system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5788 # number of demand (read+write) accesses 982system.cpu0.l2cache.demand_accesses::cpu0.inst 2045099 # number of demand (read+write) accesses 983system.cpu0.l2cache.demand_accesses::cpu0.data 813441 # number of demand (read+write) accesses 984system.cpu0.l2cache.demand_accesses::total 2954987 # number of demand (read+write) accesses 985system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 90659 # number of overall (read+write) accesses 986system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5788 # number of overall (read+write) accesses 987system.cpu0.l2cache.overall_accesses::cpu0.inst 2045099 # number of overall (read+write) accesses 988system.cpu0.l2cache.overall_accesses::cpu0.data 813441 # number of overall (read+write) accesses 989system.cpu0.l2cache.overall_accesses::total 2954987 # number of overall (read+write) accesses 990system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007986 # miss rate for ReadReq accesses 991system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.017104 # miss rate for ReadReq accesses 992system.cpu0.l2cache.ReadReq_miss_rate::total 0.008533 # miss rate for ReadReq accesses 993system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 994system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 995system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 996system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 997system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 998system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 999system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169525 # miss rate for ReadExReq accesses 1000system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169525 # miss rate for ReadExReq accesses 1001system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034143 # miss rate for ReadCleanReq accesses 1002system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034143 # miss rate for ReadCleanReq accesses 1003system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.189690 # miss rate for ReadSharedReq accesses 1004system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.189690 # miss rate for ReadSharedReq accesses 1005system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007986 # miss rate for demand accesses 1006system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.017104 # miss rate for demand accesses 1007system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034143 # miss rate for demand accesses 1008system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.182711 # miss rate for demand accesses 1009system.cpu0.l2cache.demand_miss_rate::total 0.074205 # miss rate for demand accesses 1010system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007986 # miss rate for overall accesses 1011system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.017104 # miss rate for overall accesses 1012system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034143 # miss rate for overall accesses 1013system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.182711 # miss rate for overall accesses 1014system.cpu0.l2cache.overall_miss_rate::total 0.074205 # miss rate for overall accesses 1015system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47370.165746 # average ReadReq miss latency 1016system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24969.696970 # average ReadReq miss latency 1017system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44675.577157 # average ReadReq miss latency 1018system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3630.167608 # average UpgradeReq miss latency 1019system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3630.167608 # average UpgradeReq miss latency 1020system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2210 # average SCUpgradeReq miss latency 1021system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2210 # average SCUpgradeReq miss latency 1022system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 975500 # average SCUpgradeFailReq miss latency 1023system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 975500 # average SCUpgradeFailReq miss latency 1024system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67181.515296 # average ReadExReq miss latency 1025system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67181.515296 # average ReadExReq miss latency 1026system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64561.553003 # average ReadCleanReq miss latency 1027system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64561.553003 # average ReadCleanReq miss latency 1028system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35237.222331 # average ReadSharedReq miss latency 1029system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35237.222331 # average ReadSharedReq miss latency 1030system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47370.165746 # average overall miss latency 1031system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24969.696970 # average overall miss latency 1032system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64561.553003 # average overall miss latency 1033system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45495.074819 # average overall miss latency 1034system.cpu0.l2cache.demand_avg_miss_latency::total 51563.562005 # average overall miss latency 1035system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47370.165746 # average overall miss latency 1036system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24969.696970 # average overall miss latency 1037system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64561.553003 # average overall miss latency 1038system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45495.074819 # average overall miss latency 1039system.cpu0.l2cache.overall_avg_miss_latency::total 51563.562005 # average overall miss latency 1040system.cpu0.l2cache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked 1041system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1043system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 27 # average number of cycles each access was blocked 1045system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1047system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1048system.cpu0.l2cache.writebacks::writebacks 237545 # number of writebacks 1049system.cpu0.l2cache.writebacks::total 237545 # number of writebacks 1050system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5249 # number of ReadExReq MSHR hits 1051system.cpu0.l2cache.ReadExReq_mshr_hits::total 5249 # number of ReadExReq MSHR hits 1052system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 70 # number of ReadCleanReq MSHR hits 1053system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 70 # number of ReadCleanReq MSHR hits 1054system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 588 # number of ReadSharedReq MSHR hits 1055system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 588 # number of ReadSharedReq MSHR hits 1056system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 70 # number of demand (read+write) MSHR hits 1057system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5837 # number of demand (read+write) MSHR hits 1058system.cpu0.l2cache.demand_mshr_hits::total 5907 # number of demand (read+write) MSHR hits 1059system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 70 # number of overall MSHR hits 1060system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5837 # number of overall MSHR hits 1061system.cpu0.l2cache.overall_mshr_hits::total 5907 # number of overall MSHR hits 1062system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 724 # number of ReadReq MSHR misses 1063system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 99 # number of ReadReq MSHR misses 1064system.cpu0.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses 1065system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 263623 # number of HardPFReq MSHR misses 1066system.cpu0.l2cache.HardPFReq_mshr_misses::total 263623 # number of HardPFReq MSHR misses 1067system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 57038 # number of UpgradeReq MSHR misses 1068system.cpu0.l2cache.UpgradeReq_mshr_misses::total 57038 # number of UpgradeReq MSHR misses 1069system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20500 # number of SCUpgradeReq MSHR misses 1070system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20500 # number of SCUpgradeReq MSHR misses 1071system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1072system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1073system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42477 # number of ReadExReq MSHR misses 1074system.cpu0.l2cache.ReadExReq_mshr_misses::total 42477 # number of ReadExReq MSHR misses 1075system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 69756 # number of ReadCleanReq MSHR misses 1076system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 69756 # number of ReadCleanReq MSHR misses 1077system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100311 # number of ReadSharedReq MSHR misses 1078system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100311 # number of ReadSharedReq MSHR misses 1079system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 724 # number of demand (read+write) MSHR misses 1080system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 99 # number of demand (read+write) MSHR misses 1081system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69756 # number of demand (read+write) MSHR misses 1082system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142788 # number of demand (read+write) MSHR misses 1083system.cpu0.l2cache.demand_mshr_misses::total 213367 # number of demand (read+write) MSHR misses 1084system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 724 # number of overall MSHR misses 1085system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 99 # number of overall MSHR misses 1086system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69756 # number of overall MSHR misses 1087system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142788 # number of overall MSHR misses 1088system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 263623 # number of overall MSHR misses 1089system.cpu0.l2cache.overall_mshr_misses::total 476990 # number of overall MSHR misses 1090system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 1091system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32039 # number of ReadReq MSHR uncacheable 1092system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35956 # number of ReadReq MSHR uncacheable 1093system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable 1094system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable 1095system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 1096system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60761 # number of overall MSHR uncacheable misses 1097system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 64678 # number of overall MSHR uncacheable misses 1098system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 29952000 # number of ReadReq MSHR miss cycles 1099system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1878000 # number of ReadReq MSHR miss cycles 1100system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 31830000 # number of ReadReq MSHR miss cycles 1101system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21086356444 # number of HardPFReq MSHR miss cycles 1102system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21086356444 # number of HardPFReq MSHR miss cycles 1103system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1524580500 # number of UpgradeReq MSHR miss cycles 1104system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1524580500 # number of UpgradeReq MSHR miss cycles 1105system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 363161500 # number of SCUpgradeReq MSHR miss cycles 1106system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 363161500 # number of SCUpgradeReq MSHR miss cycles 1107system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 897500 # number of SCUpgradeFailReq MSHR miss cycles 1108system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 897500 # number of SCUpgradeFailReq MSHR miss cycles 1109system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2445688500 # number of ReadExReq MSHR miss cycles 1110system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2445688500 # number of ReadExReq MSHR miss cycles 1111system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4087138500 # number of ReadCleanReq MSHR miss cycles 1112system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4087138500 # number of ReadCleanReq MSHR miss cycles 1113system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2918630996 # number of ReadSharedReq MSHR miss cycles 1114system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2918630996 # number of ReadSharedReq MSHR miss cycles 1115system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 29952000 # number of demand (read+write) MSHR miss cycles 1116system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1878000 # number of demand (read+write) MSHR miss cycles 1117system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4087138500 # number of demand (read+write) MSHR miss cycles 1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5364319496 # number of demand (read+write) MSHR miss cycles 1119system.cpu0.l2cache.demand_mshr_miss_latency::total 9483287996 # number of demand (read+write) MSHR miss cycles 1120system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 29952000 # number of overall MSHR miss cycles 1121system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1878000 # number of overall MSHR miss cycles 1122system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4087138500 # number of overall MSHR miss cycles 1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5364319496 # number of overall MSHR miss cycles 1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21086356444 # number of overall MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::total 30569644440 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles 1127system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445254500 # number of ReadReq MSHR uncacheable cycles 1128system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971274500 # number of ReadReq MSHR uncacheable cycles 1129system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5236706000 # number of WriteReq MSHR uncacheable cycles 1130system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5236706000 # number of WriteReq MSHR uncacheable cycles 1131system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles 1132system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11681960500 # number of overall MSHR uncacheable cycles 1133system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12207980500 # number of overall MSHR uncacheable cycles 1134system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for ReadReq accesses 1135system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for ReadReq accesses 1136system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008533 # mshr miss rate for ReadReq accesses 1137system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1138system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1139system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1140system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1141system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1142system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1143system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1144system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1145system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150881 # mshr miss rate for ReadExReq accesses 1146system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150881 # mshr miss rate for ReadExReq accesses 1147system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for ReadCleanReq accesses 1148system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034109 # mshr miss rate for ReadCleanReq accesses 1149system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188585 # mshr miss rate for ReadSharedReq accesses 1150system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188585 # mshr miss rate for ReadSharedReq accesses 1151system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for demand accesses 1152system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for demand accesses 1153system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for demand accesses 1154system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175536 # mshr miss rate for demand accesses 1155system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072206 # mshr miss rate for demand accesses 1156system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for overall accesses 1157system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for overall accesses 1158system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for overall accesses 1159system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175536 # mshr miss rate for overall accesses 1160system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1161system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161419 # mshr miss rate for overall accesses 1162system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average ReadReq mshr miss latency 1163system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average ReadReq mshr miss latency 1164system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38675.577157 # average ReadReq mshr miss latency 1165system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average HardPFReq mshr miss latency 1166system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79986.785842 # average HardPFReq mshr miss latency 1167system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26729.206845 # average UpgradeReq mshr miss latency 1168system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26729.206845 # average UpgradeReq mshr miss latency 1169system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17715.195122 # average SCUpgradeReq mshr miss latency 1170system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17715.195122 # average SCUpgradeReq mshr miss latency 1171system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 897500 # average SCUpgradeFailReq mshr miss latency 1172system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897500 # average SCUpgradeFailReq mshr miss latency 1173system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57576.770958 # average ReadExReq mshr miss latency 1174system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57576.770958 # average ReadExReq mshr miss latency 1175system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average ReadCleanReq mshr miss latency 1176system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58591.927576 # average ReadCleanReq mshr miss latency 1177system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29095.821954 # average ReadSharedReq mshr miss latency 1178system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29095.821954 # average ReadSharedReq mshr miss latency 1179system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency 1180system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency 1181system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency 1182system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency 1183system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44445.898363 # average overall mshr miss latency 1184system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency 1185system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency 1186system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency 1187system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency 1188system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average overall mshr miss latency 1189system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64088.648483 # average overall mshr miss latency 1190system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency 1191system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201169.028372 # average ReadReq mshr uncacheable latency 1192system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193883.482590 # average ReadReq mshr uncacheable latency 1193system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182323.863241 # average WriteReq mshr uncacheable latency 1194system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182323.863241 # average WriteReq mshr uncacheable latency 1195system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency 1196system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192260.833429 # average overall mshr uncacheable latency 1197system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188750.123690 # average overall mshr uncacheable latency 1198system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1199system.cpu0.toL2Bus.snoop_filter.tot_requests 5762889 # Total number of requests made to the snoop filter. 1200system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2904395 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1201system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 45067 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1202system.cpu0.toL2Bus.snoop_filter.tot_snoops 350664 # Total number of snoops made to the snoop filter. 1203system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1204system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1205system.cpu0.toL2Bus.trans_dist::ReadReq 143133 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::ReadResp 2769477 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::WritebackDirty 745212 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::WritebackClean 2295997 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::CleanEvict 245518 # Transaction distribution 1212system.cpu0.toL2Bus.trans_dist::HardPFReq 331271 # Transaction distribution 1213system.cpu0.toL2Bus.trans_dist::UpgradeReq 87260 # Transaction distribution 1214system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42942 # Transaction distribution 1215system.cpu0.toL2Bus.trans_dist::UpgradeResp 114488 # Transaction distribution 1216system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::ReadExReq 300512 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::ReadExResp 297211 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2045099 # Transaction distribution 1221system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606063 # Transaction distribution 1222system.cpu0.toL2Bus.trans_dist::InvalidateReq 3097 # Transaction distribution 1223system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6142602 # Packet count per connected master and slave (bytes) 1224system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2764050 # Packet count per connected master and slave (bytes) 1225system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13802 # Packet count per connected master and slave (bytes) 1226system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 189783 # Packet count per connected master and slave (bytes) 1227system.cpu0.toL2Bus.pkt_count::total 9110237 # Packet count per connected master and slave (bytes) 1228system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261989504 # Cumulative packet size per connected master and slave (bytes) 1229system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104964478 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23152 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 362636 # Cumulative packet size per connected master and slave (bytes) 1232system.cpu0.toL2Bus.pkt_size::total 367339770 # Cumulative packet size per connected master and slave (bytes) 1233system.cpu0.toL2Bus.snoops 1076533 # Total snoops (count) 1234system.cpu0.toL2Bus.snoop_fanout::samples 4071717 # Request fanout histogram 1235system.cpu0.toL2Bus.snoop_fanout::mean 0.104210 # Request fanout histogram 1236system.cpu0.toL2Bus.snoop_fanout::stdev 0.309410 # Request fanout histogram 1237system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1238system.cpu0.toL2Bus.snoop_fanout::0 3652260 89.70% 89.70% # Request fanout histogram 1239system.cpu0.toL2Bus.snoop_fanout::1 414602 10.18% 99.88% # Request fanout histogram 1240system.cpu0.toL2Bus.snoop_fanout::2 4855 0.12% 100.00% # Request fanout histogram 1241system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1243system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1244system.cpu0.toL2Bus.snoop_fanout::total 4071717 # Request fanout histogram 1245system.cpu0.toL2Bus.reqLayer0.occupancy 5772987994 # Layer occupancy (ticks) 1246system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1247system.cpu0.toL2Bus.snoopLayer0.occupancy 116128992 # Layer occupancy (ticks) 1248system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1249system.cpu0.toL2Bus.respLayer0.occupancy 3074216608 # Layer occupancy (ticks) 1250system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1251system.cpu0.toL2Bus.respLayer1.occupancy 1306190305 # Layer occupancy (ticks) 1252system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1253system.cpu0.toL2Bus.respLayer2.occupancy 8023481 # Layer occupancy (ticks) 1254system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1255system.cpu0.toL2Bus.respLayer3.occupancy 99154439 # Layer occupancy (ticks) 1256system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1257system.cpu1.branchPred.lookups 3635973 # Number of BP lookups 1258system.cpu1.branchPred.condPredicted 2046610 # Number of conditional branches predicted 1259system.cpu1.branchPred.condIncorrect 209049 # Number of conditional branches incorrect 1260system.cpu1.branchPred.BTBLookups 2276641 # Number of BTB lookups 1261system.cpu1.branchPred.BTBHits 1455770 # Number of BTB hits 1262system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1263system.cpu1.branchPred.BTBHitPct 63.943766 # BTB Hit Percentage 1264system.cpu1.branchPred.usedRAS 756757 # Number of times the RAS was used to get a target. 1265system.cpu1.branchPred.RASInCorrect 55280 # Number of incorrect RAS predictions. 1266system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1267system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1274system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1275system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1276system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1277system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1278system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1279system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1280system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1281system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1282system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1283system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1284system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1285system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1286system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1287system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1288system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1289system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1290system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1291system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1292system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1293system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1294system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1295system.cpu1.dtb.walker.walks 23538 # Table walker walks requested 1296system.cpu1.dtb.walker.walksShort 23538 # Table walker walks initiated with short descriptors 1297system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19270 # Level at which table walker walks with short descriptors terminate 1298system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4268 # Level at which table walker walks with short descriptors terminate 1299system.cpu1.dtb.walker.walkWaitTime::samples 23538 # Table walker wait (enqueue to first request) latency 1300system.cpu1.dtb.walker.walkWaitTime::0 23538 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1301system.cpu1.dtb.walker.walkWaitTime::total 23538 # Table walker wait (enqueue to first request) latency 1302system.cpu1.dtb.walker.walkCompletionTime::samples 1839 # Table walker service (enqueue to completion) latency 1303system.cpu1.dtb.walker.walkCompletionTime::mean 11777.052746 # Table walker service (enqueue to completion) latency 1304system.cpu1.dtb.walker.walkCompletionTime::gmean 10980.884481 # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::stdev 6685.927584 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::0-16383 1677 91.19% 91.19% # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::16384-32767 150 8.16% 99.35% # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.38% 99.73% # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.89% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.11% 100.00% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::total 1839 # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution 1313system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution 1314system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution 1315system.cpu1.dtb.walker.walkPageSizes::4K 1325 72.05% 72.05% # Table walker page sizes translated 1316system.cpu1.dtb.walker.walkPageSizes::1M 514 27.95% 100.00% # Table walker page sizes translated 1317system.cpu1.dtb.walker.walkPageSizes::total 1839 # Table walker page sizes translated 1318system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23538 # Table walker requests started/completed, data/inst 1319system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1320system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23538 # Table walker requests started/completed, data/inst 1321system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1839 # Table walker requests started/completed, data/inst 1322system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1323system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1839 # Table walker requests started/completed, data/inst 1324system.cpu1.dtb.walker.walkRequestOrigin::total 25377 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.inst_hits 0 # ITB inst hits 1326system.cpu1.dtb.inst_misses 0 # ITB inst misses 1327system.cpu1.dtb.read_hits 3603943 # DTB read hits 1328system.cpu1.dtb.read_misses 21681 # DTB read misses 1329system.cpu1.dtb.write_hits 2994136 # DTB write hits 1330system.cpu1.dtb.write_misses 1857 # DTB write misses 1331system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1332system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1333system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1334system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1335system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB 1336system.cpu1.dtb.align_faults 128 # Number of TLB faults due to alignment restrictions 1337system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch 1338system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1339system.cpu1.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions 1340system.cpu1.dtb.read_accesses 3625624 # DTB read accesses 1341system.cpu1.dtb.write_accesses 2995993 # DTB write accesses 1342system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1343system.cpu1.dtb.hits 6598079 # DTB hits 1344system.cpu1.dtb.misses 23538 # DTB misses 1345system.cpu1.dtb.accesses 6621617 # DTB accesses 1346system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1347system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1348system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1349system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1355system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1356system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1357system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1358system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1359system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1360system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1361system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1362system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1363system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1364system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1365system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1366system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1367system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1368system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1369system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1370system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1371system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1372system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1373system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1374system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1375system.cpu1.itb.walker.walks 1941 # Table walker walks requested 1376system.cpu1.itb.walker.walksShort 1941 # Table walker walks initiated with short descriptors 1377system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate 1378system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1790 # Level at which table walker walks with short descriptors terminate 1379system.cpu1.itb.walker.walkWaitTime::samples 1941 # Table walker wait (enqueue to first request) latency 1380system.cpu1.itb.walker.walkWaitTime::0 1941 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1381system.cpu1.itb.walker.walkWaitTime::total 1941 # Table walker wait (enqueue to first request) latency 1382system.cpu1.itb.walker.walkCompletionTime::samples 844 # Table walker service (enqueue to completion) latency 1383system.cpu1.itb.walker.walkCompletionTime::mean 11680.687204 # Table walker service (enqueue to completion) latency 1384system.cpu1.itb.walker.walkCompletionTime::gmean 11150.609492 # Table walker service (enqueue to completion) latency 1385system.cpu1.itb.walker.walkCompletionTime::stdev 4460.342613 # Table walker service (enqueue to completion) latency 1386system.cpu1.itb.walker.walkCompletionTime::4096-8191 146 17.30% 17.30% # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::8192-12287 544 64.45% 81.75% # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.27% 95.02% # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::16384-20479 21 2.49% 97.51% # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.93% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 99.05% # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.17% # Table walker service (enqueue to completion) latency 1394system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency 1395system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency 1396system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency 1397system.cpu1.itb.walker.walkCompletionTime::total 844 # Table walker service (enqueue to completion) latency 1398system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution 1399system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution 1400system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution 1401system.cpu1.itb.walker.walkPageSizes::4K 705 83.53% 83.53% # Table walker page sizes translated 1402system.cpu1.itb.walker.walkPageSizes::1M 139 16.47% 100.00% # Table walker page sizes translated 1403system.cpu1.itb.walker.walkPageSizes::total 844 # Table walker page sizes translated 1404system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1405system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1941 # Table walker requests started/completed, data/inst 1406system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1941 # Table walker requests started/completed, data/inst 1407system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1408system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 844 # Table walker requests started/completed, data/inst 1409system.cpu1.itb.walker.walkRequestOrigin_Completed::total 844 # Table walker requests started/completed, data/inst 1410system.cpu1.itb.walker.walkRequestOrigin::total 2785 # Table walker requests started/completed, data/inst 1411system.cpu1.itb.inst_hits 6953743 # ITB inst hits 1412system.cpu1.itb.inst_misses 1941 # ITB inst misses 1413system.cpu1.itb.read_hits 0 # DTB read hits 1414system.cpu1.itb.read_misses 0 # DTB read misses 1415system.cpu1.itb.write_hits 0 # DTB write hits 1416system.cpu1.itb.write_misses 0 # DTB write misses 1417system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1418system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1419system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1420system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1421system.cpu1.itb.flush_entries 908 # Number of entries that have been flushed from TLB 1422system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1423system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1424system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1425system.cpu1.itb.perms_faults 1049 # Number of TLB faults due to permissions restrictions 1426system.cpu1.itb.read_accesses 0 # DTB read accesses 1427system.cpu1.itb.write_accesses 0 # DTB write accesses 1428system.cpu1.itb.inst_accesses 6955684 # ITB inst accesses 1429system.cpu1.itb.hits 6953743 # DTB hits 1430system.cpu1.itb.misses 1941 # DTB misses 1431system.cpu1.itb.accesses 6955684 # DTB accesses 1432system.cpu1.numCycles 40734093 # number of cpu cycles simulated 1433system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1434system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1435system.cpu1.committedInsts 14107719 # Number of instructions committed 1436system.cpu1.committedOps 17288156 # Number of ops (including micro ops) committed 1437system.cpu1.discardedOps 1387486 # Number of ops (including micro ops) which were discarded before commit 1438system.cpu1.numFetchSuspends 2746 # Number of times Execute suspended instruction fetching 1439system.cpu1.quiesceCycles 5656373541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1440system.cpu1.cpi 2.887362 # CPI: cycles per instruction 1441system.cpu1.ipc 0.346337 # IPC: instructions per cycle 1442system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1443system.cpu1.kern.inst.quiesce 2746 # number of quiesce instructions executed 1444system.cpu1.tickCycles 27498026 # Number of cycles that the object actually ticked 1445system.cpu1.idleCycles 13236067 # Total number of cycles that the object has spent stopped 1446system.cpu1.dcache.tags.replacements 156251 # number of replacements 1447system.cpu1.dcache.tags.tagsinuse 474.671754 # Cycle average of tags in use 1448system.cpu1.dcache.tags.total_refs 6246920 # Total number of references to valid blocks. 1449system.cpu1.dcache.tags.sampled_refs 156599 # Sample count of references to valid blocks. 1450system.cpu1.dcache.tags.avg_refs 39.891187 # Average number of references to valid blocks. 1451system.cpu1.dcache.tags.warmup_cycle 91622282000 # Cycle when the warmup percentage was hit. 1452system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.671754 # Average occupied blocks per requestor 1453system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927093 # Average percentage of cache occupancy 1454system.cpu1.dcache.tags.occ_percent::total 0.927093 # Average percentage of cache occupancy 1455system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 1456system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id 1457system.cpu1.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id 1458system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id 1459system.cpu1.dcache.tags.tag_accesses 13254229 # Number of tag accesses 1460system.cpu1.dcache.tags.data_accesses 13254229 # Number of data accesses 1461system.cpu1.dcache.ReadReq_hits::cpu1.data 3282688 # number of ReadReq hits 1462system.cpu1.dcache.ReadReq_hits::total 3282688 # number of ReadReq hits 1463system.cpu1.dcache.WriteReq_hits::cpu1.data 2748164 # number of WriteReq hits 1464system.cpu1.dcache.WriteReq_hits::total 2748164 # number of WriteReq hits 1465system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42687 # number of SoftPFReq hits 1466system.cpu1.dcache.SoftPFReq_hits::total 42687 # number of SoftPFReq hits 1467system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70657 # number of LoadLockedReq hits 1468system.cpu1.dcache.LoadLockedReq_hits::total 70657 # number of LoadLockedReq hits 1469system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61986 # number of StoreCondReq hits 1470system.cpu1.dcache.StoreCondReq_hits::total 61986 # number of StoreCondReq hits 1471system.cpu1.dcache.demand_hits::cpu1.data 6030852 # number of demand (read+write) hits 1472system.cpu1.dcache.demand_hits::total 6030852 # number of demand (read+write) hits 1473system.cpu1.dcache.overall_hits::cpu1.data 6073539 # number of overall hits 1474system.cpu1.dcache.overall_hits::total 6073539 # number of overall hits 1475system.cpu1.dcache.ReadReq_misses::cpu1.data 134600 # number of ReadReq misses 1476system.cpu1.dcache.ReadReq_misses::total 134600 # number of ReadReq misses 1477system.cpu1.dcache.WriteReq_misses::cpu1.data 121570 # number of WriteReq misses 1478system.cpu1.dcache.WriteReq_misses::total 121570 # number of WriteReq misses 1479system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24420 # number of SoftPFReq misses 1480system.cpu1.dcache.SoftPFReq_misses::total 24420 # number of SoftPFReq misses 1481system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16487 # number of LoadLockedReq misses 1482system.cpu1.dcache.LoadLockedReq_misses::total 16487 # number of LoadLockedReq misses 1483system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23399 # number of StoreCondReq misses 1484system.cpu1.dcache.StoreCondReq_misses::total 23399 # number of StoreCondReq misses 1485system.cpu1.dcache.demand_misses::cpu1.data 256170 # number of demand (read+write) misses 1486system.cpu1.dcache.demand_misses::total 256170 # number of demand (read+write) misses 1487system.cpu1.dcache.overall_misses::cpu1.data 280590 # number of overall misses 1488system.cpu1.dcache.overall_misses::total 280590 # number of overall misses 1489system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2183210000 # number of ReadReq miss cycles 1490system.cpu1.dcache.ReadReq_miss_latency::total 2183210000 # number of ReadReq miss cycles 1491system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4500084500 # number of WriteReq miss cycles 1492system.cpu1.dcache.WriteReq_miss_latency::total 4500084500 # number of WriteReq miss cycles 1493system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 318001000 # number of LoadLockedReq miss cycles 1494system.cpu1.dcache.LoadLockedReq_miss_latency::total 318001000 # number of LoadLockedReq miss cycles 1495system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633995000 # number of StoreCondReq miss cycles 1496system.cpu1.dcache.StoreCondReq_miss_latency::total 633995000 # number of StoreCondReq miss cycles 1497system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 321000 # number of StoreCondFailReq miss cycles 1498system.cpu1.dcache.StoreCondFailReq_miss_latency::total 321000 # number of StoreCondFailReq miss cycles 1499system.cpu1.dcache.demand_miss_latency::cpu1.data 6683294500 # number of demand (read+write) miss cycles 1500system.cpu1.dcache.demand_miss_latency::total 6683294500 # number of demand (read+write) miss cycles 1501system.cpu1.dcache.overall_miss_latency::cpu1.data 6683294500 # number of overall miss cycles 1502system.cpu1.dcache.overall_miss_latency::total 6683294500 # number of overall miss cycles 1503system.cpu1.dcache.ReadReq_accesses::cpu1.data 3417288 # number of ReadReq accesses(hits+misses) 1504system.cpu1.dcache.ReadReq_accesses::total 3417288 # number of ReadReq accesses(hits+misses) 1505system.cpu1.dcache.WriteReq_accesses::cpu1.data 2869734 # number of WriteReq accesses(hits+misses) 1506system.cpu1.dcache.WriteReq_accesses::total 2869734 # number of WriteReq accesses(hits+misses) 1507system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67107 # number of SoftPFReq accesses(hits+misses) 1508system.cpu1.dcache.SoftPFReq_accesses::total 67107 # number of SoftPFReq accesses(hits+misses) 1509system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87144 # number of LoadLockedReq accesses(hits+misses) 1510system.cpu1.dcache.LoadLockedReq_accesses::total 87144 # number of LoadLockedReq accesses(hits+misses) 1511system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85385 # number of StoreCondReq accesses(hits+misses) 1512system.cpu1.dcache.StoreCondReq_accesses::total 85385 # number of StoreCondReq accesses(hits+misses) 1513system.cpu1.dcache.demand_accesses::cpu1.data 6287022 # number of demand (read+write) accesses 1514system.cpu1.dcache.demand_accesses::total 6287022 # number of demand (read+write) accesses 1515system.cpu1.dcache.overall_accesses::cpu1.data 6354129 # number of overall (read+write) accesses 1516system.cpu1.dcache.overall_accesses::total 6354129 # number of overall (read+write) accesses 1517system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039388 # miss rate for ReadReq accesses 1518system.cpu1.dcache.ReadReq_miss_rate::total 0.039388 # miss rate for ReadReq accesses 1519system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042363 # miss rate for WriteReq accesses 1520system.cpu1.dcache.WriteReq_miss_rate::total 0.042363 # miss rate for WriteReq accesses 1521system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.363896 # miss rate for SoftPFReq accesses 1522system.cpu1.dcache.SoftPFReq_miss_rate::total 0.363896 # miss rate for SoftPFReq accesses 1523system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189193 # miss rate for LoadLockedReq accesses 1524system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189193 # miss rate for LoadLockedReq accesses 1525system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274041 # miss rate for StoreCondReq accesses 1526system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274041 # miss rate for StoreCondReq accesses 1527system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040746 # miss rate for demand accesses 1528system.cpu1.dcache.demand_miss_rate::total 0.040746 # miss rate for demand accesses 1529system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044159 # miss rate for overall accesses 1530system.cpu1.dcache.overall_miss_rate::total 0.044159 # miss rate for overall accesses 1531system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16219.985141 # average ReadReq miss latency 1532system.cpu1.dcache.ReadReq_avg_miss_latency::total 16219.985141 # average ReadReq miss latency 1533system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37016.406186 # average WriteReq miss latency 1534system.cpu1.dcache.WriteReq_avg_miss_latency::total 37016.406186 # average WriteReq miss latency 1535system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19287.984473 # average LoadLockedReq miss latency 1536system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19287.984473 # average LoadLockedReq miss latency 1537system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27094.961323 # average StoreCondReq miss latency 1538system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27094.961323 # average StoreCondReq miss latency 1539system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1540system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1541system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26089.294219 # average overall miss latency 1542system.cpu1.dcache.demand_avg_miss_latency::total 26089.294219 # average overall miss latency 1543system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23818.719484 # average overall miss latency 1544system.cpu1.dcache.overall_avg_miss_latency::total 23818.719484 # average overall miss latency 1545system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1546system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1547system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1548system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1549system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1550system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1551system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1552system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1553system.cpu1.dcache.writebacks::writebacks 156252 # number of writebacks 1554system.cpu1.dcache.writebacks::total 156252 # number of writebacks 1555system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12906 # number of ReadReq MSHR hits 1556system.cpu1.dcache.ReadReq_mshr_hits::total 12906 # number of ReadReq MSHR hits 1557system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 41816 # number of WriteReq MSHR hits 1558system.cpu1.dcache.WriteReq_mshr_hits::total 41816 # number of WriteReq MSHR hits 1559system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11699 # number of LoadLockedReq MSHR hits 1560system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11699 # number of LoadLockedReq MSHR hits 1561system.cpu1.dcache.demand_mshr_hits::cpu1.data 54722 # number of demand (read+write) MSHR hits 1562system.cpu1.dcache.demand_mshr_hits::total 54722 # number of demand (read+write) MSHR hits 1563system.cpu1.dcache.overall_mshr_hits::cpu1.data 54722 # number of overall MSHR hits 1564system.cpu1.dcache.overall_mshr_hits::total 54722 # number of overall MSHR hits 1565system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 121694 # number of ReadReq MSHR misses 1566system.cpu1.dcache.ReadReq_mshr_misses::total 121694 # number of ReadReq MSHR misses 1567system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79754 # number of WriteReq MSHR misses 1568system.cpu1.dcache.WriteReq_mshr_misses::total 79754 # number of WriteReq MSHR misses 1569system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23886 # number of SoftPFReq MSHR misses 1570system.cpu1.dcache.SoftPFReq_mshr_misses::total 23886 # number of SoftPFReq MSHR misses 1571system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4788 # number of LoadLockedReq MSHR misses 1572system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4788 # number of LoadLockedReq MSHR misses 1573system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23399 # number of StoreCondReq MSHR misses 1574system.cpu1.dcache.StoreCondReq_mshr_misses::total 23399 # number of StoreCondReq MSHR misses 1575system.cpu1.dcache.demand_mshr_misses::cpu1.data 201448 # number of demand (read+write) MSHR misses 1576system.cpu1.dcache.demand_mshr_misses::total 201448 # number of demand (read+write) MSHR misses 1577system.cpu1.dcache.overall_mshr_misses::cpu1.data 225334 # number of overall MSHR misses 1578system.cpu1.dcache.overall_mshr_misses::total 225334 # number of overall MSHR misses 1579system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2976 # number of ReadReq MSHR uncacheable 1580system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2976 # number of ReadReq MSHR uncacheable 1581system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2312 # number of WriteReq MSHR uncacheable 1582system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2312 # number of WriteReq MSHR uncacheable 1583system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5288 # number of overall MSHR uncacheable misses 1584system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5288 # number of overall MSHR uncacheable misses 1585system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855487000 # number of ReadReq MSHR miss cycles 1586system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855487000 # number of ReadReq MSHR miss cycles 1587system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2737931500 # number of WriteReq MSHR miss cycles 1588system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2737931500 # number of WriteReq MSHR miss cycles 1589system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 451965000 # number of SoftPFReq MSHR miss cycles 1590system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 451965000 # number of SoftPFReq MSHR miss cycles 1591system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86630500 # number of LoadLockedReq MSHR miss cycles 1592system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86630500 # number of LoadLockedReq MSHR miss cycles 1593system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610601000 # number of StoreCondReq MSHR miss cycles 1594system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610601000 # number of StoreCondReq MSHR miss cycles 1595system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 316000 # number of StoreCondFailReq MSHR miss cycles 1596system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 316000 # number of StoreCondFailReq MSHR miss cycles 1597system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4593418500 # number of demand (read+write) MSHR miss cycles 1598system.cpu1.dcache.demand_mshr_miss_latency::total 4593418500 # number of demand (read+write) MSHR miss cycles 1599system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5045383500 # number of overall MSHR miss cycles 1600system.cpu1.dcache.overall_mshr_miss_latency::total 5045383500 # number of overall MSHR miss cycles 1601system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389399500 # number of ReadReq MSHR uncacheable cycles 1602system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389399500 # number of ReadReq MSHR uncacheable cycles 1603system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 252039500 # number of WriteReq MSHR uncacheable cycles 1604system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 252039500 # number of WriteReq MSHR uncacheable cycles 1605system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641439000 # number of overall MSHR uncacheable cycles 1606system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641439000 # number of overall MSHR uncacheable cycles 1607system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035611 # mshr miss rate for ReadReq accesses 1608system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035611 # mshr miss rate for ReadReq accesses 1609system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027791 # mshr miss rate for WriteReq accesses 1610system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027791 # mshr miss rate for WriteReq accesses 1611system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.355939 # mshr miss rate for SoftPFReq accesses 1612system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.355939 # mshr miss rate for SoftPFReq accesses 1613system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054944 # mshr miss rate for LoadLockedReq accesses 1614system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054944 # mshr miss rate for LoadLockedReq accesses 1615system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274041 # mshr miss rate for StoreCondReq accesses 1616system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274041 # mshr miss rate for StoreCondReq accesses 1617system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for demand accesses 1618system.cpu1.dcache.demand_mshr_miss_rate::total 0.032042 # mshr miss rate for demand accesses 1619system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035463 # mshr miss rate for overall accesses 1620system.cpu1.dcache.overall_mshr_miss_rate::total 0.035463 # mshr miss rate for overall accesses 1621system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15247.152694 # average ReadReq mshr miss latency 1622system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15247.152694 # average ReadReq mshr miss latency 1623system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34329.707601 # average WriteReq mshr miss latency 1624system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34329.707601 # average WriteReq mshr miss latency 1625system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18921.753328 # average SoftPFReq mshr miss latency 1626system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18921.753328 # average SoftPFReq mshr miss latency 1627system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18093.253968 # average LoadLockedReq mshr miss latency 1628system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18093.253968 # average LoadLockedReq mshr miss latency 1629system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26095.175007 # average StoreCondReq mshr miss latency 1630system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26095.175007 # average StoreCondReq mshr miss latency 1631system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1632system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1633system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22802.005977 # average overall mshr miss latency 1634system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22802.005977 # average overall mshr miss latency 1635system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22390.688933 # average overall mshr miss latency 1636system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22390.688933 # average overall mshr miss latency 1637system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130846.606183 # average ReadReq mshr uncacheable latency 1638system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130846.606183 # average ReadReq mshr uncacheable latency 1639system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109013.624567 # average WriteReq mshr uncacheable latency 1640system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 109013.624567 # average WriteReq mshr uncacheable latency 1641system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121300.869894 # average overall mshr uncacheable latency 1642system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121300.869894 # average overall mshr uncacheable latency 1643system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1644system.cpu1.icache.tags.replacements 863100 # number of replacements 1645system.cpu1.icache.tags.tagsinuse 499.134862 # Cycle average of tags in use 1646system.cpu1.icache.tags.total_refs 6088925 # Total number of references to valid blocks. 1647system.cpu1.icache.tags.sampled_refs 863612 # Sample count of references to valid blocks. 1648system.cpu1.icache.tags.avg_refs 7.050533 # Average number of references to valid blocks. 1649system.cpu1.icache.tags.warmup_cycle 73321501000 # Cycle when the warmup percentage was hit. 1650system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.134862 # Average occupied blocks per requestor 1651system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974873 # Average percentage of cache occupancy 1652system.cpu1.icache.tags.occ_percent::total 0.974873 # Average percentage of cache occupancy 1653system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1654system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id 1655system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 1656system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1657system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1658system.cpu1.icache.tags.tag_accesses 14768686 # Number of tag accesses 1659system.cpu1.icache.tags.data_accesses 14768686 # Number of data accesses 1660system.cpu1.icache.ReadReq_hits::cpu1.inst 6088925 # number of ReadReq hits 1661system.cpu1.icache.ReadReq_hits::total 6088925 # number of ReadReq hits 1662system.cpu1.icache.demand_hits::cpu1.inst 6088925 # number of demand (read+write) hits 1663system.cpu1.icache.demand_hits::total 6088925 # number of demand (read+write) hits 1664system.cpu1.icache.overall_hits::cpu1.inst 6088925 # number of overall hits 1665system.cpu1.icache.overall_hits::total 6088925 # number of overall hits 1666system.cpu1.icache.ReadReq_misses::cpu1.inst 863612 # number of ReadReq misses 1667system.cpu1.icache.ReadReq_misses::total 863612 # number of ReadReq misses 1668system.cpu1.icache.demand_misses::cpu1.inst 863612 # number of demand (read+write) misses 1669system.cpu1.icache.demand_misses::total 863612 # number of demand (read+write) misses 1670system.cpu1.icache.overall_misses::cpu1.inst 863612 # number of overall misses 1671system.cpu1.icache.overall_misses::total 863612 # number of overall misses 1672system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7643358500 # number of ReadReq miss cycles 1673system.cpu1.icache.ReadReq_miss_latency::total 7643358500 # number of ReadReq miss cycles 1674system.cpu1.icache.demand_miss_latency::cpu1.inst 7643358500 # number of demand (read+write) miss cycles 1675system.cpu1.icache.demand_miss_latency::total 7643358500 # number of demand (read+write) miss cycles 1676system.cpu1.icache.overall_miss_latency::cpu1.inst 7643358500 # number of overall miss cycles 1677system.cpu1.icache.overall_miss_latency::total 7643358500 # number of overall miss cycles 1678system.cpu1.icache.ReadReq_accesses::cpu1.inst 6952537 # number of ReadReq accesses(hits+misses) 1679system.cpu1.icache.ReadReq_accesses::total 6952537 # number of ReadReq accesses(hits+misses) 1680system.cpu1.icache.demand_accesses::cpu1.inst 6952537 # number of demand (read+write) accesses 1681system.cpu1.icache.demand_accesses::total 6952537 # number of demand (read+write) accesses 1682system.cpu1.icache.overall_accesses::cpu1.inst 6952537 # number of overall (read+write) accesses 1683system.cpu1.icache.overall_accesses::total 6952537 # number of overall (read+write) accesses 1684system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124215 # miss rate for ReadReq accesses 1685system.cpu1.icache.ReadReq_miss_rate::total 0.124215 # miss rate for ReadReq accesses 1686system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124215 # miss rate for demand accesses 1687system.cpu1.icache.demand_miss_rate::total 0.124215 # miss rate for demand accesses 1688system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124215 # miss rate for overall accesses 1689system.cpu1.icache.overall_miss_rate::total 0.124215 # miss rate for overall accesses 1690system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8850.454255 # average ReadReq miss latency 1691system.cpu1.icache.ReadReq_avg_miss_latency::total 8850.454255 # average ReadReq miss latency 1692system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency 1693system.cpu1.icache.demand_avg_miss_latency::total 8850.454255 # average overall miss latency 1694system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency 1695system.cpu1.icache.overall_avg_miss_latency::total 8850.454255 # average overall miss latency 1696system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1697system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1698system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1699system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1700system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1701system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1702system.cpu1.icache.fast_writes 0 # number of fast writes performed 1703system.cpu1.icache.cache_copies 0 # number of cache copies performed 1704system.cpu1.icache.writebacks::writebacks 863100 # number of writebacks 1705system.cpu1.icache.writebacks::total 863100 # number of writebacks 1706system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 863612 # number of ReadReq MSHR misses 1707system.cpu1.icache.ReadReq_mshr_misses::total 863612 # number of ReadReq MSHR misses 1708system.cpu1.icache.demand_mshr_misses::cpu1.inst 863612 # number of demand (read+write) MSHR misses 1709system.cpu1.icache.demand_mshr_misses::total 863612 # number of demand (read+write) MSHR misses 1710system.cpu1.icache.overall_mshr_misses::cpu1.inst 863612 # number of overall MSHR misses 1711system.cpu1.icache.overall_mshr_misses::total 863612 # number of overall MSHR misses 1712system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1713system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1714system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1715system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1716system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7211552500 # number of ReadReq MSHR miss cycles 1717system.cpu1.icache.ReadReq_mshr_miss_latency::total 7211552500 # number of ReadReq MSHR miss cycles 1718system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7211552500 # number of demand (read+write) MSHR miss cycles 1719system.cpu1.icache.demand_mshr_miss_latency::total 7211552500 # number of demand (read+write) MSHR miss cycles 1720system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7211552500 # number of overall MSHR miss cycles 1721system.cpu1.icache.overall_mshr_miss_latency::total 7211552500 # number of overall MSHR miss cycles 1722system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles 1723system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles 1724system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles 1725system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles 1726system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for ReadReq accesses 1727system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124215 # mshr miss rate for ReadReq accesses 1728system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for demand accesses 1729system.cpu1.icache.demand_mshr_miss_rate::total 0.124215 # mshr miss rate for demand accesses 1730system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for overall accesses 1731system.cpu1.icache.overall_mshr_miss_rate::total 0.124215 # mshr miss rate for overall accesses 1732system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average ReadReq mshr miss latency 1733system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8350.454255 # average ReadReq mshr miss latency 1734system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average overall mshr miss latency 1735system.cpu1.icache.demand_avg_mshr_miss_latency::total 8350.454255 # average overall mshr miss latency 1736system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average overall mshr miss latency 1737system.cpu1.icache.overall_avg_mshr_miss_latency::total 8350.454255 # average overall mshr miss latency 1738system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average ReadReq mshr uncacheable latency 1739system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency 1740system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency 1741system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency 1742system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1743system.cpu1.l2cache.prefetcher.num_hwpf_issued 119510 # number of hwpf issued 1744system.cpu1.l2cache.prefetcher.pfIdentified 119557 # number of prefetch candidates identified 1745system.cpu1.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue 1746system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1747system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1748system.cpu1.l2cache.prefetcher.pfSpanPage 49379 # number of prefetches not generated due to page crossing 1749system.cpu1.l2cache.tags.replacements 38013 # number of replacements 1750system.cpu1.l2cache.tags.tagsinuse 15156.094149 # Cycle average of tags in use 1751system.cpu1.l2cache.tags.total_refs 1857838 # Total number of references to valid blocks. 1752system.cpu1.l2cache.tags.sampled_refs 53311 # Sample count of references to valid blocks. 1753system.cpu1.l2cache.tags.avg_refs 34.849056 # Average number of references to valid blocks. 1754system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1755system.cpu1.l2cache.tags.occ_blocks::writebacks 14713.350805 # Average occupied blocks per requestor 1756system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.823499 # Average occupied blocks per requestor 1757system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.085233 # Average occupied blocks per requestor 1758system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 414.834611 # Average occupied blocks per requestor 1759system.cpu1.l2cache.tags.occ_percent::writebacks 0.898032 # Average percentage of cache occupancy 1760system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001698 # Average percentage of cache occupancy 1761system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy 1762system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025319 # Average percentage of cache occupancy 1763system.cpu1.l2cache.tags.occ_percent::total 0.925055 # Average percentage of cache occupancy 1764system.cpu1.l2cache.tags.occ_task_id_blocks::1022 902 # Occupied blocks per task id 1765system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id 1766system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14305 # Occupied blocks per task id 1767system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id 1768system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id 1769system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 862 # Occupied blocks per task id 1770system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1771system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1772system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id 1773system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id 1774system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1969 # Occupied blocks per task id 1775system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11989 # Occupied blocks per task id 1776system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055054 # Percentage of cache occupancy per task id 1777system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id 1778system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.873108 # Percentage of cache occupancy per task id 1779system.cpu1.l2cache.tags.tag_accesses 34476802 # Number of tag accesses 1780system.cpu1.l2cache.tags.data_accesses 34476802 # Number of data accesses 1781system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24946 # number of ReadReq hits 1782system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2423 # number of ReadReq hits 1783system.cpu1.l2cache.ReadReq_hits::total 27369 # number of ReadReq hits 1784system.cpu1.l2cache.WritebackDirty_hits::writebacks 94733 # number of WritebackDirty hits 1785system.cpu1.l2cache.WritebackDirty_hits::total 94733 # number of WritebackDirty hits 1786system.cpu1.l2cache.WritebackClean_hits::writebacks 906332 # number of WritebackClean hits 1787system.cpu1.l2cache.WritebackClean_hits::total 906332 # number of WritebackClean hits 1788system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18144 # number of ReadExReq hits 1789system.cpu1.l2cache.ReadExReq_hits::total 18144 # number of ReadExReq hits 1790system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 850574 # number of ReadCleanReq hits 1791system.cpu1.l2cache.ReadCleanReq_hits::total 850574 # number of ReadCleanReq hits 1792system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 83387 # number of ReadSharedReq hits 1793system.cpu1.l2cache.ReadSharedReq_hits::total 83387 # number of ReadSharedReq hits 1794system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24946 # number of demand (read+write) hits 1795system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2423 # number of demand (read+write) hits 1796system.cpu1.l2cache.demand_hits::cpu1.inst 850574 # number of demand (read+write) hits 1797system.cpu1.l2cache.demand_hits::cpu1.data 101531 # number of demand (read+write) hits 1798system.cpu1.l2cache.demand_hits::total 979474 # number of demand (read+write) hits 1799system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24946 # number of overall hits 1800system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2423 # number of overall hits 1801system.cpu1.l2cache.overall_hits::cpu1.inst 850574 # number of overall hits 1802system.cpu1.l2cache.overall_hits::cpu1.data 101531 # number of overall hits 1803system.cpu1.l2cache.overall_hits::total 979474 # number of overall hits 1804system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses 1805system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 240 # number of ReadReq misses 1806system.cpu1.l2cache.ReadReq_misses::total 922 # number of ReadReq misses 1807system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29216 # number of UpgradeReq misses 1808system.cpu1.l2cache.UpgradeReq_misses::total 29216 # number of UpgradeReq misses 1809system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23399 # number of SCUpgradeReq misses 1810system.cpu1.l2cache.SCUpgradeReq_misses::total 23399 # number of SCUpgradeReq misses 1811system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32397 # number of ReadExReq misses 1812system.cpu1.l2cache.ReadExReq_misses::total 32397 # number of ReadExReq misses 1813system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13038 # number of ReadCleanReq misses 1814system.cpu1.l2cache.ReadCleanReq_misses::total 13038 # number of ReadCleanReq misses 1815system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66978 # number of ReadSharedReq misses 1816system.cpu1.l2cache.ReadSharedReq_misses::total 66978 # number of ReadSharedReq misses 1817system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses 1818system.cpu1.l2cache.demand_misses::cpu1.itb.walker 240 # number of demand (read+write) misses 1819system.cpu1.l2cache.demand_misses::cpu1.inst 13038 # number of demand (read+write) misses 1820system.cpu1.l2cache.demand_misses::cpu1.data 99375 # number of demand (read+write) misses 1821system.cpu1.l2cache.demand_misses::total 113335 # number of demand (read+write) misses 1822system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses 1823system.cpu1.l2cache.overall_misses::cpu1.itb.walker 240 # number of overall misses 1824system.cpu1.l2cache.overall_misses::cpu1.inst 13038 # number of overall misses 1825system.cpu1.l2cache.overall_misses::cpu1.data 99375 # number of overall misses 1826system.cpu1.l2cache.overall_misses::total 113335 # number of overall misses 1827system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15377500 # number of ReadReq miss cycles 1828system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4827500 # number of ReadReq miss cycles 1829system.cpu1.l2cache.ReadReq_miss_latency::total 20205000 # number of ReadReq miss cycles 1830system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64165000 # number of UpgradeReq miss cycles 1831system.cpu1.l2cache.UpgradeReq_miss_latency::total 64165000 # number of UpgradeReq miss cycles 1832system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 56569500 # number of SCUpgradeReq miss cycles 1833system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 56569500 # number of SCUpgradeReq miss cycles 1834system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 308500 # number of SCUpgradeFailReq miss cycles 1835system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 308500 # number of SCUpgradeFailReq miss cycles 1836system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1725053500 # number of ReadExReq miss cycles 1837system.cpu1.l2cache.ReadExReq_miss_latency::total 1725053500 # number of ReadExReq miss cycles 1838system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 743147000 # number of ReadCleanReq miss cycles 1839system.cpu1.l2cache.ReadCleanReq_miss_latency::total 743147000 # number of ReadCleanReq miss cycles 1840system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1610450996 # number of ReadSharedReq miss cycles 1841system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1610450996 # number of ReadSharedReq miss cycles 1842system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15377500 # number of demand (read+write) miss cycles 1843system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4827500 # number of demand (read+write) miss cycles 1844system.cpu1.l2cache.demand_miss_latency::cpu1.inst 743147000 # number of demand (read+write) miss cycles 1845system.cpu1.l2cache.demand_miss_latency::cpu1.data 3335504496 # number of demand (read+write) miss cycles 1846system.cpu1.l2cache.demand_miss_latency::total 4098856496 # number of demand (read+write) miss cycles 1847system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15377500 # number of overall miss cycles 1848system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4827500 # number of overall miss cycles 1849system.cpu1.l2cache.overall_miss_latency::cpu1.inst 743147000 # number of overall miss cycles 1850system.cpu1.l2cache.overall_miss_latency::cpu1.data 3335504496 # number of overall miss cycles 1851system.cpu1.l2cache.overall_miss_latency::total 4098856496 # number of overall miss cycles 1852system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25628 # number of ReadReq accesses(hits+misses) 1853system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2663 # number of ReadReq accesses(hits+misses) 1854system.cpu1.l2cache.ReadReq_accesses::total 28291 # number of ReadReq accesses(hits+misses) 1855system.cpu1.l2cache.WritebackDirty_accesses::writebacks 94733 # number of WritebackDirty accesses(hits+misses) 1856system.cpu1.l2cache.WritebackDirty_accesses::total 94733 # number of WritebackDirty accesses(hits+misses) 1857system.cpu1.l2cache.WritebackClean_accesses::writebacks 906332 # number of WritebackClean accesses(hits+misses) 1858system.cpu1.l2cache.WritebackClean_accesses::total 906332 # number of WritebackClean accesses(hits+misses) 1859system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29216 # number of UpgradeReq accesses(hits+misses) 1860system.cpu1.l2cache.UpgradeReq_accesses::total 29216 # number of UpgradeReq accesses(hits+misses) 1861system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23399 # number of SCUpgradeReq accesses(hits+misses) 1862system.cpu1.l2cache.SCUpgradeReq_accesses::total 23399 # number of SCUpgradeReq accesses(hits+misses) 1863system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50541 # number of ReadExReq accesses(hits+misses) 1864system.cpu1.l2cache.ReadExReq_accesses::total 50541 # number of ReadExReq accesses(hits+misses) 1865system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 863612 # number of ReadCleanReq accesses(hits+misses) 1866system.cpu1.l2cache.ReadCleanReq_accesses::total 863612 # number of ReadCleanReq accesses(hits+misses) 1867system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 150365 # number of ReadSharedReq accesses(hits+misses) 1868system.cpu1.l2cache.ReadSharedReq_accesses::total 150365 # number of ReadSharedReq accesses(hits+misses) 1869system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25628 # number of demand (read+write) accesses 1870system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2663 # number of demand (read+write) accesses 1871system.cpu1.l2cache.demand_accesses::cpu1.inst 863612 # number of demand (read+write) accesses 1872system.cpu1.l2cache.demand_accesses::cpu1.data 200906 # number of demand (read+write) accesses 1873system.cpu1.l2cache.demand_accesses::total 1092809 # number of demand (read+write) accesses 1874system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25628 # number of overall (read+write) accesses 1875system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2663 # number of overall (read+write) accesses 1876system.cpu1.l2cache.overall_accesses::cpu1.inst 863612 # number of overall (read+write) accesses 1877system.cpu1.l2cache.overall_accesses::cpu1.data 200906 # number of overall (read+write) accesses 1878system.cpu1.l2cache.overall_accesses::total 1092809 # number of overall (read+write) accesses 1879system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026612 # miss rate for ReadReq accesses 1880system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090124 # miss rate for ReadReq accesses 1881system.cpu1.l2cache.ReadReq_miss_rate::total 0.032590 # miss rate for ReadReq accesses 1882system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1883system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1884system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1885system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1886system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641004 # miss rate for ReadExReq accesses 1887system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641004 # miss rate for ReadExReq accesses 1888system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.015097 # miss rate for ReadCleanReq accesses 1889system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.015097 # miss rate for ReadCleanReq accesses 1890system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.445436 # miss rate for ReadSharedReq accesses 1891system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.445436 # miss rate for ReadSharedReq accesses 1892system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026612 # miss rate for demand accesses 1893system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090124 # miss rate for demand accesses 1894system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.015097 # miss rate for demand accesses 1895system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.494634 # miss rate for demand accesses 1896system.cpu1.l2cache.demand_miss_rate::total 0.103710 # miss rate for demand accesses 1897system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026612 # miss rate for overall accesses 1898system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090124 # miss rate for overall accesses 1899system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.015097 # miss rate for overall accesses 1900system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.494634 # miss rate for overall accesses 1901system.cpu1.l2cache.overall_miss_rate::total 0.103710 # miss rate for overall accesses 1902system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22547.653959 # average ReadReq miss latency 1903system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20114.583333 # average ReadReq miss latency 1904system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21914.316703 # average ReadReq miss latency 1905system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2196.228094 # average UpgradeReq miss latency 1906system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2196.228094 # average UpgradeReq miss latency 1907system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2417.603316 # average SCUpgradeReq miss latency 1908system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2417.603316 # average SCUpgradeReq miss latency 1909system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1910system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1911system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53247.322283 # average ReadExReq miss latency 1912system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53247.322283 # average ReadExReq miss latency 1913system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.542721 # average ReadCleanReq miss latency 1914system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.542721 # average ReadCleanReq miss latency 1915system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24044.477231 # average ReadSharedReq miss latency 1916system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24044.477231 # average ReadSharedReq miss latency 1917system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22547.653959 # average overall miss latency 1918system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20114.583333 # average overall miss latency 1919system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.542721 # average overall miss latency 1920system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33564.825117 # average overall miss latency 1921system.cpu1.l2cache.demand_avg_miss_latency::total 36165.848996 # average overall miss latency 1922system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22547.653959 # average overall miss latency 1923system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20114.583333 # average overall miss latency 1924system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.542721 # average overall miss latency 1925system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33564.825117 # average overall miss latency 1926system.cpu1.l2cache.overall_avg_miss_latency::total 36165.848996 # average overall miss latency 1927system.cpu1.l2cache.blocked_cycles::no_mshrs 28 # number of cycles access was blocked 1928system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1929system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1930system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1931system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked 1932system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1933system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1934system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1935system.cpu1.l2cache.writebacks::writebacks 29299 # number of writebacks 1936system.cpu1.l2cache.writebacks::total 29299 # number of writebacks 1937system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 234 # number of ReadExReq MSHR hits 1938system.cpu1.l2cache.ReadExReq_mshr_hits::total 234 # number of ReadExReq MSHR hits 1939system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits 1940system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 1941system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits 1942system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits 1943system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 1944system.cpu1.l2cache.demand_mshr_hits::cpu1.data 271 # number of demand (read+write) MSHR hits 1945system.cpu1.l2cache.demand_mshr_hits::total 277 # number of demand (read+write) MSHR hits 1946system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 1947system.cpu1.l2cache.overall_mshr_hits::cpu1.data 271 # number of overall MSHR hits 1948system.cpu1.l2cache.overall_mshr_hits::total 277 # number of overall MSHR hits 1949system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 682 # number of ReadReq MSHR misses 1950system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 240 # number of ReadReq MSHR misses 1951system.cpu1.l2cache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses 1952system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19779 # number of HardPFReq MSHR misses 1953system.cpu1.l2cache.HardPFReq_mshr_misses::total 19779 # number of HardPFReq MSHR misses 1954system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29216 # number of UpgradeReq MSHR misses 1955system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29216 # number of UpgradeReq MSHR misses 1956system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23399 # number of SCUpgradeReq MSHR misses 1957system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23399 # number of SCUpgradeReq MSHR misses 1958system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32163 # number of ReadExReq MSHR misses 1959system.cpu1.l2cache.ReadExReq_mshr_misses::total 32163 # number of ReadExReq MSHR misses 1960system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13032 # number of ReadCleanReq MSHR misses 1961system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13032 # number of ReadCleanReq MSHR misses 1962system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 66941 # number of ReadSharedReq MSHR misses 1963system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 66941 # number of ReadSharedReq MSHR misses 1964system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 682 # number of demand (read+write) MSHR misses 1965system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 240 # number of demand (read+write) MSHR misses 1966system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13032 # number of demand (read+write) MSHR misses 1967system.cpu1.l2cache.demand_mshr_misses::cpu1.data 99104 # number of demand (read+write) MSHR misses 1968system.cpu1.l2cache.demand_mshr_misses::total 113058 # number of demand (read+write) MSHR misses 1969system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 682 # number of overall MSHR misses 1970system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 240 # number of overall MSHR misses 1971system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13032 # number of overall MSHR misses 1972system.cpu1.l2cache.overall_mshr_misses::cpu1.data 99104 # number of overall MSHR misses 1973system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19779 # number of overall MSHR misses 1974system.cpu1.l2cache.overall_mshr_misses::total 132837 # number of overall MSHR misses 1975system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1976system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2976 # number of ReadReq MSHR uncacheable 1977system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3088 # number of ReadReq MSHR uncacheable 1978system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2312 # number of WriteReq MSHR uncacheable 1979system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2312 # number of WriteReq MSHR uncacheable 1980system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1981system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5288 # number of overall MSHR uncacheable misses 1982system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5400 # number of overall MSHR uncacheable misses 1983system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11285500 # number of ReadReq MSHR miss cycles 1984system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3387500 # number of ReadReq MSHR miss cycles 1985system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 14673000 # number of ReadReq MSHR miss cycles 1986system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 962389435 # number of HardPFReq MSHR miss cycles 1987system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 962389435 # number of HardPFReq MSHR miss cycles 1988system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 593694500 # number of UpgradeReq MSHR miss cycles 1989system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 593694500 # number of UpgradeReq MSHR miss cycles 1990system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 433683000 # number of SCUpgradeReq MSHR miss cycles 1991system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 433683000 # number of SCUpgradeReq MSHR miss cycles 1992system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 278500 # number of SCUpgradeFailReq MSHR miss cycles 1993system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 278500 # number of SCUpgradeFailReq MSHR miss cycles 1994system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1505368500 # number of ReadExReq MSHR miss cycles 1995system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1505368500 # number of ReadExReq MSHR miss cycles 1996system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 664642000 # number of ReadCleanReq MSHR miss cycles 1997system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 664642000 # number of ReadCleanReq MSHR miss cycles 1998system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1206964996 # number of ReadSharedReq MSHR miss cycles 1999system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1206964996 # number of ReadSharedReq MSHR miss cycles 2000system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11285500 # number of demand (read+write) MSHR miss cycles 2001system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3387500 # number of demand (read+write) MSHR miss cycles 2002system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 664642000 # number of demand (read+write) MSHR miss cycles 2003system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2712333496 # number of demand (read+write) MSHR miss cycles 2004system.cpu1.l2cache.demand_mshr_miss_latency::total 3391648496 # number of demand (read+write) MSHR miss cycles 2005system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11285500 # number of overall MSHR miss cycles 2006system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3387500 # number of overall MSHR miss cycles 2007system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 664642000 # number of overall MSHR miss cycles 2008system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712333496 # number of overall MSHR miss cycles 2009system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962389435 # number of overall MSHR miss cycles 2010system.cpu1.l2cache.overall_mshr_miss_latency::total 4354037931 # number of overall MSHR miss cycles 2011system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14454500 # number of ReadReq MSHR uncacheable cycles 2012system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365531500 # number of ReadReq MSHR uncacheable cycles 2013system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 379986000 # number of ReadReq MSHR uncacheable cycles 2014system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234574500 # number of WriteReq MSHR uncacheable cycles 2015system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234574500 # number of WriteReq MSHR uncacheable cycles 2016system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14454500 # number of overall MSHR uncacheable cycles 2017system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 600106000 # number of overall MSHR uncacheable cycles 2018system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614560500 # number of overall MSHR uncacheable cycles 2019system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026612 # mshr miss rate for ReadReq accesses 2020system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090124 # mshr miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032590 # mshr miss rate for ReadReq accesses 2022system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2023system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2024system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2025system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2026system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2028system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.636374 # mshr miss rate for ReadExReq accesses 2029system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.636374 # mshr miss rate for ReadExReq accesses 2030system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015090 # mshr miss rate for ReadCleanReq accesses 2031system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.015090 # mshr miss rate for ReadCleanReq accesses 2032system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.445190 # mshr miss rate for ReadSharedReq accesses 2033system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.445190 # mshr miss rate for ReadSharedReq accesses 2034system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026612 # mshr miss rate for demand accesses 2035system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090124 # mshr miss rate for demand accesses 2036system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015090 # mshr miss rate for demand accesses 2037system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.493285 # mshr miss rate for demand accesses 2038system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103456 # mshr miss rate for demand accesses 2039system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026612 # mshr miss rate for overall accesses 2040system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090124 # mshr miss rate for overall accesses 2041system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015090 # mshr miss rate for overall accesses 2042system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.493285 # mshr miss rate for overall accesses 2043system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2044system.cpu1.l2cache.overall_mshr_miss_rate::total 0.121556 # mshr miss rate for overall accesses 2045system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average ReadReq mshr miss latency 2046system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average ReadReq mshr miss latency 2047system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15914.316703 # average ReadReq mshr miss latency 2048system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average HardPFReq mshr miss latency 2049system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48657.133070 # average HardPFReq mshr miss latency 2050system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.868702 # average UpgradeReq mshr miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20320.868702 # average UpgradeReq mshr miss latency 2052system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18534.253601 # average SCUpgradeReq mshr miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18534.253601 # average SCUpgradeReq mshr miss latency 2054system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2056system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46804.355937 # average ReadExReq mshr miss latency 2057system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46804.355937 # average ReadExReq mshr miss latency 2058system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average ReadCleanReq mshr miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51000.767342 # average ReadCleanReq mshr miss latency 2060system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18030.280336 # average ReadSharedReq mshr miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18030.280336 # average ReadSharedReq mshr miss latency 2062system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average overall mshr miss latency 2063system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency 2064system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency 2065system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency 2066system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29999.190646 # average overall mshr miss latency 2067system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average overall mshr miss latency 2068system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency 2069system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency 2070system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency 2071system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average overall mshr miss latency 2072system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32777.297974 # average overall mshr miss latency 2073system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency 2074system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122826.444892 # average ReadReq mshr uncacheable latency 2075system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123052.461140 # average ReadReq mshr uncacheable latency 2076system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101459.558824 # average WriteReq mshr uncacheable latency 2077system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101459.558824 # average WriteReq mshr uncacheable latency 2078system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency 2079system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113484.493192 # average overall mshr uncacheable latency 2080system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113807.500000 # average overall mshr uncacheable latency 2081system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2082system.cpu1.toL2Bus.snoop_filter.tot_requests 2143691 # Total number of requests made to the snoop filter. 2083system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1079194 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2084system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2085system.cpu1.toL2Bus.snoop_filter.tot_snoops 177461 # Total number of snoops made to the snoop filter. 2086system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175960 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2087system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1501 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2088system.cpu1.toL2Bus.trans_dist::ReadReq 34625 # Transaction distribution 2089system.cpu1.toL2Bus.trans_dist::ReadResp 1085487 # Transaction distribution 2090system.cpu1.toL2Bus.trans_dist::WriteReq 2312 # Transaction distribution 2091system.cpu1.toL2Bus.trans_dist::WriteResp 2312 # Transaction distribution 2092system.cpu1.toL2Bus.trans_dist::WritebackDirty 125339 # Transaction distribution 2093system.cpu1.toL2Bus.trans_dist::WritebackClean 924619 # Transaction distribution 2094system.cpu1.toL2Bus.trans_dist::CleanEvict 97697 # Transaction distribution 2095system.cpu1.toL2Bus.trans_dist::HardPFReq 24084 # Transaction distribution 2096system.cpu1.toL2Bus.trans_dist::UpgradeReq 71468 # Transaction distribution 2097system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41763 # Transaction distribution 2098system.cpu1.toL2Bus.trans_dist::UpgradeResp 84759 # Transaction distribution 2099system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2100system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution 2101system.cpu1.toL2Bus.trans_dist::ReadExReq 57626 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::ReadExResp 55185 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::ReadCleanReq 863612 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::ReadSharedReq 234129 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::InvalidateReq 33 # Transaction distribution 2106system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2590548 # Packet count per connected master and slave (bytes) 2107system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 747561 # Packet count per connected master and slave (bytes) 2108system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6394 # Packet count per connected master and slave (bytes) 2109system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 53434 # Packet count per connected master and slave (bytes) 2110system.cpu1.toL2Bus.pkt_count::total 3397937 # Packet count per connected master and slave (bytes) 2111system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 110516736 # Cumulative packet size per connected master and slave (bytes) 2112system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25535556 # Cumulative packet size per connected master and slave (bytes) 2113system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) 2114system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 102512 # Cumulative packet size per connected master and slave (bytes) 2115system.cpu1.toL2Bus.pkt_size::total 136165456 # Cumulative packet size per connected master and slave (bytes) 2116system.cpu1.toL2Bus.snoops 380835 # Total snoops (count) 2117system.cpu1.toL2Bus.snoop_fanout::samples 1457969 # Request fanout histogram 2118system.cpu1.toL2Bus.snoop_fanout::mean 0.140235 # Request fanout histogram 2119system.cpu1.toL2Bus.snoop_fanout::stdev 0.350184 # Request fanout histogram 2120system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2121system.cpu1.toL2Bus.snoop_fanout::0 1255011 86.08% 86.08% # Request fanout histogram 2122system.cpu1.toL2Bus.snoop_fanout::1 201457 13.82% 99.90% # Request fanout histogram 2123system.cpu1.toL2Bus.snoop_fanout::2 1501 0.10% 100.00% # Request fanout histogram 2124system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2125system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2126system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2127system.cpu1.toL2Bus.snoop_fanout::total 1457969 # Request fanout histogram 2128system.cpu1.toL2Bus.reqLayer0.occupancy 2107221995 # Layer occupancy (ticks) 2129system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2130system.cpu1.toL2Bus.snoopLayer0.occupancy 78416105 # Layer occupancy (ticks) 2131system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2132system.cpu1.toL2Bus.respLayer0.occupancy 1295704762 # Layer occupancy (ticks) 2133system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2134system.cpu1.toL2Bus.respLayer1.occupancy 333278550 # Layer occupancy (ticks) 2135system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2136system.cpu1.toL2Bus.respLayer2.occupancy 3731000 # Layer occupancy (ticks) 2137system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2138system.cpu1.toL2Bus.respLayer3.occupancy 27832447 # Layer occupancy (ticks) 2139system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2140system.iobus.trans_dist::ReadReq 31009 # Transaction distribution 2141system.iobus.trans_dist::ReadResp 31009 # Transaction distribution 2142system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 2143system.iobus.trans_dist::WriteResp 59425 # Transaction distribution 2144system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) 2145system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2146system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2147system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2148system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2149system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2150system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2151system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2152system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2153system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2154system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2157system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2162system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2163system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) 2164system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2165system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2166system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) 2168system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2169system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2170system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2171system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2172system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2173system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2174system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2175system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2176system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2177system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2179system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) 2187system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2188system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2189system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) 2190system.iobus.reqLayer0.occupancy 51092500 # Layer occupancy (ticks) 2191system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2192system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) 2193system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2194system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) 2195system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2196system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) 2197system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2198system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) 2199system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2200system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) 2201system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2202system.iobus.reqLayer8.occupancy 576000 # Layer occupancy (ticks) 2203system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2204system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) 2205system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2206system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 2207system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2208system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2209system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2210system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2211system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2212system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) 2213system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2214system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 2215system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2216system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 2217system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2218system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2219system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2220system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 2221system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2222system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) 2223system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2224system.iobus.reqLayer23.occupancy 6104500 # Layer occupancy (ticks) 2225system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2226system.iobus.reqLayer24.occupancy 32859000 # Layer occupancy (ticks) 2227system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2228system.iobus.reqLayer25.occupancy 187096728 # Layer occupancy (ticks) 2229system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2230system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) 2231system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2232system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2233system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2234system.iocache.tags.replacements 36449 # number of replacements 2235system.iocache.tags.tagsinuse 14.469909 # Cycle average of tags in use 2236system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2237system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2238system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2239system.iocache.tags.warmup_cycle 272427086000 # Cycle when the warmup percentage was hit. 2240system.iocache.tags.occ_blocks::realview.ide 14.469909 # Average occupied blocks per requestor 2241system.iocache.tags.occ_percent::realview.ide 0.904369 # Average percentage of cache occupancy 2242system.iocache.tags.occ_percent::total 0.904369 # Average percentage of cache occupancy 2243system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2244system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2245system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2246system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2247system.iocache.tags.data_accesses 328203 # Number of data accesses 2248system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2249system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2250system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2251system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2252system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2253system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2254system.iocache.overall_misses::realview.ide 243 # number of overall misses 2255system.iocache.overall_misses::total 243 # number of overall misses 2256system.iocache.ReadReq_miss_latency::realview.ide 31652377 # number of ReadReq miss cycles 2257system.iocache.ReadReq_miss_latency::total 31652377 # number of ReadReq miss cycles 2258system.iocache.WriteLineReq_miss_latency::realview.ide 4575926351 # number of WriteLineReq miss cycles 2259system.iocache.WriteLineReq_miss_latency::total 4575926351 # number of WriteLineReq miss cycles 2260system.iocache.demand_miss_latency::realview.ide 31652377 # number of demand (read+write) miss cycles 2261system.iocache.demand_miss_latency::total 31652377 # number of demand (read+write) miss cycles 2262system.iocache.overall_miss_latency::realview.ide 31652377 # number of overall miss cycles 2263system.iocache.overall_miss_latency::total 31652377 # number of overall miss cycles 2264system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2265system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2266system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2267system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2268system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2269system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2270system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2271system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2272system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2273system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2274system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2275system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2276system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2277system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2278system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2279system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2280system.iocache.ReadReq_avg_miss_latency::realview.ide 130256.695473 # average ReadReq miss latency 2281system.iocache.ReadReq_avg_miss_latency::total 130256.695473 # average ReadReq miss latency 2282system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126323.055184 # average WriteLineReq miss latency 2283system.iocache.WriteLineReq_avg_miss_latency::total 126323.055184 # average WriteLineReq miss latency 2284system.iocache.demand_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency 2285system.iocache.demand_avg_miss_latency::total 130256.695473 # average overall miss latency 2286system.iocache.overall_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency 2287system.iocache.overall_avg_miss_latency::total 130256.695473 # average overall miss latency 2288system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked 2289system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2290system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 2291system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2292system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked 2293system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2294system.iocache.fast_writes 0 # number of fast writes performed 2295system.iocache.cache_copies 0 # number of cache copies performed 2296system.iocache.writebacks::writebacks 36206 # number of writebacks 2297system.iocache.writebacks::total 36206 # number of writebacks 2298system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2299system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2300system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2301system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2302system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2303system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2304system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2305system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2306system.iocache.ReadReq_mshr_miss_latency::realview.ide 19502377 # number of ReadReq MSHR miss cycles 2307system.iocache.ReadReq_mshr_miss_latency::total 19502377 # number of ReadReq MSHR miss cycles 2308system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763035342 # number of WriteLineReq MSHR miss cycles 2309system.iocache.WriteLineReq_mshr_miss_latency::total 2763035342 # number of WriteLineReq MSHR miss cycles 2310system.iocache.demand_mshr_miss_latency::realview.ide 19502377 # number of demand (read+write) MSHR miss cycles 2311system.iocache.demand_mshr_miss_latency::total 19502377 # number of demand (read+write) MSHR miss cycles 2312system.iocache.overall_mshr_miss_latency::realview.ide 19502377 # number of overall MSHR miss cycles 2313system.iocache.overall_mshr_miss_latency::total 19502377 # number of overall MSHR miss cycles 2314system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2315system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2316system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2317system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2318system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2319system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2320system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2321system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2322system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80256.695473 # average ReadReq mshr miss latency 2323system.iocache.ReadReq_avg_mshr_miss_latency::total 80256.695473 # average ReadReq mshr miss latency 2324system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76276.373178 # average WriteLineReq mshr miss latency 2325system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76276.373178 # average WriteLineReq mshr miss latency 2326system.iocache.demand_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency 2327system.iocache.demand_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency 2328system.iocache.overall_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency 2329system.iocache.overall_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency 2330system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2331system.l2c.tags.replacements 132173 # number of replacements 2332system.l2c.tags.tagsinuse 63220.230545 # Cycle average of tags in use 2333system.l2c.tags.total_refs 476061 # Total number of references to valid blocks. 2334system.l2c.tags.sampled_refs 196324 # Sample count of references to valid blocks. 2335system.l2c.tags.avg_refs 2.424874 # Average number of references to valid blocks. 2336system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2337system.l2c.tags.occ_blocks::writebacks 13508.269285 # Average occupied blocks per requestor 2338system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.219026 # Average occupied blocks per requestor 2339system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034479 # Average occupied blocks per requestor 2340system.l2c.tags.occ_blocks::cpu0.inst 9248.082270 # Average occupied blocks per requestor 2341system.l2c.tags.occ_blocks::cpu0.data 2930.331388 # Average occupied blocks per requestor 2342system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33200.975902 # Average occupied blocks per requestor 2343system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.874579 # Average occupied blocks per requestor 2344system.l2c.tags.occ_blocks::cpu1.inst 1907.881821 # Average occupied blocks per requestor 2345system.l2c.tags.occ_blocks::cpu1.data 574.003662 # Average occupied blocks per requestor 2346system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1760.558132 # Average occupied blocks per requestor 2347system.l2c.tags.occ_percent::writebacks 0.206120 # Average percentage of cache occupancy 2348system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001270 # Average percentage of cache occupancy 2349system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2350system.l2c.tags.occ_percent::cpu0.inst 0.141115 # Average percentage of cache occupancy 2351system.l2c.tags.occ_percent::cpu0.data 0.044713 # Average percentage of cache occupancy 2352system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506607 # Average percentage of cache occupancy 2353system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000105 # Average percentage of cache occupancy 2354system.l2c.tags.occ_percent::cpu1.inst 0.029112 # Average percentage of cache occupancy 2355system.l2c.tags.occ_percent::cpu1.data 0.008759 # Average percentage of cache occupancy 2356system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026864 # Average percentage of cache occupancy 2357system.l2c.tags.occ_percent::total 0.964664 # Average percentage of cache occupancy 2358system.l2c.tags.occ_task_id_blocks::1022 29038 # Occupied blocks per task id 2359system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id 2360system.l2c.tags.occ_task_id_blocks::1024 35051 # Occupied blocks per task id 2361system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id 2362system.l2c.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id 2363system.l2c.tags.age_task_id_blocks_1022::4 23744 # Occupied blocks per task id 2364system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2365system.l2c.tags.age_task_id_blocks_1023::4 61 # Occupied blocks per task id 2366system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2367system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 2368system.l2c.tags.age_task_id_blocks_1024::2 489 # Occupied blocks per task id 2369system.l2c.tags.age_task_id_blocks_1024::3 3341 # Occupied blocks per task id 2370system.l2c.tags.age_task_id_blocks_1024::4 31190 # Occupied blocks per task id 2371system.l2c.tags.occ_task_id_percent::1022 0.443085 # Percentage of cache occupancy per task id 2372system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id 2373system.l2c.tags.occ_task_id_percent::1024 0.534836 # Percentage of cache occupancy per task id 2374system.l2c.tags.tag_accesses 6395223 # Number of tag accesses 2375system.l2c.tags.data_accesses 6395223 # Number of data accesses 2376system.l2c.WritebackDirty_hits::writebacks 266844 # number of WritebackDirty hits 2377system.l2c.WritebackDirty_hits::total 266844 # number of WritebackDirty hits 2378system.l2c.UpgradeReq_hits::cpu0.data 34054 # number of UpgradeReq hits 2379system.l2c.UpgradeReq_hits::cpu1.data 2186 # number of UpgradeReq hits 2380system.l2c.UpgradeReq_hits::total 36240 # number of UpgradeReq hits 2381system.l2c.SCUpgradeReq_hits::cpu0.data 2212 # number of SCUpgradeReq hits 2382system.l2c.SCUpgradeReq_hits::cpu1.data 949 # number of SCUpgradeReq hits 2383system.l2c.SCUpgradeReq_hits::total 3161 # number of SCUpgradeReq hits 2384system.l2c.ReadExReq_hits::cpu0.data 4419 # number of ReadExReq hits 2385system.l2c.ReadExReq_hits::cpu1.data 1324 # number of ReadExReq hits 2386system.l2c.ReadExReq_hits::total 5743 # number of ReadExReq hits 2387system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 427 # number of ReadSharedReq hits 2388system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits 2389system.l2c.ReadSharedReq_hits::cpu0.inst 47128 # number of ReadSharedReq hits 2390system.l2c.ReadSharedReq_hits::cpu0.data 51485 # number of ReadSharedReq hits 2391system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49241 # number of ReadSharedReq hits 2392system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 65 # number of ReadSharedReq hits 2393system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits 2394system.l2c.ReadSharedReq_hits::cpu1.inst 9897 # number of ReadSharedReq hits 2395system.l2c.ReadSharedReq_hits::cpu1.data 5499 # number of ReadSharedReq hits 2396system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3682 # number of ReadSharedReq hits 2397system.l2c.ReadSharedReq_hits::total 167536 # number of ReadSharedReq hits 2398system.l2c.demand_hits::cpu0.dtb.walker 427 # number of demand (read+write) hits 2399system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits 2400system.l2c.demand_hits::cpu0.inst 47128 # number of demand (read+write) hits 2401system.l2c.demand_hits::cpu0.data 55904 # number of demand (read+write) hits 2402system.l2c.demand_hits::cpu0.l2cache.prefetcher 49241 # number of demand (read+write) hits 2403system.l2c.demand_hits::cpu1.dtb.walker 65 # number of demand (read+write) hits 2404system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits 2405system.l2c.demand_hits::cpu1.inst 9897 # number of demand (read+write) hits 2406system.l2c.demand_hits::cpu1.data 6823 # number of demand (read+write) hits 2407system.l2c.demand_hits::cpu1.l2cache.prefetcher 3682 # number of demand (read+write) hits 2408system.l2c.demand_hits::total 173279 # number of demand (read+write) hits 2409system.l2c.overall_hits::cpu0.dtb.walker 427 # number of overall hits 2410system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits 2411system.l2c.overall_hits::cpu0.inst 47128 # number of overall hits 2412system.l2c.overall_hits::cpu0.data 55904 # number of overall hits 2413system.l2c.overall_hits::cpu0.l2cache.prefetcher 49241 # number of overall hits 2414system.l2c.overall_hits::cpu1.dtb.walker 65 # number of overall hits 2415system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits 2416system.l2c.overall_hits::cpu1.inst 9897 # number of overall hits 2417system.l2c.overall_hits::cpu1.data 6823 # number of overall hits 2418system.l2c.overall_hits::cpu1.l2cache.prefetcher 3682 # number of overall hits 2419system.l2c.overall_hits::total 173279 # number of overall hits 2420system.l2c.UpgradeReq_misses::cpu0.data 10558 # number of UpgradeReq misses 2421system.l2c.UpgradeReq_misses::cpu1.data 2446 # number of UpgradeReq misses 2422system.l2c.UpgradeReq_misses::total 13004 # number of UpgradeReq misses 2423system.l2c.SCUpgradeReq_misses::cpu0.data 813 # number of SCUpgradeReq misses 2424system.l2c.SCUpgradeReq_misses::cpu1.data 1268 # number of SCUpgradeReq misses 2425system.l2c.SCUpgradeReq_misses::total 2081 # number of SCUpgradeReq misses 2426system.l2c.ReadExReq_misses::cpu0.data 11436 # number of ReadExReq misses 2427system.l2c.ReadExReq_misses::cpu1.data 8196 # number of ReadExReq misses 2428system.l2c.ReadExReq_misses::total 19632 # number of ReadExReq misses 2429system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 136 # number of ReadSharedReq misses 2430system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2431system.l2c.ReadSharedReq_misses::cpu0.inst 22627 # number of ReadSharedReq misses 2432system.l2c.ReadSharedReq_misses::cpu0.data 9886 # number of ReadSharedReq misses 2433system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133981 # number of ReadSharedReq misses 2434system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 12 # number of ReadSharedReq misses 2435system.l2c.ReadSharedReq_misses::cpu1.inst 3135 # number of ReadSharedReq misses 2436system.l2c.ReadSharedReq_misses::cpu1.data 1669 # number of ReadSharedReq misses 2437system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5217 # number of ReadSharedReq misses 2438system.l2c.ReadSharedReq_misses::total 176664 # number of ReadSharedReq misses 2439system.l2c.demand_misses::cpu0.dtb.walker 136 # number of demand (read+write) misses 2440system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2441system.l2c.demand_misses::cpu0.inst 22627 # number of demand (read+write) misses 2442system.l2c.demand_misses::cpu0.data 21322 # number of demand (read+write) misses 2443system.l2c.demand_misses::cpu0.l2cache.prefetcher 133981 # number of demand (read+write) misses 2444system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses 2445system.l2c.demand_misses::cpu1.inst 3135 # number of demand (read+write) misses 2446system.l2c.demand_misses::cpu1.data 9865 # number of demand (read+write) misses 2447system.l2c.demand_misses::cpu1.l2cache.prefetcher 5217 # number of demand (read+write) misses 2448system.l2c.demand_misses::total 196296 # number of demand (read+write) misses 2449system.l2c.overall_misses::cpu0.dtb.walker 136 # number of overall misses 2450system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2451system.l2c.overall_misses::cpu0.inst 22627 # number of overall misses 2452system.l2c.overall_misses::cpu0.data 21322 # number of overall misses 2453system.l2c.overall_misses::cpu0.l2cache.prefetcher 133981 # number of overall misses 2454system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses 2455system.l2c.overall_misses::cpu1.inst 3135 # number of overall misses 2456system.l2c.overall_misses::cpu1.data 9865 # number of overall misses 2457system.l2c.overall_misses::cpu1.l2cache.prefetcher 5217 # number of overall misses 2458system.l2c.overall_misses::total 196296 # number of overall misses 2459system.l2c.UpgradeReq_miss_latency::cpu0.data 28885500 # number of UpgradeReq miss cycles 2460system.l2c.UpgradeReq_miss_latency::cpu1.data 6307000 # number of UpgradeReq miss cycles 2461system.l2c.UpgradeReq_miss_latency::total 35192500 # number of UpgradeReq miss cycles 2462system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4708500 # number of SCUpgradeReq miss cycles 2463system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2324500 # number of SCUpgradeReq miss cycles 2464system.l2c.SCUpgradeReq_miss_latency::total 7033000 # number of SCUpgradeReq miss cycles 2465system.l2c.ReadExReq_miss_latency::cpu0.data 1693026000 # number of ReadExReq miss cycles 2466system.l2c.ReadExReq_miss_latency::cpu1.data 1082865500 # number of ReadExReq miss cycles 2467system.l2c.ReadExReq_miss_latency::total 2775891500 # number of ReadExReq miss cycles 2468system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 18689000 # number of ReadSharedReq miss cycles 2469system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles 2470system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2964481500 # number of ReadSharedReq miss cycles 2471system.l2c.ReadSharedReq_miss_latency::cpu0.data 1360660500 # number of ReadSharedReq miss cycles 2472system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20210369984 # number of ReadSharedReq miss cycles 2473system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1607500 # number of ReadSharedReq miss cycles 2474system.l2c.ReadSharedReq_miss_latency::cpu1.inst 418091500 # number of ReadSharedReq miss cycles 2475system.l2c.ReadSharedReq_miss_latency::cpu1.data 230095000 # number of ReadSharedReq miss cycles 2476system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 884419095 # number of ReadSharedReq miss cycles 2477system.l2c.ReadSharedReq_miss_latency::total 26088547079 # number of ReadSharedReq miss cycles 2478system.l2c.demand_miss_latency::cpu0.dtb.walker 18689000 # number of demand (read+write) miss cycles 2479system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles 2480system.l2c.demand_miss_latency::cpu0.inst 2964481500 # number of demand (read+write) miss cycles 2481system.l2c.demand_miss_latency::cpu0.data 3053686500 # number of demand (read+write) miss cycles 2482system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20210369984 # number of demand (read+write) miss cycles 2483system.l2c.demand_miss_latency::cpu1.dtb.walker 1607500 # number of demand (read+write) miss cycles 2484system.l2c.demand_miss_latency::cpu1.inst 418091500 # number of demand (read+write) miss cycles 2485system.l2c.demand_miss_latency::cpu1.data 1312960500 # number of demand (read+write) miss cycles 2486system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 884419095 # number of demand (read+write) miss cycles 2487system.l2c.demand_miss_latency::total 28864438579 # number of demand (read+write) miss cycles 2488system.l2c.overall_miss_latency::cpu0.dtb.walker 18689000 # number of overall miss cycles 2489system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles 2490system.l2c.overall_miss_latency::cpu0.inst 2964481500 # number of overall miss cycles 2491system.l2c.overall_miss_latency::cpu0.data 3053686500 # number of overall miss cycles 2492system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20210369984 # number of overall miss cycles 2493system.l2c.overall_miss_latency::cpu1.dtb.walker 1607500 # number of overall miss cycles 2494system.l2c.overall_miss_latency::cpu1.inst 418091500 # number of overall miss cycles 2495system.l2c.overall_miss_latency::cpu1.data 1312960500 # number of overall miss cycles 2496system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 884419095 # number of overall miss cycles 2497system.l2c.overall_miss_latency::total 28864438579 # number of overall miss cycles 2498system.l2c.WritebackDirty_accesses::writebacks 266844 # number of WritebackDirty accesses(hits+misses) 2499system.l2c.WritebackDirty_accesses::total 266844 # number of WritebackDirty accesses(hits+misses) 2500system.l2c.UpgradeReq_accesses::cpu0.data 44612 # number of UpgradeReq accesses(hits+misses) 2501system.l2c.UpgradeReq_accesses::cpu1.data 4632 # number of UpgradeReq accesses(hits+misses) 2502system.l2c.UpgradeReq_accesses::total 49244 # number of UpgradeReq accesses(hits+misses) 2503system.l2c.SCUpgradeReq_accesses::cpu0.data 3025 # number of SCUpgradeReq accesses(hits+misses) 2504system.l2c.SCUpgradeReq_accesses::cpu1.data 2217 # number of SCUpgradeReq accesses(hits+misses) 2505system.l2c.SCUpgradeReq_accesses::total 5242 # number of SCUpgradeReq accesses(hits+misses) 2506system.l2c.ReadExReq_accesses::cpu0.data 15855 # number of ReadExReq accesses(hits+misses) 2507system.l2c.ReadExReq_accesses::cpu1.data 9520 # number of ReadExReq accesses(hits+misses) 2508system.l2c.ReadExReq_accesses::total 25375 # number of ReadExReq accesses(hits+misses) 2509system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 563 # number of ReadSharedReq accesses(hits+misses) 2510system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 97 # number of ReadSharedReq accesses(hits+misses) 2511system.l2c.ReadSharedReq_accesses::cpu0.inst 69755 # number of ReadSharedReq accesses(hits+misses) 2512system.l2c.ReadSharedReq_accesses::cpu0.data 61371 # number of ReadSharedReq accesses(hits+misses) 2513system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183222 # number of ReadSharedReq accesses(hits+misses) 2514system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 77 # number of ReadSharedReq accesses(hits+misses) 2515system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 16 # number of ReadSharedReq accesses(hits+misses) 2516system.l2c.ReadSharedReq_accesses::cpu1.inst 13032 # number of ReadSharedReq accesses(hits+misses) 2517system.l2c.ReadSharedReq_accesses::cpu1.data 7168 # number of ReadSharedReq accesses(hits+misses) 2518system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8899 # number of ReadSharedReq accesses(hits+misses) 2519system.l2c.ReadSharedReq_accesses::total 344200 # number of ReadSharedReq accesses(hits+misses) 2520system.l2c.demand_accesses::cpu0.dtb.walker 563 # number of demand (read+write) accesses 2521system.l2c.demand_accesses::cpu0.itb.walker 97 # number of demand (read+write) accesses 2522system.l2c.demand_accesses::cpu0.inst 69755 # number of demand (read+write) accesses 2523system.l2c.demand_accesses::cpu0.data 77226 # number of demand (read+write) accesses 2524system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183222 # number of demand (read+write) accesses 2525system.l2c.demand_accesses::cpu1.dtb.walker 77 # number of demand (read+write) accesses 2526system.l2c.demand_accesses::cpu1.itb.walker 16 # number of demand (read+write) accesses 2527system.l2c.demand_accesses::cpu1.inst 13032 # number of demand (read+write) accesses 2528system.l2c.demand_accesses::cpu1.data 16688 # number of demand (read+write) accesses 2529system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8899 # number of demand (read+write) accesses 2530system.l2c.demand_accesses::total 369575 # number of demand (read+write) accesses 2531system.l2c.overall_accesses::cpu0.dtb.walker 563 # number of overall (read+write) accesses 2532system.l2c.overall_accesses::cpu0.itb.walker 97 # number of overall (read+write) accesses 2533system.l2c.overall_accesses::cpu0.inst 69755 # number of overall (read+write) accesses 2534system.l2c.overall_accesses::cpu0.data 77226 # number of overall (read+write) accesses 2535system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183222 # number of overall (read+write) accesses 2536system.l2c.overall_accesses::cpu1.dtb.walker 77 # number of overall (read+write) accesses 2537system.l2c.overall_accesses::cpu1.itb.walker 16 # number of overall (read+write) accesses 2538system.l2c.overall_accesses::cpu1.inst 13032 # number of overall (read+write) accesses 2539system.l2c.overall_accesses::cpu1.data 16688 # number of overall (read+write) accesses 2540system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8899 # number of overall (read+write) accesses 2541system.l2c.overall_accesses::total 369575 # number of overall (read+write) accesses 2542system.l2c.UpgradeReq_miss_rate::cpu0.data 0.236663 # miss rate for UpgradeReq accesses 2543system.l2c.UpgradeReq_miss_rate::cpu1.data 0.528066 # miss rate for UpgradeReq accesses 2544system.l2c.UpgradeReq_miss_rate::total 0.264073 # miss rate for UpgradeReq accesses 2545system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.268760 # miss rate for SCUpgradeReq accesses 2546system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.571944 # miss rate for SCUpgradeReq accesses 2547system.l2c.SCUpgradeReq_miss_rate::total 0.396986 # miss rate for SCUpgradeReq accesses 2548system.l2c.ReadExReq_miss_rate::cpu0.data 0.721287 # miss rate for ReadExReq accesses 2549system.l2c.ReadExReq_miss_rate::cpu1.data 0.860924 # miss rate for ReadExReq accesses 2550system.l2c.ReadExReq_miss_rate::total 0.773675 # miss rate for ReadExReq accesses 2551system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.241563 # miss rate for ReadSharedReq accesses 2552system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010309 # miss rate for ReadSharedReq accesses 2553system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.324378 # miss rate for ReadSharedReq accesses 2554system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161086 # miss rate for ReadSharedReq accesses 2555system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.731250 # miss rate for ReadSharedReq accesses 2556system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155844 # miss rate for ReadSharedReq accesses 2557system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.240562 # miss rate for ReadSharedReq accesses 2558system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.232840 # miss rate for ReadSharedReq accesses 2559system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.586246 # miss rate for ReadSharedReq accesses 2560system.l2c.ReadSharedReq_miss_rate::total 0.513260 # miss rate for ReadSharedReq accesses 2561system.l2c.demand_miss_rate::cpu0.dtb.walker 0.241563 # miss rate for demand accesses 2562system.l2c.demand_miss_rate::cpu0.itb.walker 0.010309 # miss rate for demand accesses 2563system.l2c.demand_miss_rate::cpu0.inst 0.324378 # miss rate for demand accesses 2564system.l2c.demand_miss_rate::cpu0.data 0.276099 # miss rate for demand accesses 2565system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731250 # miss rate for demand accesses 2566system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155844 # miss rate for demand accesses 2567system.l2c.demand_miss_rate::cpu1.inst 0.240562 # miss rate for demand accesses 2568system.l2c.demand_miss_rate::cpu1.data 0.591143 # miss rate for demand accesses 2569system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.586246 # miss rate for demand accesses 2570system.l2c.demand_miss_rate::total 0.531140 # miss rate for demand accesses 2571system.l2c.overall_miss_rate::cpu0.dtb.walker 0.241563 # miss rate for overall accesses 2572system.l2c.overall_miss_rate::cpu0.itb.walker 0.010309 # miss rate for overall accesses 2573system.l2c.overall_miss_rate::cpu0.inst 0.324378 # miss rate for overall accesses 2574system.l2c.overall_miss_rate::cpu0.data 0.276099 # miss rate for overall accesses 2575system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731250 # miss rate for overall accesses 2576system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155844 # miss rate for overall accesses 2577system.l2c.overall_miss_rate::cpu1.inst 0.240562 # miss rate for overall accesses 2578system.l2c.overall_miss_rate::cpu1.data 0.591143 # miss rate for overall accesses 2579system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.586246 # miss rate for overall accesses 2580system.l2c.overall_miss_rate::total 0.531140 # miss rate for overall accesses 2581system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2735.887479 # average UpgradeReq miss latency 2582system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2578.495503 # average UpgradeReq miss latency 2583system.l2c.UpgradeReq_avg_miss_latency::total 2706.282682 # average UpgradeReq miss latency 2584system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5791.512915 # average SCUpgradeReq miss latency 2585system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1833.201893 # average SCUpgradeReq miss latency 2586system.l2c.SCUpgradeReq_avg_miss_latency::total 3379.625180 # average SCUpgradeReq miss latency 2587system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148043.546695 # average ReadExReq miss latency 2588system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132121.217667 # average ReadExReq miss latency 2589system.l2c.ReadExReq_avg_miss_latency::total 141396.266300 # average ReadExReq miss latency 2590system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137419.117647 # average ReadSharedReq miss latency 2591system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency 2592system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131015.225173 # average ReadSharedReq miss latency 2593system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137635.090026 # average ReadSharedReq miss latency 2594system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150845.045074 # average ReadSharedReq miss latency 2595system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 133958.333333 # average ReadSharedReq miss latency 2596system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133362.519936 # average ReadSharedReq miss latency 2597system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 137863.990413 # average ReadSharedReq miss latency 2598system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169526.374353 # average ReadSharedReq miss latency 2599system.l2c.ReadSharedReq_avg_miss_latency::total 147673.250232 # average ReadSharedReq miss latency 2600system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137419.117647 # average overall miss latency 2601system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2602system.l2c.demand_avg_miss_latency::cpu0.inst 131015.225173 # average overall miss latency 2603system.l2c.demand_avg_miss_latency::cpu0.data 143217.639058 # average overall miss latency 2604system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150845.045074 # average overall miss latency 2605system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 133958.333333 # average overall miss latency 2606system.l2c.demand_avg_miss_latency::cpu1.inst 133362.519936 # average overall miss latency 2607system.l2c.demand_avg_miss_latency::cpu1.data 133092.802838 # average overall miss latency 2608system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169526.374353 # average overall miss latency 2609system.l2c.demand_avg_miss_latency::total 147045.475094 # average overall miss latency 2610system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137419.117647 # average overall miss latency 2611system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2612system.l2c.overall_avg_miss_latency::cpu0.inst 131015.225173 # average overall miss latency 2613system.l2c.overall_avg_miss_latency::cpu0.data 143217.639058 # average overall miss latency 2614system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150845.045074 # average overall miss latency 2615system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 133958.333333 # average overall miss latency 2616system.l2c.overall_avg_miss_latency::cpu1.inst 133362.519936 # average overall miss latency 2617system.l2c.overall_avg_miss_latency::cpu1.data 133092.802838 # average overall miss latency 2618system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169526.374353 # average overall miss latency 2619system.l2c.overall_avg_miss_latency::total 147045.475094 # average overall miss latency 2620system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2621system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2622system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2623system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2624system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2625system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2626system.l2c.fast_writes 0 # number of fast writes performed 2627system.l2c.cache_copies 0 # number of cache copies performed 2628system.l2c.writebacks::writebacks 102230 # number of writebacks 2629system.l2c.writebacks::total 102230 # number of writebacks 2630system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits 2631system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 3 # number of ReadSharedReq MSHR hits 2632system.l2c.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits 2633system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 2634system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2635system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 2636system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 2637system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2638system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits 2639system.l2c.CleanEvict_mshr_misses::writebacks 3594 # number of CleanEvict MSHR misses 2640system.l2c.CleanEvict_mshr_misses::total 3594 # number of CleanEvict MSHR misses 2641system.l2c.UpgradeReq_mshr_misses::cpu0.data 10558 # number of UpgradeReq MSHR misses 2642system.l2c.UpgradeReq_mshr_misses::cpu1.data 2446 # number of UpgradeReq MSHR misses 2643system.l2c.UpgradeReq_mshr_misses::total 13004 # number of UpgradeReq MSHR misses 2644system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 813 # number of SCUpgradeReq MSHR misses 2645system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1268 # number of SCUpgradeReq MSHR misses 2646system.l2c.SCUpgradeReq_mshr_misses::total 2081 # number of SCUpgradeReq MSHR misses 2647system.l2c.ReadExReq_mshr_misses::cpu0.data 11436 # number of ReadExReq MSHR misses 2648system.l2c.ReadExReq_mshr_misses::cpu1.data 8196 # number of ReadExReq MSHR misses 2649system.l2c.ReadExReq_mshr_misses::total 19632 # number of ReadExReq MSHR misses 2650system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 136 # number of ReadSharedReq MSHR misses 2651system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2652system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22623 # number of ReadSharedReq MSHR misses 2653system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9886 # number of ReadSharedReq MSHR misses 2654system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133981 # number of ReadSharedReq MSHR misses 2655system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadSharedReq MSHR misses 2656system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3132 # number of ReadSharedReq MSHR misses 2657system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1669 # number of ReadSharedReq MSHR misses 2658system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5217 # number of ReadSharedReq MSHR misses 2659system.l2c.ReadSharedReq_mshr_misses::total 176657 # number of ReadSharedReq MSHR misses 2660system.l2c.demand_mshr_misses::cpu0.dtb.walker 136 # number of demand (read+write) MSHR misses 2661system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2662system.l2c.demand_mshr_misses::cpu0.inst 22623 # number of demand (read+write) MSHR misses 2663system.l2c.demand_mshr_misses::cpu0.data 21322 # number of demand (read+write) MSHR misses 2664system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133981 # number of demand (read+write) MSHR misses 2665system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses 2666system.l2c.demand_mshr_misses::cpu1.inst 3132 # number of demand (read+write) MSHR misses 2667system.l2c.demand_mshr_misses::cpu1.data 9865 # number of demand (read+write) MSHR misses 2668system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5217 # number of demand (read+write) MSHR misses 2669system.l2c.demand_mshr_misses::total 196289 # number of demand (read+write) MSHR misses 2670system.l2c.overall_mshr_misses::cpu0.dtb.walker 136 # number of overall MSHR misses 2671system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2672system.l2c.overall_mshr_misses::cpu0.inst 22623 # number of overall MSHR misses 2673system.l2c.overall_mshr_misses::cpu0.data 21322 # number of overall MSHR misses 2674system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133981 # number of overall MSHR misses 2675system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses 2676system.l2c.overall_mshr_misses::cpu1.inst 3132 # number of overall MSHR misses 2677system.l2c.overall_mshr_misses::cpu1.data 9865 # number of overall MSHR misses 2678system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5217 # number of overall MSHR misses 2679system.l2c.overall_mshr_misses::total 196289 # number of overall MSHR misses 2680system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 2681system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32039 # number of ReadReq MSHR uncacheable 2682system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2683system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable 2684system.l2c.ReadReq_mshr_uncacheable::total 39041 # number of ReadReq MSHR uncacheable 2685system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable 2686system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2312 # number of WriteReq MSHR uncacheable 2687system.l2c.WriteReq_mshr_uncacheable::total 31034 # number of WriteReq MSHR uncacheable 2688system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 2689system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60761 # number of overall MSHR uncacheable misses 2690system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2691system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5285 # number of overall MSHR uncacheable misses 2692system.l2c.overall_mshr_uncacheable_misses::total 70075 # number of overall MSHR uncacheable misses 2693system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 768980000 # number of UpgradeReq MSHR miss cycles 2694system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177072500 # number of UpgradeReq MSHR miss cycles 2695system.l2c.UpgradeReq_mshr_miss_latency::total 946052500 # number of UpgradeReq MSHR miss cycles 2696system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 60701000 # number of SCUpgradeReq MSHR miss cycles 2697system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 93683500 # number of SCUpgradeReq MSHR miss cycles 2698system.l2c.SCUpgradeReq_mshr_miss_latency::total 154384500 # number of SCUpgradeReq MSHR miss cycles 2699system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1578661509 # number of ReadExReq MSHR miss cycles 2700system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1000899512 # number of ReadExReq MSHR miss cycles 2701system.l2c.ReadExReq_mshr_miss_latency::total 2579561021 # number of ReadExReq MSHR miss cycles 2702system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 17329000 # number of ReadSharedReq MSHR miss cycles 2703system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles 2704system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2737799020 # number of ReadSharedReq MSHR miss cycles 2705system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1261795013 # number of ReadSharedReq MSHR miss cycles 2706system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18870521135 # number of ReadSharedReq MSHR miss cycles 2707system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1487500 # number of ReadSharedReq MSHR miss cycles 2708system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 386490025 # number of ReadSharedReq MSHR miss cycles 2709system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 213404501 # number of ReadSharedReq MSHR miss cycles 2710system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 832239127 # number of ReadSharedReq MSHR miss cycles 2711system.l2c.ReadSharedReq_mshr_miss_latency::total 24321188321 # number of ReadSharedReq MSHR miss cycles 2712system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 17329000 # number of demand (read+write) MSHR miss cycles 2713system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles 2714system.l2c.demand_mshr_miss_latency::cpu0.inst 2737799020 # number of demand (read+write) MSHR miss cycles 2715system.l2c.demand_mshr_miss_latency::cpu0.data 2840456522 # number of demand (read+write) MSHR miss cycles 2716system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18870521135 # number of demand (read+write) MSHR miss cycles 2717system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1487500 # number of demand (read+write) MSHR miss cycles 2718system.l2c.demand_mshr_miss_latency::cpu1.inst 386490025 # number of demand (read+write) MSHR miss cycles 2719system.l2c.demand_mshr_miss_latency::cpu1.data 1214304013 # number of demand (read+write) MSHR miss cycles 2720system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 832239127 # number of demand (read+write) MSHR miss cycles 2721system.l2c.demand_mshr_miss_latency::total 26900749342 # number of demand (read+write) MSHR miss cycles 2722system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 17329000 # number of overall MSHR miss cycles 2723system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles 2724system.l2c.overall_mshr_miss_latency::cpu0.inst 2737799020 # number of overall MSHR miss cycles 2725system.l2c.overall_mshr_miss_latency::cpu0.data 2840456522 # number of overall MSHR miss cycles 2726system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18870521135 # number of overall MSHR miss cycles 2727system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1487500 # number of overall MSHR miss cycles 2728system.l2c.overall_mshr_miss_latency::cpu1.inst 386490025 # number of overall MSHR miss cycles 2729system.l2c.overall_mshr_miss_latency::cpu1.data 1214304013 # number of overall MSHR miss cycles 2730system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 832239127 # number of overall MSHR miss cycles 2731system.l2c.overall_mshr_miss_latency::total 26900749342 # number of overall MSHR miss cycles 2732system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles 2733system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5868527006 # number of ReadReq MSHR uncacheable cycles 2734system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12102000 # number of ReadReq MSHR uncacheable cycles 2735system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 311952502 # number of ReadReq MSHR uncacheable cycles 2736system.l2c.ReadReq_mshr_uncacheable_latency::total 6636344508 # number of ReadReq MSHR uncacheable cycles 2737system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4748274504 # number of WriteReq MSHR uncacheable cycles 2738system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195262502 # number of WriteReq MSHR uncacheable cycles 2739system.l2c.WriteReq_mshr_uncacheable_latency::total 4943537006 # number of WriteReq MSHR uncacheable cycles 2740system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles 2741system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10616801510 # number of overall MSHR uncacheable cycles 2742system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12102000 # number of overall MSHR uncacheable cycles 2743system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507215004 # number of overall MSHR uncacheable cycles 2744system.l2c.overall_mshr_uncacheable_latency::total 11579881514 # number of overall MSHR uncacheable cycles 2745system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2746system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2747system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.236663 # mshr miss rate for UpgradeReq accesses 2748system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.528066 # mshr miss rate for UpgradeReq accesses 2749system.l2c.UpgradeReq_mshr_miss_rate::total 0.264073 # mshr miss rate for UpgradeReq accesses 2750system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.268760 # mshr miss rate for SCUpgradeReq accesses 2751system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.571944 # mshr miss rate for SCUpgradeReq accesses 2752system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396986 # mshr miss rate for SCUpgradeReq accesses 2753system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.721287 # mshr miss rate for ReadExReq accesses 2754system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.860924 # mshr miss rate for ReadExReq accesses 2755system.l2c.ReadExReq_mshr_miss_rate::total 0.773675 # mshr miss rate for ReadExReq accesses 2756system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for ReadSharedReq accesses 2757system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses 2758system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.324321 # mshr miss rate for ReadSharedReq accesses 2759system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161086 # mshr miss rate for ReadSharedReq accesses 2760system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731250 # mshr miss rate for ReadSharedReq accesses 2761system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for ReadSharedReq accesses 2762system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for ReadSharedReq accesses 2763system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.232840 # mshr miss rate for ReadSharedReq accesses 2764system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for ReadSharedReq accesses 2765system.l2c.ReadSharedReq_mshr_miss_rate::total 0.513239 # mshr miss rate for ReadSharedReq accesses 2766system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for demand accesses 2767system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses 2768system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324321 # mshr miss rate for demand accesses 2769system.l2c.demand_mshr_miss_rate::cpu0.data 0.276099 # mshr miss rate for demand accesses 2770system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731250 # mshr miss rate for demand accesses 2771system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for demand accesses 2772system.l2c.demand_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for demand accesses 2773system.l2c.demand_mshr_miss_rate::cpu1.data 0.591143 # mshr miss rate for demand accesses 2774system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for demand accesses 2775system.l2c.demand_mshr_miss_rate::total 0.531121 # mshr miss rate for demand accesses 2776system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for overall accesses 2777system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses 2778system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324321 # mshr miss rate for overall accesses 2779system.l2c.overall_mshr_miss_rate::cpu0.data 0.276099 # mshr miss rate for overall accesses 2780system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731250 # mshr miss rate for overall accesses 2781system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for overall accesses 2782system.l2c.overall_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for overall accesses 2783system.l2c.overall_mshr_miss_rate::cpu1.data 0.591143 # mshr miss rate for overall accesses 2784system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for overall accesses 2785system.l2c.overall_mshr_miss_rate::total 0.531121 # mshr miss rate for overall accesses 2786system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72833.870051 # average UpgradeReq mshr miss latency 2787system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72392.681930 # average UpgradeReq mshr miss latency 2788system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72750.884343 # average UpgradeReq mshr miss latency 2789system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74662.976630 # average SCUpgradeReq mshr miss latency 2790system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73882.886435 # average SCUpgradeReq mshr miss latency 2791system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.650168 # average SCUpgradeReq mshr miss latency 2792system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138043.153987 # average ReadExReq mshr miss latency 2793system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122120.487067 # average ReadExReq mshr miss latency 2794system.l2c.ReadExReq_avg_mshr_miss_latency::total 131395.732529 # average ReadExReq mshr miss latency 2795system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average ReadSharedReq mshr miss latency 2796system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency 2797system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average ReadSharedReq mshr miss latency 2798system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127634.534999 # average ReadSharedReq mshr miss latency 2799system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average ReadSharedReq mshr miss latency 2800system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average ReadSharedReq mshr miss latency 2801system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average ReadSharedReq mshr miss latency 2802system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127863.691432 # average ReadSharedReq mshr miss latency 2803system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average ReadSharedReq mshr miss latency 2804system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137674.636844 # average ReadSharedReq mshr miss latency 2805system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average overall mshr miss latency 2806system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2807system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average overall mshr miss latency 2808system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133217.171091 # average overall mshr miss latency 2809system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average overall mshr miss latency 2810system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average overall mshr miss latency 2811system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency 2812system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency 2813system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency 2814system.l2c.demand_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency 2815system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average overall mshr miss latency 2816system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2817system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average overall mshr miss latency 2818system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133217.171091 # average overall mshr miss latency 2819system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average overall mshr miss latency 2820system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average overall mshr miss latency 2821system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency 2822system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency 2823system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency 2824system.l2c.overall_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency 2825system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency 2826system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.232654 # average ReadReq mshr uncacheable latency 2827system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency 2828system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104928.524050 # average ReadReq mshr uncacheable latency 2829system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169983.978587 # average ReadReq mshr uncacheable latency 2830system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165318.379779 # average WriteReq mshr uncacheable latency 2831system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84456.099481 # average WriteReq mshr uncacheable latency 2832system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159294.225881 # average WriteReq mshr uncacheable latency 2833system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency 2834system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174730.526324 # average overall mshr uncacheable latency 2835system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency 2836system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95972.564617 # average overall mshr uncacheable latency 2837system.l2c.overall_avg_mshr_uncacheable_latency::total 165249.825387 # average overall mshr uncacheable latency 2838system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2839system.membus.trans_dist::ReadReq 39041 # Transaction distribution 2840system.membus.trans_dist::ReadResp 215941 # Transaction distribution 2841system.membus.trans_dist::WriteReq 31034 # Transaction distribution 2842system.membus.trans_dist::WriteResp 31034 # Transaction distribution 2843system.membus.trans_dist::WritebackDirty 138436 # Transaction distribution 2844system.membus.trans_dist::CleanEvict 18070 # Transaction distribution 2845system.membus.trans_dist::UpgradeReq 73582 # Transaction distribution 2846system.membus.trans_dist::SCUpgradeReq 40721 # Transaction distribution 2847system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2848system.membus.trans_dist::ReadExReq 40108 # Transaction distribution 2849system.membus.trans_dist::ReadExResp 19531 # Transaction distribution 2850system.membus.trans_dist::ReadSharedReq 176900 # Transaction distribution 2851system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2852system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) 2853system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2854system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14216 # Packet count per connected master and slave (bytes) 2855system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664933 # Packet count per connected master and slave (bytes) 2856system.membus.pkt_count_system.l2c.mem_side::total 787125 # Packet count per connected master and slave (bytes) 2857system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) 2858system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) 2859system.membus.pkt_count::total 860056 # Packet count per connected master and slave (bytes) 2860system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) 2861system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2862system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28432 # Cumulative packet size per connected master and slave (bytes) 2863system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19353628 # Cumulative packet size per connected master and slave (bytes) 2864system.membus.pkt_size_system.l2c.mem_side::total 19546218 # Cumulative packet size per connected master and slave (bytes) 2865system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2866system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2867system.membus.pkt_size::total 21864362 # Cumulative packet size per connected master and slave (bytes) 2868system.membus.snoops 120262 # Total snoops (count) 2869system.membus.snoop_fanout::samples 594139 # Request fanout histogram 2870system.membus.snoop_fanout::mean 1 # Request fanout histogram 2871system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2872system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2873system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2874system.membus.snoop_fanout::1 594139 100.00% 100.00% # Request fanout histogram 2875system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2876system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2877system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2878system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2879system.membus.snoop_fanout::total 594139 # Request fanout histogram 2880system.membus.reqLayer0.occupancy 91324000 # Layer occupancy (ticks) 2881system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2882system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) 2883system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2884system.membus.reqLayer2.occupancy 12307500 # Layer occupancy (ticks) 2885system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2886system.membus.reqLayer5.occupancy 1010896317 # Layer occupancy (ticks) 2887system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2888system.membus.respLayer2.occupancy 1147679286 # Layer occupancy (ticks) 2889system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2890system.membus.respLayer3.occupancy 1341127 # Layer occupancy (ticks) 2891system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2892system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2893system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2894system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2895system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2896system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2897system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2898system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2899system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2900system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2901system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2902system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2903system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2904system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2905system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2906system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2907system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2908system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2909system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2910system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2911system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2912system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2913system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2914system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2915system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2916system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2917system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2918system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2919system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2920system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2921system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2922system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2923system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2924system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2925system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2926system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2927system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2928system.realview.ethernet.droppedPackets 0 # number of packets dropped 2929system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 2930system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 2931system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 2932system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 2933system.toL2Bus.snoop_filter.tot_requests 1042334 # Total number of requests made to the snoop filter. 2934system.toL2Bus.snoop_filter.hit_single_requests 562614 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2935system.toL2Bus.snoop_filter.hit_multi_requests 153410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2936system.toL2Bus.snoop_filter.tot_snoops 21132 # Total number of snoops made to the snoop filter. 2937system.toL2Bus.snoop_filter.hit_single_snoops 20109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2938system.toL2Bus.snoop_filter.hit_multi_snoops 1023 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2939system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution 2940system.toL2Bus.trans_dist::ReadResp 500861 # Transaction distribution 2941system.toL2Bus.trans_dist::WriteReq 31034 # Transaction distribution 2942system.toL2Bus.trans_dist::WriteResp 31034 # Transaction distribution 2943system.toL2Bus.trans_dist::WritebackDirty 405302 # Transaction distribution 2944system.toL2Bus.trans_dist::CleanEvict 139265 # Transaction distribution 2945system.toL2Bus.trans_dist::UpgradeReq 109721 # Transaction distribution 2946system.toL2Bus.trans_dist::SCUpgradeReq 43882 # Transaction distribution 2947system.toL2Bus.trans_dist::UpgradeResp 153603 # Transaction distribution 2948system.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution 2949system.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution 2950system.toL2Bus.trans_dist::ReadExReq 51189 # Transaction distribution 2951system.toL2Bus.trans_dist::ReadExResp 51189 # Transaction distribution 2952system.toL2Bus.trans_dist::ReadSharedReq 461832 # Transaction distribution 2953system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2954system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1332417 # Packet count per connected master and slave (bytes) 2955system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274320 # Packet count per connected master and slave (bytes) 2956system.toL2Bus.pkt_count::total 1606737 # Packet count per connected master and slave (bytes) 2957system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36835698 # Cumulative packet size per connected master and slave (bytes) 2958system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4378808 # Cumulative packet size per connected master and slave (bytes) 2959system.toL2Bus.pkt_size::total 41214506 # Cumulative packet size per connected master and slave (bytes) 2960system.toL2Bus.snoops 447707 # Total snoops (count) 2961system.toL2Bus.snoop_fanout::samples 941615 # Request fanout histogram 2962system.toL2Bus.snoop_fanout::mean 0.339048 # Request fanout histogram 2963system.toL2Bus.snoop_fanout::stdev 0.475676 # Request fanout histogram 2964system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2965system.toL2Bus.snoop_fanout::0 623385 66.20% 66.20% # Request fanout histogram 2966system.toL2Bus.snoop_fanout::1 317207 33.69% 99.89% # Request fanout histogram 2967system.toL2Bus.snoop_fanout::2 1023 0.11% 100.00% # Request fanout histogram 2968system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2969system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2970system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2971system.toL2Bus.snoop_fanout::total 941615 # Request fanout histogram 2972system.toL2Bus.reqLayer0.occupancy 901922668 # Layer occupancy (ticks) 2973system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2974system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) 2975system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2976system.toL2Bus.respLayer0.occupancy 690834076 # Layer occupancy (ticks) 2977system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2978system.toL2Bus.respLayer1.occupancy 214047025 # Layer occupancy (ticks) 2979system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2980 2981---------- End Simulation Statistics ---------- 2982