stats.txt revision 11245:1c5102c0a7a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.848979 # Number of seconds simulated 4sim_ticks 2848979128500 # Number of ticks simulated 5final_tick 2848979128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 154282 # Simulator instruction rate (inst/s) 8host_op_rate 186830 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3456392917 # Simulator tick rate (ticks/s) 10host_mem_usage 618280 # Number of bytes of host memory used 11host_seconds 824.26 # Real time elapsed on the host 12sim_insts 127169330 # Number of instructions simulated 13sim_ops 153997543 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 8448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1698560 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1348800 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8516160 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 208256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 632788 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 357568 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12772244 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1698560 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 208256 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1906816 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8849024 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8866588 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 132 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26540 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 21601 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133065 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3254 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9908 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5587 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 200113 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 138266 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 142657 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 2965 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 596200 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 473433 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2989197 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 225 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 73098 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 222110 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 125507 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4483095 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 596200 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 73098 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 669298 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3106033 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 3112198 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3106033 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 2965 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 596200 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 479584 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2989197 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 225 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 73098 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 222124 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 125507 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7595293 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 200113 # Number of read requests accepted 80system.physmem.writeReqs 142657 # Number of write requests accepted 81system.physmem.readBursts 200113 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 142657 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12798592 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8879168 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12772244 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8866588 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 69084 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12287 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12592 # Per bank write bursts 93system.physmem.perBankRdBursts::2 13485 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12796 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15663 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12764 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12615 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12815 # Per bank write bursts 99system.physmem.perBankRdBursts::8 11998 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12140 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11596 # Per bank write bursts 102system.physmem.perBankRdBursts::11 10685 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11914 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12844 # Per bank write bursts 105system.physmem.perBankRdBursts::14 12075 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11709 # Per bank write bursts 107system.physmem.perBankWrBursts::0 8805 # Per bank write bursts 108system.physmem.perBankWrBursts::1 9189 # Per bank write bursts 109system.physmem.perBankWrBursts::2 9797 # Per bank write bursts 110system.physmem.perBankWrBursts::3 9112 # Per bank write bursts 111system.physmem.perBankWrBursts::4 8303 # Per bank write bursts 112system.physmem.perBankWrBursts::5 8892 # Per bank write bursts 113system.physmem.perBankWrBursts::6 8866 # Per bank write bursts 114system.physmem.perBankWrBursts::7 8915 # Per bank write bursts 115system.physmem.perBankWrBursts::8 8401 # Per bank write bursts 116system.physmem.perBankWrBursts::9 8590 # Per bank write bursts 117system.physmem.perBankWrBursts::10 8283 # Per bank write bursts 118system.physmem.perBankWrBursts::11 7752 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8566 # Per bank write bursts 120system.physmem.perBankWrBursts::13 8822 # Per bank write bursts 121system.physmem.perBankWrBursts::14 8545 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7899 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 18 # Number of times write queue was full causing retry 125system.physmem.totGap 2848978583000 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 557 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 199528 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 138266 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 88817 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 60985 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9494 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7806 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6286 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4625 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3738 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 641 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 202 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 157 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 136 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 113 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2866 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3333 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 4614 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5998 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6540 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 7779 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7940 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8957 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 9084 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 9291 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 10972 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 9095 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 9017 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 10232 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8688 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7869 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7517 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 557 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 414 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 220 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 146 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 55 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 92122 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 235.314387 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 133.718922 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 297.822907 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 49981 54.26% 54.26% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17852 19.38% 73.63% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6274 6.81% 80.44% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3559 3.86% 84.31% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2993 3.25% 87.56% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1358 1.47% 89.03% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 900 0.98% 90.01% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 994 1.08% 91.09% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8211 8.91% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 92122 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6829 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 29.283204 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 564.566486 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6828 99.99% 99.99% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::total 6829 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6829 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 20.315859 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 18.777431 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 12.379766 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-19 5626 82.38% 82.38% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20-23 466 6.82% 89.21% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::24-27 97 1.42% 90.63% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::28-31 149 2.18% 92.81% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::32-35 29 0.42% 93.23% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::36-39 128 1.87% 95.11% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::40-43 35 0.51% 95.62% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::44-47 17 0.25% 95.87% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::48-51 25 0.37% 96.24% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::52-55 23 0.34% 96.57% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::56-59 7 0.10% 96.68% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::60-63 8 0.12% 96.79% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-67 138 2.02% 98.81% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::68-71 8 0.12% 98.93% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::72-75 4 0.06% 98.99% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::76-79 26 0.38% 99.37% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::84-87 4 0.06% 99.52% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::92-95 1 0.01% 99.53% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::104-107 1 0.01% 99.59% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::120-123 2 0.03% 99.63% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::128-131 14 0.21% 99.87% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::152-155 2 0.03% 99.96% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::156-159 1 0.01% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::total 6829 # Writes before turning the bus around for reads 293system.physmem.totQLat 5270639949 # Total ticks spent queuing 294system.physmem.totMemAccLat 9020227449 # Total ticks spent from burst creation until serviced by the DRAM 295system.physmem.totBusLat 999890000 # Total ticks spent in databus transfers 296system.physmem.avgQLat 26356.10 # Average queueing delay per DRAM burst 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 298system.physmem.avgMemAccLat 45106.10 # Average memory access latency per DRAM burst 299system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s 300system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s 301system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s 302system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 0.06 # Data bus utilization in percentage 305system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 307system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 308system.physmem.avgWrQLen 21.71 # Average write queue length when enqueuing 309system.physmem.readRowHits 166028 # Number of row buffer hits during reads 310system.physmem.writeRowHits 80563 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes 313system.physmem.avgGap 8311633.41 # Average gap between requests 314system.physmem.pageHitRate 72.80 # Row buffer hit rate, read and write combined 315system.physmem_0.actEnergy 367945200 # Energy for activate commands per rank (pJ) 316system.physmem_0.preEnergy 200763750 # Energy for precharge commands per rank (pJ) 317system.physmem_0.readEnergy 819124800 # Energy for read commands per rank (pJ) 318system.physmem_0.writeEnergy 465775920 # Energy for write commands per rank (pJ) 319system.physmem_0.refreshEnergy 186081086880 # Energy for refresh commands per rank (pJ) 320system.physmem_0.actBackEnergy 85063480605 # Energy for active background per rank (pJ) 321system.physmem_0.preBackEnergy 1634767041000 # Energy for precharge background per rank (pJ) 322system.physmem_0.totalEnergy 1907765218155 # Total energy per rank (pJ) 323system.physmem_0.averagePower 669.632478 # Core power per rank (mW) 324system.physmem_0.memoryStateTime::IDLE 2719452348147 # Time in different power states 325system.physmem_0.memoryStateTime::REF 95133480000 # Time in different power states 326system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 327system.physmem_0.memoryStateTime::ACT 34391644853 # Time in different power states 328system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 329system.physmem_1.actEnergy 328497120 # Energy for activate commands per rank (pJ) 330system.physmem_1.preEnergy 179239500 # Energy for precharge commands per rank (pJ) 331system.physmem_1.readEnergy 740688000 # Energy for read commands per rank (pJ) 332system.physmem_1.writeEnergy 433239840 # Energy for write commands per rank (pJ) 333system.physmem_1.refreshEnergy 186081086880 # Energy for refresh commands per rank (pJ) 334system.physmem_1.actBackEnergy 83753939520 # Energy for active background per rank (pJ) 335system.physmem_1.preBackEnergy 1635915761250 # Energy for precharge background per rank (pJ) 336system.physmem_1.totalEnergy 1907432452110 # Total energy per rank (pJ) 337system.physmem_1.averagePower 669.515676 # Core power per rank (mW) 338system.physmem_1.memoryStateTime::IDLE 2721369982715 # Time in different power states 339system.physmem_1.memoryStateTime::REF 95133480000 # Time in different power states 340system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 341system.physmem_1.memoryStateTime::ACT 32475502785 # Time in different power states 342system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 343system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 349system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 350system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 352system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 361system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 362system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 363system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 364system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 365system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 366system.cf0.dma_write_txs 631 # Number of DMA write transactions. 367system.cpu0.branchPred.lookups 36411615 # Number of BP lookups 368system.cpu0.branchPred.condPredicted 17748077 # Number of conditional branches predicted 369system.cpu0.branchPred.condIncorrect 1698439 # Number of conditional branches incorrect 370system.cpu0.branchPred.BTBLookups 20740706 # Number of BTB lookups 371system.cpu0.branchPred.BTBHits 15063288 # Number of BTB hits 372system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 373system.cpu0.branchPred.BTBHitPct 72.626689 # BTB Hit Percentage 374system.cpu0.branchPred.usedRAS 11337600 # Number of times the RAS was used to get a target. 375system.cpu0.branchPred.RASInCorrect 822333 # Number of incorrect RAS predictions. 376system.cpu_clk_domain.clock 500 # Clock period in ticks 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 386system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 387system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 388system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 389system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 390system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 391system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 393system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 395system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 396system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 397system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 398system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 401system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 402system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 403system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 404system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 405system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 406system.cpu0.dtb.walker.walks 73296 # Table walker walks requested 407system.cpu0.dtb.walker.walksShort 73296 # Table walker walks initiated with short descriptors 408system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47393 # Level at which table walker walks with short descriptors terminate 409system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25903 # Level at which table walker walks with short descriptors terminate 410system.cpu0.dtb.walker.walkWaitTime::samples 73296 # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::0 73296 100.00% 100.00% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::total 73296 # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkCompletionTime::samples 7538 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::mean 12243.300610 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::gmean 11373.544979 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::stdev 7165.218707 # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::0-32767 7499 99.48% 99.48% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::32768-65535 33 0.44% 99.92% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.97% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::total 7538 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution 424system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution 425system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution 426system.cpu0.dtb.walker.walkPageSizes::4K 5846 77.55% 77.55% # Table walker page sizes translated 427system.cpu0.dtb.walker.walkPageSizes::1M 1692 22.45% 100.00% # Table walker page sizes translated 428system.cpu0.dtb.walker.walkPageSizes::total 7538 # Table walker page sizes translated 429system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73296 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73296 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7538 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 434system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7538 # Table walker requests started/completed, data/inst 435system.cpu0.dtb.walker.walkRequestOrigin::total 80834 # Table walker requests started/completed, data/inst 436system.cpu0.dtb.inst_hits 0 # ITB inst hits 437system.cpu0.dtb.inst_misses 0 # ITB inst misses 438system.cpu0.dtb.read_hits 24914388 # DTB read hits 439system.cpu0.dtb.read_misses 66763 # DTB read misses 440system.cpu0.dtb.write_hits 18539888 # DTB write hits 441system.cpu0.dtb.write_misses 6533 # DTB write misses 442system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 443system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 444system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 445system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 446system.cpu0.dtb.flush_entries 3822 # Number of entries that have been flushed from TLB 447system.cpu0.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions 448system.cpu0.dtb.prefetch_faults 2016 # Number of TLB faults due to prefetch 449system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 450system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions 451system.cpu0.dtb.read_accesses 24981151 # DTB read accesses 452system.cpu0.dtb.write_accesses 18546421 # DTB write accesses 453system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 454system.cpu0.dtb.hits 43454276 # DTB hits 455system.cpu0.dtb.misses 73296 # DTB misses 456system.cpu0.dtb.accesses 43527572 # DTB accesses 457system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 466system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 467system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 468system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 469system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 470system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 471system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 472system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 473system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 474system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 475system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 476system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 477system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 478system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 479system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 480system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 481system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 482system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 483system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 484system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 485system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 486system.cpu0.itb.walker.walks 4166 # Table walker walks requested 487system.cpu0.itb.walker.walksShort 4166 # Table walker walks initiated with short descriptors 488system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate 489system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3842 # Level at which table walker walks with short descriptors terminate 490system.cpu0.itb.walker.walkWaitTime::samples 4166 # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::0 4166 100.00% 100.00% # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkWaitTime::total 4166 # Table walker wait (enqueue to first request) latency 493system.cpu0.itb.walker.walkCompletionTime::samples 2675 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::mean 12725.794393 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::gmean 12032.430474 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::stdev 5005.050560 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::0-16383 2427 90.73% 90.73% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::16384-32767 233 8.71% 99.44% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::32768-49151 14 0.52% 99.96% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::total 2675 # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution 503system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution 504system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution 505system.cpu0.itb.walker.walkPageSizes::4K 2356 88.07% 88.07% # Table walker page sizes translated 506system.cpu0.itb.walker.walkPageSizes::1M 319 11.93% 100.00% # Table walker page sizes translated 507system.cpu0.itb.walker.walkPageSizes::total 2675 # Table walker page sizes translated 508system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4166 # Table walker requests started/completed, data/inst 510system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4166 # Table walker requests started/completed, data/inst 511system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2675 # Table walker requests started/completed, data/inst 513system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2675 # Table walker requests started/completed, data/inst 514system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst 515system.cpu0.itb.inst_hits 71495102 # ITB inst hits 516system.cpu0.itb.inst_misses 4166 # ITB inst misses 517system.cpu0.itb.read_hits 0 # DTB read hits 518system.cpu0.itb.read_misses 0 # DTB read misses 519system.cpu0.itb.write_hits 0 # DTB write hits 520system.cpu0.itb.write_misses 0 # DTB write misses 521system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 522system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 523system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 524system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 525system.cpu0.itb.flush_entries 2450 # Number of entries that have been flushed from TLB 526system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 527system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 528system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 529system.cpu0.itb.perms_faults 8197 # Number of TLB faults due to permissions restrictions 530system.cpu0.itb.read_accesses 0 # DTB read accesses 531system.cpu0.itb.write_accesses 0 # DTB write accesses 532system.cpu0.itb.inst_accesses 71499268 # ITB inst accesses 533system.cpu0.itb.hits 71495102 # DTB hits 534system.cpu0.itb.misses 4166 # DTB misses 535system.cpu0.itb.accesses 71499268 # DTB accesses 536system.cpu0.numCycles 248928104 # number of cpu cycles simulated 537system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 538system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 539system.cpu0.committedInsts 113059938 # Number of instructions committed 540system.cpu0.committedOps 136701894 # Number of ops (including micro ops) committed 541system.cpu0.discardedOps 8937139 # Number of ops (including micro ops) which were discarded before commit 542system.cpu0.numFetchSuspends 1889 # Number of times Execute suspended instruction fetching 543system.cpu0.quiesceCycles 5449058014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 544system.cpu0.cpi 2.201736 # CPI: cycles per instruction 545system.cpu0.ipc 0.454187 # IPC: instructions per cycle 546system.cpu0.kern.inst.arm 0 # number of arm instructions executed 547system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed 548system.cpu0.tickCycles 199965513 # Number of cycles that the object actually ticked 549system.cpu0.idleCycles 48962591 # Total number of cycles that the object has spent stopped 550system.cpu0.dcache.tags.replacements 758556 # number of replacements 551system.cpu0.dcache.tags.tagsinuse 498.399366 # Cycle average of tags in use 552system.cpu0.dcache.tags.total_refs 41853464 # Total number of references to valid blocks. 553system.cpu0.dcache.tags.sampled_refs 759068 # Sample count of references to valid blocks. 554system.cpu0.dcache.tags.avg_refs 55.137964 # Average number of references to valid blocks. 555system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. 556system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.399366 # Average occupied blocks per requestor 557system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973436 # Average percentage of cache occupancy 558system.cpu0.dcache.tags.occ_percent::total 0.973436 # Average percentage of cache occupancy 559system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 560system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 561system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 562system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 563system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 564system.cpu0.dcache.tags.tag_accesses 86857605 # Number of tag accesses 565system.cpu0.dcache.tags.data_accesses 86857605 # Number of data accesses 566system.cpu0.dcache.ReadReq_hits::cpu0.data 23301250 # number of ReadReq hits 567system.cpu0.dcache.ReadReq_hits::total 23301250 # number of ReadReq hits 568system.cpu0.dcache.WriteReq_hits::cpu0.data 17363998 # number of WriteReq hits 569system.cpu0.dcache.WriteReq_hits::total 17363998 # number of WriteReq hits 570system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329371 # number of SoftPFReq hits 571system.cpu0.dcache.SoftPFReq_hits::total 329371 # number of SoftPFReq hits 572system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374920 # number of LoadLockedReq hits 573system.cpu0.dcache.LoadLockedReq_hits::total 374920 # number of LoadLockedReq hits 574system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370784 # number of StoreCondReq hits 575system.cpu0.dcache.StoreCondReq_hits::total 370784 # number of StoreCondReq hits 576system.cpu0.dcache.demand_hits::cpu0.data 40665248 # number of demand (read+write) hits 577system.cpu0.dcache.demand_hits::total 40665248 # number of demand (read+write) hits 578system.cpu0.dcache.overall_hits::cpu0.data 40994619 # number of overall hits 579system.cpu0.dcache.overall_hits::total 40994619 # number of overall hits 580system.cpu0.dcache.ReadReq_misses::cpu0.data 492930 # number of ReadReq misses 581system.cpu0.dcache.ReadReq_misses::total 492930 # number of ReadReq misses 582system.cpu0.dcache.WriteReq_misses::cpu0.data 604783 # number of WriteReq misses 583system.cpu0.dcache.WriteReq_misses::total 604783 # number of WriteReq misses 584system.cpu0.dcache.SoftPFReq_misses::cpu0.data 142057 # number of SoftPFReq misses 585system.cpu0.dcache.SoftPFReq_misses::total 142057 # number of SoftPFReq misses 586system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21393 # number of LoadLockedReq misses 587system.cpu0.dcache.LoadLockedReq_misses::total 21393 # number of LoadLockedReq misses 588system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20582 # number of StoreCondReq misses 589system.cpu0.dcache.StoreCondReq_misses::total 20582 # number of StoreCondReq misses 590system.cpu0.dcache.demand_misses::cpu0.data 1097713 # number of demand (read+write) misses 591system.cpu0.dcache.demand_misses::total 1097713 # number of demand (read+write) misses 592system.cpu0.dcache.overall_misses::cpu0.data 1239770 # number of overall misses 593system.cpu0.dcache.overall_misses::total 1239770 # number of overall misses 594system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6978123000 # number of ReadReq miss cycles 595system.cpu0.dcache.ReadReq_miss_latency::total 6978123000 # number of ReadReq miss cycles 596system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12569253000 # number of WriteReq miss cycles 597system.cpu0.dcache.WriteReq_miss_latency::total 12569253000 # number of WriteReq miss cycles 598system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330022000 # number of LoadLockedReq miss cycles 599system.cpu0.dcache.LoadLockedReq_miss_latency::total 330022000 # number of LoadLockedReq miss cycles 600system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 544680500 # number of StoreCondReq miss cycles 601system.cpu0.dcache.StoreCondReq_miss_latency::total 544680500 # number of StoreCondReq miss cycles 602system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles 603system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles 604system.cpu0.dcache.demand_miss_latency::cpu0.data 19547376000 # number of demand (read+write) miss cycles 605system.cpu0.dcache.demand_miss_latency::total 19547376000 # number of demand (read+write) miss cycles 606system.cpu0.dcache.overall_miss_latency::cpu0.data 19547376000 # number of overall miss cycles 607system.cpu0.dcache.overall_miss_latency::total 19547376000 # number of overall miss cycles 608system.cpu0.dcache.ReadReq_accesses::cpu0.data 23794180 # number of ReadReq accesses(hits+misses) 609system.cpu0.dcache.ReadReq_accesses::total 23794180 # number of ReadReq accesses(hits+misses) 610system.cpu0.dcache.WriteReq_accesses::cpu0.data 17968781 # number of WriteReq accesses(hits+misses) 611system.cpu0.dcache.WriteReq_accesses::total 17968781 # number of WriteReq accesses(hits+misses) 612system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471428 # number of SoftPFReq accesses(hits+misses) 613system.cpu0.dcache.SoftPFReq_accesses::total 471428 # number of SoftPFReq accesses(hits+misses) 614system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396313 # number of LoadLockedReq accesses(hits+misses) 615system.cpu0.dcache.LoadLockedReq_accesses::total 396313 # number of LoadLockedReq accesses(hits+misses) 616system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391366 # number of StoreCondReq accesses(hits+misses) 617system.cpu0.dcache.StoreCondReq_accesses::total 391366 # number of StoreCondReq accesses(hits+misses) 618system.cpu0.dcache.demand_accesses::cpu0.data 41762961 # number of demand (read+write) accesses 619system.cpu0.dcache.demand_accesses::total 41762961 # number of demand (read+write) accesses 620system.cpu0.dcache.overall_accesses::cpu0.data 42234389 # number of overall (read+write) accesses 621system.cpu0.dcache.overall_accesses::total 42234389 # number of overall (read+write) accesses 622system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020716 # miss rate for ReadReq accesses 623system.cpu0.dcache.ReadReq_miss_rate::total 0.020716 # miss rate for ReadReq accesses 624system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033657 # miss rate for WriteReq accesses 625system.cpu0.dcache.WriteReq_miss_rate::total 0.033657 # miss rate for WriteReq accesses 626system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301333 # miss rate for SoftPFReq accesses 627system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301333 # miss rate for SoftPFReq accesses 628system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053980 # miss rate for LoadLockedReq accesses 629system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053980 # miss rate for LoadLockedReq accesses 630system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052590 # miss rate for StoreCondReq accesses 631system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052590 # miss rate for StoreCondReq accesses 632system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026284 # miss rate for demand accesses 633system.cpu0.dcache.demand_miss_rate::total 0.026284 # miss rate for demand accesses 634system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029355 # miss rate for overall accesses 635system.cpu0.dcache.overall_miss_rate::total 0.029355 # miss rate for overall accesses 636system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14156.417747 # average ReadReq miss latency 637system.cpu0.dcache.ReadReq_avg_miss_latency::total 14156.417747 # average ReadReq miss latency 638system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20783.079220 # average WriteReq miss latency 639system.cpu0.dcache.WriteReq_avg_miss_latency::total 20783.079220 # average WriteReq miss latency 640system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15426.634881 # average LoadLockedReq miss latency 641system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15426.634881 # average LoadLockedReq miss latency 642system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26463.924789 # average StoreCondReq miss latency 643system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26463.924789 # average StoreCondReq miss latency 644system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 645system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 646system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17807.364949 # average overall miss latency 647system.cpu0.dcache.demand_avg_miss_latency::total 17807.364949 # average overall miss latency 648system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.937416 # average overall miss latency 649system.cpu0.dcache.overall_avg_miss_latency::total 15766.937416 # average overall miss latency 650system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu0.dcache.fast_writes 0 # number of fast writes performed 657system.cpu0.dcache.cache_copies 0 # number of cache copies performed 658system.cpu0.dcache.writebacks::writebacks 758556 # number of writebacks 659system.cpu0.dcache.writebacks::total 758556 # number of writebacks 660system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75954 # number of ReadReq MSHR hits 661system.cpu0.dcache.ReadReq_mshr_hits::total 75954 # number of ReadReq MSHR hits 662system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266286 # number of WriteReq MSHR hits 663system.cpu0.dcache.WriteReq_mshr_hits::total 266286 # number of WriteReq MSHR hits 664system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14845 # number of LoadLockedReq MSHR hits 665system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14845 # number of LoadLockedReq MSHR hits 666system.cpu0.dcache.demand_mshr_hits::cpu0.data 342240 # number of demand (read+write) MSHR hits 667system.cpu0.dcache.demand_mshr_hits::total 342240 # number of demand (read+write) MSHR hits 668system.cpu0.dcache.overall_mshr_hits::cpu0.data 342240 # number of overall MSHR hits 669system.cpu0.dcache.overall_mshr_hits::total 342240 # number of overall MSHR hits 670system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416976 # number of ReadReq MSHR misses 671system.cpu0.dcache.ReadReq_mshr_misses::total 416976 # number of ReadReq MSHR misses 672system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 338497 # number of WriteReq MSHR misses 673system.cpu0.dcache.WriteReq_mshr_misses::total 338497 # number of WriteReq MSHR misses 674system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108439 # number of SoftPFReq MSHR misses 675system.cpu0.dcache.SoftPFReq_mshr_misses::total 108439 # number of SoftPFReq MSHR misses 676system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6548 # number of LoadLockedReq MSHR misses 677system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6548 # number of LoadLockedReq MSHR misses 678system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20582 # number of StoreCondReq MSHR misses 679system.cpu0.dcache.StoreCondReq_mshr_misses::total 20582 # number of StoreCondReq MSHR misses 680system.cpu0.dcache.demand_mshr_misses::cpu0.data 755473 # number of demand (read+write) MSHR misses 681system.cpu0.dcache.demand_mshr_misses::total 755473 # number of demand (read+write) MSHR misses 682system.cpu0.dcache.overall_mshr_misses::cpu0.data 863912 # number of overall MSHR misses 683system.cpu0.dcache.overall_mshr_misses::total 863912 # number of overall MSHR misses 684system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32047 # number of ReadReq MSHR uncacheable 685system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32047 # number of ReadReq MSHR uncacheable 686system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable 687system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable 688system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60771 # number of overall MSHR uncacheable misses 689system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60771 # number of overall MSHR uncacheable misses 690system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5288189500 # number of ReadReq MSHR miss cycles 691system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5288189500 # number of ReadReq MSHR miss cycles 692system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7115551000 # number of WriteReq MSHR miss cycles 693system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7115551000 # number of WriteReq MSHR miss cycles 694system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1805226500 # number of SoftPFReq MSHR miss cycles 695system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1805226500 # number of SoftPFReq MSHR miss cycles 696system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104756500 # number of LoadLockedReq MSHR miss cycles 697system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104756500 # number of LoadLockedReq MSHR miss cycles 698system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 524110500 # number of StoreCondReq MSHR miss cycles 699system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 524110500 # number of StoreCondReq MSHR miss cycles 700system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 625500 # number of StoreCondFailReq MSHR miss cycles 701system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles 702system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403740500 # number of demand (read+write) MSHR miss cycles 703system.cpu0.dcache.demand_mshr_miss_latency::total 12403740500 # number of demand (read+write) MSHR miss cycles 704system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14208967000 # number of overall MSHR miss cycles 705system.cpu0.dcache.overall_mshr_miss_latency::total 14208967000 # number of overall MSHR miss cycles 706system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702515500 # number of ReadReq MSHR uncacheable cycles 707system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702515500 # number of ReadReq MSHR uncacheable cycles 708system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452693000 # number of WriteReq MSHR uncacheable cycles 709system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452693000 # number of WriteReq MSHR uncacheable cycles 710system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12155208500 # number of overall MSHR uncacheable cycles 711system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12155208500 # number of overall MSHR uncacheable cycles 712system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017524 # mshr miss rate for ReadReq accesses 713system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017524 # mshr miss rate for ReadReq accesses 714system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018838 # mshr miss rate for WriteReq accesses 715system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018838 # mshr miss rate for WriteReq accesses 716system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230022 # mshr miss rate for SoftPFReq accesses 717system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230022 # mshr miss rate for SoftPFReq accesses 718system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016522 # mshr miss rate for LoadLockedReq accesses 719system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016522 # mshr miss rate for LoadLockedReq accesses 720system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052590 # mshr miss rate for StoreCondReq accesses 721system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052590 # mshr miss rate for StoreCondReq accesses 722system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018090 # mshr miss rate for demand accesses 723system.cpu0.dcache.demand_mshr_miss_rate::total 0.018090 # mshr miss rate for demand accesses 724system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020455 # mshr miss rate for overall accesses 725system.cpu0.dcache.overall_mshr_miss_rate::total 0.020455 # mshr miss rate for overall accesses 726system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12682.239505 # average ReadReq mshr miss latency 727system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12682.239505 # average ReadReq mshr miss latency 728system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21021.016434 # average WriteReq mshr miss latency 729system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21021.016434 # average WriteReq mshr miss latency 730system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16647.391621 # average SoftPFReq mshr miss latency 731system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16647.391621 # average SoftPFReq mshr miss latency 732system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15998.243739 # average LoadLockedReq mshr miss latency 733system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15998.243739 # average LoadLockedReq mshr miss latency 734system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25464.507822 # average StoreCondReq mshr miss latency 735system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25464.507822 # average StoreCondReq mshr miss latency 736system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 737system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 738system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16418.509331 # average overall mshr miss latency 739system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16418.509331 # average overall mshr miss latency 740system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16447.238839 # average overall mshr miss latency 741system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16447.238839 # average overall mshr miss latency 742system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209146.425562 # average ReadReq mshr uncacheable latency 743system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209146.425562 # average ReadReq mshr uncacheable latency 744system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189830.559811 # average WriteReq mshr uncacheable latency 745system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189830.559811 # average WriteReq mshr uncacheable latency 746system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200016.595086 # average overall mshr uncacheable latency 747system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200016.595086 # average overall mshr uncacheable latency 748system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 749system.cpu0.icache.tags.replacements 2041160 # number of replacements 750system.cpu0.icache.tags.tagsinuse 511.728196 # Cycle average of tags in use 751system.cpu0.icache.tags.total_refs 69444830 # Total number of references to valid blocks. 752system.cpu0.icache.tags.sampled_refs 2041672 # Sample count of references to valid blocks. 753system.cpu0.icache.tags.avg_refs 34.013705 # Average number of references to valid blocks. 754system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit. 755system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728196 # Average occupied blocks per requestor 756system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999469 # Average percentage of cache occupancy 757system.cpu0.icache.tags.occ_percent::total 0.999469 # Average percentage of cache occupancy 758system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 759system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 760system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id 761system.cpu0.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 762system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 763system.cpu0.icache.tags.tag_accesses 145014717 # Number of tag accesses 764system.cpu0.icache.tags.data_accesses 145014717 # Number of data accesses 765system.cpu0.icache.ReadReq_hits::cpu0.inst 69444830 # number of ReadReq hits 766system.cpu0.icache.ReadReq_hits::total 69444830 # number of ReadReq hits 767system.cpu0.icache.demand_hits::cpu0.inst 69444830 # number of demand (read+write) hits 768system.cpu0.icache.demand_hits::total 69444830 # number of demand (read+write) hits 769system.cpu0.icache.overall_hits::cpu0.inst 69444830 # number of overall hits 770system.cpu0.icache.overall_hits::total 69444830 # number of overall hits 771system.cpu0.icache.ReadReq_misses::cpu0.inst 2041686 # number of ReadReq misses 772system.cpu0.icache.ReadReq_misses::total 2041686 # number of ReadReq misses 773system.cpu0.icache.demand_misses::cpu0.inst 2041686 # number of demand (read+write) misses 774system.cpu0.icache.demand_misses::total 2041686 # number of demand (read+write) misses 775system.cpu0.icache.overall_misses::cpu0.inst 2041686 # number of overall misses 776system.cpu0.icache.overall_misses::total 2041686 # number of overall misses 777system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20560339500 # number of ReadReq miss cycles 778system.cpu0.icache.ReadReq_miss_latency::total 20560339500 # number of ReadReq miss cycles 779system.cpu0.icache.demand_miss_latency::cpu0.inst 20560339500 # number of demand (read+write) miss cycles 780system.cpu0.icache.demand_miss_latency::total 20560339500 # number of demand (read+write) miss cycles 781system.cpu0.icache.overall_miss_latency::cpu0.inst 20560339500 # number of overall miss cycles 782system.cpu0.icache.overall_miss_latency::total 20560339500 # number of overall miss cycles 783system.cpu0.icache.ReadReq_accesses::cpu0.inst 71486516 # number of ReadReq accesses(hits+misses) 784system.cpu0.icache.ReadReq_accesses::total 71486516 # number of ReadReq accesses(hits+misses) 785system.cpu0.icache.demand_accesses::cpu0.inst 71486516 # number of demand (read+write) accesses 786system.cpu0.icache.demand_accesses::total 71486516 # number of demand (read+write) accesses 787system.cpu0.icache.overall_accesses::cpu0.inst 71486516 # number of overall (read+write) accesses 788system.cpu0.icache.overall_accesses::total 71486516 # number of overall (read+write) accesses 789system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028560 # miss rate for ReadReq accesses 790system.cpu0.icache.ReadReq_miss_rate::total 0.028560 # miss rate for ReadReq accesses 791system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028560 # miss rate for demand accesses 792system.cpu0.icache.demand_miss_rate::total 0.028560 # miss rate for demand accesses 793system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028560 # miss rate for overall accesses 794system.cpu0.icache.overall_miss_rate::total 0.028560 # miss rate for overall accesses 795system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10070.275008 # average ReadReq miss latency 796system.cpu0.icache.ReadReq_avg_miss_latency::total 10070.275008 # average ReadReq miss latency 797system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10070.275008 # average overall miss latency 798system.cpu0.icache.demand_avg_miss_latency::total 10070.275008 # average overall miss latency 799system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10070.275008 # average overall miss latency 800system.cpu0.icache.overall_avg_miss_latency::total 10070.275008 # average overall miss latency 801system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu0.icache.fast_writes 0 # number of fast writes performed 808system.cpu0.icache.cache_copies 0 # number of cache copies performed 809system.cpu0.icache.writebacks::writebacks 2041160 # number of writebacks 810system.cpu0.icache.writebacks::total 2041160 # number of writebacks 811system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2041686 # number of ReadReq MSHR misses 812system.cpu0.icache.ReadReq_mshr_misses::total 2041686 # number of ReadReq MSHR misses 813system.cpu0.icache.demand_mshr_misses::cpu0.inst 2041686 # number of demand (read+write) MSHR misses 814system.cpu0.icache.demand_mshr_misses::total 2041686 # number of demand (read+write) MSHR misses 815system.cpu0.icache.overall_mshr_misses::cpu0.inst 2041686 # number of overall MSHR misses 816system.cpu0.icache.overall_mshr_misses::total 2041686 # number of overall MSHR misses 817system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 818system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable 819system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 820system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses 821system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19539497000 # number of ReadReq MSHR miss cycles 822system.cpu0.icache.ReadReq_mshr_miss_latency::total 19539497000 # number of ReadReq MSHR miss cycles 823system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19539497000 # number of demand (read+write) MSHR miss cycles 824system.cpu0.icache.demand_mshr_miss_latency::total 19539497000 # number of demand (read+write) MSHR miss cycles 825system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19539497000 # number of overall MSHR miss cycles 826system.cpu0.icache.overall_mshr_miss_latency::total 19539497000 # number of overall MSHR miss cycles 827system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles 828system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles 830system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles 831system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for ReadReq accesses 832system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028560 # mshr miss rate for ReadReq accesses 833system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for demand accesses 834system.cpu0.icache.demand_mshr_miss_rate::total 0.028560 # mshr miss rate for demand accesses 835system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for overall accesses 836system.cpu0.icache.overall_mshr_miss_rate::total 0.028560 # mshr miss rate for overall accesses 837system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average ReadReq mshr miss latency 838system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9570.275253 # average ReadReq mshr miss latency 839system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average overall mshr miss latency 840system.cpu0.icache.demand_avg_mshr_miss_latency::total 9570.275253 # average overall mshr miss latency 841system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average overall mshr miss latency 842system.cpu0.icache.overall_avg_mshr_miss_latency::total 9570.275253 # average overall mshr miss latency 843system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency 844system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency 845system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency 846system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency 847system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 848system.cpu0.l2cache.prefetcher.num_hwpf_issued 1926179 # number of hwpf issued 849system.cpu0.l2cache.prefetcher.pfIdentified 1926371 # number of prefetch candidates identified 850system.cpu0.l2cache.prefetcher.pfBufferHit 166 # number of redundant prefetches already in prefetch queue 851system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 852system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 853system.cpu0.l2cache.prefetcher.pfSpanPage 244645 # number of prefetches not generated due to page crossing 854system.cpu0.l2cache.tags.replacements 305884 # number of replacements 855system.cpu0.l2cache.tags.tagsinuse 16117.392846 # Cycle average of tags in use 856system.cpu0.l2cache.tags.total_refs 4898605 # Total number of references to valid blocks. 857system.cpu0.l2cache.tags.sampled_refs 322066 # Sample count of references to valid blocks. 858system.cpu0.l2cache.tags.avg_refs 15.209941 # Average number of references to valid blocks. 859system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 860system.cpu0.l2cache.tags.occ_blocks::writebacks 14778.459491 # Average occupied blocks per requestor 861system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.434424 # Average occupied blocks per requestor 862system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065090 # Average occupied blocks per requestor 863system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1278.433841 # Average occupied blocks per requestor 864system.cpu0.l2cache.tags.occ_percent::writebacks 0.902006 # Average percentage of cache occupancy 865system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003689 # Average percentage of cache occupancy 866system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 867system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.078029 # Average percentage of cache occupancy 868system.cpu0.l2cache.tags.occ_percent::total 0.983728 # Average percentage of cache occupancy 869system.cpu0.l2cache.tags.occ_task_id_blocks::1022 978 # Occupied blocks per task id 870system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 871system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15192 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 874system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 328 # Occupied blocks per task id 875system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 213 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 881system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 882system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 403 # Occupied blocks per task id 883system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4034 # Occupied blocks per task id 884system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8338 # Occupied blocks per task id 885system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id 886system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059692 # Percentage of cache occupancy per task id 887system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 888system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927246 # Percentage of cache occupancy per task id 889system.cpu0.l2cache.tags.tag_accesses 93368748 # Number of tag accesses 890system.cpu0.l2cache.tags.data_accesses 93368748 # Number of data accesses 891system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 90396 # number of ReadReq hits 892system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5742 # number of ReadReq hits 893system.cpu0.l2cache.ReadReq_hits::total 96138 # number of ReadReq hits 894system.cpu0.l2cache.WritebackDirty_hits::writebacks 507659 # number of WritebackDirty hits 895system.cpu0.l2cache.WritebackDirty_hits::total 507659 # number of WritebackDirty hits 896system.cpu0.l2cache.WritebackClean_hits::writebacks 2247535 # number of WritebackClean hits 897system.cpu0.l2cache.WritebackClean_hits::total 2247535 # number of WritebackClean hits 898system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233006 # number of ReadExReq hits 899system.cpu0.l2cache.ReadExReq_hits::total 233006 # number of ReadExReq hits 900system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1971438 # number of ReadCleanReq hits 901system.cpu0.l2cache.ReadCleanReq_hits::total 1971438 # number of ReadCleanReq hits 902system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 430811 # number of ReadSharedReq hits 903system.cpu0.l2cache.ReadSharedReq_hits::total 430811 # number of ReadSharedReq hits 904system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 90396 # number of demand (read+write) hits 905system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5742 # number of demand (read+write) hits 906system.cpu0.l2cache.demand_hits::cpu0.inst 1971438 # number of demand (read+write) hits 907system.cpu0.l2cache.demand_hits::cpu0.data 663817 # number of demand (read+write) hits 908system.cpu0.l2cache.demand_hits::total 2731393 # number of demand (read+write) hits 909system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 90396 # number of overall hits 910system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5742 # number of overall hits 911system.cpu0.l2cache.overall_hits::cpu0.inst 1971438 # number of overall hits 912system.cpu0.l2cache.overall_hits::cpu0.data 663817 # number of overall hits 913system.cpu0.l2cache.overall_hits::total 2731393 # number of overall hits 914system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 708 # number of ReadReq misses 915system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 94 # number of ReadReq misses 916system.cpu0.l2cache.ReadReq_misses::total 802 # number of ReadReq misses 917system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57006 # number of UpgradeReq misses 918system.cpu0.l2cache.UpgradeReq_misses::total 57006 # number of UpgradeReq misses 919system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20580 # number of SCUpgradeReq misses 920system.cpu0.l2cache.SCUpgradeReq_misses::total 20580 # number of SCUpgradeReq misses 921system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 922system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 923system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48494 # number of ReadExReq misses 924system.cpu0.l2cache.ReadExReq_misses::total 48494 # number of ReadExReq misses 925system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70248 # number of ReadCleanReq misses 926system.cpu0.l2cache.ReadCleanReq_misses::total 70248 # number of ReadCleanReq misses 927system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101145 # number of ReadSharedReq misses 928system.cpu0.l2cache.ReadSharedReq_misses::total 101145 # number of ReadSharedReq misses 929system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 708 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::cpu0.itb.walker 94 # number of demand (read+write) misses 931system.cpu0.l2cache.demand_misses::cpu0.inst 70248 # number of demand (read+write) misses 932system.cpu0.l2cache.demand_misses::cpu0.data 149639 # number of demand (read+write) misses 933system.cpu0.l2cache.demand_misses::total 220689 # number of demand (read+write) misses 934system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 708 # number of overall misses 935system.cpu0.l2cache.overall_misses::cpu0.itb.walker 94 # number of overall misses 936system.cpu0.l2cache.overall_misses::cpu0.inst 70248 # number of overall misses 937system.cpu0.l2cache.overall_misses::cpu0.data 149639 # number of overall misses 938system.cpu0.l2cache.overall_misses::total 220689 # number of overall misses 939system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 33565000 # number of ReadReq miss cycles 940system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2328500 # number of ReadReq miss cycles 941system.cpu0.l2cache.ReadReq_miss_latency::total 35893500 # number of ReadReq miss cycles 942system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 209633000 # number of UpgradeReq miss cycles 943system.cpu0.l2cache.UpgradeReq_miss_latency::total 209633000 # number of UpgradeReq miss cycles 944system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 49175500 # number of SCUpgradeReq miss cycles 945system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 49175500 # number of SCUpgradeReq miss cycles 946system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 605000 # number of SCUpgradeFailReq miss cycles 947system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 605000 # number of SCUpgradeFailReq miss cycles 948system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3197349498 # number of ReadExReq miss cycles 949system.cpu0.l2cache.ReadExReq_miss_latency::total 3197349498 # number of ReadExReq miss cycles 950system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4517158000 # number of ReadCleanReq miss cycles 951system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4517158000 # number of ReadCleanReq miss cycles 952system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3550453498 # number of ReadSharedReq miss cycles 953system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3550453498 # number of ReadSharedReq miss cycles 954system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 33565000 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2328500 # number of demand (read+write) miss cycles 956system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4517158000 # number of demand (read+write) miss cycles 957system.cpu0.l2cache.demand_miss_latency::cpu0.data 6747802996 # number of demand (read+write) miss cycles 958system.cpu0.l2cache.demand_miss_latency::total 11300854496 # number of demand (read+write) miss cycles 959system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 33565000 # number of overall miss cycles 960system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2328500 # number of overall miss cycles 961system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4517158000 # number of overall miss cycles 962system.cpu0.l2cache.overall_miss_latency::cpu0.data 6747802996 # number of overall miss cycles 963system.cpu0.l2cache.overall_miss_latency::total 11300854496 # number of overall miss cycles 964system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 91104 # number of ReadReq accesses(hits+misses) 965system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5836 # number of ReadReq accesses(hits+misses) 966system.cpu0.l2cache.ReadReq_accesses::total 96940 # number of ReadReq accesses(hits+misses) 967system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507659 # number of WritebackDirty accesses(hits+misses) 968system.cpu0.l2cache.WritebackDirty_accesses::total 507659 # number of WritebackDirty accesses(hits+misses) 969system.cpu0.l2cache.WritebackClean_accesses::writebacks 2247535 # number of WritebackClean accesses(hits+misses) 970system.cpu0.l2cache.WritebackClean_accesses::total 2247535 # number of WritebackClean accesses(hits+misses) 971system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 57006 # number of UpgradeReq accesses(hits+misses) 972system.cpu0.l2cache.UpgradeReq_accesses::total 57006 # number of UpgradeReq accesses(hits+misses) 973system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20580 # number of SCUpgradeReq accesses(hits+misses) 974system.cpu0.l2cache.SCUpgradeReq_accesses::total 20580 # number of SCUpgradeReq accesses(hits+misses) 975system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 976system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 977system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 281500 # number of ReadExReq accesses(hits+misses) 978system.cpu0.l2cache.ReadExReq_accesses::total 281500 # number of ReadExReq accesses(hits+misses) 979system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2041686 # number of ReadCleanReq accesses(hits+misses) 980system.cpu0.l2cache.ReadCleanReq_accesses::total 2041686 # number of ReadCleanReq accesses(hits+misses) 981system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 531956 # number of ReadSharedReq accesses(hits+misses) 982system.cpu0.l2cache.ReadSharedReq_accesses::total 531956 # number of ReadSharedReq accesses(hits+misses) 983system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 91104 # number of demand (read+write) accesses 984system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5836 # number of demand (read+write) accesses 985system.cpu0.l2cache.demand_accesses::cpu0.inst 2041686 # number of demand (read+write) accesses 986system.cpu0.l2cache.demand_accesses::cpu0.data 813456 # number of demand (read+write) accesses 987system.cpu0.l2cache.demand_accesses::total 2952082 # number of demand (read+write) accesses 988system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 91104 # number of overall (read+write) accesses 989system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5836 # number of overall (read+write) accesses 990system.cpu0.l2cache.overall_accesses::cpu0.inst 2041686 # number of overall (read+write) accesses 991system.cpu0.l2cache.overall_accesses::cpu0.data 813456 # number of overall (read+write) accesses 992system.cpu0.l2cache.overall_accesses::total 2952082 # number of overall (read+write) accesses 993system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007771 # miss rate for ReadReq accesses 994system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016107 # miss rate for ReadReq accesses 995system.cpu0.l2cache.ReadReq_miss_rate::total 0.008273 # miss rate for ReadReq accesses 996system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 997system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 998system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 999system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1000system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1001system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1002system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.172270 # miss rate for ReadExReq accesses 1003system.cpu0.l2cache.ReadExReq_miss_rate::total 0.172270 # miss rate for ReadExReq accesses 1004system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034407 # miss rate for ReadCleanReq accesses 1005system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034407 # miss rate for ReadCleanReq accesses 1006system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.190138 # miss rate for ReadSharedReq accesses 1007system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.190138 # miss rate for ReadSharedReq accesses 1008system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007771 # miss rate for demand accesses 1009system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016107 # miss rate for demand accesses 1010system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034407 # miss rate for demand accesses 1011system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183955 # miss rate for demand accesses 1012system.cpu0.l2cache.demand_miss_rate::total 0.074757 # miss rate for demand accesses 1013system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007771 # miss rate for overall accesses 1014system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016107 # miss rate for overall accesses 1015system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034407 # miss rate for overall accesses 1016system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183955 # miss rate for overall accesses 1017system.cpu0.l2cache.overall_miss_rate::total 0.074757 # miss rate for overall accesses 1018system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47408.192090 # average ReadReq miss latency 1019system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24771.276596 # average ReadReq miss latency 1020system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44754.987531 # average ReadReq miss latency 1021system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3677.384837 # average UpgradeReq miss latency 1022system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3677.384837 # average UpgradeReq miss latency 1023system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2389.480078 # average SCUpgradeReq miss latency 1024system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2389.480078 # average SCUpgradeReq miss latency 1025system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 302500 # average SCUpgradeFailReq miss latency 1026system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302500 # average SCUpgradeFailReq miss latency 1027system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65932.888564 # average ReadExReq miss latency 1028system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65932.888564 # average ReadExReq miss latency 1029system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64303.012185 # average ReadCleanReq miss latency 1030system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64303.012185 # average ReadCleanReq miss latency 1031system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35102.610094 # average ReadSharedReq miss latency 1032system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35102.610094 # average ReadSharedReq miss latency 1033system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47408.192090 # average overall miss latency 1034system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24771.276596 # average overall miss latency 1035system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64303.012185 # average overall miss latency 1036system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45093.879243 # average overall miss latency 1037system.cpu0.l2cache.demand_avg_miss_latency::total 51207.148956 # average overall miss latency 1038system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47408.192090 # average overall miss latency 1039system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24771.276596 # average overall miss latency 1040system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64303.012185 # average overall miss latency 1041system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45093.879243 # average overall miss latency 1042system.cpu0.l2cache.overall_avg_miss_latency::total 51207.148956 # average overall miss latency 1043system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked 1044system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1046system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 1048system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1050system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1051system.cpu0.l2cache.writebacks::writebacks 237808 # number of writebacks 1052system.cpu0.l2cache.writebacks::total 237808 # number of writebacks 1053system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5210 # number of ReadExReq MSHR hits 1054system.cpu0.l2cache.ReadExReq_mshr_hits::total 5210 # number of ReadExReq MSHR hits 1055system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 69 # number of ReadCleanReq MSHR hits 1056system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 69 # number of ReadCleanReq MSHR hits 1057system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 569 # number of ReadSharedReq MSHR hits 1058system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 569 # number of ReadSharedReq MSHR hits 1059system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 69 # number of demand (read+write) MSHR hits 1060system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5779 # number of demand (read+write) MSHR hits 1061system.cpu0.l2cache.demand_mshr_hits::total 5848 # number of demand (read+write) MSHR hits 1062system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 69 # number of overall MSHR hits 1063system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5779 # number of overall MSHR hits 1064system.cpu0.l2cache.overall_mshr_hits::total 5848 # number of overall MSHR hits 1065system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 708 # number of ReadReq MSHR misses 1066system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 94 # number of ReadReq MSHR misses 1067system.cpu0.l2cache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses 1068system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264185 # number of HardPFReq MSHR misses 1069system.cpu0.l2cache.HardPFReq_mshr_misses::total 264185 # number of HardPFReq MSHR misses 1070system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 57006 # number of UpgradeReq MSHR misses 1071system.cpu0.l2cache.UpgradeReq_mshr_misses::total 57006 # number of UpgradeReq MSHR misses 1072system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20580 # number of SCUpgradeReq MSHR misses 1073system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20580 # number of SCUpgradeReq MSHR misses 1074system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1075system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1076system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43284 # number of ReadExReq MSHR misses 1077system.cpu0.l2cache.ReadExReq_mshr_misses::total 43284 # number of ReadExReq MSHR misses 1078system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70179 # number of ReadCleanReq MSHR misses 1079system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70179 # number of ReadCleanReq MSHR misses 1080system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100576 # number of ReadSharedReq MSHR misses 1081system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100576 # number of ReadSharedReq MSHR misses 1082system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 708 # number of demand (read+write) MSHR misses 1083system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 94 # number of demand (read+write) MSHR misses 1084system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70179 # number of demand (read+write) MSHR misses 1085system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143860 # number of demand (read+write) MSHR misses 1086system.cpu0.l2cache.demand_mshr_misses::total 214841 # number of demand (read+write) MSHR misses 1087system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 708 # number of overall MSHR misses 1088system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 94 # number of overall MSHR misses 1089system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70179 # number of overall MSHR misses 1090system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143860 # number of overall MSHR misses 1091system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264185 # number of overall MSHR misses 1092system.cpu0.l2cache.overall_mshr_misses::total 479026 # number of overall MSHR misses 1093system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 1094system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32047 # number of ReadReq MSHR uncacheable 1095system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35964 # number of ReadReq MSHR uncacheable 1096system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable 1097system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable 1098system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 1099system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60771 # number of overall MSHR uncacheable misses 1100system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 64688 # number of overall MSHR uncacheable misses 1101system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 29317000 # number of ReadReq MSHR miss cycles 1102system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1764500 # number of ReadReq MSHR miss cycles 1103system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 31081500 # number of ReadReq MSHR miss cycles 1104system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20868982731 # number of HardPFReq MSHR miss cycles 1105system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20868982731 # number of HardPFReq MSHR miss cycles 1106system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1541137000 # number of UpgradeReq MSHR miss cycles 1107system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1541137000 # number of UpgradeReq MSHR miss cycles 1108system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 368989000 # number of SCUpgradeReq MSHR miss cycles 1109system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 368989000 # number of SCUpgradeReq MSHR miss cycles 1110system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 533000 # number of SCUpgradeFailReq MSHR miss cycles 1111system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 533000 # number of SCUpgradeFailReq MSHR miss cycles 1112system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2455445500 # number of ReadExReq MSHR miss cycles 1113system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2455445500 # number of ReadExReq MSHR miss cycles 1114system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4093922000 # number of ReadCleanReq MSHR miss cycles 1115system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4093922000 # number of ReadCleanReq MSHR miss cycles 1116system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2912555498 # number of ReadSharedReq MSHR miss cycles 1117system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2912555498 # number of ReadSharedReq MSHR miss cycles 1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 29317000 # number of demand (read+write) MSHR miss cycles 1119system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1764500 # number of demand (read+write) MSHR miss cycles 1120system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4093922000 # number of demand (read+write) MSHR miss cycles 1121system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5368000998 # number of demand (read+write) MSHR miss cycles 1122system.cpu0.l2cache.demand_mshr_miss_latency::total 9493004498 # number of demand (read+write) MSHR miss cycles 1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 29317000 # number of overall MSHR miss cycles 1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1764500 # number of overall MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4093922000 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5368000998 # number of overall MSHR miss cycles 1127system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20868982731 # number of overall MSHR miss cycles 1128system.cpu0.l2cache.overall_mshr_miss_latency::total 30361987229 # number of overall MSHR miss cycles 1129system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles 1130system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445976000 # number of ReadReq MSHR uncacheable cycles 1131system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971996000 # number of ReadReq MSHR uncacheable cycles 1132system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5236748000 # number of WriteReq MSHR uncacheable cycles 1133system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5236748000 # number of WriteReq MSHR uncacheable cycles 1134system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles 1135system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11682724000 # number of overall MSHR uncacheable cycles 1136system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12208744000 # number of overall MSHR uncacheable cycles 1137system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007771 # mshr miss rate for ReadReq accesses 1138system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016107 # mshr miss rate for ReadReq accesses 1139system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008273 # mshr miss rate for ReadReq accesses 1140system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1141system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1142system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1143system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1144system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1145system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1146system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1147system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1148system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153762 # mshr miss rate for ReadExReq accesses 1149system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153762 # mshr miss rate for ReadExReq accesses 1150system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034373 # mshr miss rate for ReadCleanReq accesses 1151system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034373 # mshr miss rate for ReadCleanReq accesses 1152system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189068 # mshr miss rate for ReadSharedReq accesses 1153system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189068 # mshr miss rate for ReadSharedReq accesses 1154system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007771 # mshr miss rate for demand accesses 1155system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016107 # mshr miss rate for demand accesses 1156system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034373 # mshr miss rate for demand accesses 1157system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.176850 # mshr miss rate for demand accesses 1158system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072776 # mshr miss rate for demand accesses 1159system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007771 # mshr miss rate for overall accesses 1160system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016107 # mshr miss rate for overall accesses 1161system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034373 # mshr miss rate for overall accesses 1162system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.176850 # mshr miss rate for overall accesses 1163system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1164system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162267 # mshr miss rate for overall accesses 1165system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090 # average ReadReq mshr miss latency 1166system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596 # average ReadReq mshr miss latency 1167system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38754.987531 # average ReadReq mshr miss latency 1168system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493 # average HardPFReq mshr miss latency 1169system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 78993.821493 # average HardPFReq mshr miss latency 1170system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 27034.645476 # average UpgradeReq mshr miss latency 1171system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 27034.645476 # average UpgradeReq mshr miss latency 1172system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17929.494655 # average SCUpgradeReq mshr miss latency 1173system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17929.494655 # average SCUpgradeReq mshr miss latency 1174system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 266500 # average SCUpgradeFailReq mshr miss latency 1175system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 266500 # average SCUpgradeFailReq mshr miss latency 1176system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56728.710378 # average ReadExReq mshr miss latency 1177system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56728.710378 # average ReadExReq mshr miss latency 1178system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58335.427977 # average ReadCleanReq mshr miss latency 1179system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58335.427977 # average ReadCleanReq mshr miss latency 1180system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28958.752565 # average ReadSharedReq mshr miss latency 1181system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28958.752565 # average ReadSharedReq mshr miss latency 1182system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090 # average overall mshr miss latency 1183system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596 # average overall mshr miss latency 1184system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58335.427977 # average overall mshr miss latency 1185system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37314.062269 # average overall mshr miss latency 1186system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44186.186519 # average overall mshr miss latency 1187system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090 # average overall mshr miss latency 1188system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596 # average overall mshr miss latency 1189system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58335.427977 # average overall mshr miss latency 1190system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37314.062269 # average overall mshr miss latency 1191system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493 # average overall mshr miss latency 1192system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63382.754233 # average overall mshr miss latency 1193system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency 1194system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201141.323681 # average ReadReq mshr uncacheable latency 1195system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193860.415972 # average ReadReq mshr uncacheable latency 1196system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182312.630553 # average WriteReq mshr uncacheable latency 1197system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182312.630553 # average WriteReq mshr uncacheable latency 1198system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency 1199system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192241.760050 # average overall mshr uncacheable latency 1200system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188732.747959 # average overall mshr uncacheable latency 1201system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1202system.cpu0.toL2Bus.snoop_filter.tot_requests 5755750 # Total number of requests made to the snoop filter. 1203system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900650 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1204system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1205system.cpu0.toL2Bus.snoop_filter.tot_snoops 351752 # Total number of snoops made to the snoop filter. 1206system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 347037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1207system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4715 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1208system.cpu0.toL2Bus.trans_dist::ReadReq 143210 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::ReadResp 2766468 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution 1212system.cpu0.toL2Bus.trans_dist::WritebackDirty 746011 # Transaction distribution 1213system.cpu0.toL2Bus.trans_dist::WritebackClean 2247535 # Transaction distribution 1214system.cpu0.toL2Bus.trans_dist::CleanEvict 246533 # Transaction distribution 1215system.cpu0.toL2Bus.trans_dist::HardPFReq 331594 # Transaction distribution 1216system.cpu0.toL2Bus.trans_dist::UpgradeReq 87502 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43040 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::UpgradeResp 114569 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 1221system.cpu0.toL2Bus.trans_dist::ReadExReq 300476 # Transaction distribution 1222system.cpu0.toL2Bus.trans_dist::ReadExResp 297107 # Transaction distribution 1223system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2041686 # Transaction distribution 1224system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606504 # Transaction distribution 1225system.cpu0.toL2Bus.trans_dist::InvalidateReq 3118 # Transaction distribution 1226system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6096444 # Packet count per connected master and slave (bytes) 1227system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2755852 # Packet count per connected master and slave (bytes) 1228system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13844 # Packet count per connected master and slave (bytes) 1229system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 190303 # Packet count per connected master and slave (bytes) 1230system.cpu0.toL2Bus.pkt_count::total 9056443 # Packet count per connected master and slave (bytes) 1231system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 259253824 # Cumulative packet size per connected master and slave (bytes) 1232system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104429286 # Cumulative packet size per connected master and slave (bytes) 1233system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23344 # Cumulative packet size per connected master and slave (bytes) 1234system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 364416 # Cumulative packet size per connected master and slave (bytes) 1235system.cpu0.toL2Bus.pkt_size::total 364070870 # Cumulative packet size per connected master and slave (bytes) 1236system.cpu0.toL2Bus.snoops 1078661 # Total snoops (count) 1237system.cpu0.toL2Bus.snoop_fanout::samples 4070756 # Request fanout histogram 1238system.cpu0.toL2Bus.snoop_fanout::mean 0.104237 # Request fanout histogram 1239system.cpu0.toL2Bus.snoop_fanout::stdev 0.309335 # Request fanout histogram 1240system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1241system.cpu0.toL2Bus.snoop_fanout::0 3651149 89.69% 89.69% # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::1 414892 10.19% 99.88% # Request fanout histogram 1243system.cpu0.toL2Bus.snoop_fanout::2 4715 0.12% 100.00% # Request fanout histogram 1244system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1245system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1246system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1247system.cpu0.toL2Bus.snoop_fanout::total 4070756 # Request fanout histogram 1248system.cpu0.toL2Bus.reqLayer0.occupancy 5766247494 # Layer occupancy (ticks) 1249system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1250system.cpu0.toL2Bus.snoopLayer0.occupancy 116466956 # Layer occupancy (ticks) 1251system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1252system.cpu0.toL2Bus.respLayer0.occupancy 3069095112 # Layer occupancy (ticks) 1253system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1254system.cpu0.toL2Bus.respLayer1.occupancy 1306223847 # Layer occupancy (ticks) 1255system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1256system.cpu0.toL2Bus.respLayer2.occupancy 8018479 # Layer occupancy (ticks) 1257system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1258system.cpu0.toL2Bus.respLayer3.occupancy 99225447 # Layer occupancy (ticks) 1259system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1260system.cpu1.branchPred.lookups 3641195 # Number of BP lookups 1261system.cpu1.branchPred.condPredicted 2056746 # Number of conditional branches predicted 1262system.cpu1.branchPred.condIncorrect 213596 # Number of conditional branches incorrect 1263system.cpu1.branchPred.BTBLookups 2171070 # Number of BTB lookups 1264system.cpu1.branchPred.BTBHits 1462919 # Number of BTB hits 1265system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1266system.cpu1.branchPred.BTBHitPct 67.382397 # BTB Hit Percentage 1267system.cpu1.branchPred.usedRAS 753966 # Number of times the RAS was used to get a target. 1268system.cpu1.branchPred.RASInCorrect 56559 # Number of incorrect RAS predictions. 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1274system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1275system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1276system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1277system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1278system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1279system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1280system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1281system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1282system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1283system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1284system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1285system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1286system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1287system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1288system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1289system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1290system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1291system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1292system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1293system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1294system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1295system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1296system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1297system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1298system.cpu1.dtb.walker.walks 23130 # Table walker walks requested 1299system.cpu1.dtb.walker.walksShort 23130 # Table walker walks initiated with short descriptors 1300system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18836 # Level at which table walker walks with short descriptors terminate 1301system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4294 # Level at which table walker walks with short descriptors terminate 1302system.cpu1.dtb.walker.walkWaitTime::samples 23130 # Table walker wait (enqueue to first request) latency 1303system.cpu1.dtb.walker.walkWaitTime::0 23130 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1304system.cpu1.dtb.walker.walkWaitTime::total 23130 # Table walker wait (enqueue to first request) latency 1305system.cpu1.dtb.walker.walkCompletionTime::samples 1830 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::mean 11932.513661 # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::gmean 11127.774947 # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::stdev 7404.648675 # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::0-16383 1668 91.15% 91.15% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::16384-32767 148 8.09% 99.23% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.44% 99.67% # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.84% # Table walker service (enqueue to completion) latency 1313system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.16% 100.00% # Table walker service (enqueue to completion) latency 1314system.cpu1.dtb.walker.walkCompletionTime::total 1830 # Table walker service (enqueue to completion) latency 1315system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution 1316system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution 1317system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution 1318system.cpu1.dtb.walker.walkPageSizes::4K 1322 72.24% 72.24% # Table walker page sizes translated 1319system.cpu1.dtb.walker.walkPageSizes::1M 508 27.76% 100.00% # Table walker page sizes translated 1320system.cpu1.dtb.walker.walkPageSizes::total 1830 # Table walker page sizes translated 1321system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23130 # Table walker requests started/completed, data/inst 1322system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1323system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23130 # Table walker requests started/completed, data/inst 1324system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1830 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1326system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1830 # Table walker requests started/completed, data/inst 1327system.cpu1.dtb.walker.walkRequestOrigin::total 24960 # Table walker requests started/completed, data/inst 1328system.cpu1.dtb.inst_hits 0 # ITB inst hits 1329system.cpu1.dtb.inst_misses 0 # ITB inst misses 1330system.cpu1.dtb.read_hits 3607725 # DTB read hits 1331system.cpu1.dtb.read_misses 21408 # DTB read misses 1332system.cpu1.dtb.write_hits 2997772 # DTB write hits 1333system.cpu1.dtb.write_misses 1722 # DTB write misses 1334system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1335system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1336system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1337system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1338system.cpu1.dtb.flush_entries 1725 # Number of entries that have been flushed from TLB 1339system.cpu1.dtb.align_faults 120 # Number of TLB faults due to alignment restrictions 1340system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch 1341system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1342system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions 1343system.cpu1.dtb.read_accesses 3629133 # DTB read accesses 1344system.cpu1.dtb.write_accesses 2999494 # DTB write accesses 1345system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1346system.cpu1.dtb.hits 6605497 # DTB hits 1347system.cpu1.dtb.misses 23130 # DTB misses 1348system.cpu1.dtb.accesses 6628627 # DTB accesses 1349system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1355system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1356system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1357system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1358system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1359system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1360system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1361system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1362system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1363system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1364system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1365system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1366system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1367system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1368system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1369system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1370system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1371system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1372system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1373system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1374system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1375system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1376system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1377system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1378system.cpu1.itb.walker.walks 1936 # Table walker walks requested 1379system.cpu1.itb.walker.walksShort 1936 # Table walker walks initiated with short descriptors 1380system.cpu1.itb.walker.walksShortTerminationLevel::Level1 152 # Level at which table walker walks with short descriptors terminate 1381system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1784 # Level at which table walker walks with short descriptors terminate 1382system.cpu1.itb.walker.walkWaitTime::samples 1936 # Table walker wait (enqueue to first request) latency 1383system.cpu1.itb.walker.walkWaitTime::0 1936 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1384system.cpu1.itb.walker.walkWaitTime::total 1936 # Table walker wait (enqueue to first request) latency 1385system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency 1386system.cpu1.itb.walker.walkCompletionTime::mean 11855.029586 # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::gmean 11358.377652 # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::stdev 4391.934541 # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::4096-8191 130 15.38% 15.38% # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::8192-12287 557 65.92% 81.30% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.25% 94.56% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::16384-20479 22 2.60% 97.16% # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.36% 97.51% # Table walker service (enqueue to completion) latency 1394system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.70% # Table walker service (enqueue to completion) latency 1395system.cpu1.itb.walker.walkCompletionTime::28672-32767 2 0.24% 98.93% # Table walker service (enqueue to completion) latency 1396system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.05% # Table walker service (enqueue to completion) latency 1397system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.71% 99.76% # Table walker service (enqueue to completion) latency 1398system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency 1399system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency 1400system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency 1401system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution 1402system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution 1403system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution 1404system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated 1405system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated 1406system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated 1407system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1408system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1936 # Table walker requests started/completed, data/inst 1409system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1936 # Table walker requests started/completed, data/inst 1410system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1411system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst 1412system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst 1413system.cpu1.itb.walker.walkRequestOrigin::total 2781 # Table walker requests started/completed, data/inst 1414system.cpu1.itb.inst_hits 6961088 # ITB inst hits 1415system.cpu1.itb.inst_misses 1936 # ITB inst misses 1416system.cpu1.itb.read_hits 0 # DTB read hits 1417system.cpu1.itb.read_misses 0 # DTB read misses 1418system.cpu1.itb.write_hits 0 # DTB write hits 1419system.cpu1.itb.write_misses 0 # DTB write misses 1420system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1421system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1422system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1423system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1424system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB 1425system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1426system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1427system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1428system.cpu1.itb.perms_faults 1058 # Number of TLB faults due to permissions restrictions 1429system.cpu1.itb.read_accesses 0 # DTB read accesses 1430system.cpu1.itb.write_accesses 0 # DTB write accesses 1431system.cpu1.itb.inst_accesses 6963024 # ITB inst accesses 1432system.cpu1.itb.hits 6961088 # DTB hits 1433system.cpu1.itb.misses 1936 # DTB misses 1434system.cpu1.itb.accesses 6963024 # DTB accesses 1435system.cpu1.numCycles 40816703 # number of cpu cycles simulated 1436system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1437system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1438system.cpu1.committedInsts 14109392 # Number of instructions committed 1439system.cpu1.committedOps 17295649 # Number of ops (including micro ops) committed 1440system.cpu1.discardedOps 1386756 # Number of ops (including micro ops) which were discarded before commit 1441system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching 1442system.cpu1.quiesceCycles 5656506173 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1443system.cpu1.cpi 2.892875 # CPI: cycles per instruction 1444system.cpu1.ipc 0.345677 # IPC: instructions per cycle 1445system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1446system.cpu1.kern.inst.quiesce 2772 # number of quiesce instructions executed 1447system.cpu1.tickCycles 27557255 # Number of cycles that the object actually ticked 1448system.cpu1.idleCycles 13259448 # Total number of cycles that the object has spent stopped 1449system.cpu1.dcache.tags.replacements 157096 # number of replacements 1450system.cpu1.dcache.tags.tagsinuse 475.586306 # Cycle average of tags in use 1451system.cpu1.dcache.tags.total_refs 6254726 # Total number of references to valid blocks. 1452system.cpu1.dcache.tags.sampled_refs 157444 # Sample count of references to valid blocks. 1453system.cpu1.dcache.tags.avg_refs 39.726671 # Average number of references to valid blocks. 1454system.cpu1.dcache.tags.warmup_cycle 91652045000 # Cycle when the warmup percentage was hit. 1455system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.586306 # Average occupied blocks per requestor 1456system.cpu1.dcache.tags.occ_percent::cpu1.data 0.928880 # Average percentage of cache occupancy 1457system.cpu1.dcache.tags.occ_percent::total 0.928880 # Average percentage of cache occupancy 1458system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 1459system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 1460system.cpu1.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id 1461system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id 1462system.cpu1.dcache.tags.tag_accesses 13266107 # Number of tag accesses 1463system.cpu1.dcache.tags.data_accesses 13266107 # Number of data accesses 1464system.cpu1.dcache.ReadReq_hits::cpu1.data 3282974 # number of ReadReq hits 1465system.cpu1.dcache.ReadReq_hits::total 3282974 # number of ReadReq hits 1466system.cpu1.dcache.WriteReq_hits::cpu1.data 2751908 # number of WriteReq hits 1467system.cpu1.dcache.WriteReq_hits::total 2751908 # number of WriteReq hits 1468system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42647 # number of SoftPFReq hits 1469system.cpu1.dcache.SoftPFReq_hits::total 42647 # number of SoftPFReq hits 1470system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70687 # number of LoadLockedReq hits 1471system.cpu1.dcache.LoadLockedReq_hits::total 70687 # number of LoadLockedReq hits 1472system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62029 # number of StoreCondReq hits 1473system.cpu1.dcache.StoreCondReq_hits::total 62029 # number of StoreCondReq hits 1474system.cpu1.dcache.demand_hits::cpu1.data 6034882 # number of demand (read+write) hits 1475system.cpu1.dcache.demand_hits::total 6034882 # number of demand (read+write) hits 1476system.cpu1.dcache.overall_hits::cpu1.data 6077529 # number of overall hits 1477system.cpu1.dcache.overall_hits::total 6077529 # number of overall hits 1478system.cpu1.dcache.ReadReq_misses::cpu1.data 135266 # number of ReadReq misses 1479system.cpu1.dcache.ReadReq_misses::total 135266 # number of ReadReq misses 1480system.cpu1.dcache.WriteReq_misses::cpu1.data 122118 # number of WriteReq misses 1481system.cpu1.dcache.WriteReq_misses::total 122118 # number of WriteReq misses 1482system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24580 # number of SoftPFReq misses 1483system.cpu1.dcache.SoftPFReq_misses::total 24580 # number of SoftPFReq misses 1484system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16502 # number of LoadLockedReq misses 1485system.cpu1.dcache.LoadLockedReq_misses::total 16502 # number of LoadLockedReq misses 1486system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23395 # number of StoreCondReq misses 1487system.cpu1.dcache.StoreCondReq_misses::total 23395 # number of StoreCondReq misses 1488system.cpu1.dcache.demand_misses::cpu1.data 257384 # number of demand (read+write) misses 1489system.cpu1.dcache.demand_misses::total 257384 # number of demand (read+write) misses 1490system.cpu1.dcache.overall_misses::cpu1.data 281964 # number of overall misses 1491system.cpu1.dcache.overall_misses::total 281964 # number of overall misses 1492system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2192537500 # number of ReadReq miss cycles 1493system.cpu1.dcache.ReadReq_miss_latency::total 2192537500 # number of ReadReq miss cycles 1494system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4529521000 # number of WriteReq miss cycles 1495system.cpu1.dcache.WriteReq_miss_latency::total 4529521000 # number of WriteReq miss cycles 1496system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 318889500 # number of LoadLockedReq miss cycles 1497system.cpu1.dcache.LoadLockedReq_miss_latency::total 318889500 # number of LoadLockedReq miss cycles 1498system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 637518000 # number of StoreCondReq miss cycles 1499system.cpu1.dcache.StoreCondReq_miss_latency::total 637518000 # number of StoreCondReq miss cycles 1500system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095000 # number of StoreCondFailReq miss cycles 1501system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095000 # number of StoreCondFailReq miss cycles 1502system.cpu1.dcache.demand_miss_latency::cpu1.data 6722058500 # number of demand (read+write) miss cycles 1503system.cpu1.dcache.demand_miss_latency::total 6722058500 # number of demand (read+write) miss cycles 1504system.cpu1.dcache.overall_miss_latency::cpu1.data 6722058500 # number of overall miss cycles 1505system.cpu1.dcache.overall_miss_latency::total 6722058500 # number of overall miss cycles 1506system.cpu1.dcache.ReadReq_accesses::cpu1.data 3418240 # number of ReadReq accesses(hits+misses) 1507system.cpu1.dcache.ReadReq_accesses::total 3418240 # number of ReadReq accesses(hits+misses) 1508system.cpu1.dcache.WriteReq_accesses::cpu1.data 2874026 # number of WriteReq accesses(hits+misses) 1509system.cpu1.dcache.WriteReq_accesses::total 2874026 # number of WriteReq accesses(hits+misses) 1510system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67227 # number of SoftPFReq accesses(hits+misses) 1511system.cpu1.dcache.SoftPFReq_accesses::total 67227 # number of SoftPFReq accesses(hits+misses) 1512system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87189 # number of LoadLockedReq accesses(hits+misses) 1513system.cpu1.dcache.LoadLockedReq_accesses::total 87189 # number of LoadLockedReq accesses(hits+misses) 1514system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85424 # number of StoreCondReq accesses(hits+misses) 1515system.cpu1.dcache.StoreCondReq_accesses::total 85424 # number of StoreCondReq accesses(hits+misses) 1516system.cpu1.dcache.demand_accesses::cpu1.data 6292266 # number of demand (read+write) accesses 1517system.cpu1.dcache.demand_accesses::total 6292266 # number of demand (read+write) accesses 1518system.cpu1.dcache.overall_accesses::cpu1.data 6359493 # number of overall (read+write) accesses 1519system.cpu1.dcache.overall_accesses::total 6359493 # number of overall (read+write) accesses 1520system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039572 # miss rate for ReadReq accesses 1521system.cpu1.dcache.ReadReq_miss_rate::total 0.039572 # miss rate for ReadReq accesses 1522system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042490 # miss rate for WriteReq accesses 1523system.cpu1.dcache.WriteReq_miss_rate::total 0.042490 # miss rate for WriteReq accesses 1524system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.365627 # miss rate for SoftPFReq accesses 1525system.cpu1.dcache.SoftPFReq_miss_rate::total 0.365627 # miss rate for SoftPFReq accesses 1526system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189267 # miss rate for LoadLockedReq accesses 1527system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189267 # miss rate for LoadLockedReq accesses 1528system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273869 # miss rate for StoreCondReq accesses 1529system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273869 # miss rate for StoreCondReq accesses 1530system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040905 # miss rate for demand accesses 1531system.cpu1.dcache.demand_miss_rate::total 0.040905 # miss rate for demand accesses 1532system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044337 # miss rate for overall accesses 1533system.cpu1.dcache.overall_miss_rate::total 0.044337 # miss rate for overall accesses 1534system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16209.080626 # average ReadReq miss latency 1535system.cpu1.dcache.ReadReq_avg_miss_latency::total 16209.080626 # average ReadReq miss latency 1536system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37091.346075 # average WriteReq miss latency 1537system.cpu1.dcache.WriteReq_avg_miss_latency::total 37091.346075 # average WriteReq miss latency 1538system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19324.294025 # average LoadLockedReq miss latency 1539system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19324.294025 # average LoadLockedReq miss latency 1540system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27250.181663 # average StoreCondReq miss latency 1541system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27250.181663 # average StoreCondReq miss latency 1542system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1543system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1544system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26116.846813 # average overall miss latency 1545system.cpu1.dcache.demand_avg_miss_latency::total 26116.846813 # average overall miss latency 1546system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23840.130300 # average overall miss latency 1547system.cpu1.dcache.overall_avg_miss_latency::total 23840.130300 # average overall miss latency 1548system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1549system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1550system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1551system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1552system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1553system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1554system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1555system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1556system.cpu1.dcache.writebacks::writebacks 157097 # number of writebacks 1557system.cpu1.dcache.writebacks::total 157097 # number of writebacks 1558system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12921 # number of ReadReq MSHR hits 1559system.cpu1.dcache.ReadReq_mshr_hits::total 12921 # number of ReadReq MSHR hits 1560system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42016 # number of WriteReq MSHR hits 1561system.cpu1.dcache.WriteReq_mshr_hits::total 42016 # number of WriteReq MSHR hits 1562system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11695 # number of LoadLockedReq MSHR hits 1563system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11695 # number of LoadLockedReq MSHR hits 1564system.cpu1.dcache.demand_mshr_hits::cpu1.data 54937 # number of demand (read+write) MSHR hits 1565system.cpu1.dcache.demand_mshr_hits::total 54937 # number of demand (read+write) MSHR hits 1566system.cpu1.dcache.overall_mshr_hits::cpu1.data 54937 # number of overall MSHR hits 1567system.cpu1.dcache.overall_mshr_hits::total 54937 # number of overall MSHR hits 1568system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122345 # number of ReadReq MSHR misses 1569system.cpu1.dcache.ReadReq_mshr_misses::total 122345 # number of ReadReq MSHR misses 1570system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 80102 # number of WriteReq MSHR misses 1571system.cpu1.dcache.WriteReq_mshr_misses::total 80102 # number of WriteReq MSHR misses 1572system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24073 # number of SoftPFReq MSHR misses 1573system.cpu1.dcache.SoftPFReq_mshr_misses::total 24073 # number of SoftPFReq MSHR misses 1574system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4807 # number of LoadLockedReq MSHR misses 1575system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4807 # number of LoadLockedReq MSHR misses 1576system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23395 # number of StoreCondReq MSHR misses 1577system.cpu1.dcache.StoreCondReq_mshr_misses::total 23395 # number of StoreCondReq MSHR misses 1578system.cpu1.dcache.demand_mshr_misses::cpu1.data 202447 # number of demand (read+write) MSHR misses 1579system.cpu1.dcache.demand_mshr_misses::total 202447 # number of demand (read+write) MSHR misses 1580system.cpu1.dcache.overall_mshr_misses::cpu1.data 226520 # number of overall MSHR misses 1581system.cpu1.dcache.overall_mshr_misses::total 226520 # number of overall MSHR misses 1582system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable 1583system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2973 # number of ReadReq MSHR uncacheable 1584system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable 1585system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable 1586system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses 1587system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5284 # number of overall MSHR uncacheable misses 1588system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862537500 # number of ReadReq MSHR miss cycles 1589system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862537500 # number of ReadReq MSHR miss cycles 1590system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2760870000 # number of WriteReq MSHR miss cycles 1591system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2760870000 # number of WriteReq MSHR miss cycles 1592system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 453287500 # number of SoftPFReq MSHR miss cycles 1593system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 453287500 # number of SoftPFReq MSHR miss cycles 1594system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939500 # number of LoadLockedReq MSHR miss cycles 1595system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939500 # number of LoadLockedReq MSHR miss cycles 1596system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 614134000 # number of StoreCondReq MSHR miss cycles 1597system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 614134000 # number of StoreCondReq MSHR miss cycles 1598system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1084000 # number of StoreCondFailReq MSHR miss cycles 1599system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1084000 # number of StoreCondFailReq MSHR miss cycles 1600system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4623407500 # number of demand (read+write) MSHR miss cycles 1601system.cpu1.dcache.demand_mshr_miss_latency::total 4623407500 # number of demand (read+write) MSHR miss cycles 1602system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5076695000 # number of overall MSHR miss cycles 1603system.cpu1.dcache.overall_mshr_miss_latency::total 5076695000 # number of overall MSHR miss cycles 1604system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389226500 # number of ReadReq MSHR uncacheable cycles 1605system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389226500 # number of ReadReq MSHR uncacheable cycles 1606system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251720500 # number of WriteReq MSHR uncacheable cycles 1607system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251720500 # number of WriteReq MSHR uncacheable cycles 1608system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 640947000 # number of overall MSHR uncacheable cycles 1609system.cpu1.dcache.overall_mshr_uncacheable_latency::total 640947000 # number of overall MSHR uncacheable cycles 1610system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035792 # mshr miss rate for ReadReq accesses 1611system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035792 # mshr miss rate for ReadReq accesses 1612system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027871 # mshr miss rate for WriteReq accesses 1613system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027871 # mshr miss rate for WriteReq accesses 1614system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.358085 # mshr miss rate for SoftPFReq accesses 1615system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.358085 # mshr miss rate for SoftPFReq accesses 1616system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055133 # mshr miss rate for LoadLockedReq accesses 1617system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055133 # mshr miss rate for LoadLockedReq accesses 1618system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273869 # mshr miss rate for StoreCondReq accesses 1619system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273869 # mshr miss rate for StoreCondReq accesses 1620system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032174 # mshr miss rate for demand accesses 1621system.cpu1.dcache.demand_mshr_miss_rate::total 0.032174 # mshr miss rate for demand accesses 1622system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035619 # mshr miss rate for overall accesses 1623system.cpu1.dcache.overall_mshr_miss_rate::total 0.035619 # mshr miss rate for overall accesses 1624system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15223.650333 # average ReadReq mshr miss latency 1625system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15223.650333 # average ReadReq mshr miss latency 1626system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34466.929665 # average WriteReq mshr miss latency 1627system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34466.929665 # average WriteReq mshr miss latency 1628system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18829.705479 # average SoftPFReq mshr miss latency 1629system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18829.705479 # average SoftPFReq mshr miss latency 1630system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18086.020387 # average LoadLockedReq mshr miss latency 1631system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18086.020387 # average LoadLockedReq mshr miss latency 1632system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26250.651849 # average StoreCondReq mshr miss latency 1633system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26250.651849 # average StoreCondReq mshr miss latency 1634system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1635system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1636system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22837.619229 # average overall mshr miss latency 1637system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22837.619229 # average overall mshr miss latency 1638system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22411.685502 # average overall mshr miss latency 1639system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22411.685502 # average overall mshr miss latency 1640system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130920.450723 # average ReadReq mshr uncacheable latency 1641system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130920.450723 # average ReadReq mshr uncacheable latency 1642system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108922.760710 # average WriteReq mshr uncacheable latency 1643system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108922.760710 # average WriteReq mshr uncacheable latency 1644system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121299.583649 # average overall mshr uncacheable latency 1645system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121299.583649 # average overall mshr uncacheable latency 1646system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1647system.cpu1.icache.tags.replacements 864194 # number of replacements 1648system.cpu1.icache.tags.tagsinuse 499.135415 # Cycle average of tags in use 1649system.cpu1.icache.tags.total_refs 6095160 # Total number of references to valid blocks. 1650system.cpu1.icache.tags.sampled_refs 864706 # Sample count of references to valid blocks. 1651system.cpu1.icache.tags.avg_refs 7.048824 # Average number of references to valid blocks. 1652system.cpu1.icache.tags.warmup_cycle 73316283000 # Cycle when the warmup percentage was hit. 1653system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135415 # Average occupied blocks per requestor 1654system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974874 # Average percentage of cache occupancy 1655system.cpu1.icache.tags.occ_percent::total 0.974874 # Average percentage of cache occupancy 1656system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1657system.cpu1.icache.tags.age_task_id_blocks_1024::2 460 # Occupied blocks per task id 1658system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id 1659system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1660system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1661system.cpu1.icache.tags.tag_accesses 14784438 # Number of tag accesses 1662system.cpu1.icache.tags.data_accesses 14784438 # Number of data accesses 1663system.cpu1.icache.ReadReq_hits::cpu1.inst 6095160 # number of ReadReq hits 1664system.cpu1.icache.ReadReq_hits::total 6095160 # number of ReadReq hits 1665system.cpu1.icache.demand_hits::cpu1.inst 6095160 # number of demand (read+write) hits 1666system.cpu1.icache.demand_hits::total 6095160 # number of demand (read+write) hits 1667system.cpu1.icache.overall_hits::cpu1.inst 6095160 # number of overall hits 1668system.cpu1.icache.overall_hits::total 6095160 # number of overall hits 1669system.cpu1.icache.ReadReq_misses::cpu1.inst 864706 # number of ReadReq misses 1670system.cpu1.icache.ReadReq_misses::total 864706 # number of ReadReq misses 1671system.cpu1.icache.demand_misses::cpu1.inst 864706 # number of demand (read+write) misses 1672system.cpu1.icache.demand_misses::total 864706 # number of demand (read+write) misses 1673system.cpu1.icache.overall_misses::cpu1.inst 864706 # number of overall misses 1674system.cpu1.icache.overall_misses::total 864706 # number of overall misses 1675system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7648423000 # number of ReadReq miss cycles 1676system.cpu1.icache.ReadReq_miss_latency::total 7648423000 # number of ReadReq miss cycles 1677system.cpu1.icache.demand_miss_latency::cpu1.inst 7648423000 # number of demand (read+write) miss cycles 1678system.cpu1.icache.demand_miss_latency::total 7648423000 # number of demand (read+write) miss cycles 1679system.cpu1.icache.overall_miss_latency::cpu1.inst 7648423000 # number of overall miss cycles 1680system.cpu1.icache.overall_miss_latency::total 7648423000 # number of overall miss cycles 1681system.cpu1.icache.ReadReq_accesses::cpu1.inst 6959866 # number of ReadReq accesses(hits+misses) 1682system.cpu1.icache.ReadReq_accesses::total 6959866 # number of ReadReq accesses(hits+misses) 1683system.cpu1.icache.demand_accesses::cpu1.inst 6959866 # number of demand (read+write) accesses 1684system.cpu1.icache.demand_accesses::total 6959866 # number of demand (read+write) accesses 1685system.cpu1.icache.overall_accesses::cpu1.inst 6959866 # number of overall (read+write) accesses 1686system.cpu1.icache.overall_accesses::total 6959866 # number of overall (read+write) accesses 1687system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124242 # miss rate for ReadReq accesses 1688system.cpu1.icache.ReadReq_miss_rate::total 0.124242 # miss rate for ReadReq accesses 1689system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124242 # miss rate for demand accesses 1690system.cpu1.icache.demand_miss_rate::total 0.124242 # miss rate for demand accesses 1691system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124242 # miss rate for overall accesses 1692system.cpu1.icache.overall_miss_rate::total 0.124242 # miss rate for overall accesses 1693system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8845.113831 # average ReadReq miss latency 1694system.cpu1.icache.ReadReq_avg_miss_latency::total 8845.113831 # average ReadReq miss latency 1695system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8845.113831 # average overall miss latency 1696system.cpu1.icache.demand_avg_miss_latency::total 8845.113831 # average overall miss latency 1697system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8845.113831 # average overall miss latency 1698system.cpu1.icache.overall_avg_miss_latency::total 8845.113831 # average overall miss latency 1699system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1700system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1701system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1702system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1703system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1704system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1705system.cpu1.icache.fast_writes 0 # number of fast writes performed 1706system.cpu1.icache.cache_copies 0 # number of cache copies performed 1707system.cpu1.icache.writebacks::writebacks 864194 # number of writebacks 1708system.cpu1.icache.writebacks::total 864194 # number of writebacks 1709system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 864706 # number of ReadReq MSHR misses 1710system.cpu1.icache.ReadReq_mshr_misses::total 864706 # number of ReadReq MSHR misses 1711system.cpu1.icache.demand_mshr_misses::cpu1.inst 864706 # number of demand (read+write) MSHR misses 1712system.cpu1.icache.demand_mshr_misses::total 864706 # number of demand (read+write) MSHR misses 1713system.cpu1.icache.overall_mshr_misses::cpu1.inst 864706 # number of overall MSHR misses 1714system.cpu1.icache.overall_mshr_misses::total 864706 # number of overall MSHR misses 1715system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1716system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1717system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1718system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1719system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7216070000 # number of ReadReq MSHR miss cycles 1720system.cpu1.icache.ReadReq_mshr_miss_latency::total 7216070000 # number of ReadReq MSHR miss cycles 1721system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7216070000 # number of demand (read+write) MSHR miss cycles 1722system.cpu1.icache.demand_mshr_miss_latency::total 7216070000 # number of demand (read+write) MSHR miss cycles 1723system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7216070000 # number of overall MSHR miss cycles 1724system.cpu1.icache.overall_mshr_miss_latency::total 7216070000 # number of overall MSHR miss cycles 1725system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles 1726system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles 1727system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles 1728system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles 1729system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for ReadReq accesses 1730system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124242 # mshr miss rate for ReadReq accesses 1731system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for demand accesses 1732system.cpu1.icache.demand_mshr_miss_rate::total 0.124242 # mshr miss rate for demand accesses 1733system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for overall accesses 1734system.cpu1.icache.overall_mshr_miss_rate::total 0.124242 # mshr miss rate for overall accesses 1735system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average ReadReq mshr miss latency 1736system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8345.113831 # average ReadReq mshr miss latency 1737system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average overall mshr miss latency 1738system.cpu1.icache.demand_avg_mshr_miss_latency::total 8345.113831 # average overall mshr miss latency 1739system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average overall mshr miss latency 1740system.cpu1.icache.overall_avg_mshr_miss_latency::total 8345.113831 # average overall mshr miss latency 1741system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average ReadReq mshr uncacheable latency 1742system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency 1743system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency 1744system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency 1745system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1746system.cpu1.l2cache.prefetcher.num_hwpf_issued 119025 # number of hwpf issued 1747system.cpu1.l2cache.prefetcher.pfIdentified 119084 # number of prefetch candidates identified 1748system.cpu1.l2cache.prefetcher.pfBufferHit 52 # number of redundant prefetches already in prefetch queue 1749system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1750system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1751system.cpu1.l2cache.prefetcher.pfSpanPage 48684 # number of prefetches not generated due to page crossing 1752system.cpu1.l2cache.tags.replacements 38075 # number of replacements 1753system.cpu1.l2cache.tags.tagsinuse 15173.951540 # Cycle average of tags in use 1754system.cpu1.l2cache.tags.total_refs 1858742 # Total number of references to valid blocks. 1755system.cpu1.l2cache.tags.sampled_refs 53288 # Sample count of references to valid blocks. 1756system.cpu1.l2cache.tags.avg_refs 34.881061 # Average number of references to valid blocks. 1757system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1758system.cpu1.l2cache.tags.occ_blocks::writebacks 14749.353983 # Average occupied blocks per requestor 1759system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.286789 # Average occupied blocks per requestor 1760system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.078849 # Average occupied blocks per requestor 1761system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.231918 # Average occupied blocks per requestor 1762system.cpu1.l2cache.tags.occ_percent::writebacks 0.900229 # Average percentage of cache occupancy 1763system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy 1764system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy 1765system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023635 # Average percentage of cache occupancy 1766system.cpu1.l2cache.tags.occ_percent::total 0.926145 # Average percentage of cache occupancy 1767system.cpu1.l2cache.tags.occ_task_id_blocks::1022 919 # Occupied blocks per task id 1768system.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 1769system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14202 # Occupied blocks per task id 1770system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id 1771system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 50 # Occupied blocks per task id 1772system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 864 # Occupied blocks per task id 1773system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id 1774system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1775system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 56 # Occupied blocks per task id 1776system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id 1777system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1786 # Occupied blocks per task id 1778system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12079 # Occupied blocks per task id 1779system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056091 # Percentage of cache occupancy per task id 1780system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 1781system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.866821 # Percentage of cache occupancy per task id 1782system.cpu1.l2cache.tags.tag_accesses 34538889 # Number of tag accesses 1783system.cpu1.l2cache.tags.data_accesses 34538889 # Number of data accesses 1784system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24515 # number of ReadReq hits 1785system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits 1786system.cpu1.l2cache.ReadReq_hits::total 26968 # number of ReadReq hits 1787system.cpu1.l2cache.WritebackDirty_hits::writebacks 95201 # number of WritebackDirty hits 1788system.cpu1.l2cache.WritebackDirty_hits::total 95201 # number of WritebackDirty hits 1789system.cpu1.l2cache.WritebackClean_hits::writebacks 907759 # number of WritebackClean hits 1790system.cpu1.l2cache.WritebackClean_hits::total 907759 # number of WritebackClean hits 1791system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18142 # number of ReadExReq hits 1792system.cpu1.l2cache.ReadExReq_hits::total 18142 # number of ReadExReq hits 1793system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 851797 # number of ReadCleanReq hits 1794system.cpu1.l2cache.ReadCleanReq_hits::total 851797 # number of ReadCleanReq hits 1795system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 83849 # number of ReadSharedReq hits 1796system.cpu1.l2cache.ReadSharedReq_hits::total 83849 # number of ReadSharedReq hits 1797system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24515 # number of demand (read+write) hits 1798system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits 1799system.cpu1.l2cache.demand_hits::cpu1.inst 851797 # number of demand (read+write) hits 1800system.cpu1.l2cache.demand_hits::cpu1.data 101991 # number of demand (read+write) hits 1801system.cpu1.l2cache.demand_hits::total 980756 # number of demand (read+write) hits 1802system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24515 # number of overall hits 1803system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2453 # number of overall hits 1804system.cpu1.l2cache.overall_hits::cpu1.inst 851797 # number of overall hits 1805system.cpu1.l2cache.overall_hits::cpu1.data 101991 # number of overall hits 1806system.cpu1.l2cache.overall_hits::total 980756 # number of overall hits 1807system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 708 # number of ReadReq misses 1808system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 242 # number of ReadReq misses 1809system.cpu1.l2cache.ReadReq_misses::total 950 # number of ReadReq misses 1810system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29444 # number of UpgradeReq misses 1811system.cpu1.l2cache.UpgradeReq_misses::total 29444 # number of UpgradeReq misses 1812system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23394 # number of SCUpgradeReq misses 1813system.cpu1.l2cache.SCUpgradeReq_misses::total 23394 # number of SCUpgradeReq misses 1814system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 1815system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1816system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32519 # number of ReadExReq misses 1817system.cpu1.l2cache.ReadExReq_misses::total 32519 # number of ReadExReq misses 1818system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12909 # number of ReadCleanReq misses 1819system.cpu1.l2cache.ReadCleanReq_misses::total 12909 # number of ReadCleanReq misses 1820system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67373 # number of ReadSharedReq misses 1821system.cpu1.l2cache.ReadSharedReq_misses::total 67373 # number of ReadSharedReq misses 1822system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 708 # number of demand (read+write) misses 1823system.cpu1.l2cache.demand_misses::cpu1.itb.walker 242 # number of demand (read+write) misses 1824system.cpu1.l2cache.demand_misses::cpu1.inst 12909 # number of demand (read+write) misses 1825system.cpu1.l2cache.demand_misses::cpu1.data 99892 # number of demand (read+write) misses 1826system.cpu1.l2cache.demand_misses::total 113751 # number of demand (read+write) misses 1827system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 708 # number of overall misses 1828system.cpu1.l2cache.overall_misses::cpu1.itb.walker 242 # number of overall misses 1829system.cpu1.l2cache.overall_misses::cpu1.inst 12909 # number of overall misses 1830system.cpu1.l2cache.overall_misses::cpu1.data 99892 # number of overall misses 1831system.cpu1.l2cache.overall_misses::total 113751 # number of overall misses 1832system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15804500 # number of ReadReq miss cycles 1833system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4851500 # number of ReadReq miss cycles 1834system.cpu1.l2cache.ReadReq_miss_latency::total 20656000 # number of ReadReq miss cycles 1835system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65469500 # number of UpgradeReq miss cycles 1836system.cpu1.l2cache.UpgradeReq_miss_latency::total 65469500 # number of UpgradeReq miss cycles 1837system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 59113000 # number of SCUpgradeReq miss cycles 1838system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 59113000 # number of SCUpgradeReq miss cycles 1839system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1066999 # number of SCUpgradeFailReq miss cycles 1840system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1066999 # number of SCUpgradeFailReq miss cycles 1841system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1736092499 # number of ReadExReq miss cycles 1842system.cpu1.l2cache.ReadExReq_miss_latency::total 1736092499 # number of ReadExReq miss cycles 1843system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 738228000 # number of ReadCleanReq miss cycles 1844system.cpu1.l2cache.ReadCleanReq_miss_latency::total 738228000 # number of ReadCleanReq miss cycles 1845system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1614591996 # number of ReadSharedReq miss cycles 1846system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1614591996 # number of ReadSharedReq miss cycles 1847system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15804500 # number of demand (read+write) miss cycles 1848system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4851500 # number of demand (read+write) miss cycles 1849system.cpu1.l2cache.demand_miss_latency::cpu1.inst 738228000 # number of demand (read+write) miss cycles 1850system.cpu1.l2cache.demand_miss_latency::cpu1.data 3350684495 # number of demand (read+write) miss cycles 1851system.cpu1.l2cache.demand_miss_latency::total 4109568495 # number of demand (read+write) miss cycles 1852system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15804500 # number of overall miss cycles 1853system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4851500 # number of overall miss cycles 1854system.cpu1.l2cache.overall_miss_latency::cpu1.inst 738228000 # number of overall miss cycles 1855system.cpu1.l2cache.overall_miss_latency::cpu1.data 3350684495 # number of overall miss cycles 1856system.cpu1.l2cache.overall_miss_latency::total 4109568495 # number of overall miss cycles 1857system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25223 # number of ReadReq accesses(hits+misses) 1858system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2695 # number of ReadReq accesses(hits+misses) 1859system.cpu1.l2cache.ReadReq_accesses::total 27918 # number of ReadReq accesses(hits+misses) 1860system.cpu1.l2cache.WritebackDirty_accesses::writebacks 95201 # number of WritebackDirty accesses(hits+misses) 1861system.cpu1.l2cache.WritebackDirty_accesses::total 95201 # number of WritebackDirty accesses(hits+misses) 1862system.cpu1.l2cache.WritebackClean_accesses::writebacks 907759 # number of WritebackClean accesses(hits+misses) 1863system.cpu1.l2cache.WritebackClean_accesses::total 907759 # number of WritebackClean accesses(hits+misses) 1864system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29444 # number of UpgradeReq accesses(hits+misses) 1865system.cpu1.l2cache.UpgradeReq_accesses::total 29444 # number of UpgradeReq accesses(hits+misses) 1866system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23394 # number of SCUpgradeReq accesses(hits+misses) 1867system.cpu1.l2cache.SCUpgradeReq_accesses::total 23394 # number of SCUpgradeReq accesses(hits+misses) 1868system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1869system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1870system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50661 # number of ReadExReq accesses(hits+misses) 1871system.cpu1.l2cache.ReadExReq_accesses::total 50661 # number of ReadExReq accesses(hits+misses) 1872system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 864706 # number of ReadCleanReq accesses(hits+misses) 1873system.cpu1.l2cache.ReadCleanReq_accesses::total 864706 # number of ReadCleanReq accesses(hits+misses) 1874system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 151222 # number of ReadSharedReq accesses(hits+misses) 1875system.cpu1.l2cache.ReadSharedReq_accesses::total 151222 # number of ReadSharedReq accesses(hits+misses) 1876system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25223 # number of demand (read+write) accesses 1877system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2695 # number of demand (read+write) accesses 1878system.cpu1.l2cache.demand_accesses::cpu1.inst 864706 # number of demand (read+write) accesses 1879system.cpu1.l2cache.demand_accesses::cpu1.data 201883 # number of demand (read+write) accesses 1880system.cpu1.l2cache.demand_accesses::total 1094507 # number of demand (read+write) accesses 1881system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25223 # number of overall (read+write) accesses 1882system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2695 # number of overall (read+write) accesses 1883system.cpu1.l2cache.overall_accesses::cpu1.inst 864706 # number of overall (read+write) accesses 1884system.cpu1.l2cache.overall_accesses::cpu1.data 201883 # number of overall (read+write) accesses 1885system.cpu1.l2cache.overall_accesses::total 1094507 # number of overall (read+write) accesses 1886system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028070 # miss rate for ReadReq accesses 1887system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.089796 # miss rate for ReadReq accesses 1888system.cpu1.l2cache.ReadReq_miss_rate::total 0.034028 # miss rate for ReadReq accesses 1889system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1890system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1891system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1892system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1893system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1894system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1895system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641894 # miss rate for ReadExReq accesses 1896system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641894 # miss rate for ReadExReq accesses 1897system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.014929 # miss rate for ReadCleanReq accesses 1898system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.014929 # miss rate for ReadCleanReq accesses 1899system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.445524 # miss rate for ReadSharedReq accesses 1900system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.445524 # miss rate for ReadSharedReq accesses 1901system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028070 # miss rate for demand accesses 1902system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.089796 # miss rate for demand accesses 1903system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.014929 # miss rate for demand accesses 1904system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.494801 # miss rate for demand accesses 1905system.cpu1.l2cache.demand_miss_rate::total 0.103929 # miss rate for demand accesses 1906system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028070 # miss rate for overall accesses 1907system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.089796 # miss rate for overall accesses 1908system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.014929 # miss rate for overall accesses 1909system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.494801 # miss rate for overall accesses 1910system.cpu1.l2cache.overall_miss_rate::total 0.103929 # miss rate for overall accesses 1911system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22322.740113 # average ReadReq miss latency 1912system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20047.520661 # average ReadReq miss latency 1913system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21743.157895 # average ReadReq miss latency 1914system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2223.526015 # average UpgradeReq miss latency 1915system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2223.526015 # average UpgradeReq miss latency 1916system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2526.844490 # average SCUpgradeReq miss latency 1917system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2526.844490 # average SCUpgradeReq miss latency 1918system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1066999 # average SCUpgradeFailReq miss latency 1919system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1066999 # average SCUpgradeFailReq miss latency 1920system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53387.019865 # average ReadExReq miss latency 1921system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53387.019865 # average ReadExReq miss latency 1922system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57187.078782 # average ReadCleanReq miss latency 1923system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57187.078782 # average ReadCleanReq miss latency 1924system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23964.971071 # average ReadSharedReq miss latency 1925system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23964.971071 # average ReadSharedReq miss latency 1926system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22322.740113 # average overall miss latency 1927system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20047.520661 # average overall miss latency 1928system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57187.078782 # average overall miss latency 1929system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33543.071467 # average overall miss latency 1930system.cpu1.l2cache.demand_avg_miss_latency::total 36127.757075 # average overall miss latency 1931system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22322.740113 # average overall miss latency 1932system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20047.520661 # average overall miss latency 1933system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57187.078782 # average overall miss latency 1934system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33543.071467 # average overall miss latency 1935system.cpu1.l2cache.overall_avg_miss_latency::total 36127.757075 # average overall miss latency 1936system.cpu1.l2cache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked 1937system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1938system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked 1939system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1940system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked 1941system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1942system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1943system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1944system.cpu1.l2cache.writebacks::writebacks 29108 # number of writebacks 1945system.cpu1.l2cache.writebacks::total 29108 # number of writebacks 1946system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 236 # number of ReadExReq MSHR hits 1947system.cpu1.l2cache.ReadExReq_mshr_hits::total 236 # number of ReadExReq MSHR hits 1948system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits 1949system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 1950system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits 1951system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits 1952system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits 1953system.cpu1.l2cache.demand_mshr_hits::cpu1.data 271 # number of demand (read+write) MSHR hits 1954system.cpu1.l2cache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits 1955system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits 1956system.cpu1.l2cache.overall_mshr_hits::cpu1.data 271 # number of overall MSHR hits 1957system.cpu1.l2cache.overall_mshr_hits::total 280 # number of overall MSHR hits 1958system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 708 # number of ReadReq MSHR misses 1959system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 242 # number of ReadReq MSHR misses 1960system.cpu1.l2cache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses 1961system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 20082 # number of HardPFReq MSHR misses 1962system.cpu1.l2cache.HardPFReq_mshr_misses::total 20082 # number of HardPFReq MSHR misses 1963system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29444 # number of UpgradeReq MSHR misses 1964system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29444 # number of UpgradeReq MSHR misses 1965system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23394 # number of SCUpgradeReq MSHR misses 1966system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23394 # number of SCUpgradeReq MSHR misses 1967system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 1968system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1969system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32283 # number of ReadExReq MSHR misses 1970system.cpu1.l2cache.ReadExReq_mshr_misses::total 32283 # number of ReadExReq MSHR misses 1971system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 12900 # number of ReadCleanReq MSHR misses 1972system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 12900 # number of ReadCleanReq MSHR misses 1973system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 67338 # number of ReadSharedReq MSHR misses 1974system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 67338 # number of ReadSharedReq MSHR misses 1975system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 708 # number of demand (read+write) MSHR misses 1976system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 242 # number of demand (read+write) MSHR misses 1977system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12900 # number of demand (read+write) MSHR misses 1978system.cpu1.l2cache.demand_mshr_misses::cpu1.data 99621 # number of demand (read+write) MSHR misses 1979system.cpu1.l2cache.demand_mshr_misses::total 113471 # number of demand (read+write) MSHR misses 1980system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 708 # number of overall MSHR misses 1981system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 242 # number of overall MSHR misses 1982system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12900 # number of overall MSHR misses 1983system.cpu1.l2cache.overall_mshr_misses::cpu1.data 99621 # number of overall MSHR misses 1984system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 20082 # number of overall MSHR misses 1985system.cpu1.l2cache.overall_mshr_misses::total 133553 # number of overall MSHR misses 1986system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1987system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable 1988system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable 1989system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable 1990system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable 1991system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1992system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses 1993system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5396 # number of overall MSHR uncacheable misses 1994system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11556500 # number of ReadReq MSHR miss cycles 1995system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3399500 # number of ReadReq MSHR miss cycles 1996system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 14956000 # number of ReadReq MSHR miss cycles 1997system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1023264430 # number of HardPFReq MSHR miss cycles 1998system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1023264430 # number of HardPFReq MSHR miss cycles 1999system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 603797000 # number of UpgradeReq MSHR miss cycles 2000system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 603797000 # number of UpgradeReq MSHR miss cycles 2001system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 437130500 # number of SCUpgradeReq MSHR miss cycles 2002system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 437130500 # number of SCUpgradeReq MSHR miss cycles 2003system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1000999 # number of SCUpgradeFailReq MSHR miss cycles 2004system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1000999 # number of SCUpgradeFailReq MSHR miss cycles 2005system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1515754000 # number of ReadExReq MSHR miss cycles 2006system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1515754000 # number of ReadExReq MSHR miss cycles 2007system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 660362000 # number of ReadCleanReq MSHR miss cycles 2008system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 660362000 # number of ReadCleanReq MSHR miss cycles 2009system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1209005996 # number of ReadSharedReq MSHR miss cycles 2010system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1209005996 # number of ReadSharedReq MSHR miss cycles 2011system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11556500 # number of demand (read+write) MSHR miss cycles 2012system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3399500 # number of demand (read+write) MSHR miss cycles 2013system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 660362000 # number of demand (read+write) MSHR miss cycles 2014system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2724759996 # number of demand (read+write) MSHR miss cycles 2015system.cpu1.l2cache.demand_mshr_miss_latency::total 3400077996 # number of demand (read+write) MSHR miss cycles 2016system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11556500 # number of overall MSHR miss cycles 2017system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3399500 # number of overall MSHR miss cycles 2018system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 660362000 # number of overall MSHR miss cycles 2019system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2724759996 # number of overall MSHR miss cycles 2020system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1023264430 # number of overall MSHR miss cycles 2021system.cpu1.l2cache.overall_mshr_miss_latency::total 4423342426 # number of overall MSHR miss cycles 2022system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14454500 # number of ReadReq MSHR uncacheable cycles 2023system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365375500 # number of ReadReq MSHR uncacheable cycles 2024system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 379830000 # number of ReadReq MSHR uncacheable cycles 2025system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234264000 # number of WriteReq MSHR uncacheable cycles 2026system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234264000 # number of WriteReq MSHR uncacheable cycles 2027system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14454500 # number of overall MSHR uncacheable cycles 2028system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599639500 # number of overall MSHR uncacheable cycles 2029system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614094000 # number of overall MSHR uncacheable cycles 2030system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028070 # mshr miss rate for ReadReq accesses 2031system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.089796 # mshr miss rate for ReadReq accesses 2032system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.034028 # mshr miss rate for ReadReq accesses 2033system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2034system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2035system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2036system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2037system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2038system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2039system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2040system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2041system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637236 # mshr miss rate for ReadExReq accesses 2042system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637236 # mshr miss rate for ReadExReq accesses 2043system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014918 # mshr miss rate for ReadCleanReq accesses 2044system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014918 # mshr miss rate for ReadCleanReq accesses 2045system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.445292 # mshr miss rate for ReadSharedReq accesses 2046system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.445292 # mshr miss rate for ReadSharedReq accesses 2047system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028070 # mshr miss rate for demand accesses 2048system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.089796 # mshr miss rate for demand accesses 2049system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014918 # mshr miss rate for demand accesses 2050system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.493459 # mshr miss rate for demand accesses 2051system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103673 # mshr miss rate for demand accesses 2052system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028070 # mshr miss rate for overall accesses 2053system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.089796 # mshr miss rate for overall accesses 2054system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014918 # mshr miss rate for overall accesses 2055system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.493459 # mshr miss rate for overall accesses 2056system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2057system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122021 # mshr miss rate for overall accesses 2058system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113 # average ReadReq mshr miss latency 2059system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661 # average ReadReq mshr miss latency 2060system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15743.157895 # average ReadReq mshr miss latency 2061system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834 # average HardPFReq mshr miss latency 2062system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50954.308834 # average HardPFReq mshr miss latency 2063system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20506.622741 # average UpgradeReq mshr miss latency 2064system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20506.622741 # average UpgradeReq mshr miss latency 2065system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.581773 # average SCUpgradeReq mshr miss latency 2066system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.581773 # average SCUpgradeReq mshr miss latency 2067system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1000999 # average SCUpgradeFailReq mshr miss latency 2068system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1000999 # average SCUpgradeFailReq mshr miss latency 2069system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46952.080042 # average ReadExReq mshr miss latency 2070system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46952.080042 # average ReadExReq mshr miss latency 2071system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51190.852713 # average ReadCleanReq mshr miss latency 2072system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51190.852713 # average ReadCleanReq mshr miss latency 2073system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17954.290237 # average ReadSharedReq mshr miss latency 2074system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17954.290237 # average ReadSharedReq mshr miss latency 2075system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113 # average overall mshr miss latency 2076system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661 # average overall mshr miss latency 2077system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51190.852713 # average overall mshr miss latency 2078system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27351.261240 # average overall mshr miss latency 2079system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29964.290400 # average overall mshr miss latency 2080system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113 # average overall mshr miss latency 2081system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661 # average overall mshr miss latency 2082system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51190.852713 # average overall mshr miss latency 2083system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27351.261240 # average overall mshr miss latency 2084system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834 # average overall mshr miss latency 2085system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33120.502168 # average overall mshr miss latency 2086system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency 2087system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122897.914564 # average ReadReq mshr uncacheable latency 2088system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123121.555916 # average ReadReq mshr uncacheable latency 2089system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101369.104284 # average WriteReq mshr uncacheable latency 2090system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101369.104284 # average WriteReq mshr uncacheable latency 2091system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency 2092system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113482.115821 # average overall mshr uncacheable latency 2093system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113805.411416 # average overall mshr uncacheable latency 2094system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2095system.cpu1.toL2Bus.snoop_filter.tot_requests 2148021 # Total number of requests made to the snoop filter. 2096system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1081444 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2097system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18331 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2098system.cpu1.toL2Bus.snoop_filter.tot_snoops 178235 # Total number of snoops made to the snoop filter. 2099system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 177001 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2100system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1234 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2101system.cpu1.toL2Bus.trans_dist::ReadReq 34229 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::ReadResp 1087159 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::WritebackDirty 125656 # Transaction distribution 2106system.cpu1.toL2Bus.trans_dist::WritebackClean 907759 # Transaction distribution 2107system.cpu1.toL2Bus.trans_dist::CleanEvict 98212 # Transaction distribution 2108system.cpu1.toL2Bus.trans_dist::HardPFReq 24432 # Transaction distribution 2109system.cpu1.toL2Bus.trans_dist::UpgradeReq 72484 # Transaction distribution 2110system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41782 # Transaction distribution 2111system.cpu1.toL2Bus.trans_dist::UpgradeResp 85083 # Transaction distribution 2112system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2113system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 2114system.cpu1.toL2Bus.trans_dist::ReadExReq 57811 # Transaction distribution 2115system.cpu1.toL2Bus.trans_dist::ReadExResp 55294 # Transaction distribution 2116system.cpu1.toL2Bus.trans_dist::ReadCleanReq 864706 # Transaction distribution 2117system.cpu1.toL2Bus.trans_dist::ReadSharedReq 235840 # Transaction distribution 2118system.cpu1.toL2Bus.trans_dist::InvalidateReq 36 # Transaction distribution 2119system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2577500 # Packet count per connected master and slave (bytes) 2120system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 749010 # Packet count per connected master and slave (bytes) 2121system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6415 # Packet count per connected master and slave (bytes) 2122system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52647 # Packet count per connected master and slave (bytes) 2123system.cpu1.toL2Bus.pkt_count::total 3385572 # Packet count per connected master and slave (bytes) 2124system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109611648 # Cumulative packet size per connected master and slave (bytes) 2125system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25531190 # Cumulative packet size per connected master and slave (bytes) 2126system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10780 # Cumulative packet size per connected master and slave (bytes) 2127system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100892 # Cumulative packet size per connected master and slave (bytes) 2128system.cpu1.toL2Bus.pkt_size::total 135254510 # Cumulative packet size per connected master and slave (bytes) 2129system.cpu1.toL2Bus.snoops 383471 # Total snoops (count) 2130system.cpu1.toL2Bus.snoop_fanout::samples 1462314 # Request fanout histogram 2131system.cpu1.toL2Bus.snoop_fanout::mean 0.140260 # Request fanout histogram 2132system.cpu1.toL2Bus.snoop_fanout::stdev 0.349678 # Request fanout histogram 2133system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2134system.cpu1.toL2Bus.snoop_fanout::0 1258444 86.06% 86.06% # Request fanout histogram 2135system.cpu1.toL2Bus.snoop_fanout::1 202636 13.86% 99.92% # Request fanout histogram 2136system.cpu1.toL2Bus.snoop_fanout::2 1234 0.08% 100.00% # Request fanout histogram 2137system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2138system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2139system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2140system.cpu1.toL2Bus.snoop_fanout::total 1462314 # Request fanout histogram 2141system.cpu1.toL2Bus.reqLayer0.occupancy 2111082490 # Layer occupancy (ticks) 2142system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2143system.cpu1.toL2Bus.snoopLayer0.occupancy 78627228 # Layer occupancy (ticks) 2144system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2145system.cpu1.toL2Bus.respLayer0.occupancy 1297343267 # Layer occupancy (ticks) 2146system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2147system.cpu1.toL2Bus.respLayer1.occupancy 334901961 # Layer occupancy (ticks) 2148system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2149system.cpu1.toL2Bus.respLayer2.occupancy 3720499 # Layer occupancy (ticks) 2150system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2151system.cpu1.toL2Bus.respLayer3.occupancy 27451445 # Layer occupancy (ticks) 2152system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2153system.iobus.trans_dist::ReadReq 31009 # Transaction distribution 2154system.iobus.trans_dist::ReadResp 31009 # Transaction distribution 2155system.iobus.trans_dist::WriteReq 59424 # Transaction distribution 2156system.iobus.trans_dist::WriteResp 59424 # Transaction distribution 2157system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2162system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2163system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2164system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2165system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2166system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2168system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2169system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2170system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2171system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2172system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2173system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2174system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2175system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2176system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) 2177system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2178system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2179system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2187system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2188system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2189system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2190system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2191system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2192system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2193system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2194system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2195system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2196system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2197system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2198system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2199system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) 2200system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2201system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2202system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) 2203system.iobus.reqLayer0.occupancy 51120500 # Layer occupancy (ticks) 2204system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2205system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) 2206system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2207system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) 2208system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2209system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) 2210system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2211system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) 2212system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2213system.iobus.reqLayer7.occupancy 84500 # Layer occupancy (ticks) 2214system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2215system.iobus.reqLayer8.occupancy 571500 # Layer occupancy (ticks) 2216system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2217system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 2218system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2219system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2220system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2221system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2222system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2223system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2224system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2225system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) 2226system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2227system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 2228system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2229system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) 2230system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2231system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2232system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2233system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 2234system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2235system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) 2236system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2237system.iobus.reqLayer23.occupancy 6117000 # Layer occupancy (ticks) 2238system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2239system.iobus.reqLayer24.occupancy 32846500 # Layer occupancy (ticks) 2240system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2241system.iobus.reqLayer25.occupancy 186337026 # Layer occupancy (ticks) 2242system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2243system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) 2244system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2245system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2246system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2247system.iocache.tags.replacements 36449 # number of replacements 2248system.iocache.tags.tagsinuse 14.469949 # Cycle average of tags in use 2249system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2250system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2251system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2252system.iocache.tags.warmup_cycle 272430408000 # Cycle when the warmup percentage was hit. 2253system.iocache.tags.occ_blocks::realview.ide 14.469949 # Average occupied blocks per requestor 2254system.iocache.tags.occ_percent::realview.ide 0.904372 # Average percentage of cache occupancy 2255system.iocache.tags.occ_percent::total 0.904372 # Average percentage of cache occupancy 2256system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2257system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2258system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2259system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2260system.iocache.tags.data_accesses 328203 # Number of data accesses 2261system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2262system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2263system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2264system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2265system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2266system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2267system.iocache.overall_misses::realview.ide 243 # number of overall misses 2268system.iocache.overall_misses::total 243 # number of overall misses 2269system.iocache.ReadReq_miss_latency::realview.ide 32247375 # number of ReadReq miss cycles 2270system.iocache.ReadReq_miss_latency::total 32247375 # number of ReadReq miss cycles 2271system.iocache.WriteLineReq_miss_latency::realview.ide 4733187651 # number of WriteLineReq miss cycles 2272system.iocache.WriteLineReq_miss_latency::total 4733187651 # number of WriteLineReq miss cycles 2273system.iocache.demand_miss_latency::realview.ide 32247375 # number of demand (read+write) miss cycles 2274system.iocache.demand_miss_latency::total 32247375 # number of demand (read+write) miss cycles 2275system.iocache.overall_miss_latency::realview.ide 32247375 # number of overall miss cycles 2276system.iocache.overall_miss_latency::total 32247375 # number of overall miss cycles 2277system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2278system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2279system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2280system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2281system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2282system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2283system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2284system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2285system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2286system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2287system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2288system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2289system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2290system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2291system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2292system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2293system.iocache.ReadReq_avg_miss_latency::realview.ide 132705.246914 # average ReadReq miss latency 2294system.iocache.ReadReq_avg_miss_latency::total 132705.246914 # average ReadReq miss latency 2295system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130664.411744 # average WriteLineReq miss latency 2296system.iocache.WriteLineReq_avg_miss_latency::total 130664.411744 # average WriteLineReq miss latency 2297system.iocache.demand_avg_miss_latency::realview.ide 132705.246914 # average overall miss latency 2298system.iocache.demand_avg_miss_latency::total 132705.246914 # average overall miss latency 2299system.iocache.overall_avg_miss_latency::realview.ide 132705.246914 # average overall miss latency 2300system.iocache.overall_avg_miss_latency::total 132705.246914 # average overall miss latency 2301system.iocache.blocked_cycles::no_mshrs 621 # number of cycles access was blocked 2302system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2303system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked 2304system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2305system.iocache.avg_blocked_cycles::no_mshrs 7.860759 # average number of cycles each access was blocked 2306system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2307system.iocache.fast_writes 0 # number of fast writes performed 2308system.iocache.cache_copies 0 # number of cache copies performed 2309system.iocache.writebacks::writebacks 36206 # number of writebacks 2310system.iocache.writebacks::total 36206 # number of writebacks 2311system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2312system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2313system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2314system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2315system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2316system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2317system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2318system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2319system.iocache.ReadReq_mshr_miss_latency::realview.ide 20097375 # number of ReadReq MSHR miss cycles 2320system.iocache.ReadReq_mshr_miss_latency::total 20097375 # number of ReadReq MSHR miss cycles 2321system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2921987651 # number of WriteLineReq MSHR miss cycles 2322system.iocache.WriteLineReq_mshr_miss_latency::total 2921987651 # number of WriteLineReq MSHR miss cycles 2323system.iocache.demand_mshr_miss_latency::realview.ide 20097375 # number of demand (read+write) MSHR miss cycles 2324system.iocache.demand_mshr_miss_latency::total 20097375 # number of demand (read+write) MSHR miss cycles 2325system.iocache.overall_mshr_miss_latency::realview.ide 20097375 # number of overall MSHR miss cycles 2326system.iocache.overall_mshr_miss_latency::total 20097375 # number of overall MSHR miss cycles 2327system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2328system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2329system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2330system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2331system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2332system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2333system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2334system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2335system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82705.246914 # average ReadReq mshr miss latency 2336system.iocache.ReadReq_avg_mshr_miss_latency::total 82705.246914 # average ReadReq mshr miss latency 2337system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80664.411744 # average WriteLineReq mshr miss latency 2338system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80664.411744 # average WriteLineReq mshr miss latency 2339system.iocache.demand_avg_mshr_miss_latency::realview.ide 82705.246914 # average overall mshr miss latency 2340system.iocache.demand_avg_mshr_miss_latency::total 82705.246914 # average overall mshr miss latency 2341system.iocache.overall_avg_mshr_miss_latency::realview.ide 82705.246914 # average overall mshr miss latency 2342system.iocache.overall_avg_mshr_miss_latency::total 82705.246914 # average overall mshr miss latency 2343system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2344system.l2c.tags.replacements 131701 # number of replacements 2345system.l2c.tags.tagsinuse 63232.493895 # Cycle average of tags in use 2346system.l2c.tags.total_refs 477114 # Total number of references to valid blocks. 2347system.l2c.tags.sampled_refs 195835 # Sample count of references to valid blocks. 2348system.l2c.tags.avg_refs 2.436306 # Average number of references to valid blocks. 2349system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2350system.l2c.tags.occ_blocks::writebacks 13499.183462 # Average occupied blocks per requestor 2351system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.189305 # Average occupied blocks per requestor 2352system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030804 # Average occupied blocks per requestor 2353system.l2c.tags.occ_blocks::cpu0.inst 9276.099032 # Average occupied blocks per requestor 2354system.l2c.tags.occ_blocks::cpu0.data 2886.907500 # Average occupied blocks per requestor 2355system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33207.909394 # Average occupied blocks per requestor 2356system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.955383 # Average occupied blocks per requestor 2357system.l2c.tags.occ_blocks::cpu1.inst 1918.551839 # Average occupied blocks per requestor 2358system.l2c.tags.occ_blocks::cpu1.data 583.845643 # Average occupied blocks per requestor 2359system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1772.821532 # Average occupied blocks per requestor 2360system.l2c.tags.occ_percent::writebacks 0.205981 # Average percentage of cache occupancy 2361system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001239 # Average percentage of cache occupancy 2362system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2363system.l2c.tags.occ_percent::cpu0.inst 0.141542 # Average percentage of cache occupancy 2364system.l2c.tags.occ_percent::cpu0.data 0.044051 # Average percentage of cache occupancy 2365system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506712 # Average percentage of cache occupancy 2366system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000091 # Average percentage of cache occupancy 2367system.l2c.tags.occ_percent::cpu1.inst 0.029275 # Average percentage of cache occupancy 2368system.l2c.tags.occ_percent::cpu1.data 0.008909 # Average percentage of cache occupancy 2369system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027051 # Average percentage of cache occupancy 2370system.l2c.tags.occ_percent::total 0.964851 # Average percentage of cache occupancy 2371system.l2c.tags.occ_task_id_blocks::1022 28913 # Occupied blocks per task id 2372system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 2373system.l2c.tags.occ_task_id_blocks::1024 35162 # Occupied blocks per task id 2374system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id 2375system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id 2376system.l2c.tags.age_task_id_blocks_1022::3 4903 # Occupied blocks per task id 2377system.l2c.tags.age_task_id_blocks_1022::4 23890 # Occupied blocks per task id 2378system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id 2379system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 2380system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 2381system.l2c.tags.age_task_id_blocks_1024::2 486 # Occupied blocks per task id 2382system.l2c.tags.age_task_id_blocks_1024::3 3361 # Occupied blocks per task id 2383system.l2c.tags.age_task_id_blocks_1024::4 31288 # Occupied blocks per task id 2384system.l2c.tags.occ_task_id_percent::1022 0.441177 # Percentage of cache occupancy per task id 2385system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id 2386system.l2c.tags.occ_task_id_percent::1024 0.536530 # Percentage of cache occupancy per task id 2387system.l2c.tags.tag_accesses 6403013 # Number of tag accesses 2388system.l2c.tags.data_accesses 6403013 # Number of data accesses 2389system.l2c.WritebackDirty_hits::writebacks 266916 # number of WritebackDirty hits 2390system.l2c.WritebackDirty_hits::total 266916 # number of WritebackDirty hits 2391system.l2c.UpgradeReq_hits::cpu0.data 34147 # number of UpgradeReq hits 2392system.l2c.UpgradeReq_hits::cpu1.data 2219 # number of UpgradeReq hits 2393system.l2c.UpgradeReq_hits::total 36366 # number of UpgradeReq hits 2394system.l2c.SCUpgradeReq_hits::cpu0.data 2260 # number of SCUpgradeReq hits 2395system.l2c.SCUpgradeReq_hits::cpu1.data 929 # number of SCUpgradeReq hits 2396system.l2c.SCUpgradeReq_hits::total 3189 # number of SCUpgradeReq hits 2397system.l2c.ReadExReq_hits::cpu0.data 4341 # number of ReadExReq hits 2398system.l2c.ReadExReq_hits::cpu1.data 1335 # number of ReadExReq hits 2399system.l2c.ReadExReq_hits::total 5676 # number of ReadExReq hits 2400system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 425 # number of ReadSharedReq hits 2401system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits 2402system.l2c.ReadSharedReq_hits::cpu0.inst 47541 # number of ReadSharedReq hits 2403system.l2c.ReadSharedReq_hits::cpu0.data 51775 # number of ReadSharedReq hits 2404system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49659 # number of ReadSharedReq hits 2405system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 78 # number of ReadSharedReq hits 2406system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits 2407system.l2c.ReadSharedReq_hits::cpu1.inst 9744 # number of ReadSharedReq hits 2408system.l2c.ReadSharedReq_hits::cpu1.data 5530 # number of ReadSharedReq hits 2409system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3532 # number of ReadSharedReq hits 2410system.l2c.ReadSharedReq_hits::total 168385 # number of ReadSharedReq hits 2411system.l2c.demand_hits::cpu0.dtb.walker 425 # number of demand (read+write) hits 2412system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits 2413system.l2c.demand_hits::cpu0.inst 47541 # number of demand (read+write) hits 2414system.l2c.demand_hits::cpu0.data 56116 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.l2cache.prefetcher 49659 # number of demand (read+write) hits 2416system.l2c.demand_hits::cpu1.dtb.walker 78 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu1.itb.walker 12 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu1.inst 9744 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu1.data 6865 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu1.l2cache.prefetcher 3532 # number of demand (read+write) hits 2421system.l2c.demand_hits::total 174061 # number of demand (read+write) hits 2422system.l2c.overall_hits::cpu0.dtb.walker 425 # number of overall hits 2423system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits 2424system.l2c.overall_hits::cpu0.inst 47541 # number of overall hits 2425system.l2c.overall_hits::cpu0.data 56116 # number of overall hits 2426system.l2c.overall_hits::cpu0.l2cache.prefetcher 49659 # number of overall hits 2427system.l2c.overall_hits::cpu1.dtb.walker 78 # number of overall hits 2428system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits 2429system.l2c.overall_hits::cpu1.inst 9744 # number of overall hits 2430system.l2c.overall_hits::cpu1.data 6865 # number of overall hits 2431system.l2c.overall_hits::cpu1.l2cache.prefetcher 3532 # number of overall hits 2432system.l2c.overall_hits::total 174061 # number of overall hits 2433system.l2c.UpgradeReq_misses::cpu0.data 10466 # number of UpgradeReq misses 2434system.l2c.UpgradeReq_misses::cpu1.data 2461 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::total 12927 # number of UpgradeReq misses 2436system.l2c.SCUpgradeReq_misses::cpu0.data 842 # number of SCUpgradeReq misses 2437system.l2c.SCUpgradeReq_misses::cpu1.data 1269 # number of SCUpgradeReq misses 2438system.l2c.SCUpgradeReq_misses::total 2111 # number of SCUpgradeReq misses 2439system.l2c.ReadExReq_misses::cpu0.data 11510 # number of ReadExReq misses 2440system.l2c.ReadExReq_misses::cpu1.data 8279 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::total 19789 # number of ReadExReq misses 2442system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 132 # number of ReadSharedReq misses 2443system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2444system.l2c.ReadSharedReq_misses::cpu0.inst 22638 # number of ReadSharedReq misses 2445system.l2c.ReadSharedReq_misses::cpu0.data 9815 # number of ReadSharedReq misses 2446system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133222 # number of ReadSharedReq misses 2447system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 10 # number of ReadSharedReq misses 2448system.l2c.ReadSharedReq_misses::cpu1.inst 3156 # number of ReadSharedReq misses 2449system.l2c.ReadSharedReq_misses::cpu1.data 1620 # number of ReadSharedReq misses 2450system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5587 # number of ReadSharedReq misses 2451system.l2c.ReadSharedReq_misses::total 176181 # number of ReadSharedReq misses 2452system.l2c.demand_misses::cpu0.dtb.walker 132 # number of demand (read+write) misses 2453system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2454system.l2c.demand_misses::cpu0.inst 22638 # number of demand (read+write) misses 2455system.l2c.demand_misses::cpu0.data 21325 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu0.l2cache.prefetcher 133222 # number of demand (read+write) misses 2457system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu1.inst 3156 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu1.data 9899 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu1.l2cache.prefetcher 5587 # number of demand (read+write) misses 2461system.l2c.demand_misses::total 195970 # number of demand (read+write) misses 2462system.l2c.overall_misses::cpu0.dtb.walker 132 # number of overall misses 2463system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2464system.l2c.overall_misses::cpu0.inst 22638 # number of overall misses 2465system.l2c.overall_misses::cpu0.data 21325 # number of overall misses 2466system.l2c.overall_misses::cpu0.l2cache.prefetcher 133222 # number of overall misses 2467system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 2468system.l2c.overall_misses::cpu1.inst 3156 # number of overall misses 2469system.l2c.overall_misses::cpu1.data 9899 # number of overall misses 2470system.l2c.overall_misses::cpu1.l2cache.prefetcher 5587 # number of overall misses 2471system.l2c.overall_misses::total 195970 # number of overall misses 2472system.l2c.UpgradeReq_miss_latency::cpu0.data 30632500 # number of UpgradeReq miss cycles 2473system.l2c.UpgradeReq_miss_latency::cpu1.data 6192500 # number of UpgradeReq miss cycles 2474system.l2c.UpgradeReq_miss_latency::total 36825000 # number of UpgradeReq miss cycles 2475system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4484000 # number of SCUpgradeReq miss cycles 2476system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2324500 # number of SCUpgradeReq miss cycles 2477system.l2c.SCUpgradeReq_miss_latency::total 6808500 # number of SCUpgradeReq miss cycles 2478system.l2c.ReadExReq_miss_latency::cpu0.data 1686851000 # number of ReadExReq miss cycles 2479system.l2c.ReadExReq_miss_latency::cpu1.data 1090555500 # number of ReadExReq miss cycles 2480system.l2c.ReadExReq_miss_latency::total 2777406500 # number of ReadExReq miss cycles 2481system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 18272000 # number of ReadSharedReq miss cycles 2482system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles 2483system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2964447500 # number of ReadSharedReq miss cycles 2484system.l2c.ReadSharedReq_miss_latency::cpu0.data 1349172500 # number of ReadSharedReq miss cycles 2485system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19981710279 # number of ReadSharedReq miss cycles 2486system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1426000 # number of ReadSharedReq miss cycles 2487system.l2c.ReadSharedReq_miss_latency::cpu1.inst 417581000 # number of ReadSharedReq miss cycles 2488system.l2c.ReadSharedReq_miss_latency::cpu1.data 225572000 # number of ReadSharedReq miss cycles 2489system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 946990899 # number of ReadSharedReq miss cycles 2490system.l2c.ReadSharedReq_miss_latency::total 25905305178 # number of ReadSharedReq miss cycles 2491system.l2c.demand_miss_latency::cpu0.dtb.walker 18272000 # number of demand (read+write) miss cycles 2492system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::cpu0.inst 2964447500 # number of demand (read+write) miss cycles 2494system.l2c.demand_miss_latency::cpu0.data 3036023500 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19981710279 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu1.dtb.walker 1426000 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu1.inst 417581000 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu1.data 1316127500 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 946990899 # number of demand (read+write) miss cycles 2500system.l2c.demand_miss_latency::total 28682711678 # number of demand (read+write) miss cycles 2501system.l2c.overall_miss_latency::cpu0.dtb.walker 18272000 # number of overall miss cycles 2502system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles 2503system.l2c.overall_miss_latency::cpu0.inst 2964447500 # number of overall miss cycles 2504system.l2c.overall_miss_latency::cpu0.data 3036023500 # number of overall miss cycles 2505system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19981710279 # number of overall miss cycles 2506system.l2c.overall_miss_latency::cpu1.dtb.walker 1426000 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu1.inst 417581000 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu1.data 1316127500 # number of overall miss cycles 2509system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 946990899 # number of overall miss cycles 2510system.l2c.overall_miss_latency::total 28682711678 # number of overall miss cycles 2511system.l2c.WritebackDirty_accesses::writebacks 266916 # number of WritebackDirty accesses(hits+misses) 2512system.l2c.WritebackDirty_accesses::total 266916 # number of WritebackDirty accesses(hits+misses) 2513system.l2c.UpgradeReq_accesses::cpu0.data 44613 # number of UpgradeReq accesses(hits+misses) 2514system.l2c.UpgradeReq_accesses::cpu1.data 4680 # number of UpgradeReq accesses(hits+misses) 2515system.l2c.UpgradeReq_accesses::total 49293 # number of UpgradeReq accesses(hits+misses) 2516system.l2c.SCUpgradeReq_accesses::cpu0.data 3102 # number of SCUpgradeReq accesses(hits+misses) 2517system.l2c.SCUpgradeReq_accesses::cpu1.data 2198 # number of SCUpgradeReq accesses(hits+misses) 2518system.l2c.SCUpgradeReq_accesses::total 5300 # number of SCUpgradeReq accesses(hits+misses) 2519system.l2c.ReadExReq_accesses::cpu0.data 15851 # number of ReadExReq accesses(hits+misses) 2520system.l2c.ReadExReq_accesses::cpu1.data 9614 # number of ReadExReq accesses(hits+misses) 2521system.l2c.ReadExReq_accesses::total 25465 # number of ReadExReq accesses(hits+misses) 2522system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 557 # number of ReadSharedReq accesses(hits+misses) 2523system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 90 # number of ReadSharedReq accesses(hits+misses) 2524system.l2c.ReadSharedReq_accesses::cpu0.inst 70179 # number of ReadSharedReq accesses(hits+misses) 2525system.l2c.ReadSharedReq_accesses::cpu0.data 61590 # number of ReadSharedReq accesses(hits+misses) 2526system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182881 # number of ReadSharedReq accesses(hits+misses) 2527system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 88 # number of ReadSharedReq accesses(hits+misses) 2528system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses) 2529system.l2c.ReadSharedReq_accesses::cpu1.inst 12900 # number of ReadSharedReq accesses(hits+misses) 2530system.l2c.ReadSharedReq_accesses::cpu1.data 7150 # number of ReadSharedReq accesses(hits+misses) 2531system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 9119 # number of ReadSharedReq accesses(hits+misses) 2532system.l2c.ReadSharedReq_accesses::total 344566 # number of ReadSharedReq accesses(hits+misses) 2533system.l2c.demand_accesses::cpu0.dtb.walker 557 # number of demand (read+write) accesses 2534system.l2c.demand_accesses::cpu0.itb.walker 90 # number of demand (read+write) accesses 2535system.l2c.demand_accesses::cpu0.inst 70179 # number of demand (read+write) accesses 2536system.l2c.demand_accesses::cpu0.data 77441 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182881 # number of demand (read+write) accesses 2538system.l2c.demand_accesses::cpu1.dtb.walker 88 # number of demand (read+write) accesses 2539system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu1.inst 12900 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu1.data 16764 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::cpu1.l2cache.prefetcher 9119 # number of demand (read+write) accesses 2543system.l2c.demand_accesses::total 370031 # number of demand (read+write) accesses 2544system.l2c.overall_accesses::cpu0.dtb.walker 557 # number of overall (read+write) accesses 2545system.l2c.overall_accesses::cpu0.itb.walker 90 # number of overall (read+write) accesses 2546system.l2c.overall_accesses::cpu0.inst 70179 # number of overall (read+write) accesses 2547system.l2c.overall_accesses::cpu0.data 77441 # number of overall (read+write) accesses 2548system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182881 # number of overall (read+write) accesses 2549system.l2c.overall_accesses::cpu1.dtb.walker 88 # number of overall (read+write) accesses 2550system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::cpu1.inst 12900 # number of overall (read+write) accesses 2552system.l2c.overall_accesses::cpu1.data 16764 # number of overall (read+write) accesses 2553system.l2c.overall_accesses::cpu1.l2cache.prefetcher 9119 # number of overall (read+write) accesses 2554system.l2c.overall_accesses::total 370031 # number of overall (read+write) accesses 2555system.l2c.UpgradeReq_miss_rate::cpu0.data 0.234595 # miss rate for UpgradeReq accesses 2556system.l2c.UpgradeReq_miss_rate::cpu1.data 0.525855 # miss rate for UpgradeReq accesses 2557system.l2c.UpgradeReq_miss_rate::total 0.262248 # miss rate for UpgradeReq accesses 2558system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.271438 # miss rate for SCUpgradeReq accesses 2559system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.577343 # miss rate for SCUpgradeReq accesses 2560system.l2c.SCUpgradeReq_miss_rate::total 0.398302 # miss rate for SCUpgradeReq accesses 2561system.l2c.ReadExReq_miss_rate::cpu0.data 0.726137 # miss rate for ReadExReq accesses 2562system.l2c.ReadExReq_miss_rate::cpu1.data 0.861140 # miss rate for ReadExReq accesses 2563system.l2c.ReadExReq_miss_rate::total 0.777106 # miss rate for ReadExReq accesses 2564system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.236984 # miss rate for ReadSharedReq accesses 2565system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011111 # miss rate for ReadSharedReq accesses 2566system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.322575 # miss rate for ReadSharedReq accesses 2567system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.159360 # miss rate for ReadSharedReq accesses 2568system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.728463 # miss rate for ReadSharedReq accesses 2569system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.113636 # miss rate for ReadSharedReq accesses 2570system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.244651 # miss rate for ReadSharedReq accesses 2571system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.226573 # miss rate for ReadSharedReq accesses 2572system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.612677 # miss rate for ReadSharedReq accesses 2573system.l2c.ReadSharedReq_miss_rate::total 0.511313 # miss rate for ReadSharedReq accesses 2574system.l2c.demand_miss_rate::cpu0.dtb.walker 0.236984 # miss rate for demand accesses 2575system.l2c.demand_miss_rate::cpu0.itb.walker 0.011111 # miss rate for demand accesses 2576system.l2c.demand_miss_rate::cpu0.inst 0.322575 # miss rate for demand accesses 2577system.l2c.demand_miss_rate::cpu0.data 0.275371 # miss rate for demand accesses 2578system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.728463 # miss rate for demand accesses 2579system.l2c.demand_miss_rate::cpu1.dtb.walker 0.113636 # miss rate for demand accesses 2580system.l2c.demand_miss_rate::cpu1.inst 0.244651 # miss rate for demand accesses 2581system.l2c.demand_miss_rate::cpu1.data 0.590492 # miss rate for demand accesses 2582system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.612677 # miss rate for demand accesses 2583system.l2c.demand_miss_rate::total 0.529604 # miss rate for demand accesses 2584system.l2c.overall_miss_rate::cpu0.dtb.walker 0.236984 # miss rate for overall accesses 2585system.l2c.overall_miss_rate::cpu0.itb.walker 0.011111 # miss rate for overall accesses 2586system.l2c.overall_miss_rate::cpu0.inst 0.322575 # miss rate for overall accesses 2587system.l2c.overall_miss_rate::cpu0.data 0.275371 # miss rate for overall accesses 2588system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.728463 # miss rate for overall accesses 2589system.l2c.overall_miss_rate::cpu1.dtb.walker 0.113636 # miss rate for overall accesses 2590system.l2c.overall_miss_rate::cpu1.inst 0.244651 # miss rate for overall accesses 2591system.l2c.overall_miss_rate::cpu1.data 0.590492 # miss rate for overall accesses 2592system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.612677 # miss rate for overall accesses 2593system.l2c.overall_miss_rate::total 0.529604 # miss rate for overall accesses 2594system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2926.858399 # average UpgradeReq miss latency 2595system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2516.253555 # average UpgradeReq miss latency 2596system.l2c.UpgradeReq_avg_miss_latency::total 2848.688791 # average UpgradeReq miss latency 2597system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5325.415677 # average SCUpgradeReq miss latency 2598system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1831.757289 # average SCUpgradeReq miss latency 2599system.l2c.SCUpgradeReq_avg_miss_latency::total 3225.248697 # average SCUpgradeReq miss latency 2600system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146555.256299 # average ReadExReq miss latency 2601system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131725.510327 # average ReadExReq miss latency 2602system.l2c.ReadExReq_avg_miss_latency::total 140351.028349 # average ReadExReq miss latency 2603system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138424.242424 # average ReadSharedReq miss latency 2604system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency 2605system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130950.061843 # average ReadSharedReq miss latency 2606system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137460.264901 # average ReadSharedReq miss latency 2607system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 149988.067129 # average ReadSharedReq miss latency 2608system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142600 # average ReadSharedReq miss latency 2609system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132313.371356 # average ReadSharedReq miss latency 2610system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139241.975309 # average ReadSharedReq miss latency 2611system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169498.997494 # average ReadSharedReq miss latency 2612system.l2c.ReadSharedReq_avg_miss_latency::total 147038.018731 # average ReadSharedReq miss latency 2613system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138424.242424 # average overall miss latency 2614system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2615system.l2c.demand_avg_miss_latency::cpu0.inst 130950.061843 # average overall miss latency 2616system.l2c.demand_avg_miss_latency::cpu0.data 142369.214537 # average overall miss latency 2617system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 149988.067129 # average overall miss latency 2618system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142600 # average overall miss latency 2619system.l2c.demand_avg_miss_latency::cpu1.inst 132313.371356 # average overall miss latency 2620system.l2c.demand_avg_miss_latency::cpu1.data 132955.601576 # average overall miss latency 2621system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169498.997494 # average overall miss latency 2622system.l2c.demand_avg_miss_latency::total 146362.768169 # average overall miss latency 2623system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138424.242424 # average overall miss latency 2624system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2625system.l2c.overall_avg_miss_latency::cpu0.inst 130950.061843 # average overall miss latency 2626system.l2c.overall_avg_miss_latency::cpu0.data 142369.214537 # average overall miss latency 2627system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 149988.067129 # average overall miss latency 2628system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142600 # average overall miss latency 2629system.l2c.overall_avg_miss_latency::cpu1.inst 132313.371356 # average overall miss latency 2630system.l2c.overall_avg_miss_latency::cpu1.data 132955.601576 # average overall miss latency 2631system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169498.997494 # average overall miss latency 2632system.l2c.overall_avg_miss_latency::total 146362.768169 # average overall miss latency 2633system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2634system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2635system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2636system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2637system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2638system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2639system.l2c.fast_writes 0 # number of fast writes performed 2640system.l2c.cache_copies 0 # number of cache copies performed 2641system.l2c.writebacks::writebacks 102060 # number of writebacks 2642system.l2c.writebacks::total 102060 # number of writebacks 2643system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits 2644system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 1 # number of ReadSharedReq MSHR hits 2645system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 2646system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 2647system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2648system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 2649system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 2650system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2651system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits 2652system.l2c.CleanEvict_mshr_misses::writebacks 3561 # number of CleanEvict MSHR misses 2653system.l2c.CleanEvict_mshr_misses::total 3561 # number of CleanEvict MSHR misses 2654system.l2c.UpgradeReq_mshr_misses::cpu0.data 10466 # number of UpgradeReq MSHR misses 2655system.l2c.UpgradeReq_mshr_misses::cpu1.data 2461 # number of UpgradeReq MSHR misses 2656system.l2c.UpgradeReq_mshr_misses::total 12927 # number of UpgradeReq MSHR misses 2657system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 842 # number of SCUpgradeReq MSHR misses 2658system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1269 # number of SCUpgradeReq MSHR misses 2659system.l2c.SCUpgradeReq_mshr_misses::total 2111 # number of SCUpgradeReq MSHR misses 2660system.l2c.ReadExReq_mshr_misses::cpu0.data 11510 # number of ReadExReq MSHR misses 2661system.l2c.ReadExReq_mshr_misses::cpu1.data 8279 # number of ReadExReq MSHR misses 2662system.l2c.ReadExReq_mshr_misses::total 19789 # number of ReadExReq MSHR misses 2663system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 132 # number of ReadSharedReq MSHR misses 2664system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2665system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22634 # number of ReadSharedReq MSHR misses 2666system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9815 # number of ReadSharedReq MSHR misses 2667system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133222 # number of ReadSharedReq MSHR misses 2668system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadSharedReq MSHR misses 2669system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3155 # number of ReadSharedReq MSHR misses 2670system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1620 # number of ReadSharedReq MSHR misses 2671system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5587 # number of ReadSharedReq MSHR misses 2672system.l2c.ReadSharedReq_mshr_misses::total 176176 # number of ReadSharedReq MSHR misses 2673system.l2c.demand_mshr_misses::cpu0.dtb.walker 132 # number of demand (read+write) MSHR misses 2674system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2675system.l2c.demand_mshr_misses::cpu0.inst 22634 # number of demand (read+write) MSHR misses 2676system.l2c.demand_mshr_misses::cpu0.data 21325 # number of demand (read+write) MSHR misses 2677system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133222 # number of demand (read+write) MSHR misses 2678system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses 2679system.l2c.demand_mshr_misses::cpu1.inst 3155 # number of demand (read+write) MSHR misses 2680system.l2c.demand_mshr_misses::cpu1.data 9899 # number of demand (read+write) MSHR misses 2681system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5587 # number of demand (read+write) MSHR misses 2682system.l2c.demand_mshr_misses::total 195965 # number of demand (read+write) MSHR misses 2683system.l2c.overall_mshr_misses::cpu0.dtb.walker 132 # number of overall MSHR misses 2684system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2685system.l2c.overall_mshr_misses::cpu0.inst 22634 # number of overall MSHR misses 2686system.l2c.overall_mshr_misses::cpu0.data 21325 # number of overall MSHR misses 2687system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133222 # number of overall MSHR misses 2688system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses 2689system.l2c.overall_mshr_misses::cpu1.inst 3155 # number of overall MSHR misses 2690system.l2c.overall_mshr_misses::cpu1.data 9899 # number of overall MSHR misses 2691system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5587 # number of overall MSHR misses 2692system.l2c.overall_mshr_misses::total 195965 # number of overall MSHR misses 2693system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable 2694system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32047 # number of ReadReq MSHR uncacheable 2695system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2696system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2970 # number of ReadReq MSHR uncacheable 2697system.l2c.ReadReq_mshr_uncacheable::total 39046 # number of ReadReq MSHR uncacheable 2698system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable 2699system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable 2700system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable 2701system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses 2702system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60771 # number of overall MSHR uncacheable misses 2703system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2704system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5281 # number of overall MSHR uncacheable misses 2705system.l2c.overall_mshr_uncacheable_misses::total 70081 # number of overall MSHR uncacheable misses 2706system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 791418000 # number of UpgradeReq MSHR miss cycles 2707system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 185319000 # number of UpgradeReq MSHR miss cycles 2708system.l2c.UpgradeReq_mshr_miss_latency::total 976737000 # number of UpgradeReq MSHR miss cycles 2709system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 65159500 # number of SCUpgradeReq MSHR miss cycles 2710system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97313500 # number of SCUpgradeReq MSHR miss cycles 2711system.l2c.SCUpgradeReq_mshr_miss_latency::total 162473000 # number of SCUpgradeReq MSHR miss cycles 2712system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1571751000 # number of ReadExReq MSHR miss cycles 2713system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1007765500 # number of ReadExReq MSHR miss cycles 2714system.l2c.ReadExReq_mshr_miss_latency::total 2579516500 # number of ReadExReq MSHR miss cycles 2715system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 16952000 # number of ReadSharedReq MSHR miss cycles 2716system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles 2717system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2737736000 # number of ReadSharedReq MSHR miss cycles 2718system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1251022500 # number of ReadSharedReq MSHR miss cycles 2719system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18649490279 # number of ReadSharedReq MSHR miss cycles 2720system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1326000 # number of ReadSharedReq MSHR miss cycles 2721system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 385923000 # number of ReadSharedReq MSHR miss cycles 2722system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 209372000 # number of ReadSharedReq MSHR miss cycles 2723system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 891120899 # number of ReadSharedReq MSHR miss cycles 2724system.l2c.ReadSharedReq_mshr_miss_latency::total 24143065678 # number of ReadSharedReq MSHR miss cycles 2725system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 16952000 # number of demand (read+write) MSHR miss cycles 2726system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles 2727system.l2c.demand_mshr_miss_latency::cpu0.inst 2737736000 # number of demand (read+write) MSHR miss cycles 2728system.l2c.demand_mshr_miss_latency::cpu0.data 2822773500 # number of demand (read+write) MSHR miss cycles 2729system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18649490279 # number of demand (read+write) MSHR miss cycles 2730system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1326000 # number of demand (read+write) MSHR miss cycles 2731system.l2c.demand_mshr_miss_latency::cpu1.inst 385923000 # number of demand (read+write) MSHR miss cycles 2732system.l2c.demand_mshr_miss_latency::cpu1.data 1217137500 # number of demand (read+write) MSHR miss cycles 2733system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 891120899 # number of demand (read+write) MSHR miss cycles 2734system.l2c.demand_mshr_miss_latency::total 26722582178 # number of demand (read+write) MSHR miss cycles 2735system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 16952000 # number of overall MSHR miss cycles 2736system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles 2737system.l2c.overall_mshr_miss_latency::cpu0.inst 2737736000 # number of overall MSHR miss cycles 2738system.l2c.overall_mshr_miss_latency::cpu0.data 2822773500 # number of overall MSHR miss cycles 2739system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18649490279 # number of overall MSHR miss cycles 2740system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1326000 # number of overall MSHR miss cycles 2741system.l2c.overall_mshr_miss_latency::cpu1.inst 385923000 # number of overall MSHR miss cycles 2742system.l2c.overall_mshr_miss_latency::cpu1.data 1217137500 # number of overall MSHR miss cycles 2743system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 891120899 # number of overall MSHR miss cycles 2744system.l2c.overall_mshr_miss_latency::total 26722582178 # number of overall MSHR miss cycles 2745system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles 2746system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869112000 # number of ReadReq MSHR uncacheable cycles 2747system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12102000 # number of ReadReq MSHR uncacheable cycles 2748system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 311853000 # number of ReadReq MSHR uncacheable cycles 2749system.l2c.ReadReq_mshr_uncacheable_latency::total 6636830000 # number of ReadReq MSHR uncacheable cycles 2750system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4748303000 # number of WriteReq MSHR uncacheable cycles 2751system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 194971500 # number of WriteReq MSHR uncacheable cycles 2752system.l2c.WriteReq_mshr_uncacheable_latency::total 4943274500 # number of WriteReq MSHR uncacheable cycles 2753system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles 2754system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10617415000 # number of overall MSHR uncacheable cycles 2755system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12102000 # number of overall MSHR uncacheable cycles 2756system.l2c.overall_mshr_uncacheable_latency::cpu1.data 506824500 # number of overall MSHR uncacheable cycles 2757system.l2c.overall_mshr_uncacheable_latency::total 11580104500 # number of overall MSHR uncacheable cycles 2758system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2759system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2760system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.234595 # mshr miss rate for UpgradeReq accesses 2761system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.525855 # mshr miss rate for UpgradeReq accesses 2762system.l2c.UpgradeReq_mshr_miss_rate::total 0.262248 # mshr miss rate for UpgradeReq accesses 2763system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.271438 # mshr miss rate for SCUpgradeReq accesses 2764system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.577343 # mshr miss rate for SCUpgradeReq accesses 2765system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.398302 # mshr miss rate for SCUpgradeReq accesses 2766system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.726137 # mshr miss rate for ReadExReq accesses 2767system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.861140 # mshr miss rate for ReadExReq accesses 2768system.l2c.ReadExReq_mshr_miss_rate::total 0.777106 # mshr miss rate for ReadExReq accesses 2769system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.236984 # mshr miss rate for ReadSharedReq accesses 2770system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011111 # mshr miss rate for ReadSharedReq accesses 2771system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.322518 # mshr miss rate for ReadSharedReq accesses 2772system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159360 # mshr miss rate for ReadSharedReq accesses 2773system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728463 # mshr miss rate for ReadSharedReq accesses 2774system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.113636 # mshr miss rate for ReadSharedReq accesses 2775system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.244574 # mshr miss rate for ReadSharedReq accesses 2776system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.226573 # mshr miss rate for ReadSharedReq accesses 2777system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.612677 # mshr miss rate for ReadSharedReq accesses 2778system.l2c.ReadSharedReq_mshr_miss_rate::total 0.511298 # mshr miss rate for ReadSharedReq accesses 2779system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.236984 # mshr miss rate for demand accesses 2780system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011111 # mshr miss rate for demand accesses 2781system.l2c.demand_mshr_miss_rate::cpu0.inst 0.322518 # mshr miss rate for demand accesses 2782system.l2c.demand_mshr_miss_rate::cpu0.data 0.275371 # mshr miss rate for demand accesses 2783system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728463 # mshr miss rate for demand accesses 2784system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.113636 # mshr miss rate for demand accesses 2785system.l2c.demand_mshr_miss_rate::cpu1.inst 0.244574 # mshr miss rate for demand accesses 2786system.l2c.demand_mshr_miss_rate::cpu1.data 0.590492 # mshr miss rate for demand accesses 2787system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.612677 # mshr miss rate for demand accesses 2788system.l2c.demand_mshr_miss_rate::total 0.529591 # mshr miss rate for demand accesses 2789system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.236984 # mshr miss rate for overall accesses 2790system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011111 # mshr miss rate for overall accesses 2791system.l2c.overall_mshr_miss_rate::cpu0.inst 0.322518 # mshr miss rate for overall accesses 2792system.l2c.overall_mshr_miss_rate::cpu0.data 0.275371 # mshr miss rate for overall accesses 2793system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728463 # mshr miss rate for overall accesses 2794system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.113636 # mshr miss rate for overall accesses 2795system.l2c.overall_mshr_miss_rate::cpu1.inst 0.244574 # mshr miss rate for overall accesses 2796system.l2c.overall_mshr_miss_rate::cpu1.data 0.590492 # mshr miss rate for overall accesses 2797system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.612677 # mshr miss rate for overall accesses 2798system.l2c.overall_mshr_miss_rate::total 0.529591 # mshr miss rate for overall accesses 2799system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75618.001147 # average UpgradeReq mshr miss latency 2800system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75302.316132 # average UpgradeReq mshr miss latency 2801system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75557.902065 # average UpgradeReq mshr miss latency 2802system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77386.579572 # average SCUpgradeReq mshr miss latency 2803system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76685.185185 # average SCUpgradeReq mshr miss latency 2804system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76964.945523 # average SCUpgradeReq mshr miss latency 2805system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136555.256299 # average ReadExReq mshr miss latency 2806system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121725.510327 # average ReadExReq mshr miss latency 2807system.l2c.ReadExReq_avg_mshr_miss_latency::total 130351.028349 # average ReadExReq mshr miss latency 2808system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average ReadSharedReq mshr miss latency 2809system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency 2810system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average ReadSharedReq mshr miss latency 2811system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127460.264901 # average ReadSharedReq mshr miss latency 2812system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average ReadSharedReq mshr miss latency 2813system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average ReadSharedReq mshr miss latency 2814system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average ReadSharedReq mshr miss latency 2815system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129241.975309 # average ReadSharedReq mshr miss latency 2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average ReadSharedReq mshr miss latency 2817system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137039.470064 # average ReadSharedReq mshr miss latency 2818system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average overall mshr miss latency 2819system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2820system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average overall mshr miss latency 2821system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132369.214537 # average overall mshr miss latency 2822system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average overall mshr miss latency 2823system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average overall mshr miss latency 2824system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average overall mshr miss latency 2825system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122955.601576 # average overall mshr miss latency 2826system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average overall mshr miss latency 2827system.l2c.demand_avg_mshr_miss_latency::total 136364.055714 # average overall mshr miss latency 2828system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average overall mshr miss latency 2829system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2830system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average overall mshr miss latency 2831system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132369.214537 # average overall mshr miss latency 2832system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average overall mshr miss latency 2833system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average overall mshr miss latency 2834system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average overall mshr miss latency 2835system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122955.601576 # average overall mshr miss latency 2836system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average overall mshr miss latency 2837system.l2c.overall_avg_mshr_miss_latency::total 136364.055714 # average overall mshr miss latency 2838system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency 2839system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183140.762006 # average ReadReq mshr uncacheable latency 2840system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency 2841system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105001.010101 # average ReadReq mshr uncacheable latency 2842system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169974.645290 # average ReadReq mshr uncacheable latency 2843system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165307.861022 # average WriteReq mshr uncacheable latency 2844system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84366.724362 # average WriteReq mshr uncacheable latency 2845system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159280.634767 # average WriteReq mshr uncacheable latency 2846system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency 2847system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174711.869148 # average overall mshr uncacheable latency 2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency 2849system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95971.312251 # average overall mshr uncacheable latency 2850system.l2c.overall_avg_mshr_uncacheable_latency::total 165238.859320 # average overall mshr uncacheable latency 2851system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2852system.membus.trans_dist::ReadReq 39046 # Transaction distribution 2853system.membus.trans_dist::ReadResp 215465 # Transaction distribution 2854system.membus.trans_dist::WriteReq 31035 # Transaction distribution 2855system.membus.trans_dist::WriteResp 31035 # Transaction distribution 2856system.membus.trans_dist::WritebackDirty 138266 # Transaction distribution 2857system.membus.trans_dist::CleanEvict 17702 # Transaction distribution 2858system.membus.trans_dist::UpgradeReq 74461 # Transaction distribution 2859system.membus.trans_dist::SCUpgradeReq 40765 # Transaction distribution 2860system.membus.trans_dist::UpgradeResp 15160 # Transaction distribution 2861system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 2862system.membus.trans_dist::ReadExReq 40157 # Transaction distribution 2863system.membus.trans_dist::ReadExResp 19667 # Transaction distribution 2864system.membus.trans_dist::ReadSharedReq 176419 # Transaction distribution 2865system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2866system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 2867system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) 2868system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2869system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14220 # Packet count per connected master and slave (bytes) 2870system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 679941 # Packet count per connected master and slave (bytes) 2871system.membus.pkt_count_system.l2c.mem_side::total 802135 # Packet count per connected master and slave (bytes) 2872system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108925 # Packet count per connected master and slave (bytes) 2873system.membus.pkt_count_system.iocache.mem_side::total 108925 # Packet count per connected master and slave (bytes) 2874system.membus.pkt_count::total 911060 # Packet count per connected master and slave (bytes) 2875system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) 2876system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2877system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28440 # Cumulative packet size per connected master and slave (bytes) 2878system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19320688 # Cumulative packet size per connected master and slave (bytes) 2879system.membus.pkt_size_system.l2c.mem_side::total 19513284 # Cumulative packet size per connected master and slave (bytes) 2880system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2881system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2882system.membus.pkt_size::total 21831428 # Cumulative packet size per connected master and slave (bytes) 2883system.membus.snoops 121126 # Total snoops (count) 2884system.membus.snoop_fanout::samples 594326 # Request fanout histogram 2885system.membus.snoop_fanout::mean 1 # Request fanout histogram 2886system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2887system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2888system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2889system.membus.snoop_fanout::1 594326 100.00% 100.00% # Request fanout histogram 2890system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2891system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2892system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2893system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2894system.membus.snoop_fanout::total 594326 # Request fanout histogram 2895system.membus.reqLayer0.occupancy 91340500 # Layer occupancy (ticks) 2896system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2897system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) 2898system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2899system.membus.reqLayer2.occupancy 12352499 # Layer occupancy (ticks) 2900system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2901system.membus.reqLayer5.occupancy 1009821404 # Layer occupancy (ticks) 2902system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2903system.membus.respLayer2.occupancy 1176071579 # Layer occupancy (ticks) 2904system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2905system.membus.respLayer3.occupancy 64144132 # Layer occupancy (ticks) 2906system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2907system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2908system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2909system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2910system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2911system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2912system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2913system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2914system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2915system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2916system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2917system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2918system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2919system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2920system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2921system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2922system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2923system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2924system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2925system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2926system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2927system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2928system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2929system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2930system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2931system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2932system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2933system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2934system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2935system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2936system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2937system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2938system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2939system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2940system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2941system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2942system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2943system.realview.ethernet.droppedPackets 0 # number of packets dropped 2944system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 2945system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 2946system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 2947system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 2948system.toL2Bus.snoop_filter.tot_requests 1045963 # Total number of requests made to the snoop filter. 2949system.toL2Bus.snoop_filter.hit_single_requests 564632 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2950system.toL2Bus.snoop_filter.hit_multi_requests 154673 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2951system.toL2Bus.snoop_filter.tot_snoops 20991 # Total number of snoops made to the snoop filter. 2952system.toL2Bus.snoop_filter.hit_single_snoops 19997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2953system.toL2Bus.snoop_filter.hit_multi_snoops 994 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2954system.toL2Bus.trans_dist::ReadReq 39049 # Transaction distribution 2955system.toL2Bus.trans_dist::ReadResp 502457 # Transaction distribution 2956system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution 2957system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution 2958system.toL2Bus.trans_dist::WritebackDirty 405200 # Transaction distribution 2959system.toL2Bus.trans_dist::CleanEvict 105572 # Transaction distribution 2960system.toL2Bus.trans_dist::UpgradeReq 110705 # Transaction distribution 2961system.toL2Bus.trans_dist::SCUpgradeReq 43954 # Transaction distribution 2962system.toL2Bus.trans_dist::UpgradeResp 154659 # Transaction distribution 2963system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution 2964system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 2965system.toL2Bus.trans_dist::ReadExReq 51324 # Transaction distribution 2966system.toL2Bus.trans_dist::ReadExResp 51324 # Transaction distribution 2967system.toL2Bus.trans_dist::ReadSharedReq 463423 # Transaction distribution 2968system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2969system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1306764 # Packet count per connected master and slave (bytes) 2970system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270016 # Packet count per connected master and slave (bytes) 2971system.toL2Bus.pkt_count::total 1576780 # Packet count per connected master and slave (bytes) 2972system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36870810 # Cumulative packet size per connected master and slave (bytes) 2973system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4377514 # Cumulative packet size per connected master and slave (bytes) 2974system.toL2Bus.pkt_size::total 41248324 # Cumulative packet size per connected master and slave (bytes) 2975system.toL2Bus.snoops 449455 # Total snoops (count) 2976system.toL2Bus.snoop_fanout::samples 943932 # Request fanout histogram 2977system.toL2Bus.snoop_fanout::mean 0.340597 # Request fanout histogram 2978system.toL2Bus.snoop_fanout::stdev 0.476127 # Request fanout histogram 2979system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2980system.toL2Bus.snoop_fanout::0 623426 66.05% 66.05% # Request fanout histogram 2981system.toL2Bus.snoop_fanout::1 319512 33.85% 99.89% # Request fanout histogram 2982system.toL2Bus.snoop_fanout::2 994 0.11% 100.00% # Request fanout histogram 2983system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2984system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2985system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2986system.toL2Bus.snoop_fanout::total 943932 # Request fanout histogram 2987system.toL2Bus.reqLayer0.occupancy 904213819 # Layer occupancy (ticks) 2988system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2989system.toL2Bus.snoopLayer0.occupancy 343121 # Layer occupancy (ticks) 2990system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2991system.toL2Bus.respLayer0.occupancy 693007025 # Layer occupancy (ticks) 2992system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2993system.toL2Bus.respLayer1.occupancy 215048953 # Layer occupancy (ticks) 2994system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2995 2996---------- End Simulation Statistics ---------- 2997