stats.txt revision 11138:a611a23c8cc2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.848053 # Number of seconds simulated 4sim_ticks 2848053071500 # Number of ticks simulated 5final_tick 2848053071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 153295 # Simulator instruction rate (inst/s) 8host_op_rate 185627 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3443122383 # Simulator tick rate (ticks/s) 10host_mem_usage 659004 # Number of bytes of host memory used 11host_seconds 827.17 # Real time elapsed on the host 12sim_insts 126801159 # Number of instructions simulated 13sim_ops 153545030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 8768 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1683840 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1312624 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8530944 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 199296 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 609360 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 366080 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12712960 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1683840 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 199296 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1883136 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8845504 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8863068 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 137 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26310 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 21032 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133296 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3114 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9541 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5720 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 199182 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 138211 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 142602 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 3079 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 591225 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 460885 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2995360 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 360 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 69976 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 213957 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 128537 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4463737 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 591225 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 69976 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 661201 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3105807 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 3111974 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3105807 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 3079 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 591225 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 467038 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2995360 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 360 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 69976 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 213971 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 128537 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7575711 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199182 # Number of read requests accepted 80system.physmem.writeReqs 142602 # Number of write requests accepted 81system.physmem.readBursts 199182 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 142602 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12737472 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8875904 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12712960 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8863068 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 49648 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12703 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12645 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12416 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12383 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15579 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12155 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12470 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12693 # Per bank write bursts 99system.physmem.perBankRdBursts::8 11969 # Per bank write bursts 100system.physmem.perBankRdBursts::9 11857 # Per bank write bursts 101system.physmem.perBankRdBursts::10 12504 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11838 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11708 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12391 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11950 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11762 # Per bank write bursts 107system.physmem.perBankWrBursts::0 9214 # Per bank write bursts 108system.physmem.perBankWrBursts::1 9232 # Per bank write bursts 109system.physmem.perBankWrBursts::2 9104 # Per bank write bursts 110system.physmem.perBankWrBursts::3 8883 # Per bank write bursts 111system.physmem.perBankWrBursts::4 8269 # Per bank write bursts 112system.physmem.perBankWrBursts::5 8437 # Per bank write bursts 113system.physmem.perBankWrBursts::6 8818 # Per bank write bursts 114system.physmem.perBankWrBursts::7 8777 # Per bank write bursts 115system.physmem.perBankWrBursts::8 8437 # Per bank write bursts 116system.physmem.perBankWrBursts::9 8418 # Per bank write bursts 117system.physmem.perBankWrBursts::10 9013 # Per bank write bursts 118system.physmem.perBankWrBursts::11 8780 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8383 # Per bank write bursts 120system.physmem.perBankWrBursts::13 8480 # Per bank write bursts 121system.physmem.perBankWrBursts::14 8424 # Per bank write bursts 122system.physmem.perBankWrBursts::15 8017 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 125system.physmem.totGap 2848052462500 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 552 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 198602 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 138211 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 87578 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 61104 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 11612 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9452 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7822 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6360 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5253 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4675 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3805 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 696 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 143 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2725 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3230 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 4408 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4909 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6431 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 7731 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7825 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8951 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 9319 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 9452 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 10926 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 9238 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 9075 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 10229 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8920 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7997 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7566 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 103 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 99 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 58 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 89100 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 242.573648 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 137.731983 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 302.151175 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 46893 52.63% 52.63% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17637 19.79% 72.42% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6363 7.14% 79.57% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3624 4.07% 83.63% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2948 3.31% 86.94% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1436 1.61% 88.55% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 938 1.05% 89.61% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 975 1.09% 90.70% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8286 9.30% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 89100 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6864 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 28.995047 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 543.916897 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6863 99.99% 99.99% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::total 6864 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6864 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 20.204837 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 18.711823 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 11.958888 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-19 5637 82.12% 82.12% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20-23 489 7.12% 89.25% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::24-27 82 1.19% 90.44% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::28-31 154 2.24% 92.69% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::32-35 37 0.54% 93.23% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::36-39 124 1.81% 95.03% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::40-43 47 0.68% 95.72% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::44-47 16 0.23% 95.95% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::48-51 21 0.31% 96.26% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::52-55 19 0.28% 96.53% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::56-59 6 0.09% 96.62% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::60-63 10 0.15% 96.77% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::64-67 153 2.23% 98.99% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::68-71 1 0.01% 99.01% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::72-75 5 0.07% 99.08% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::76-79 30 0.44% 99.52% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::80-83 4 0.06% 99.58% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::88-91 2 0.03% 99.62% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::116-119 1 0.01% 99.71% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::128-131 11 0.16% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::132-135 1 0.01% 99.88% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::144-147 1 0.01% 99.94% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::total 6864 # Writes before turning the bus around for reads 289system.physmem.totQLat 5502163905 # Total ticks spent queuing 290system.physmem.totMemAccLat 9233845155 # Total ticks spent from burst creation until serviced by the DRAM 291system.physmem.totBusLat 995115000 # Total ticks spent in databus transfers 292system.physmem.avgQLat 27645.87 # Average queueing delay per DRAM burst 293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 294system.physmem.avgMemAccLat 46395.87 # Average memory access latency per DRAM burst 295system.physmem.avgRdBW 4.47 # Average DRAM read bandwidth in MiByte/s 296system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s 297system.physmem.avgRdBWSys 4.46 # Average system read bandwidth in MiByte/s 298system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s 299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 300system.physmem.busUtil 0.06 # Data bus utilization in percentage 301system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 303system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 304system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing 305system.physmem.readRowHits 165564 # Number of row buffer hits during reads 306system.physmem.writeRowHits 83044 # Number of row buffer hits during writes 307system.physmem.readRowHitRate 83.19 # Row buffer hit rate for reads 308system.physmem.writeRowHitRate 59.87 # Row buffer hit rate for writes 309system.physmem.avgGap 8332901.66 # Average gap between requests 310system.physmem.pageHitRate 73.61 # Row buffer hit rate, read and write combined 311system.physmem_0.actEnergy 347056920 # Energy for activate commands per rank (pJ) 312system.physmem_0.preEnergy 189366375 # Energy for precharge commands per rank (pJ) 313system.physmem_0.readEnergy 803743200 # Energy for read commands per rank (pJ) 314system.physmem_0.writeEnergy 458356320 # Energy for write commands per rank (pJ) 315system.physmem_0.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ) 316system.physmem_0.actBackEnergy 84074155830 # Energy for active background per rank (pJ) 317system.physmem_0.preBackEnergy 1635078931500 # Energy for precharge background per rank (pJ) 318system.physmem_0.totalEnergy 1906972178385 # Total energy per rank (pJ) 319system.physmem_0.averagePower 669.571882 # Core power per rank (mW) 320system.physmem_0.memoryStateTime::IDLE 2719967809945 # Time in different power states 321system.physmem_0.memoryStateTime::REF 95102540000 # Time in different power states 322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 323system.physmem_0.memoryStateTime::ACT 32976648805 # Time in different power states 324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ) 326system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ) 327system.physmem_1.readEnergy 748628400 # Energy for read commands per rank (pJ) 328system.physmem_1.writeEnergy 440328960 # Energy for write commands per rank (pJ) 329system.physmem_1.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ) 330system.physmem_1.actBackEnergy 83156024340 # Energy for active background per rank (pJ) 331system.physmem_1.preBackEnergy 1635884310000 # Energy for precharge background per rank (pJ) 332system.physmem_1.totalEnergy 1906754570145 # Total energy per rank (pJ) 333system.physmem_1.averagePower 669.495475 # Core power per rank (mW) 334system.physmem_1.memoryStateTime::IDLE 2721316836638 # Time in different power states 335system.physmem_1.memoryStateTime::REF 95102540000 # Time in different power states 336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 337system.physmem_1.memoryStateTime::ACT 31633548862 # Time in different power states 338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 339system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 345system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 346system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 348system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 349system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 357system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 358system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 359system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 360system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 361system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 362system.cf0.dma_write_txs 631 # Number of DMA write transactions. 363system.cpu0.branchPred.lookups 36422708 # Number of BP lookups 364system.cpu0.branchPred.condPredicted 17757542 # Number of conditional branches predicted 365system.cpu0.branchPred.condIncorrect 1699668 # Number of conditional branches incorrect 366system.cpu0.branchPred.BTBLookups 20591819 # Number of BTB lookups 367system.cpu0.branchPred.BTBHits 15078708 # Number of BTB hits 368system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 369system.cpu0.branchPred.BTBHitPct 73.226693 # BTB Hit Percentage 370system.cpu0.branchPred.usedRAS 11344544 # Number of times the RAS was used to get a target. 371system.cpu0.branchPred.RASInCorrect 821497 # Number of incorrect RAS predictions. 372system.cpu_clk_domain.clock 500 # Clock period in ticks 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 382system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 383system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 384system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 385system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 386system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 388system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 389system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 390system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 391system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 392system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 394system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 402system.cpu0.dtb.walker.walks 72997 # Table walker walks requested 403system.cpu0.dtb.walker.walksShort 72997 # Table walker walks initiated with short descriptors 404system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47155 # Level at which table walker walks with short descriptors terminate 405system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25842 # Level at which table walker walks with short descriptors terminate 406system.cpu0.dtb.walker.walkWaitTime::samples 72997 # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkWaitTime::0 72997 100.00% 100.00% # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::total 72997 # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkCompletionTime::samples 7509 # Table walker service (enqueue to completion) latency 410system.cpu0.dtb.walker.walkCompletionTime::mean 10509.122386 # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::gmean 9271.690184 # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::stdev 8241.046102 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::0-32767 7465 99.41% 99.41% # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::32768-65535 36 0.48% 99.89% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::total 7509 # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walksPending::samples 581566000 # Table walker pending requests distribution 419system.cpu0.dtb.walker.walksPending::0 581566000 100.00% 100.00% # Table walker pending requests distribution 420system.cpu0.dtb.walker.walksPending::total 581566000 # Table walker pending requests distribution 421system.cpu0.dtb.walker.walkPageSizes::4K 5843 77.81% 77.81% # Table walker page sizes translated 422system.cpu0.dtb.walker.walkPageSizes::1M 1666 22.19% 100.00% # Table walker page sizes translated 423system.cpu0.dtb.walker.walkPageSizes::total 7509 # Table walker page sizes translated 424system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72997 # Table walker requests started/completed, data/inst 425system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 426system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72997 # Table walker requests started/completed, data/inst 427system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7509 # Table walker requests started/completed, data/inst 428system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7509 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin::total 80506 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.inst_hits 0 # ITB inst hits 432system.cpu0.dtb.inst_misses 0 # ITB inst misses 433system.cpu0.dtb.read_hits 24918355 # DTB read hits 434system.cpu0.dtb.read_misses 66392 # DTB read misses 435system.cpu0.dtb.write_hits 18544526 # DTB write hits 436system.cpu0.dtb.write_misses 6605 # DTB write misses 437system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 438system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 439system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 440system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 441system.cpu0.dtb.flush_entries 3803 # Number of entries that have been flushed from TLB 442system.cpu0.dtb.align_faults 1293 # Number of TLB faults due to alignment restrictions 443system.cpu0.dtb.prefetch_faults 2019 # Number of TLB faults due to prefetch 444system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 445system.cpu0.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions 446system.cpu0.dtb.read_accesses 24984747 # DTB read accesses 447system.cpu0.dtb.write_accesses 18551131 # DTB write accesses 448system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 449system.cpu0.dtb.hits 43462881 # DTB hits 450system.cpu0.dtb.misses 72997 # DTB misses 451system.cpu0.dtb.accesses 43535878 # DTB accesses 452system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 461system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 462system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 463system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 464system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 465system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 466system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 467system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 468system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 469system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 470system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 471system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 472system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 473system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 475system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 476system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 477system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 478system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 479system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 480system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 481system.cpu0.itb.walker.walks 4165 # Table walker walks requested 482system.cpu0.itb.walker.walksShort 4165 # Table walker walks initiated with short descriptors 483system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate 484system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3841 # Level at which table walker walks with short descriptors terminate 485system.cpu0.itb.walker.walkWaitTime::samples 4165 # Table walker wait (enqueue to first request) latency 486system.cpu0.itb.walker.walkWaitTime::0 4165 100.00% 100.00% # Table walker wait (enqueue to first request) latency 487system.cpu0.itb.walker.walkWaitTime::total 4165 # Table walker wait (enqueue to first request) latency 488system.cpu0.itb.walker.walkCompletionTime::samples 2676 # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walkCompletionTime::mean 10991.778774 # Table walker service (enqueue to completion) latency 490system.cpu0.itb.walker.walkCompletionTime::gmean 9686.198014 # Table walker service (enqueue to completion) latency 491system.cpu0.itb.walker.walkCompletionTime::stdev 6109.891448 # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::0-16383 2598 97.09% 97.09% # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::16384-32767 50 1.87% 98.95% # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::32768-49151 27 1.01% 99.96% # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::total 2676 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walksPending::samples 580856500 # Table walker pending requests distribution 498system.cpu0.itb.walker.walksPending::0 580856500 100.00% 100.00% # Table walker pending requests distribution 499system.cpu0.itb.walker.walksPending::total 580856500 # Table walker pending requests distribution 500system.cpu0.itb.walker.walkPageSizes::4K 2357 88.08% 88.08% # Table walker page sizes translated 501system.cpu0.itb.walker.walkPageSizes::1M 319 11.92% 100.00% # Table walker page sizes translated 502system.cpu0.itb.walker.walkPageSizes::total 2676 # Table walker page sizes translated 503system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 504system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4165 # Table walker requests started/completed, data/inst 505system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4165 # Table walker requests started/completed, data/inst 506system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 507system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2676 # Table walker requests started/completed, data/inst 508system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2676 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst 510system.cpu0.itb.inst_hits 71531107 # ITB inst hits 511system.cpu0.itb.inst_misses 4165 # ITB inst misses 512system.cpu0.itb.read_hits 0 # DTB read hits 513system.cpu0.itb.read_misses 0 # DTB read misses 514system.cpu0.itb.write_hits 0 # DTB write hits 515system.cpu0.itb.write_misses 0 # DTB write misses 516system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 517system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 518system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 519system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 520system.cpu0.itb.flush_entries 2451 # Number of entries that have been flushed from TLB 521system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 522system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 523system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 524system.cpu0.itb.perms_faults 8112 # Number of TLB faults due to permissions restrictions 525system.cpu0.itb.read_accesses 0 # DTB read accesses 526system.cpu0.itb.write_accesses 0 # DTB write accesses 527system.cpu0.itb.inst_accesses 71535272 # ITB inst accesses 528system.cpu0.itb.hits 71531107 # DTB hits 529system.cpu0.itb.misses 4165 # DTB misses 530system.cpu0.itb.accesses 71535272 # DTB accesses 531system.cpu0.numCycles 246249018 # number of cpu cycles simulated 532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 534system.cpu0.committedInsts 113090684 # Number of instructions committed 535system.cpu0.committedOps 136745700 # Number of ops (including micro ops) committed 536system.cpu0.discardedOps 8942808 # Number of ops (including micro ops) which were discarded before commit 537system.cpu0.numFetchSuspends 1853 # Number of times Execute suspended instruction fetching 538system.cpu0.quiesceCycles 5449882320 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 539system.cpu0.cpi 2.177447 # CPI: cycles per instruction 540system.cpu0.ipc 0.459253 # IPC: instructions per cycle 541system.cpu0.kern.inst.arm 0 # number of arm instructions executed 542system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed 543system.cpu0.tickCycles 199226503 # Number of cycles that the object actually ticked 544system.cpu0.idleCycles 47022515 # Total number of cycles that the object has spent stopped 545system.cpu0.dcache.tags.replacements 754267 # number of replacements 546system.cpu0.dcache.tags.tagsinuse 495.799422 # Cycle average of tags in use 547system.cpu0.dcache.tags.total_refs 41868735 # Total number of references to valid blocks. 548system.cpu0.dcache.tags.sampled_refs 754779 # Sample count of references to valid blocks. 549system.cpu0.dcache.tags.avg_refs 55.471516 # Average number of references to valid blocks. 550system.cpu0.dcache.tags.warmup_cycle 600230000 # Cycle when the warmup percentage was hit. 551system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.799422 # Average occupied blocks per requestor 552system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968358 # Average percentage of cache occupancy 553system.cpu0.dcache.tags.occ_percent::total 0.968358 # Average percentage of cache occupancy 554system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 555system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 556system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 557system.cpu0.dcache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id 558system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 559system.cpu0.dcache.tags.tag_accesses 86874809 # Number of tag accesses 560system.cpu0.dcache.tags.data_accesses 86874809 # Number of data accesses 561system.cpu0.dcache.ReadReq_hits::cpu0.data 23308542 # number of ReadReq hits 562system.cpu0.dcache.ReadReq_hits::total 23308542 # number of ReadReq hits 563system.cpu0.dcache.WriteReq_hits::cpu0.data 17374131 # number of WriteReq hits 564system.cpu0.dcache.WriteReq_hits::total 17374131 # number of WriteReq hits 565system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329905 # number of SoftPFReq hits 566system.cpu0.dcache.SoftPFReq_hits::total 329905 # number of SoftPFReq hits 567system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374910 # number of LoadLockedReq hits 568system.cpu0.dcache.LoadLockedReq_hits::total 374910 # number of LoadLockedReq hits 569system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371257 # number of StoreCondReq hits 570system.cpu0.dcache.StoreCondReq_hits::total 371257 # number of StoreCondReq hits 571system.cpu0.dcache.demand_hits::cpu0.data 40682673 # number of demand (read+write) hits 572system.cpu0.dcache.demand_hits::total 40682673 # number of demand (read+write) hits 573system.cpu0.dcache.overall_hits::cpu0.data 41012578 # number of overall hits 574system.cpu0.dcache.overall_hits::total 41012578 # number of overall hits 575system.cpu0.dcache.ReadReq_misses::cpu0.data 490349 # number of ReadReq misses 576system.cpu0.dcache.ReadReq_misses::total 490349 # number of ReadReq misses 577system.cpu0.dcache.WriteReq_misses::cpu0.data 600389 # number of WriteReq misses 578system.cpu0.dcache.WriteReq_misses::total 600389 # number of WriteReq misses 579system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141605 # number of SoftPFReq misses 580system.cpu0.dcache.SoftPFReq_misses::total 141605 # number of SoftPFReq misses 581system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21484 # number of LoadLockedReq misses 582system.cpu0.dcache.LoadLockedReq_misses::total 21484 # number of LoadLockedReq misses 583system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20155 # number of StoreCondReq misses 584system.cpu0.dcache.StoreCondReq_misses::total 20155 # number of StoreCondReq misses 585system.cpu0.dcache.demand_misses::cpu0.data 1090738 # number of demand (read+write) misses 586system.cpu0.dcache.demand_misses::total 1090738 # number of demand (read+write) misses 587system.cpu0.dcache.overall_misses::cpu0.data 1232343 # number of overall misses 588system.cpu0.dcache.overall_misses::total 1232343 # number of overall misses 589system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6919620500 # number of ReadReq miss cycles 590system.cpu0.dcache.ReadReq_miss_latency::total 6919620500 # number of ReadReq miss cycles 591system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11358969500 # number of WriteReq miss cycles 592system.cpu0.dcache.WriteReq_miss_latency::total 11358969500 # number of WriteReq miss cycles 593system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328836500 # number of LoadLockedReq miss cycles 594system.cpu0.dcache.LoadLockedReq_miss_latency::total 328836500 # number of LoadLockedReq miss cycles 595system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472700000 # number of StoreCondReq miss cycles 596system.cpu0.dcache.StoreCondReq_miss_latency::total 472700000 # number of StoreCondReq miss cycles 597system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 403000 # number of StoreCondFailReq miss cycles 598system.cpu0.dcache.StoreCondFailReq_miss_latency::total 403000 # number of StoreCondFailReq miss cycles 599system.cpu0.dcache.demand_miss_latency::cpu0.data 18278590000 # number of demand (read+write) miss cycles 600system.cpu0.dcache.demand_miss_latency::total 18278590000 # number of demand (read+write) miss cycles 601system.cpu0.dcache.overall_miss_latency::cpu0.data 18278590000 # number of overall miss cycles 602system.cpu0.dcache.overall_miss_latency::total 18278590000 # number of overall miss cycles 603system.cpu0.dcache.ReadReq_accesses::cpu0.data 23798891 # number of ReadReq accesses(hits+misses) 604system.cpu0.dcache.ReadReq_accesses::total 23798891 # number of ReadReq accesses(hits+misses) 605system.cpu0.dcache.WriteReq_accesses::cpu0.data 17974520 # number of WriteReq accesses(hits+misses) 606system.cpu0.dcache.WriteReq_accesses::total 17974520 # number of WriteReq accesses(hits+misses) 607system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471510 # number of SoftPFReq accesses(hits+misses) 608system.cpu0.dcache.SoftPFReq_accesses::total 471510 # number of SoftPFReq accesses(hits+misses) 609system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396394 # number of LoadLockedReq accesses(hits+misses) 610system.cpu0.dcache.LoadLockedReq_accesses::total 396394 # number of LoadLockedReq accesses(hits+misses) 611system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391412 # number of StoreCondReq accesses(hits+misses) 612system.cpu0.dcache.StoreCondReq_accesses::total 391412 # number of StoreCondReq accesses(hits+misses) 613system.cpu0.dcache.demand_accesses::cpu0.data 41773411 # number of demand (read+write) accesses 614system.cpu0.dcache.demand_accesses::total 41773411 # number of demand (read+write) accesses 615system.cpu0.dcache.overall_accesses::cpu0.data 42244921 # number of overall (read+write) accesses 616system.cpu0.dcache.overall_accesses::total 42244921 # number of overall (read+write) accesses 617system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020604 # miss rate for ReadReq accesses 618system.cpu0.dcache.ReadReq_miss_rate::total 0.020604 # miss rate for ReadReq accesses 619system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033402 # miss rate for WriteReq accesses 620system.cpu0.dcache.WriteReq_miss_rate::total 0.033402 # miss rate for WriteReq accesses 621system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300322 # miss rate for SoftPFReq accesses 622system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300322 # miss rate for SoftPFReq accesses 623system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054199 # miss rate for LoadLockedReq accesses 624system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054199 # miss rate for LoadLockedReq accesses 625system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051493 # miss rate for StoreCondReq accesses 626system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051493 # miss rate for StoreCondReq accesses 627system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026111 # miss rate for demand accesses 628system.cpu0.dcache.demand_miss_rate::total 0.026111 # miss rate for demand accesses 629system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029171 # miss rate for overall accesses 630system.cpu0.dcache.overall_miss_rate::total 0.029171 # miss rate for overall accesses 631system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14111.623558 # average ReadReq miss latency 632system.cpu0.dcache.ReadReq_avg_miss_latency::total 14111.623558 # average ReadReq miss latency 633system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18919.349788 # average WriteReq miss latency 634system.cpu0.dcache.WriteReq_avg_miss_latency::total 18919.349788 # average WriteReq miss latency 635system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15306.111525 # average LoadLockedReq miss latency 636system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15306.111525 # average LoadLockedReq miss latency 637system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23453.237410 # average StoreCondReq miss latency 638system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23453.237410 # average StoreCondReq miss latency 639system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 640system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 641system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16758.002380 # average overall miss latency 642system.cpu0.dcache.demand_avg_miss_latency::total 16758.002380 # average overall miss latency 643system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14832.388385 # average overall miss latency 644system.cpu0.dcache.overall_avg_miss_latency::total 14832.388385 # average overall miss latency 645system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 651system.cpu0.dcache.fast_writes 0 # number of fast writes performed 652system.cpu0.dcache.cache_copies 0 # number of cache copies performed 653system.cpu0.dcache.writebacks::writebacks 540480 # number of writebacks 654system.cpu0.dcache.writebacks::total 540480 # number of writebacks 655system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 76076 # number of ReadReq MSHR hits 656system.cpu0.dcache.ReadReq_mshr_hits::total 76076 # number of ReadReq MSHR hits 657system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 264589 # number of WriteReq MSHR hits 658system.cpu0.dcache.WriteReq_mshr_hits::total 264589 # number of WriteReq MSHR hits 659system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14754 # number of LoadLockedReq MSHR hits 660system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14754 # number of LoadLockedReq MSHR hits 661system.cpu0.dcache.demand_mshr_hits::cpu0.data 340665 # number of demand (read+write) MSHR hits 662system.cpu0.dcache.demand_mshr_hits::total 340665 # number of demand (read+write) MSHR hits 663system.cpu0.dcache.overall_mshr_hits::cpu0.data 340665 # number of overall MSHR hits 664system.cpu0.dcache.overall_mshr_hits::total 340665 # number of overall MSHR hits 665system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414273 # number of ReadReq MSHR misses 666system.cpu0.dcache.ReadReq_mshr_misses::total 414273 # number of ReadReq MSHR misses 667system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335800 # number of WriteReq MSHR misses 668system.cpu0.dcache.WriteReq_mshr_misses::total 335800 # number of WriteReq MSHR misses 669system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107967 # number of SoftPFReq MSHR misses 670system.cpu0.dcache.SoftPFReq_mshr_misses::total 107967 # number of SoftPFReq MSHR misses 671system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6730 # number of LoadLockedReq MSHR misses 672system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6730 # number of LoadLockedReq MSHR misses 673system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20155 # number of StoreCondReq MSHR misses 674system.cpu0.dcache.StoreCondReq_mshr_misses::total 20155 # number of StoreCondReq MSHR misses 675system.cpu0.dcache.demand_mshr_misses::cpu0.data 750073 # number of demand (read+write) MSHR misses 676system.cpu0.dcache.demand_mshr_misses::total 750073 # number of demand (read+write) MSHR misses 677system.cpu0.dcache.overall_mshr_misses::cpu0.data 858040 # number of overall MSHR misses 678system.cpu0.dcache.overall_mshr_misses::total 858040 # number of overall MSHR misses 679system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable 680system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32040 # number of ReadReq MSHR uncacheable 681system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable 682system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable 683system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses 684system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60762 # number of overall MSHR uncacheable misses 685system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5238286000 # number of ReadReq MSHR miss cycles 686system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5238286000 # number of ReadReq MSHR miss cycles 687system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6456534000 # number of WriteReq MSHR miss cycles 688system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6456534000 # number of WriteReq MSHR miss cycles 689system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1810830000 # number of SoftPFReq MSHR miss cycles 690system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810830000 # number of SoftPFReq MSHR miss cycles 691system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104761500 # number of LoadLockedReq MSHR miss cycles 692system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104761500 # number of LoadLockedReq MSHR miss cycles 693system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452552000 # number of StoreCondReq MSHR miss cycles 694system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452552000 # number of StoreCondReq MSHR miss cycles 695system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 396000 # number of StoreCondFailReq MSHR miss cycles 696system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 396000 # number of StoreCondFailReq MSHR miss cycles 697system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11694820000 # number of demand (read+write) MSHR miss cycles 698system.cpu0.dcache.demand_mshr_miss_latency::total 11694820000 # number of demand (read+write) MSHR miss cycles 699system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13505650000 # number of overall MSHR miss cycles 700system.cpu0.dcache.overall_mshr_miss_latency::total 13505650000 # number of overall MSHR miss cycles 701system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6348331500 # number of ReadReq MSHR uncacheable cycles 702system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6348331500 # number of ReadReq MSHR uncacheable cycles 703system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5156547500 # number of WriteReq MSHR uncacheable cycles 704system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5156547500 # number of WriteReq MSHR uncacheable cycles 705system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11504879000 # number of overall MSHR uncacheable cycles 706system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11504879000 # number of overall MSHR uncacheable cycles 707system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017407 # mshr miss rate for ReadReq accesses 708system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017407 # mshr miss rate for ReadReq accesses 709system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018682 # mshr miss rate for WriteReq accesses 710system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018682 # mshr miss rate for WriteReq accesses 711system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228981 # mshr miss rate for SoftPFReq accesses 712system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228981 # mshr miss rate for SoftPFReq accesses 713system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016978 # mshr miss rate for LoadLockedReq accesses 714system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016978 # mshr miss rate for LoadLockedReq accesses 715system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051493 # mshr miss rate for StoreCondReq accesses 716system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051493 # mshr miss rate for StoreCondReq accesses 717system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017956 # mshr miss rate for demand accesses 718system.cpu0.dcache.demand_mshr_miss_rate::total 0.017956 # mshr miss rate for demand accesses 719system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020311 # mshr miss rate for overall accesses 720system.cpu0.dcache.overall_mshr_miss_rate::total 0.020311 # mshr miss rate for overall accesses 721system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12644.526677 # average ReadReq mshr miss latency 722system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12644.526677 # average ReadReq mshr miss latency 723system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19227.319833 # average WriteReq mshr miss latency 724system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19227.319833 # average WriteReq mshr miss latency 725system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16772.069243 # average SoftPFReq mshr miss latency 726system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16772.069243 # average SoftPFReq mshr miss latency 727system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15566.344725 # average LoadLockedReq mshr miss latency 728system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15566.344725 # average LoadLockedReq mshr miss latency 729system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.584718 # average StoreCondReq mshr miss latency 730system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.584718 # average StoreCondReq mshr miss latency 731system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 732system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 733system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15591.575753 # average overall mshr miss latency 734system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15591.575753 # average overall mshr miss latency 735system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15740.117011 # average overall mshr miss latency 736system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15740.117011 # average overall mshr miss latency 737system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198137.687266 # average ReadReq mshr uncacheable latency 738system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198137.687266 # average ReadReq mshr uncacheable latency 739system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179533.023466 # average WriteReq mshr uncacheable latency 740system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179533.023466 # average WriteReq mshr uncacheable latency 741system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189343.323130 # average overall mshr uncacheable latency 742system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189343.323130 # average overall mshr uncacheable latency 743system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 744system.cpu0.icache.tags.replacements 2044285 # number of replacements 745system.cpu0.icache.tags.tagsinuse 511.729271 # Cycle average of tags in use 746system.cpu0.icache.tags.total_refs 69477789 # Total number of references to valid blocks. 747system.cpu0.icache.tags.sampled_refs 2044797 # Sample count of references to valid blocks. 748system.cpu0.icache.tags.avg_refs 33.977842 # Average number of references to valid blocks. 749system.cpu0.icache.tags.warmup_cycle 6924011000 # Cycle when the warmup percentage was hit. 750system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.729271 # Average occupied blocks per requestor 751system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999471 # Average percentage of cache occupancy 752system.cpu0.icache.tags.occ_percent::total 0.999471 # Average percentage of cache occupancy 753system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 754system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 755system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id 756system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id 757system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 758system.cpu0.icache.tags.tag_accesses 145090031 # Number of tag accesses 759system.cpu0.icache.tags.data_accesses 145090031 # Number of data accesses 760system.cpu0.icache.ReadReq_hits::cpu0.inst 69477789 # number of ReadReq hits 761system.cpu0.icache.ReadReq_hits::total 69477789 # number of ReadReq hits 762system.cpu0.icache.demand_hits::cpu0.inst 69477789 # number of demand (read+write) hits 763system.cpu0.icache.demand_hits::total 69477789 # number of demand (read+write) hits 764system.cpu0.icache.overall_hits::cpu0.inst 69477789 # number of overall hits 765system.cpu0.icache.overall_hits::total 69477789 # number of overall hits 766system.cpu0.icache.ReadReq_misses::cpu0.inst 2044818 # number of ReadReq misses 767system.cpu0.icache.ReadReq_misses::total 2044818 # number of ReadReq misses 768system.cpu0.icache.demand_misses::cpu0.inst 2044818 # number of demand (read+write) misses 769system.cpu0.icache.demand_misses::total 2044818 # number of demand (read+write) misses 770system.cpu0.icache.overall_misses::cpu0.inst 2044818 # number of overall misses 771system.cpu0.icache.overall_misses::total 2044818 # number of overall misses 772system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20517256500 # number of ReadReq miss cycles 773system.cpu0.icache.ReadReq_miss_latency::total 20517256500 # number of ReadReq miss cycles 774system.cpu0.icache.demand_miss_latency::cpu0.inst 20517256500 # number of demand (read+write) miss cycles 775system.cpu0.icache.demand_miss_latency::total 20517256500 # number of demand (read+write) miss cycles 776system.cpu0.icache.overall_miss_latency::cpu0.inst 20517256500 # number of overall miss cycles 777system.cpu0.icache.overall_miss_latency::total 20517256500 # number of overall miss cycles 778system.cpu0.icache.ReadReq_accesses::cpu0.inst 71522607 # number of ReadReq accesses(hits+misses) 779system.cpu0.icache.ReadReq_accesses::total 71522607 # number of ReadReq accesses(hits+misses) 780system.cpu0.icache.demand_accesses::cpu0.inst 71522607 # number of demand (read+write) accesses 781system.cpu0.icache.demand_accesses::total 71522607 # number of demand (read+write) accesses 782system.cpu0.icache.overall_accesses::cpu0.inst 71522607 # number of overall (read+write) accesses 783system.cpu0.icache.overall_accesses::total 71522607 # number of overall (read+write) accesses 784system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028590 # miss rate for ReadReq accesses 785system.cpu0.icache.ReadReq_miss_rate::total 0.028590 # miss rate for ReadReq accesses 786system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028590 # miss rate for demand accesses 787system.cpu0.icache.demand_miss_rate::total 0.028590 # miss rate for demand accesses 788system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028590 # miss rate for overall accesses 789system.cpu0.icache.overall_miss_rate::total 0.028590 # miss rate for overall accesses 790system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10033.781246 # average ReadReq miss latency 791system.cpu0.icache.ReadReq_avg_miss_latency::total 10033.781246 # average ReadReq miss latency 792system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10033.781246 # average overall miss latency 793system.cpu0.icache.demand_avg_miss_latency::total 10033.781246 # average overall miss latency 794system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10033.781246 # average overall miss latency 795system.cpu0.icache.overall_avg_miss_latency::total 10033.781246 # average overall miss latency 796system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 797system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 798system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 799system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 800system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 801system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 802system.cpu0.icache.fast_writes 0 # number of fast writes performed 803system.cpu0.icache.cache_copies 0 # number of cache copies performed 804system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2044818 # number of ReadReq MSHR misses 805system.cpu0.icache.ReadReq_mshr_misses::total 2044818 # number of ReadReq MSHR misses 806system.cpu0.icache.demand_mshr_misses::cpu0.inst 2044818 # number of demand (read+write) MSHR misses 807system.cpu0.icache.demand_mshr_misses::total 2044818 # number of demand (read+write) MSHR misses 808system.cpu0.icache.overall_mshr_misses::cpu0.inst 2044818 # number of overall MSHR misses 809system.cpu0.icache.overall_mshr_misses::total 2044818 # number of overall MSHR misses 810system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable 811system.cpu0.icache.ReadReq_mshr_uncacheable::total 3915 # number of ReadReq MSHR uncacheable 812system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses 813system.cpu0.icache.overall_mshr_uncacheable_misses::total 3915 # number of overall MSHR uncacheable misses 814system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19494848000 # number of ReadReq MSHR miss cycles 815system.cpu0.icache.ReadReq_mshr_miss_latency::total 19494848000 # number of ReadReq MSHR miss cycles 816system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19494848000 # number of demand (read+write) MSHR miss cycles 817system.cpu0.icache.demand_mshr_miss_latency::total 19494848000 # number of demand (read+write) MSHR miss cycles 818system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19494848000 # number of overall MSHR miss cycles 819system.cpu0.icache.overall_mshr_miss_latency::total 19494848000 # number of overall MSHR miss cycles 820system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557217500 # number of ReadReq MSHR uncacheable cycles 821system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557217500 # number of ReadReq MSHR uncacheable cycles 822system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557217500 # number of overall MSHR uncacheable cycles 823system.cpu0.icache.overall_mshr_uncacheable_latency::total 557217500 # number of overall MSHR uncacheable cycles 824system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for ReadReq accesses 825system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028590 # mshr miss rate for ReadReq accesses 826system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for demand accesses 827system.cpu0.icache.demand_mshr_miss_rate::total 0.028590 # mshr miss rate for demand accesses 828system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for overall accesses 829system.cpu0.icache.overall_mshr_miss_rate::total 0.028590 # mshr miss rate for overall accesses 830system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average ReadReq mshr miss latency 831system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9533.781491 # average ReadReq mshr miss latency 832system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average overall mshr miss latency 833system.cpu0.icache.demand_avg_mshr_miss_latency::total 9533.781491 # average overall mshr miss latency 834system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average overall mshr miss latency 835system.cpu0.icache.overall_avg_mshr_miss_latency::total 9533.781491 # average overall mshr miss latency 836system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average ReadReq mshr uncacheable latency 837system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142328.863346 # average ReadReq mshr uncacheable latency 838system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average overall mshr uncacheable latency 839system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142328.863346 # average overall mshr uncacheable latency 840system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 841system.cpu0.l2cache.prefetcher.num_hwpf_issued 1923323 # number of hwpf issued 842system.cpu0.l2cache.prefetcher.pfIdentified 1923513 # number of prefetch candidates identified 843system.cpu0.l2cache.prefetcher.pfBufferHit 165 # number of redundant prefetches already in prefetch queue 844system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 845system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 846system.cpu0.l2cache.prefetcher.pfSpanPage 243791 # number of prefetches not generated due to page crossing 847system.cpu0.l2cache.tags.replacements 310417 # number of replacements 848system.cpu0.l2cache.tags.tagsinuse 16162.197478 # Cycle average of tags in use 849system.cpu0.l2cache.tags.total_refs 5245257 # Total number of references to valid blocks. 850system.cpu0.l2cache.tags.sampled_refs 326630 # Sample count of references to valid blocks. 851system.cpu0.l2cache.tags.avg_refs 16.058712 # Average number of references to valid blocks. 852system.cpu0.l2cache.tags.warmup_cycle 2827807181000 # Cycle when the warmup percentage was hit. 853system.cpu0.l2cache.tags.occ_blocks::writebacks 6560.031691 # Average occupied blocks per requestor 854system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 62.859334 # Average occupied blocks per requestor 855system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055204 # Average occupied blocks per requestor 856system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5926.735945 # Average occupied blocks per requestor 857system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1926.535864 # Average occupied blocks per requestor 858system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1685.979439 # Average occupied blocks per requestor 859system.cpu0.l2cache.tags.occ_percent::writebacks 0.400393 # Average percentage of cache occupancy 860system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003837 # Average percentage of cache occupancy 861system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy 862system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361739 # Average percentage of cache occupancy 863system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.117586 # Average percentage of cache occupancy 864system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.102904 # Average percentage of cache occupancy 865system.cpu0.l2cache.tags.occ_percent::total 0.986462 # Average percentage of cache occupancy 866system.cpu0.l2cache.tags.occ_task_id_blocks::1022 984 # Occupied blocks per task id 867system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 868system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15223 # Occupied blocks per task id 869system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 870system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 330 # Occupied blocks per task id 871system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 428 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 218 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 874system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 875system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4188 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8533 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id 881system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.060059 # Percentage of cache occupancy per task id 882system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 883system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.929138 # Percentage of cache occupancy per task id 884system.cpu0.l2cache.tags.tag_accesses 93116780 # Number of tag accesses 885system.cpu0.l2cache.tags.data_accesses 93116780 # Number of data accesses 886system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 86201 # number of ReadReq hits 887system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4393 # number of ReadReq hits 888system.cpu0.l2cache.ReadReq_hits::total 90594 # number of ReadReq hits 889system.cpu0.l2cache.Writeback_hits::writebacks 540479 # number of Writeback hits 890system.cpu0.l2cache.Writeback_hits::total 540479 # number of Writeback hits 891system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28758 # number of UpgradeReq hits 892system.cpu0.l2cache.UpgradeReq_hits::total 28758 # number of UpgradeReq hits 893system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2008 # number of SCUpgradeReq hits 894system.cpu0.l2cache.SCUpgradeReq_hits::total 2008 # number of SCUpgradeReq hits 895system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233257 # number of ReadExReq hits 896system.cpu0.l2cache.ReadExReq_hits::total 233257 # number of ReadExReq hits 897system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1970223 # number of ReadCleanReq hits 898system.cpu0.l2cache.ReadCleanReq_hits::total 1970223 # number of ReadCleanReq hits 899system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 427246 # number of ReadSharedReq hits 900system.cpu0.l2cache.ReadSharedReq_hits::total 427246 # number of ReadSharedReq hits 901system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 86201 # number of demand (read+write) hits 902system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4393 # number of demand (read+write) hits 903system.cpu0.l2cache.demand_hits::cpu0.inst 1970223 # number of demand (read+write) hits 904system.cpu0.l2cache.demand_hits::cpu0.data 660503 # number of demand (read+write) hits 905system.cpu0.l2cache.demand_hits::total 2721320 # number of demand (read+write) hits 906system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 86201 # number of overall hits 907system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4393 # number of overall hits 908system.cpu0.l2cache.overall_hits::cpu0.inst 1970223 # number of overall hits 909system.cpu0.l2cache.overall_hits::cpu0.data 660503 # number of overall hits 910system.cpu0.l2cache.overall_hits::total 2721320 # number of overall hits 911system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 779 # number of ReadReq misses 912system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 93 # number of ReadReq misses 913system.cpu0.l2cache.ReadReq_misses::total 872 # number of ReadReq misses 914system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26665 # number of UpgradeReq misses 915system.cpu0.l2cache.UpgradeReq_misses::total 26665 # number of UpgradeReq misses 916system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18145 # number of SCUpgradeReq misses 917system.cpu0.l2cache.SCUpgradeReq_misses::total 18145 # number of SCUpgradeReq misses 918system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 919system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 920system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47128 # number of ReadExReq misses 921system.cpu0.l2cache.ReadExReq_misses::total 47128 # number of ReadExReq misses 922system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 74595 # number of ReadCleanReq misses 923system.cpu0.l2cache.ReadCleanReq_misses::total 74595 # number of ReadCleanReq misses 924system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101717 # number of ReadSharedReq misses 925system.cpu0.l2cache.ReadSharedReq_misses::total 101717 # number of ReadSharedReq misses 926system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 779 # number of demand (read+write) misses 927system.cpu0.l2cache.demand_misses::cpu0.itb.walker 93 # number of demand (read+write) misses 928system.cpu0.l2cache.demand_misses::cpu0.inst 74595 # number of demand (read+write) misses 929system.cpu0.l2cache.demand_misses::cpu0.data 148845 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::total 224312 # number of demand (read+write) misses 931system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 779 # number of overall misses 932system.cpu0.l2cache.overall_misses::cpu0.itb.walker 93 # number of overall misses 933system.cpu0.l2cache.overall_misses::cpu0.inst 74595 # number of overall misses 934system.cpu0.l2cache.overall_misses::cpu0.data 148845 # number of overall misses 935system.cpu0.l2cache.overall_misses::total 224312 # number of overall misses 936system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 36149500 # number of ReadReq miss cycles 937system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2302000 # number of ReadReq miss cycles 938system.cpu0.l2cache.ReadReq_miss_latency::total 38451500 # number of ReadReq miss cycles 939system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 622250500 # number of UpgradeReq miss cycles 940system.cpu0.l2cache.UpgradeReq_miss_latency::total 622250500 # number of UpgradeReq miss cycles 941system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 390027000 # number of SCUpgradeReq miss cycles 942system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 390027000 # number of SCUpgradeReq miss cycles 943system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 384498 # number of SCUpgradeFailReq miss cycles 944system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 384498 # number of SCUpgradeFailReq miss cycles 945system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3148896999 # number of ReadExReq miss cycles 946system.cpu0.l2cache.ReadExReq_miss_latency::total 3148896999 # number of ReadExReq miss cycles 947system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4603637500 # number of ReadCleanReq miss cycles 948system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4603637500 # number of ReadCleanReq miss cycles 949system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3550040997 # number of ReadSharedReq miss cycles 950system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3550040997 # number of ReadSharedReq miss cycles 951system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 36149500 # number of demand (read+write) miss cycles 952system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2302000 # number of demand (read+write) miss cycles 953system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4603637500 # number of demand (read+write) miss cycles 954system.cpu0.l2cache.demand_miss_latency::cpu0.data 6698937996 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.demand_miss_latency::total 11341026996 # number of demand (read+write) miss cycles 956system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 36149500 # number of overall miss cycles 957system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2302000 # number of overall miss cycles 958system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4603637500 # number of overall miss cycles 959system.cpu0.l2cache.overall_miss_latency::cpu0.data 6698937996 # number of overall miss cycles 960system.cpu0.l2cache.overall_miss_latency::total 11341026996 # number of overall miss cycles 961system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 86980 # number of ReadReq accesses(hits+misses) 962system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4486 # number of ReadReq accesses(hits+misses) 963system.cpu0.l2cache.ReadReq_accesses::total 91466 # number of ReadReq accesses(hits+misses) 964system.cpu0.l2cache.Writeback_accesses::writebacks 540479 # number of Writeback accesses(hits+misses) 965system.cpu0.l2cache.Writeback_accesses::total 540479 # number of Writeback accesses(hits+misses) 966system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55423 # number of UpgradeReq accesses(hits+misses) 967system.cpu0.l2cache.UpgradeReq_accesses::total 55423 # number of UpgradeReq accesses(hits+misses) 968system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20153 # number of SCUpgradeReq accesses(hits+misses) 969system.cpu0.l2cache.SCUpgradeReq_accesses::total 20153 # number of SCUpgradeReq accesses(hits+misses) 970system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 971system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 972system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280385 # number of ReadExReq accesses(hits+misses) 973system.cpu0.l2cache.ReadExReq_accesses::total 280385 # number of ReadExReq accesses(hits+misses) 974system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2044818 # number of ReadCleanReq accesses(hits+misses) 975system.cpu0.l2cache.ReadCleanReq_accesses::total 2044818 # number of ReadCleanReq accesses(hits+misses) 976system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 528963 # number of ReadSharedReq accesses(hits+misses) 977system.cpu0.l2cache.ReadSharedReq_accesses::total 528963 # number of ReadSharedReq accesses(hits+misses) 978system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 86980 # number of demand (read+write) accesses 979system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4486 # number of demand (read+write) accesses 980system.cpu0.l2cache.demand_accesses::cpu0.inst 2044818 # number of demand (read+write) accesses 981system.cpu0.l2cache.demand_accesses::cpu0.data 809348 # number of demand (read+write) accesses 982system.cpu0.l2cache.demand_accesses::total 2945632 # number of demand (read+write) accesses 983system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 86980 # number of overall (read+write) accesses 984system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4486 # number of overall (read+write) accesses 985system.cpu0.l2cache.overall_accesses::cpu0.inst 2044818 # number of overall (read+write) accesses 986system.cpu0.l2cache.overall_accesses::cpu0.data 809348 # number of overall (read+write) accesses 987system.cpu0.l2cache.overall_accesses::total 2945632 # number of overall (read+write) accesses 988system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008956 # miss rate for ReadReq accesses 989system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.020731 # miss rate for ReadReq accesses 990system.cpu0.l2cache.ReadReq_miss_rate::total 0.009534 # miss rate for ReadReq accesses 991system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.481118 # miss rate for UpgradeReq accesses 992system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.481118 # miss rate for UpgradeReq accesses 993system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.900362 # miss rate for SCUpgradeReq accesses 994system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.900362 # miss rate for SCUpgradeReq accesses 995system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 996system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 997system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.168083 # miss rate for ReadExReq accesses 998system.cpu0.l2cache.ReadExReq_miss_rate::total 0.168083 # miss rate for ReadExReq accesses 999system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.036480 # miss rate for ReadCleanReq accesses 1000system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.036480 # miss rate for ReadCleanReq accesses 1001system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.192295 # miss rate for ReadSharedReq accesses 1002system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.192295 # miss rate for ReadSharedReq accesses 1003system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008956 # miss rate for demand accesses 1004system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.020731 # miss rate for demand accesses 1005system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036480 # miss rate for demand accesses 1006system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183907 # miss rate for demand accesses 1007system.cpu0.l2cache.demand_miss_rate::total 0.076151 # miss rate for demand accesses 1008system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008956 # miss rate for overall accesses 1009system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.020731 # miss rate for overall accesses 1010system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036480 # miss rate for overall accesses 1011system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183907 # miss rate for overall accesses 1012system.cpu0.l2cache.overall_miss_rate::total 0.076151 # miss rate for overall accesses 1013system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 46405.006418 # average ReadReq miss latency 1014system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24752.688172 # average ReadReq miss latency 1015system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44095.756881 # average ReadReq miss latency 1016system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 23335.852241 # average UpgradeReq miss latency 1017system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 23335.852241 # average UpgradeReq miss latency 1018system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21495.012400 # average SCUpgradeReq miss latency 1019system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21495.012400 # average SCUpgradeReq miss latency 1020system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 192249 # average SCUpgradeFailReq miss latency 1021system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 192249 # average SCUpgradeFailReq miss latency 1022system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66815.841941 # average ReadExReq miss latency 1023system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66815.841941 # average ReadExReq miss latency 1024system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 61715.094845 # average ReadCleanReq miss latency 1025system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 61715.094845 # average ReadCleanReq miss latency 1026system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34901.157103 # average ReadSharedReq miss latency 1027system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34901.157103 # average ReadSharedReq miss latency 1028system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 46405.006418 # average overall miss latency 1029system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24752.688172 # average overall miss latency 1030system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 61715.094845 # average overall miss latency 1031system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45006.133871 # average overall miss latency 1032system.cpu0.l2cache.demand_avg_miss_latency::total 50559.163112 # average overall miss latency 1033system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 46405.006418 # average overall miss latency 1034system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24752.688172 # average overall miss latency 1035system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 61715.094845 # average overall miss latency 1036system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45006.133871 # average overall miss latency 1037system.cpu0.l2cache.overall_avg_miss_latency::total 50559.163112 # average overall miss latency 1038system.cpu0.l2cache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked 1039system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1040system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked 1041system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1042system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 1043system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1044system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1045system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1046system.cpu0.l2cache.writebacks::writebacks 205168 # number of writebacks 1047system.cpu0.l2cache.writebacks::total 205168 # number of writebacks 1048system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5239 # number of ReadExReq MSHR hits 1049system.cpu0.l2cache.ReadExReq_mshr_hits::total 5239 # number of ReadExReq MSHR hits 1050system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 89 # number of ReadCleanReq MSHR hits 1051system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 89 # number of ReadCleanReq MSHR hits 1052system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 602 # number of ReadSharedReq MSHR hits 1053system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 602 # number of ReadSharedReq MSHR hits 1054system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 89 # number of demand (read+write) MSHR hits 1055system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5841 # number of demand (read+write) MSHR hits 1056system.cpu0.l2cache.demand_mshr_hits::total 5930 # number of demand (read+write) MSHR hits 1057system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 89 # number of overall MSHR hits 1058system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5841 # number of overall MSHR hits 1059system.cpu0.l2cache.overall_mshr_hits::total 5930 # number of overall MSHR hits 1060system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 779 # number of ReadReq MSHR misses 1061system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 93 # number of ReadReq MSHR misses 1062system.cpu0.l2cache.ReadReq_mshr_misses::total 872 # number of ReadReq MSHR misses 1063system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 10393 # number of CleanEvict MSHR misses 1064system.cpu0.l2cache.CleanEvict_mshr_misses::total 10393 # number of CleanEvict MSHR misses 1065system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 251914 # number of HardPFReq MSHR misses 1066system.cpu0.l2cache.HardPFReq_mshr_misses::total 251914 # number of HardPFReq MSHR misses 1067system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26665 # number of UpgradeReq MSHR misses 1068system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26665 # number of UpgradeReq MSHR misses 1069system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18145 # number of SCUpgradeReq MSHR misses 1070system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18145 # number of SCUpgradeReq MSHR misses 1071system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1072system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1073system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41889 # number of ReadExReq MSHR misses 1074system.cpu0.l2cache.ReadExReq_mshr_misses::total 41889 # number of ReadExReq MSHR misses 1075system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 74506 # number of ReadCleanReq MSHR misses 1076system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 74506 # number of ReadCleanReq MSHR misses 1077system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101115 # number of ReadSharedReq MSHR misses 1078system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101115 # number of ReadSharedReq MSHR misses 1079system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 779 # number of demand (read+write) MSHR misses 1080system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 93 # number of demand (read+write) MSHR misses 1081system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 74506 # number of demand (read+write) MSHR misses 1082system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143004 # number of demand (read+write) MSHR misses 1083system.cpu0.l2cache.demand_mshr_misses::total 218382 # number of demand (read+write) MSHR misses 1084system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 779 # number of overall MSHR misses 1085system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 93 # number of overall MSHR misses 1086system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 74506 # number of overall MSHR misses 1087system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143004 # number of overall MSHR misses 1088system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 251914 # number of overall MSHR misses 1089system.cpu0.l2cache.overall_mshr_misses::total 470296 # number of overall MSHR misses 1090system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable 1091system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable 1092system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35955 # number of ReadReq MSHR uncacheable 1093system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable 1094system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable 1095system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses 1096system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses 1097system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 64677 # number of overall MSHR uncacheable misses 1098system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 31475500 # number of ReadReq MSHR miss cycles 1099system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1744000 # number of ReadReq MSHR miss cycles 1100system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33219500 # number of ReadReq MSHR miss cycles 1101system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21126531245 # number of HardPFReq MSHR miss cycles 1102system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21126531245 # number of HardPFReq MSHR miss cycles 1103system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 933301999 # number of UpgradeReq MSHR miss cycles 1104system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 933301999 # number of UpgradeReq MSHR miss cycles 1105system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 299858500 # number of SCUpgradeReq MSHR miss cycles 1106system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 299858500 # number of SCUpgradeReq MSHR miss cycles 1107system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 342498 # number of SCUpgradeFailReq MSHR miss cycles 1108system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 342498 # number of SCUpgradeFailReq MSHR miss cycles 1109system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2392710000 # number of ReadExReq MSHR miss cycles 1110system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2392710000 # number of ReadExReq MSHR miss cycles 1111system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4153675000 # number of ReadCleanReq MSHR miss cycles 1112system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4153675000 # number of ReadCleanReq MSHR miss cycles 1113system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2908093997 # number of ReadSharedReq MSHR miss cycles 1114system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2908093997 # number of ReadSharedReq MSHR miss cycles 1115system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 31475500 # number of demand (read+write) MSHR miss cycles 1116system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1744000 # number of demand (read+write) MSHR miss cycles 1117system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4153675000 # number of demand (read+write) MSHR miss cycles 1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5300803997 # number of demand (read+write) MSHR miss cycles 1119system.cpu0.l2cache.demand_mshr_miss_latency::total 9487698497 # number of demand (read+write) MSHR miss cycles 1120system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 31475500 # number of overall MSHR miss cycles 1121system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1744000 # number of overall MSHR miss cycles 1122system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4153675000 # number of overall MSHR miss cycles 1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5300803997 # number of overall MSHR miss cycles 1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21126531245 # number of overall MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::total 30614229742 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 525897000 # number of ReadReq MSHR uncacheable cycles 1127system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6091912000 # number of ReadReq MSHR uncacheable cycles 1128system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6617809000 # number of ReadReq MSHR uncacheable cycles 1129system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4940592000 # number of WriteReq MSHR uncacheable cycles 1130system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4940592000 # number of WriteReq MSHR uncacheable cycles 1131system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 525897000 # number of overall MSHR uncacheable cycles 1132system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11032504000 # number of overall MSHR uncacheable cycles 1133system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11558401000 # number of overall MSHR uncacheable cycles 1134system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for ReadReq accesses 1135system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for ReadReq accesses 1136system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009534 # mshr miss rate for ReadReq accesses 1137system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1138system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1139system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1140system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1141system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.481118 # mshr miss rate for UpgradeReq accesses 1142system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.481118 # mshr miss rate for UpgradeReq accesses 1143system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.900362 # mshr miss rate for SCUpgradeReq accesses 1144system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.900362 # mshr miss rate for SCUpgradeReq accesses 1145system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1146system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1147system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149398 # mshr miss rate for ReadExReq accesses 1148system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149398 # mshr miss rate for ReadExReq accesses 1149system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for ReadCleanReq accesses 1150system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036436 # mshr miss rate for ReadCleanReq accesses 1151system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.191157 # mshr miss rate for ReadSharedReq accesses 1152system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.191157 # mshr miss rate for ReadSharedReq accesses 1153system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for demand accesses 1154system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for demand accesses 1155system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for demand accesses 1156system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.176690 # mshr miss rate for demand accesses 1157system.cpu0.l2cache.demand_mshr_miss_rate::total 0.074138 # mshr miss rate for demand accesses 1158system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for overall accesses 1159system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for overall accesses 1160system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for overall accesses 1161system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.176690 # mshr miss rate for overall accesses 1162system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1163system.cpu0.l2cache.overall_mshr_miss_rate::total 0.159659 # mshr miss rate for overall accesses 1164system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average ReadReq mshr miss latency 1165system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average ReadReq mshr miss latency 1166system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38095.756881 # average ReadReq mshr miss latency 1167system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average HardPFReq mshr miss latency 1168system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83864.061723 # average HardPFReq mshr miss latency 1169system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35001.012526 # average UpgradeReq mshr miss latency 1170system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35001.012526 # average UpgradeReq mshr miss latency 1171system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16525.682006 # average SCUpgradeReq mshr miss latency 1172system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16525.682006 # average SCUpgradeReq mshr miss latency 1173system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 171249 # average SCUpgradeFailReq mshr miss latency 1174system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 171249 # average SCUpgradeFailReq mshr miss latency 1175system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57120.246365 # average ReadExReq mshr miss latency 1176system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57120.246365 # average ReadExReq mshr miss latency 1177system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average ReadCleanReq mshr miss latency 1178system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 55749.536950 # average ReadCleanReq mshr miss latency 1179system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28760.263037 # average ReadSharedReq mshr miss latency 1180system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28760.263037 # average ReadSharedReq mshr miss latency 1181system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency 1182system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency 1183system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency 1184system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency 1185system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43445.423602 # average overall mshr miss latency 1186system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency 1187system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency 1188system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency 1189system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency 1190system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average overall mshr miss latency 1191system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 65095.662608 # average overall mshr miss latency 1192system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average ReadReq mshr uncacheable latency 1193system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190134.581773 # average ReadReq mshr uncacheable latency 1194system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 184058.100403 # average ReadReq mshr uncacheable latency 1195system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172014.205139 # average WriteReq mshr uncacheable latency 1196system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172014.205139 # average WriteReq mshr uncacheable latency 1197system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average overall mshr uncacheable latency 1198system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181569.138606 # average overall mshr uncacheable latency 1199system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 178709.603105 # average overall mshr uncacheable latency 1200system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1201system.cpu0.toL2Bus.snoop_filter.tot_requests 5752448 # Total number of requests made to the snoop filter. 1202system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2898331 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1203system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1204system.cpu0.toL2Bus.snoop_filter.tot_snoops 171817 # Total number of snoops made to the snoop filter. 1205system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 171638 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1206system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1207system.cpu0.toL2Bus.trans_dist::ReadReq 142841 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::ReadResp 2765458 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::Writeback 746343 # Transaction distribution 1212system.cpu0.toL2Bus.trans_dist::CleanEvict 2333999 # Transaction distribution 1213system.cpu0.toL2Bus.trans_dist::HardPFReq 319529 # Transaction distribution 1214system.cpu0.toL2Bus.trans_dist::UpgradeReq 85747 # Transaction distribution 1215system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42548 # Transaction distribution 1216system.cpu0.toL2Bus.trans_dist::UpgradeResp 112824 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::ReadExReq 299375 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::ReadExResp 296092 # Transaction distribution 1221system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2044818 # Transaction distribution 1222system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602268 # Transaction distribution 1223system.cpu0.toL2Bus.trans_dist::InvalidateReq 3078 # Transaction distribution 1224system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6106044 # Packet count per connected master and slave (bytes) 1225system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739032 # Packet count per connected master and slave (bytes) 1226system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12492 # Packet count per connected master and slave (bytes) 1227system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185819 # Packet count per connected master and slave (bytes) 1228system.cpu0.toL2Bus.pkt_count::total 9043387 # Packet count per connected master and slave (bytes) 1229system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 131118848 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90716354 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17944 # Cumulative packet size per connected master and slave (bytes) 1232system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 347920 # Cumulative packet size per connected master and slave (bytes) 1233system.cpu0.toL2Bus.pkt_size::total 222201066 # Cumulative packet size per connected master and slave (bytes) 1234system.cpu0.toL2Bus.snoops 910866 # Total snoops (count) 1235system.cpu0.toL2Bus.snoop_fanout::samples 6693455 # Request fanout histogram 1236system.cpu0.toL2Bus.snoop_fanout::mean 0.042507 # Request fanout histogram 1237system.cpu0.toL2Bus.snoop_fanout::stdev 0.201876 # Request fanout histogram 1238system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1239system.cpu0.toL2Bus.snoop_fanout::0 6409112 95.75% 95.75% # Request fanout histogram 1240system.cpu0.toL2Bus.snoop_fanout::1 284164 4.25% 100.00% # Request fanout histogram 1241system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1243system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1244system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1245system.cpu0.toL2Bus.snoop_fanout::total 6693455 # Request fanout histogram 1246system.cpu0.toL2Bus.reqLayer0.occupancy 3504755489 # Layer occupancy (ticks) 1247system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1248system.cpu0.toL2Bus.snoopLayer0.occupancy 115583734 # Layer occupancy (ticks) 1249system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1250system.cpu0.toL2Bus.respLayer0.occupancy 3073459276 # Layer occupancy (ticks) 1251system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1252system.cpu0.toL2Bus.respLayer1.occupancy 1298870694 # Layer occupancy (ticks) 1253system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1254system.cpu0.toL2Bus.respLayer2.occupancy 8011489 # Layer occupancy (ticks) 1255system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1256system.cpu0.toL2Bus.respLayer3.occupancy 98861455 # Layer occupancy (ticks) 1257system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1258system.cpu1.branchPred.lookups 3534290 # Number of BP lookups 1259system.cpu1.branchPred.condPredicted 1990183 # Number of conditional branches predicted 1260system.cpu1.branchPred.condIncorrect 201553 # Number of conditional branches incorrect 1261system.cpu1.branchPred.BTBLookups 2067319 # Number of BTB lookups 1262system.cpu1.branchPred.BTBHits 1417438 # Number of BTB hits 1263system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1264system.cpu1.branchPred.BTBHitPct 68.564068 # BTB Hit Percentage 1265system.cpu1.branchPred.usedRAS 735878 # Number of times the RAS was used to get a target. 1266system.cpu1.branchPred.RASInCorrect 53173 # Number of incorrect RAS predictions. 1267system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1274system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1275system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1276system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1277system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1278system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1279system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1280system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1281system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1282system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1283system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1284system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1285system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1286system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1287system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1288system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1289system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1290system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1291system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1292system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1293system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1294system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1295system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1296system.cpu1.dtb.walker.walks 21952 # Table walker walks requested 1297system.cpu1.dtb.walker.walksShort 21952 # Table walker walks initiated with short descriptors 1298system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 17656 # Level at which table walker walks with short descriptors terminate 1299system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4296 # Level at which table walker walks with short descriptors terminate 1300system.cpu1.dtb.walker.walkWaitTime::samples 21952 # Table walker wait (enqueue to first request) latency 1301system.cpu1.dtb.walker.walkWaitTime::0 21952 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1302system.cpu1.dtb.walker.walkWaitTime::total 21952 # Table walker wait (enqueue to first request) latency 1303system.cpu1.dtb.walker.walkCompletionTime::samples 1858 # Table walker service (enqueue to completion) latency 1304system.cpu1.dtb.walker.walkCompletionTime::mean 11787.944026 # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::gmean 10957.170839 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::stdev 8000.267562 # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::0-16383 1715 92.30% 92.30% # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::16384-32767 133 7.16% 99.46% # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::32768-49151 6 0.32% 99.78% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.84% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.89% # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 99.95% # Table walker service (enqueue to completion) latency 1313system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.05% 100.00% # Table walker service (enqueue to completion) latency 1314system.cpu1.dtb.walker.walkCompletionTime::total 1858 # Table walker service (enqueue to completion) latency 1315system.cpu1.dtb.walker.walksPending::samples -2099073032 # Table walker pending requests distribution 1316system.cpu1.dtb.walker.walksPending::0 -2099073032 100.00% 100.00% # Table walker pending requests distribution 1317system.cpu1.dtb.walker.walksPending::total -2099073032 # Table walker pending requests distribution 1318system.cpu1.dtb.walker.walkPageSizes::4K 1319 70.99% 70.99% # Table walker page sizes translated 1319system.cpu1.dtb.walker.walkPageSizes::1M 539 29.01% 100.00% # Table walker page sizes translated 1320system.cpu1.dtb.walker.walkPageSizes::total 1858 # Table walker page sizes translated 1321system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21952 # Table walker requests started/completed, data/inst 1322system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1323system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21952 # Table walker requests started/completed, data/inst 1324system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1858 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1326system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1858 # Table walker requests started/completed, data/inst 1327system.cpu1.dtb.walker.walkRequestOrigin::total 23810 # Table walker requests started/completed, data/inst 1328system.cpu1.dtb.inst_hits 0 # ITB inst hits 1329system.cpu1.dtb.inst_misses 0 # ITB inst misses 1330system.cpu1.dtb.read_hits 3504265 # DTB read hits 1331system.cpu1.dtb.read_misses 20273 # DTB read misses 1332system.cpu1.dtb.write_hits 2919622 # DTB write hits 1333system.cpu1.dtb.write_misses 1679 # DTB write misses 1334system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1335system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1336system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1337system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1338system.cpu1.dtb.flush_entries 1723 # Number of entries that have been flushed from TLB 1339system.cpu1.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions 1340system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch 1341system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1342system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions 1343system.cpu1.dtb.read_accesses 3524538 # DTB read accesses 1344system.cpu1.dtb.write_accesses 2921301 # DTB write accesses 1345system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1346system.cpu1.dtb.hits 6423887 # DTB hits 1347system.cpu1.dtb.misses 21952 # DTB misses 1348system.cpu1.dtb.accesses 6445839 # DTB accesses 1349system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1355system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1356system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1357system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1358system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1359system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1360system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1361system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1362system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1363system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1364system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1365system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1366system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1367system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1368system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1369system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1370system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1371system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1372system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1373system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1374system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1375system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1376system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1377system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1378system.cpu1.itb.walker.walks 1951 # Table walker walks requested 1379system.cpu1.itb.walker.walksShort 1951 # Table walker walks initiated with short descriptors 1380system.cpu1.itb.walker.walksShortTerminationLevel::Level1 155 # Level at which table walker walks with short descriptors terminate 1381system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1796 # Level at which table walker walks with short descriptors terminate 1382system.cpu1.itb.walker.walkWaitTime::samples 1951 # Table walker wait (enqueue to first request) latency 1383system.cpu1.itb.walker.walkWaitTime::0 1951 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1384system.cpu1.itb.walker.walkWaitTime::total 1951 # Table walker wait (enqueue to first request) latency 1385system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency 1386system.cpu1.itb.walker.walkCompletionTime::mean 11383.431953 # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::gmean 10916.753394 # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::stdev 4130.106784 # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::4096-8191 149 17.63% 17.63% # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::8192-12287 569 67.34% 84.97% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 12.66% 97.63% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 97.75% # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.82% # Table walker service (enqueue to completion) latency 1394system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.47% 99.29% # Table walker service (enqueue to completion) latency 1395system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.47% 99.76% # Table walker service (enqueue to completion) latency 1396system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency 1397system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency 1398system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency 1399system.cpu1.itb.walker.walksPending::samples -2099960532 # Table walker pending requests distribution 1400system.cpu1.itb.walker.walksPending::0 -2099960532 100.00% 100.00% # Table walker pending requests distribution 1401system.cpu1.itb.walker.walksPending::total -2099960532 # Table walker pending requests distribution 1402system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated 1403system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated 1404system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated 1405system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1406system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1951 # Table walker requests started/completed, data/inst 1407system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1951 # Table walker requests started/completed, data/inst 1408system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1409system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst 1410system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst 1411system.cpu1.itb.walker.walkRequestOrigin::total 2796 # Table walker requests started/completed, data/inst 1412system.cpu1.itb.inst_hits 6761340 # ITB inst hits 1413system.cpu1.itb.inst_misses 1951 # ITB inst misses 1414system.cpu1.itb.read_hits 0 # DTB read hits 1415system.cpu1.itb.read_misses 0 # DTB read misses 1416system.cpu1.itb.write_hits 0 # DTB write hits 1417system.cpu1.itb.write_misses 0 # DTB write misses 1418system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1419system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1420system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1421system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1422system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB 1423system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1424system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1425system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1426system.cpu1.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions 1427system.cpu1.itb.read_accesses 0 # DTB read accesses 1428system.cpu1.itb.write_accesses 0 # DTB write accesses 1429system.cpu1.itb.inst_accesses 6763291 # ITB inst accesses 1430system.cpu1.itb.hits 6761340 # DTB hits 1431system.cpu1.itb.misses 1951 # DTB misses 1432system.cpu1.itb.accesses 6763291 # DTB accesses 1433system.cpu1.numCycles 39381699 # number of cpu cycles simulated 1434system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1435system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1436system.cpu1.committedInsts 13710475 # Number of instructions committed 1437system.cpu1.committedOps 16799330 # Number of ops (including micro ops) committed 1438system.cpu1.discardedOps 1340837 # Number of ops (including micro ops) which were discarded before commit 1439system.cpu1.numFetchSuspends 2719 # Number of times Execute suspended instruction fetching 1440system.cpu1.quiesceCycles 5656091241 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1441system.cpu1.cpi 2.872380 # CPI: cycles per instruction 1442system.cpu1.ipc 0.348143 # IPC: instructions per cycle 1443system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1444system.cpu1.kern.inst.quiesce 2719 # number of quiesce instructions executed 1445system.cpu1.tickCycles 26653258 # Number of cycles that the object actually ticked 1446system.cpu1.idleCycles 12728441 # Total number of cycles that the object has spent stopped 1447system.cpu1.dcache.tags.replacements 152894 # number of replacements 1448system.cpu1.dcache.tags.tagsinuse 470.093140 # Cycle average of tags in use 1449system.cpu1.dcache.tags.total_refs 6072239 # Total number of references to valid blocks. 1450system.cpu1.dcache.tags.sampled_refs 153243 # Sample count of references to valid blocks. 1451system.cpu1.dcache.tags.avg_refs 39.624903 # Average number of references to valid blocks. 1452system.cpu1.dcache.tags.warmup_cycle 110033723500 # Cycle when the warmup percentage was hit. 1453system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.093140 # Average occupied blocks per requestor 1454system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918151 # Average percentage of cache occupancy 1455system.cpu1.dcache.tags.occ_percent::total 0.918151 # Average percentage of cache occupancy 1456system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 1457system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id 1458system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1459system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id 1460system.cpu1.dcache.tags.tag_accesses 12903758 # Number of tag accesses 1461system.cpu1.dcache.tags.data_accesses 12903758 # Number of data accesses 1462system.cpu1.dcache.ReadReq_hits::cpu1.data 3189039 # number of ReadReq hits 1463system.cpu1.dcache.ReadReq_hits::total 3189039 # number of ReadReq hits 1464system.cpu1.dcache.WriteReq_hits::cpu1.data 2677291 # number of WriteReq hits 1465system.cpu1.dcache.WriteReq_hits::total 2677291 # number of WriteReq hits 1466system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41980 # number of SoftPFReq hits 1467system.cpu1.dcache.SoftPFReq_hits::total 41980 # number of SoftPFReq hits 1468system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69267 # number of LoadLockedReq hits 1469system.cpu1.dcache.LoadLockedReq_hits::total 69267 # number of LoadLockedReq hits 1470system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60867 # number of StoreCondReq hits 1471system.cpu1.dcache.StoreCondReq_hits::total 60867 # number of StoreCondReq hits 1472system.cpu1.dcache.demand_hits::cpu1.data 5866330 # number of demand (read+write) hits 1473system.cpu1.dcache.demand_hits::total 5866330 # number of demand (read+write) hits 1474system.cpu1.dcache.overall_hits::cpu1.data 5908310 # number of overall hits 1475system.cpu1.dcache.overall_hits::total 5908310 # number of overall hits 1476system.cpu1.dcache.ReadReq_misses::cpu1.data 130563 # number of ReadReq misses 1477system.cpu1.dcache.ReadReq_misses::total 130563 # number of ReadReq misses 1478system.cpu1.dcache.WriteReq_misses::cpu1.data 120040 # number of WriteReq misses 1479system.cpu1.dcache.WriteReq_misses::total 120040 # number of WriteReq misses 1480system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24252 # number of SoftPFReq misses 1481system.cpu1.dcache.SoftPFReq_misses::total 24252 # number of SoftPFReq misses 1482system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16672 # number of LoadLockedReq misses 1483system.cpu1.dcache.LoadLockedReq_misses::total 16672 # number of LoadLockedReq misses 1484system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23310 # number of StoreCondReq misses 1485system.cpu1.dcache.StoreCondReq_misses::total 23310 # number of StoreCondReq misses 1486system.cpu1.dcache.demand_misses::cpu1.data 250603 # number of demand (read+write) misses 1487system.cpu1.dcache.demand_misses::total 250603 # number of demand (read+write) misses 1488system.cpu1.dcache.overall_misses::cpu1.data 274855 # number of overall misses 1489system.cpu1.dcache.overall_misses::total 274855 # number of overall misses 1490system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2128187500 # number of ReadReq miss cycles 1491system.cpu1.dcache.ReadReq_miss_latency::total 2128187500 # number of ReadReq miss cycles 1492system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4337924000 # number of WriteReq miss cycles 1493system.cpu1.dcache.WriteReq_miss_latency::total 4337924000 # number of WriteReq miss cycles 1494system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321753000 # number of LoadLockedReq miss cycles 1495system.cpu1.dcache.LoadLockedReq_miss_latency::total 321753000 # number of LoadLockedReq miss cycles 1496system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615942500 # number of StoreCondReq miss cycles 1497system.cpu1.dcache.StoreCondReq_miss_latency::total 615942500 # number of StoreCondReq miss cycles 1498system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1442500 # number of StoreCondFailReq miss cycles 1499system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1442500 # number of StoreCondFailReq miss cycles 1500system.cpu1.dcache.demand_miss_latency::cpu1.data 6466111500 # number of demand (read+write) miss cycles 1501system.cpu1.dcache.demand_miss_latency::total 6466111500 # number of demand (read+write) miss cycles 1502system.cpu1.dcache.overall_miss_latency::cpu1.data 6466111500 # number of overall miss cycles 1503system.cpu1.dcache.overall_miss_latency::total 6466111500 # number of overall miss cycles 1504system.cpu1.dcache.ReadReq_accesses::cpu1.data 3319602 # number of ReadReq accesses(hits+misses) 1505system.cpu1.dcache.ReadReq_accesses::total 3319602 # number of ReadReq accesses(hits+misses) 1506system.cpu1.dcache.WriteReq_accesses::cpu1.data 2797331 # number of WriteReq accesses(hits+misses) 1507system.cpu1.dcache.WriteReq_accesses::total 2797331 # number of WriteReq accesses(hits+misses) 1508system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66232 # number of SoftPFReq accesses(hits+misses) 1509system.cpu1.dcache.SoftPFReq_accesses::total 66232 # number of SoftPFReq accesses(hits+misses) 1510system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85939 # number of LoadLockedReq accesses(hits+misses) 1511system.cpu1.dcache.LoadLockedReq_accesses::total 85939 # number of LoadLockedReq accesses(hits+misses) 1512system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84177 # number of StoreCondReq accesses(hits+misses) 1513system.cpu1.dcache.StoreCondReq_accesses::total 84177 # number of StoreCondReq accesses(hits+misses) 1514system.cpu1.dcache.demand_accesses::cpu1.data 6116933 # number of demand (read+write) accesses 1515system.cpu1.dcache.demand_accesses::total 6116933 # number of demand (read+write) accesses 1516system.cpu1.dcache.overall_accesses::cpu1.data 6183165 # number of overall (read+write) accesses 1517system.cpu1.dcache.overall_accesses::total 6183165 # number of overall (read+write) accesses 1518system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039331 # miss rate for ReadReq accesses 1519system.cpu1.dcache.ReadReq_miss_rate::total 0.039331 # miss rate for ReadReq accesses 1520system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042912 # miss rate for WriteReq accesses 1521system.cpu1.dcache.WriteReq_miss_rate::total 0.042912 # miss rate for WriteReq accesses 1522system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366167 # miss rate for SoftPFReq accesses 1523system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366167 # miss rate for SoftPFReq accesses 1524system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.193998 # miss rate for LoadLockedReq accesses 1525system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.193998 # miss rate for LoadLockedReq accesses 1526system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.276916 # miss rate for StoreCondReq accesses 1527system.cpu1.dcache.StoreCondReq_miss_rate::total 0.276916 # miss rate for StoreCondReq accesses 1528system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040969 # miss rate for demand accesses 1529system.cpu1.dcache.demand_miss_rate::total 0.040969 # miss rate for demand accesses 1530system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044452 # miss rate for overall accesses 1531system.cpu1.dcache.overall_miss_rate::total 0.044452 # miss rate for overall accesses 1532system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.081187 # average ReadReq miss latency 1533system.cpu1.dcache.ReadReq_avg_miss_latency::total 16300.081187 # average ReadReq miss latency 1534system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36137.320893 # average WriteReq miss latency 1535system.cpu1.dcache.WriteReq_avg_miss_latency::total 36137.320893 # average WriteReq miss latency 1536system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19299.004319 # average LoadLockedReq miss latency 1537system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19299.004319 # average LoadLockedReq miss latency 1538system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26423.959674 # average StoreCondReq miss latency 1539system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26423.959674 # average StoreCondReq miss latency 1540system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1541system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1542system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25802.211067 # average overall miss latency 1543system.cpu1.dcache.demand_avg_miss_latency::total 25802.211067 # average overall miss latency 1544system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23525.537101 # average overall miss latency 1545system.cpu1.dcache.overall_avg_miss_latency::total 23525.537101 # average overall miss latency 1546system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1547system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1548system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1549system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1550system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1551system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1552system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1553system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1554system.cpu1.dcache.writebacks::writebacks 95329 # number of writebacks 1555system.cpu1.dcache.writebacks::total 95329 # number of writebacks 1556system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12149 # number of ReadReq MSHR hits 1557system.cpu1.dcache.ReadReq_mshr_hits::total 12149 # number of ReadReq MSHR hits 1558system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 41106 # number of WriteReq MSHR hits 1559system.cpu1.dcache.WriteReq_mshr_hits::total 41106 # number of WriteReq MSHR hits 1560system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11576 # number of LoadLockedReq MSHR hits 1561system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11576 # number of LoadLockedReq MSHR hits 1562system.cpu1.dcache.demand_mshr_hits::cpu1.data 53255 # number of demand (read+write) MSHR hits 1563system.cpu1.dcache.demand_mshr_hits::total 53255 # number of demand (read+write) MSHR hits 1564system.cpu1.dcache.overall_mshr_hits::cpu1.data 53255 # number of overall MSHR hits 1565system.cpu1.dcache.overall_mshr_hits::total 53255 # number of overall MSHR hits 1566system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118414 # number of ReadReq MSHR misses 1567system.cpu1.dcache.ReadReq_mshr_misses::total 118414 # number of ReadReq MSHR misses 1568system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78934 # number of WriteReq MSHR misses 1569system.cpu1.dcache.WriteReq_mshr_misses::total 78934 # number of WriteReq MSHR misses 1570system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23724 # number of SoftPFReq MSHR misses 1571system.cpu1.dcache.SoftPFReq_mshr_misses::total 23724 # number of SoftPFReq MSHR misses 1572system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5096 # number of LoadLockedReq MSHR misses 1573system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5096 # number of LoadLockedReq MSHR misses 1574system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23310 # number of StoreCondReq MSHR misses 1575system.cpu1.dcache.StoreCondReq_mshr_misses::total 23310 # number of StoreCondReq MSHR misses 1576system.cpu1.dcache.demand_mshr_misses::cpu1.data 197348 # number of demand (read+write) MSHR misses 1577system.cpu1.dcache.demand_mshr_misses::total 197348 # number of demand (read+write) MSHR misses 1578system.cpu1.dcache.overall_mshr_misses::cpu1.data 221072 # number of overall MSHR misses 1579system.cpu1.dcache.overall_mshr_misses::total 221072 # number of overall MSHR misses 1580system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2845 # number of ReadReq MSHR uncacheable 1581system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2845 # number of ReadReq MSHR uncacheable 1582system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2191 # number of WriteReq MSHR uncacheable 1583system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2191 # number of WriteReq MSHR uncacheable 1584system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5036 # number of overall MSHR uncacheable misses 1585system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5036 # number of overall MSHR uncacheable misses 1586system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811744000 # number of ReadReq MSHR miss cycles 1587system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811744000 # number of ReadReq MSHR miss cycles 1588system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2651572500 # number of WriteReq MSHR miss cycles 1589system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2651572500 # number of WriteReq MSHR miss cycles 1590system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 432946000 # number of SoftPFReq MSHR miss cycles 1591system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 432946000 # number of SoftPFReq MSHR miss cycles 1592system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92138000 # number of LoadLockedReq MSHR miss cycles 1593system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92138000 # number of LoadLockedReq MSHR miss cycles 1594system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592646500 # number of StoreCondReq MSHR miss cycles 1595system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592646500 # number of StoreCondReq MSHR miss cycles 1596system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1428500 # number of StoreCondFailReq MSHR miss cycles 1597system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1428500 # number of StoreCondFailReq MSHR miss cycles 1598system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4463316500 # number of demand (read+write) MSHR miss cycles 1599system.cpu1.dcache.demand_mshr_miss_latency::total 4463316500 # number of demand (read+write) MSHR miss cycles 1600system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4896262500 # number of overall MSHR miss cycles 1601system.cpu1.dcache.overall_mshr_miss_latency::total 4896262500 # number of overall MSHR miss cycles 1602system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 356276500 # number of ReadReq MSHR uncacheable cycles 1603system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 356276500 # number of ReadReq MSHR uncacheable cycles 1604system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224816500 # number of WriteReq MSHR uncacheable cycles 1605system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224816500 # number of WriteReq MSHR uncacheable cycles 1606system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 581093000 # number of overall MSHR uncacheable cycles 1607system.cpu1.dcache.overall_mshr_uncacheable_latency::total 581093000 # number of overall MSHR uncacheable cycles 1608system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035671 # mshr miss rate for ReadReq accesses 1609system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035671 # mshr miss rate for ReadReq accesses 1610system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028218 # mshr miss rate for WriteReq accesses 1611system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028218 # mshr miss rate for WriteReq accesses 1612system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.358195 # mshr miss rate for SoftPFReq accesses 1613system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.358195 # mshr miss rate for SoftPFReq accesses 1614system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059298 # mshr miss rate for LoadLockedReq accesses 1615system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059298 # mshr miss rate for LoadLockedReq accesses 1616system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.276916 # mshr miss rate for StoreCondReq accesses 1617system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.276916 # mshr miss rate for StoreCondReq accesses 1618system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032263 # mshr miss rate for demand accesses 1619system.cpu1.dcache.demand_mshr_miss_rate::total 0.032263 # mshr miss rate for demand accesses 1620system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035754 # mshr miss rate for overall accesses 1621system.cpu1.dcache.overall_mshr_miss_rate::total 0.035754 # mshr miss rate for overall accesses 1622system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15300.082760 # average ReadReq mshr miss latency 1623system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15300.082760 # average ReadReq mshr miss latency 1624system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33592.273292 # average WriteReq mshr miss latency 1625system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33592.273292 # average WriteReq mshr miss latency 1626system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18249.283426 # average SoftPFReq mshr miss latency 1627system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18249.283426 # average SoftPFReq mshr miss latency 1628system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18080.455259 # average LoadLockedReq mshr miss latency 1629system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18080.455259 # average LoadLockedReq mshr miss latency 1630system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25424.560275 # average StoreCondReq mshr miss latency 1631system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25424.560275 # average StoreCondReq mshr miss latency 1632system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1633system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1634system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22616.476985 # average overall mshr miss latency 1635system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22616.476985 # average overall mshr miss latency 1636system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22147.818358 # average overall mshr miss latency 1637system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22147.818358 # average overall mshr miss latency 1638system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125228.998243 # average ReadReq mshr uncacheable latency 1639system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125228.998243 # average ReadReq mshr uncacheable latency 1640system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102609.082611 # average WriteReq mshr uncacheable latency 1641system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 102609.082611 # average WriteReq mshr uncacheable latency 1642system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115387.807784 # average overall mshr uncacheable latency 1643system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 115387.807784 # average overall mshr uncacheable latency 1644system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1645system.cpu1.icache.tags.replacements 837637 # number of replacements 1646system.cpu1.icache.tags.tagsinuse 499.228366 # Cycle average of tags in use 1647system.cpu1.icache.tags.total_refs 5922018 # Total number of references to valid blocks. 1648system.cpu1.icache.tags.sampled_refs 838149 # Sample count of references to valid blocks. 1649system.cpu1.icache.tags.avg_refs 7.065591 # Average number of references to valid blocks. 1650system.cpu1.icache.tags.warmup_cycle 72771979500 # Cycle when the warmup percentage was hit. 1651system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.228366 # Average occupied blocks per requestor 1652system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975055 # Average percentage of cache occupancy 1653system.cpu1.icache.tags.occ_percent::total 0.975055 # Average percentage of cache occupancy 1654system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1655system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id 1656system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 1657system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1658system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1659system.cpu1.icache.tags.tag_accesses 14358483 # Number of tag accesses 1660system.cpu1.icache.tags.data_accesses 14358483 # Number of data accesses 1661system.cpu1.icache.ReadReq_hits::cpu1.inst 5922018 # number of ReadReq hits 1662system.cpu1.icache.ReadReq_hits::total 5922018 # number of ReadReq hits 1663system.cpu1.icache.demand_hits::cpu1.inst 5922018 # number of demand (read+write) hits 1664system.cpu1.icache.demand_hits::total 5922018 # number of demand (read+write) hits 1665system.cpu1.icache.overall_hits::cpu1.inst 5922018 # number of overall hits 1666system.cpu1.icache.overall_hits::total 5922018 # number of overall hits 1667system.cpu1.icache.ReadReq_misses::cpu1.inst 838149 # number of ReadReq misses 1668system.cpu1.icache.ReadReq_misses::total 838149 # number of ReadReq misses 1669system.cpu1.icache.demand_misses::cpu1.inst 838149 # number of demand (read+write) misses 1670system.cpu1.icache.demand_misses::total 838149 # number of demand (read+write) misses 1671system.cpu1.icache.overall_misses::cpu1.inst 838149 # number of overall misses 1672system.cpu1.icache.overall_misses::total 838149 # number of overall misses 1673system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7371671000 # number of ReadReq miss cycles 1674system.cpu1.icache.ReadReq_miss_latency::total 7371671000 # number of ReadReq miss cycles 1675system.cpu1.icache.demand_miss_latency::cpu1.inst 7371671000 # number of demand (read+write) miss cycles 1676system.cpu1.icache.demand_miss_latency::total 7371671000 # number of demand (read+write) miss cycles 1677system.cpu1.icache.overall_miss_latency::cpu1.inst 7371671000 # number of overall miss cycles 1678system.cpu1.icache.overall_miss_latency::total 7371671000 # number of overall miss cycles 1679system.cpu1.icache.ReadReq_accesses::cpu1.inst 6760167 # number of ReadReq accesses(hits+misses) 1680system.cpu1.icache.ReadReq_accesses::total 6760167 # number of ReadReq accesses(hits+misses) 1681system.cpu1.icache.demand_accesses::cpu1.inst 6760167 # number of demand (read+write) accesses 1682system.cpu1.icache.demand_accesses::total 6760167 # number of demand (read+write) accesses 1683system.cpu1.icache.overall_accesses::cpu1.inst 6760167 # number of overall (read+write) accesses 1684system.cpu1.icache.overall_accesses::total 6760167 # number of overall (read+write) accesses 1685system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.123983 # miss rate for ReadReq accesses 1686system.cpu1.icache.ReadReq_miss_rate::total 0.123983 # miss rate for ReadReq accesses 1687system.cpu1.icache.demand_miss_rate::cpu1.inst 0.123983 # miss rate for demand accesses 1688system.cpu1.icache.demand_miss_rate::total 0.123983 # miss rate for demand accesses 1689system.cpu1.icache.overall_miss_rate::cpu1.inst 0.123983 # miss rate for overall accesses 1690system.cpu1.icache.overall_miss_rate::total 0.123983 # miss rate for overall accesses 1691system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8795.179616 # average ReadReq miss latency 1692system.cpu1.icache.ReadReq_avg_miss_latency::total 8795.179616 # average ReadReq miss latency 1693system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency 1694system.cpu1.icache.demand_avg_miss_latency::total 8795.179616 # average overall miss latency 1695system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency 1696system.cpu1.icache.overall_avg_miss_latency::total 8795.179616 # average overall miss latency 1697system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1698system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1699system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1700system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1701system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1702system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1703system.cpu1.icache.fast_writes 0 # number of fast writes performed 1704system.cpu1.icache.cache_copies 0 # number of cache copies performed 1705system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 838149 # number of ReadReq MSHR misses 1706system.cpu1.icache.ReadReq_mshr_misses::total 838149 # number of ReadReq MSHR misses 1707system.cpu1.icache.demand_mshr_misses::cpu1.inst 838149 # number of demand (read+write) MSHR misses 1708system.cpu1.icache.demand_mshr_misses::total 838149 # number of demand (read+write) MSHR misses 1709system.cpu1.icache.overall_mshr_misses::cpu1.inst 838149 # number of overall MSHR misses 1710system.cpu1.icache.overall_mshr_misses::total 838149 # number of overall MSHR misses 1711system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1712system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1713system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1714system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1715system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6952596500 # number of ReadReq MSHR miss cycles 1716system.cpu1.icache.ReadReq_mshr_miss_latency::total 6952596500 # number of ReadReq MSHR miss cycles 1717system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6952596500 # number of demand (read+write) MSHR miss cycles 1718system.cpu1.icache.demand_mshr_miss_latency::total 6952596500 # number of demand (read+write) MSHR miss cycles 1719system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6952596500 # number of overall MSHR miss cycles 1720system.cpu1.icache.overall_mshr_miss_latency::total 6952596500 # number of overall MSHR miss cycles 1721system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15127000 # number of ReadReq MSHR uncacheable cycles 1722system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15127000 # number of ReadReq MSHR uncacheable cycles 1723system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15127000 # number of overall MSHR uncacheable cycles 1724system.cpu1.icache.overall_mshr_uncacheable_latency::total 15127000 # number of overall MSHR uncacheable cycles 1725system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for ReadReq accesses 1726system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.123983 # mshr miss rate for ReadReq accesses 1727system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for demand accesses 1728system.cpu1.icache.demand_mshr_miss_rate::total 0.123983 # mshr miss rate for demand accesses 1729system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for overall accesses 1730system.cpu1.icache.overall_mshr_miss_rate::total 0.123983 # mshr miss rate for overall accesses 1731system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average ReadReq mshr miss latency 1732system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8295.179616 # average ReadReq mshr miss latency 1733system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average overall mshr miss latency 1734system.cpu1.icache.demand_avg_mshr_miss_latency::total 8295.179616 # average overall mshr miss latency 1735system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average overall mshr miss latency 1736system.cpu1.icache.overall_avg_mshr_miss_latency::total 8295.179616 # average overall mshr miss latency 1737system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000 # average ReadReq mshr uncacheable latency 1738system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135062.500000 # average ReadReq mshr uncacheable latency 1739system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000 # average overall mshr uncacheable latency 1740system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135062.500000 # average overall mshr uncacheable latency 1741system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1742system.cpu1.l2cache.prefetcher.num_hwpf_issued 119402 # number of hwpf issued 1743system.cpu1.l2cache.prefetcher.pfIdentified 119476 # number of prefetch candidates identified 1744system.cpu1.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue 1745system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1746system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1747system.cpu1.l2cache.prefetcher.pfSpanPage 48156 # number of prefetches not generated due to page crossing 1748system.cpu1.l2cache.tags.replacements 37250 # number of replacements 1749system.cpu1.l2cache.tags.tagsinuse 15275.676235 # Cycle average of tags in use 1750system.cpu1.l2cache.tags.total_refs 1897057 # Total number of references to valid blocks. 1751system.cpu1.l2cache.tags.sampled_refs 52360 # Sample count of references to valid blocks. 1752system.cpu1.l2cache.tags.avg_refs 36.231035 # Average number of references to valid blocks. 1753system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1754system.cpu1.l2cache.tags.occ_blocks::writebacks 7998.087446 # Average occupied blocks per requestor 1755system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 32.292792 # Average occupied blocks per requestor 1756system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.074638 # Average occupied blocks per requestor 1757system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4213.861593 # Average occupied blocks per requestor 1758system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2174.488490 # Average occupied blocks per requestor 1759system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 856.871276 # Average occupied blocks per requestor 1760system.cpu1.l2cache.tags.occ_percent::writebacks 0.488165 # Average percentage of cache occupancy 1761system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001971 # Average percentage of cache occupancy 1762system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy 1763system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.257194 # Average percentage of cache occupancy 1764system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132720 # Average percentage of cache occupancy 1765system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052299 # Average percentage of cache occupancy 1766system.cpu1.l2cache.tags.occ_percent::total 0.932353 # Average percentage of cache occupancy 1767system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1099 # Occupied blocks per task id 1768system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id 1769system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13920 # Occupied blocks per task id 1770system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id 1771system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 56 # Occupied blocks per task id 1772system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1042 # Occupied blocks per task id 1773system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1774system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1775system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id 1776system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id 1777system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1993 # Occupied blocks per task id 1778system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11603 # Occupied blocks per task id 1779system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067078 # Percentage of cache occupancy per task id 1780system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id 1781system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id 1782system.cpu1.l2cache.tags.tag_accesses 33573934 # Number of tag accesses 1783system.cpu1.l2cache.tags.data_accesses 33573934 # Number of data accesses 1784system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23345 # number of ReadReq hits 1785system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2401 # number of ReadReq hits 1786system.cpu1.l2cache.ReadReq_hits::total 25746 # number of ReadReq hits 1787system.cpu1.l2cache.Writeback_hits::writebacks 95329 # number of Writeback hits 1788system.cpu1.l2cache.Writeback_hits::total 95329 # number of Writeback hits 1789system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1276 # number of UpgradeReq hits 1790system.cpu1.l2cache.UpgradeReq_hits::total 1276 # number of UpgradeReq hits 1791system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 784 # number of SCUpgradeReq hits 1792system.cpu1.l2cache.SCUpgradeReq_hits::total 784 # number of SCUpgradeReq hits 1793system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17759 # number of ReadExReq hits 1794system.cpu1.l2cache.ReadExReq_hits::total 17759 # number of ReadExReq hits 1795system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 825014 # number of ReadCleanReq hits 1796system.cpu1.l2cache.ReadCleanReq_hits::total 825014 # number of ReadCleanReq hits 1797system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81245 # number of ReadSharedReq hits 1798system.cpu1.l2cache.ReadSharedReq_hits::total 81245 # number of ReadSharedReq hits 1799system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23345 # number of demand (read+write) hits 1800system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2401 # number of demand (read+write) hits 1801system.cpu1.l2cache.demand_hits::cpu1.inst 825014 # number of demand (read+write) hits 1802system.cpu1.l2cache.demand_hits::cpu1.data 99004 # number of demand (read+write) hits 1803system.cpu1.l2cache.demand_hits::total 949764 # number of demand (read+write) hits 1804system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23345 # number of overall hits 1805system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2401 # number of overall hits 1806system.cpu1.l2cache.overall_hits::cpu1.inst 825014 # number of overall hits 1807system.cpu1.l2cache.overall_hits::cpu1.data 99004 # number of overall hits 1808system.cpu1.l2cache.overall_hits::total 949764 # number of overall hits 1809system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 724 # number of ReadReq misses 1810system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 240 # number of ReadReq misses 1811system.cpu1.l2cache.ReadReq_misses::total 964 # number of ReadReq misses 1812system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27711 # number of UpgradeReq misses 1813system.cpu1.l2cache.UpgradeReq_misses::total 27711 # number of UpgradeReq misses 1814system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22526 # number of SCUpgradeReq misses 1815system.cpu1.l2cache.SCUpgradeReq_misses::total 22526 # number of SCUpgradeReq misses 1816system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32189 # number of ReadExReq misses 1817system.cpu1.l2cache.ReadExReq_misses::total 32189 # number of ReadExReq misses 1818system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13135 # number of ReadCleanReq misses 1819system.cpu1.l2cache.ReadCleanReq_misses::total 13135 # number of ReadCleanReq misses 1820system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 65988 # number of ReadSharedReq misses 1821system.cpu1.l2cache.ReadSharedReq_misses::total 65988 # number of ReadSharedReq misses 1822system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 724 # number of demand (read+write) misses 1823system.cpu1.l2cache.demand_misses::cpu1.itb.walker 240 # number of demand (read+write) misses 1824system.cpu1.l2cache.demand_misses::cpu1.inst 13135 # number of demand (read+write) misses 1825system.cpu1.l2cache.demand_misses::cpu1.data 98177 # number of demand (read+write) misses 1826system.cpu1.l2cache.demand_misses::total 112276 # number of demand (read+write) misses 1827system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 724 # number of overall misses 1828system.cpu1.l2cache.overall_misses::cpu1.itb.walker 240 # number of overall misses 1829system.cpu1.l2cache.overall_misses::cpu1.inst 13135 # number of overall misses 1830system.cpu1.l2cache.overall_misses::cpu1.data 98177 # number of overall misses 1831system.cpu1.l2cache.overall_misses::total 112276 # number of overall misses 1832system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 16832000 # number of ReadReq miss cycles 1833system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4807500 # number of ReadReq miss cycles 1834system.cpu1.l2cache.ReadReq_miss_latency::total 21639500 # number of ReadReq miss cycles 1835system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 545169500 # number of UpgradeReq miss cycles 1836system.cpu1.l2cache.UpgradeReq_miss_latency::total 545169500 # number of UpgradeReq miss cycles 1837system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 480035000 # number of SCUpgradeReq miss cycles 1838system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 480035000 # number of SCUpgradeReq miss cycles 1839system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1407500 # number of SCUpgradeFailReq miss cycles 1840system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1407500 # number of SCUpgradeFailReq miss cycles 1841system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1686123500 # number of ReadExReq miss cycles 1842system.cpu1.l2cache.ReadExReq_miss_latency::total 1686123500 # number of ReadExReq miss cycles 1843system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 733172000 # number of ReadCleanReq miss cycles 1844system.cpu1.l2cache.ReadCleanReq_miss_latency::total 733172000 # number of ReadCleanReq miss cycles 1845system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1579312997 # number of ReadSharedReq miss cycles 1846system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1579312997 # number of ReadSharedReq miss cycles 1847system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 16832000 # number of demand (read+write) miss cycles 1848system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4807500 # number of demand (read+write) miss cycles 1849system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733172000 # number of demand (read+write) miss cycles 1850system.cpu1.l2cache.demand_miss_latency::cpu1.data 3265436497 # number of demand (read+write) miss cycles 1851system.cpu1.l2cache.demand_miss_latency::total 4020247997 # number of demand (read+write) miss cycles 1852system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 16832000 # number of overall miss cycles 1853system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4807500 # number of overall miss cycles 1854system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733172000 # number of overall miss cycles 1855system.cpu1.l2cache.overall_miss_latency::cpu1.data 3265436497 # number of overall miss cycles 1856system.cpu1.l2cache.overall_miss_latency::total 4020247997 # number of overall miss cycles 1857system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24069 # number of ReadReq accesses(hits+misses) 1858system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2641 # number of ReadReq accesses(hits+misses) 1859system.cpu1.l2cache.ReadReq_accesses::total 26710 # number of ReadReq accesses(hits+misses) 1860system.cpu1.l2cache.Writeback_accesses::writebacks 95329 # number of Writeback accesses(hits+misses) 1861system.cpu1.l2cache.Writeback_accesses::total 95329 # number of Writeback accesses(hits+misses) 1862system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28987 # number of UpgradeReq accesses(hits+misses) 1863system.cpu1.l2cache.UpgradeReq_accesses::total 28987 # number of UpgradeReq accesses(hits+misses) 1864system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23310 # number of SCUpgradeReq accesses(hits+misses) 1865system.cpu1.l2cache.SCUpgradeReq_accesses::total 23310 # number of SCUpgradeReq accesses(hits+misses) 1866system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49948 # number of ReadExReq accesses(hits+misses) 1867system.cpu1.l2cache.ReadExReq_accesses::total 49948 # number of ReadExReq accesses(hits+misses) 1868system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 838149 # number of ReadCleanReq accesses(hits+misses) 1869system.cpu1.l2cache.ReadCleanReq_accesses::total 838149 # number of ReadCleanReq accesses(hits+misses) 1870system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 147233 # number of ReadSharedReq accesses(hits+misses) 1871system.cpu1.l2cache.ReadSharedReq_accesses::total 147233 # number of ReadSharedReq accesses(hits+misses) 1872system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24069 # number of demand (read+write) accesses 1873system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2641 # number of demand (read+write) accesses 1874system.cpu1.l2cache.demand_accesses::cpu1.inst 838149 # number of demand (read+write) accesses 1875system.cpu1.l2cache.demand_accesses::cpu1.data 197181 # number of demand (read+write) accesses 1876system.cpu1.l2cache.demand_accesses::total 1062040 # number of demand (read+write) accesses 1877system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24069 # number of overall (read+write) accesses 1878system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2641 # number of overall (read+write) accesses 1879system.cpu1.l2cache.overall_accesses::cpu1.inst 838149 # number of overall (read+write) accesses 1880system.cpu1.l2cache.overall_accesses::cpu1.data 197181 # number of overall (read+write) accesses 1881system.cpu1.l2cache.overall_accesses::total 1062040 # number of overall (read+write) accesses 1882system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030080 # miss rate for ReadReq accesses 1883system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090875 # miss rate for ReadReq accesses 1884system.cpu1.l2cache.ReadReq_miss_rate::total 0.036091 # miss rate for ReadReq accesses 1885system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.955980 # miss rate for UpgradeReq accesses 1886system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.955980 # miss rate for UpgradeReq accesses 1887system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.966366 # miss rate for SCUpgradeReq accesses 1888system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.966366 # miss rate for SCUpgradeReq accesses 1889system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.644450 # miss rate for ReadExReq accesses 1890system.cpu1.l2cache.ReadExReq_miss_rate::total 0.644450 # miss rate for ReadExReq accesses 1891system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.015671 # miss rate for ReadCleanReq accesses 1892system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.015671 # miss rate for ReadCleanReq accesses 1893system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.448188 # miss rate for ReadSharedReq accesses 1894system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.448188 # miss rate for ReadSharedReq accesses 1895system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030080 # miss rate for demand accesses 1896system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090875 # miss rate for demand accesses 1897system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.015671 # miss rate for demand accesses 1898system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.497903 # miss rate for demand accesses 1899system.cpu1.l2cache.demand_miss_rate::total 0.105717 # miss rate for demand accesses 1900system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030080 # miss rate for overall accesses 1901system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090875 # miss rate for overall accesses 1902system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.015671 # miss rate for overall accesses 1903system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.497903 # miss rate for overall accesses 1904system.cpu1.l2cache.overall_miss_rate::total 0.105717 # miss rate for overall accesses 1905system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23248.618785 # average ReadReq miss latency 1906system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20031.250000 # average ReadReq miss latency 1907system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22447.614108 # average ReadReq miss latency 1908system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19673.396846 # average UpgradeReq miss latency 1909system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19673.396846 # average UpgradeReq miss latency 1910system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21310.263695 # average SCUpgradeReq miss latency 1911system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21310.263695 # average SCUpgradeReq miss latency 1912system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1913system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1914system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52381.978316 # average ReadExReq miss latency 1915system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52381.978316 # average ReadExReq miss latency 1916system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55818.195660 # average ReadCleanReq miss latency 1917system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55818.195660 # average ReadCleanReq miss latency 1918system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23933.336319 # average ReadSharedReq miss latency 1919system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23933.336319 # average ReadSharedReq miss latency 1920system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23248.618785 # average overall miss latency 1921system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20031.250000 # average overall miss latency 1922system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 55818.195660 # average overall miss latency 1923system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33260.707671 # average overall miss latency 1924system.cpu1.l2cache.demand_avg_miss_latency::total 35806.833134 # average overall miss latency 1925system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23248.618785 # average overall miss latency 1926system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20031.250000 # average overall miss latency 1927system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 55818.195660 # average overall miss latency 1928system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33260.707671 # average overall miss latency 1929system.cpu1.l2cache.overall_avg_miss_latency::total 35806.833134 # average overall miss latency 1930system.cpu1.l2cache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked 1931system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1932system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1933system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1934system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 27 # average number of cycles each access was blocked 1935system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1936system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1937system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1938system.cpu1.l2cache.writebacks::writebacks 25088 # number of writebacks 1939system.cpu1.l2cache.writebacks::total 25088 # number of writebacks 1940system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 258 # number of ReadExReq MSHR hits 1941system.cpu1.l2cache.ReadExReq_mshr_hits::total 258 # number of ReadExReq MSHR hits 1942system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 13 # number of ReadCleanReq MSHR hits 1943system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 1944system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 45 # number of ReadSharedReq MSHR hits 1945system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 45 # number of ReadSharedReq MSHR hits 1946system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits 1947system.cpu1.l2cache.demand_mshr_hits::cpu1.data 303 # number of demand (read+write) MSHR hits 1948system.cpu1.l2cache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits 1949system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits 1950system.cpu1.l2cache.overall_mshr_hits::cpu1.data 303 # number of overall MSHR hits 1951system.cpu1.l2cache.overall_mshr_hits::total 316 # number of overall MSHR hits 1952system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 724 # number of ReadReq MSHR misses 1953system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 240 # number of ReadReq MSHR misses 1954system.cpu1.l2cache.ReadReq_mshr_misses::total 964 # number of ReadReq MSHR misses 1955system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 1571 # number of CleanEvict MSHR misses 1956system.cpu1.l2cache.CleanEvict_mshr_misses::total 1571 # number of CleanEvict MSHR misses 1957system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18681 # number of HardPFReq MSHR misses 1958system.cpu1.l2cache.HardPFReq_mshr_misses::total 18681 # number of HardPFReq MSHR misses 1959system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27711 # number of UpgradeReq MSHR misses 1960system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27711 # number of UpgradeReq MSHR misses 1961system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22526 # number of SCUpgradeReq MSHR misses 1962system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22526 # number of SCUpgradeReq MSHR misses 1963system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31931 # number of ReadExReq MSHR misses 1964system.cpu1.l2cache.ReadExReq_mshr_misses::total 31931 # number of ReadExReq MSHR misses 1965system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13122 # number of ReadCleanReq MSHR misses 1966system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13122 # number of ReadCleanReq MSHR misses 1967system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 65943 # number of ReadSharedReq MSHR misses 1968system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 65943 # number of ReadSharedReq MSHR misses 1969system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 724 # number of demand (read+write) MSHR misses 1970system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 240 # number of demand (read+write) MSHR misses 1971system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13122 # number of demand (read+write) MSHR misses 1972system.cpu1.l2cache.demand_mshr_misses::cpu1.data 97874 # number of demand (read+write) MSHR misses 1973system.cpu1.l2cache.demand_mshr_misses::total 111960 # number of demand (read+write) MSHR misses 1974system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 724 # number of overall MSHR misses 1975system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 240 # number of overall MSHR misses 1976system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13122 # number of overall MSHR misses 1977system.cpu1.l2cache.overall_mshr_misses::cpu1.data 97874 # number of overall MSHR misses 1978system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18681 # number of overall MSHR misses 1979system.cpu1.l2cache.overall_mshr_misses::total 130641 # number of overall MSHR misses 1980system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1981system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2845 # number of ReadReq MSHR uncacheable 1982system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2957 # number of ReadReq MSHR uncacheable 1983system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2191 # number of WriteReq MSHR uncacheable 1984system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2191 # number of WriteReq MSHR uncacheable 1985system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1986system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5036 # number of overall MSHR uncacheable misses 1987system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5148 # number of overall MSHR uncacheable misses 1988system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 12488000 # number of ReadReq MSHR miss cycles 1989system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3367500 # number of ReadReq MSHR miss cycles 1990system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15855500 # number of ReadReq MSHR miss cycles 1991system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1045426686 # number of HardPFReq MSHR miss cycles 1992system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1045426686 # number of HardPFReq MSHR miss cycles 1993system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 554064000 # number of UpgradeReq MSHR miss cycles 1994system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 554064000 # number of UpgradeReq MSHR miss cycles 1995system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 417044500 # number of SCUpgradeReq MSHR miss cycles 1996system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 417044500 # number of SCUpgradeReq MSHR miss cycles 1997system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1323500 # number of SCUpgradeFailReq MSHR miss cycles 1998system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1323500 # number of SCUpgradeFailReq MSHR miss cycles 1999system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1465371000 # number of ReadExReq MSHR miss cycles 2000system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1465371000 # number of ReadExReq MSHR miss cycles 2001system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 653754000 # number of ReadCleanReq MSHR miss cycles 2002system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 653754000 # number of ReadCleanReq MSHR miss cycles 2003system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1181307497 # number of ReadSharedReq MSHR miss cycles 2004system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1181307497 # number of ReadSharedReq MSHR miss cycles 2005system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 12488000 # number of demand (read+write) MSHR miss cycles 2006system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3367500 # number of demand (read+write) MSHR miss cycles 2007system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 653754000 # number of demand (read+write) MSHR miss cycles 2008system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2646678497 # number of demand (read+write) MSHR miss cycles 2009system.cpu1.l2cache.demand_mshr_miss_latency::total 3316287997 # number of demand (read+write) MSHR miss cycles 2010system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 12488000 # number of overall MSHR miss cycles 2011system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3367500 # number of overall MSHR miss cycles 2012system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 653754000 # number of overall MSHR miss cycles 2013system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2646678497 # number of overall MSHR miss cycles 2014system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1045426686 # number of overall MSHR miss cycles 2015system.cpu1.l2cache.overall_mshr_miss_latency::total 4361714683 # number of overall MSHR miss cycles 2016system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14231000 # number of ReadReq MSHR uncacheable cycles 2017system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 333495000 # number of ReadReq MSHR uncacheable cycles 2018system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 347726000 # number of ReadReq MSHR uncacheable cycles 2019system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 208256000 # number of WriteReq MSHR uncacheable cycles 2020system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 208256000 # number of WriteReq MSHR uncacheable cycles 2021system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14231000 # number of overall MSHR uncacheable cycles 2022system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 541751000 # number of overall MSHR uncacheable cycles 2023system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 555982000 # number of overall MSHR uncacheable cycles 2024system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for ReadReq accesses 2025system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for ReadReq accesses 2026system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.036091 # mshr miss rate for ReadReq accesses 2027system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2028system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2029system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2030system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2031system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.955980 # mshr miss rate for UpgradeReq accesses 2032system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.955980 # mshr miss rate for UpgradeReq accesses 2033system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966366 # mshr miss rate for SCUpgradeReq accesses 2034system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966366 # mshr miss rate for SCUpgradeReq accesses 2035system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639285 # mshr miss rate for ReadExReq accesses 2036system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639285 # mshr miss rate for ReadExReq accesses 2037system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for ReadCleanReq accesses 2038system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.015656 # mshr miss rate for ReadCleanReq accesses 2039system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.447882 # mshr miss rate for ReadSharedReq accesses 2040system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.447882 # mshr miss rate for ReadSharedReq accesses 2041system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for demand accesses 2042system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for demand accesses 2043system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for demand accesses 2044system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for demand accesses 2045system.cpu1.l2cache.demand_mshr_miss_rate::total 0.105420 # mshr miss rate for demand accesses 2046system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for overall accesses 2047system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for overall accesses 2048system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for overall accesses 2049system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for overall accesses 2050system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2051system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123009 # mshr miss rate for overall accesses 2052system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average ReadReq mshr miss latency 2053system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average ReadReq mshr miss latency 2054system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16447.614108 # average ReadReq mshr miss latency 2055system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average HardPFReq mshr miss latency 2056system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55962.030191 # average HardPFReq mshr miss latency 2057system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19994.370467 # average UpgradeReq mshr miss latency 2058system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19994.370467 # average UpgradeReq mshr miss latency 2059system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18513.917251 # average SCUpgradeReq mshr miss latency 2060system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18513.917251 # average SCUpgradeReq mshr miss latency 2061system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2062system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2063system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45891.797939 # average ReadExReq mshr miss latency 2064system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45891.797939 # average ReadExReq mshr miss latency 2065system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average ReadCleanReq mshr miss latency 2066system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49821.216278 # average ReadCleanReq mshr miss latency 2067system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.069681 # average ReadSharedReq mshr miss latency 2068system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.069681 # average ReadSharedReq mshr miss latency 2069system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency 2070system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency 2071system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency 2072system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency 2073system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29620.292935 # average overall mshr miss latency 2074system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency 2075system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency 2076system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency 2077system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency 2078system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average overall mshr miss latency 2079system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33387.027679 # average overall mshr miss latency 2080system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average ReadReq mshr uncacheable latency 2081system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117221.441125 # average ReadReq mshr uncacheable latency 2082system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117594.183294 # average ReadReq mshr uncacheable latency 2083system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95050.661798 # average WriteReq mshr uncacheable latency 2084system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 95050.661798 # average WriteReq mshr uncacheable latency 2085system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average overall mshr uncacheable latency 2086system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 107575.655282 # average overall mshr uncacheable latency 2087system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 107999.611500 # average overall mshr uncacheable latency 2088system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2089system.cpu1.toL2Bus.snoop_filter.tot_requests 2085429 # Total number of requests made to the snoop filter. 2090system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1050114 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2091system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2092system.cpu1.toL2Bus.snoop_filter.tot_snoops 105283 # Total number of snoops made to the snoop filter. 2093system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 105064 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2094system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2095system.cpu1.toL2Bus.trans_dist::ReadReq 32952 # Transaction distribution 2096system.cpu1.toL2Bus.trans_dist::ReadResp 1055933 # Transaction distribution 2097system.cpu1.toL2Bus.trans_dist::WriteReq 2191 # Transaction distribution 2098system.cpu1.toL2Bus.trans_dist::WriteResp 2191 # Transaction distribution 2099system.cpu1.toL2Bus.trans_dist::Writeback 125445 # Transaction distribution 2100system.cpu1.toL2Bus.trans_dist::CleanEvict 933113 # Transaction distribution 2101system.cpu1.toL2Bus.trans_dist::HardPFReq 22957 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::UpgradeReq 71384 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41419 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::UpgradeResp 84915 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution 2106system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 2107system.cpu1.toL2Bus.trans_dist::ReadExReq 57410 # Transaction distribution 2108system.cpu1.toL2Bus.trans_dist::ReadExResp 54585 # Transaction distribution 2109system.cpu1.toL2Bus.trans_dist::ReadCleanReq 838149 # Transaction distribution 2110system.cpu1.toL2Bus.trans_dist::ReadSharedReq 236592 # Transaction distribution 2111system.cpu1.toL2Bus.trans_dist::InvalidateReq 39 # Transaction distribution 2112system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2498025 # Packet count per connected master and slave (bytes) 2113system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 734861 # Packet count per connected master and slave (bytes) 2114system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6388 # Packet count per connected master and slave (bytes) 2115system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50317 # Packet count per connected master and slave (bytes) 2116system.cpu1.toL2Bus.pkt_count::total 3289591 # Packet count per connected master and slave (bytes) 2117system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 53648704 # Cumulative packet size per connected master and slave (bytes) 2118system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21442516 # Cumulative packet size per connected master and slave (bytes) 2119system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10564 # Cumulative packet size per connected master and slave (bytes) 2120system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 96276 # Cumulative packet size per connected master and slave (bytes) 2121system.cpu1.toL2Bus.pkt_size::total 75198060 # Cumulative packet size per connected master and slave (bytes) 2122system.cpu1.toL2Bus.snoops 344587 # Total snoops (count) 2123system.cpu1.toL2Bus.snoop_fanout::samples 2379730 # Request fanout histogram 2124system.cpu1.toL2Bus.snoop_fanout::mean 0.062577 # Request fanout histogram 2125system.cpu1.toL2Bus.snoop_fanout::stdev 0.242581 # Request fanout histogram 2126system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2127system.cpu1.toL2Bus.snoop_fanout::0 2231032 93.75% 93.75% # Request fanout histogram 2128system.cpu1.toL2Bus.snoop_fanout::1 148479 6.24% 99.99% # Request fanout histogram 2129system.cpu1.toL2Bus.snoop_fanout::2 219 0.01% 100.00% # Request fanout histogram 2130system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2131system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2132system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2133system.cpu1.toL2Bus.snoop_fanout::total 2379730 # Request fanout histogram 2134system.cpu1.toL2Bus.reqLayer0.occupancy 1153078495 # Layer occupancy (ticks) 2135system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2136system.cpu1.toL2Bus.snoopLayer0.occupancy 79714518 # Layer occupancy (ticks) 2137system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2138system.cpu1.toL2Bus.respLayer0.occupancy 1257481819 # Layer occupancy (ticks) 2139system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2140system.cpu1.toL2Bus.respLayer1.occupancy 326951344 # Layer occupancy (ticks) 2141system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2142system.cpu1.toL2Bus.respLayer2.occupancy 3747000 # Layer occupancy (ticks) 2143system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2144system.cpu1.toL2Bus.respLayer3.occupancy 26275944 # Layer occupancy (ticks) 2145system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2146system.iobus.trans_dist::ReadReq 31009 # Transaction distribution 2147system.iobus.trans_dist::ReadResp 31009 # Transaction distribution 2148system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 2149system.iobus.trans_dist::WriteResp 59425 # Transaction distribution 2150system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) 2151system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2152system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2153system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2154system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2157system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2162system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2163system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2164system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2165system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2166system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2168system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2169system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2170system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2171system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) 2172system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2173system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2174system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) 2175system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) 2176system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2177system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2179system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2187system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2188system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2189system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2190system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2191system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2192system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2193system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2194system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2195system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2196system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) 2197system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2198system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2199system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) 2200system.iobus.reqLayer0.occupancy 40103000 # Layer occupancy (ticks) 2201system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2202system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2203system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2204system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2205system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2206system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2207system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2208system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2209system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2210system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 2211system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2212system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2213system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2214system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2215system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2216system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2217system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2218system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2219system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2220system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2221system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2222system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2223system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2224system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2225system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2226system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2227system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2228system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2229system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2230system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2231system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2232system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2233system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2234system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2235system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2236system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2237system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2238system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2239system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2240system.iobus.reqLayer27.occupancy 186411762 # Layer occupancy (ticks) 2241system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2242system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2243system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2244system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) 2245system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2246system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2247system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2248system.iocache.tags.replacements 36433 # number of replacements 2249system.iocache.tags.tagsinuse 14.472862 # Cycle average of tags in use 2250system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2251system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. 2252system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2253system.iocache.tags.warmup_cycle 271656669000 # Cycle when the warmup percentage was hit. 2254system.iocache.tags.occ_blocks::realview.ide 14.472862 # Average occupied blocks per requestor 2255system.iocache.tags.occ_percent::realview.ide 0.904554 # Average percentage of cache occupancy 2256system.iocache.tags.occ_percent::total 0.904554 # Average percentage of cache occupancy 2257system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2258system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2259system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2260system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2261system.iocache.tags.data_accesses 328203 # Number of data accesses 2262system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2263system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2264system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2265system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2266system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2267system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2268system.iocache.overall_misses::realview.ide 243 # number of overall misses 2269system.iocache.overall_misses::total 243 # number of overall misses 2270system.iocache.ReadReq_miss_latency::realview.ide 31866877 # number of ReadReq miss cycles 2271system.iocache.ReadReq_miss_latency::total 31866877 # number of ReadReq miss cycles 2272system.iocache.WriteLineReq_miss_latency::realview.ide 4715834885 # number of WriteLineReq miss cycles 2273system.iocache.WriteLineReq_miss_latency::total 4715834885 # number of WriteLineReq miss cycles 2274system.iocache.demand_miss_latency::realview.ide 31866877 # number of demand (read+write) miss cycles 2275system.iocache.demand_miss_latency::total 31866877 # number of demand (read+write) miss cycles 2276system.iocache.overall_miss_latency::realview.ide 31866877 # number of overall miss cycles 2277system.iocache.overall_miss_latency::total 31866877 # number of overall miss cycles 2278system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2279system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2280system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2281system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2282system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2283system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2284system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2285system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2286system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2287system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2288system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2289system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2290system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2291system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2292system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2293system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2294system.iocache.ReadReq_avg_miss_latency::realview.ide 131139.411523 # average ReadReq miss latency 2295system.iocache.ReadReq_avg_miss_latency::total 131139.411523 # average ReadReq miss latency 2296system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130185.371163 # average WriteLineReq miss latency 2297system.iocache.WriteLineReq_avg_miss_latency::total 130185.371163 # average WriteLineReq miss latency 2298system.iocache.demand_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency 2299system.iocache.demand_avg_miss_latency::total 131139.411523 # average overall miss latency 2300system.iocache.overall_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency 2301system.iocache.overall_avg_miss_latency::total 131139.411523 # average overall miss latency 2302system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked 2303system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2304system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked 2305system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2306system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked 2307system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2308system.iocache.fast_writes 0 # number of fast writes performed 2309system.iocache.cache_copies 0 # number of cache copies performed 2310system.iocache.writebacks::writebacks 36190 # number of writebacks 2311system.iocache.writebacks::total 36190 # number of writebacks 2312system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2313system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2314system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2315system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2316system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2317system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2318system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2319system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2320system.iocache.ReadReq_mshr_miss_latency::realview.ide 19716877 # number of ReadReq MSHR miss cycles 2321system.iocache.ReadReq_mshr_miss_latency::total 19716877 # number of ReadReq MSHR miss cycles 2322system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904634885 # number of WriteLineReq MSHR miss cycles 2323system.iocache.WriteLineReq_mshr_miss_latency::total 2904634885 # number of WriteLineReq MSHR miss cycles 2324system.iocache.demand_mshr_miss_latency::realview.ide 19716877 # number of demand (read+write) MSHR miss cycles 2325system.iocache.demand_mshr_miss_latency::total 19716877 # number of demand (read+write) MSHR miss cycles 2326system.iocache.overall_mshr_miss_latency::realview.ide 19716877 # number of overall MSHR miss cycles 2327system.iocache.overall_mshr_miss_latency::total 19716877 # number of overall MSHR miss cycles 2328system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2329system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2330system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2331system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2332system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2333system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2334system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2335system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2336system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81139.411523 # average ReadReq mshr miss latency 2337system.iocache.ReadReq_avg_mshr_miss_latency::total 81139.411523 # average ReadReq mshr miss latency 2338system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80185.371163 # average WriteLineReq mshr miss latency 2339system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80185.371163 # average WriteLineReq mshr miss latency 2340system.iocache.demand_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency 2341system.iocache.demand_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency 2342system.iocache.overall_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency 2343system.iocache.overall_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency 2344system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2345system.l2c.tags.replacements 133318 # number of replacements 2346system.l2c.tags.tagsinuse 64014.997062 # Cycle average of tags in use 2347system.l2c.tags.total_refs 446453 # Total number of references to valid blocks. 2348system.l2c.tags.sampled_refs 198047 # Sample count of references to valid blocks. 2349system.l2c.tags.avg_refs 2.254278 # Average number of references to valid blocks. 2350system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2351system.l2c.tags.occ_blocks::writebacks 12007.955719 # Average occupied blocks per requestor 2352system.l2c.tags.occ_blocks::cpu0.dtb.walker 82.059666 # Average occupied blocks per requestor 2353system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029625 # Average occupied blocks per requestor 2354system.l2c.tags.occ_blocks::cpu0.inst 9722.429733 # Average occupied blocks per requestor 2355system.l2c.tags.occ_blocks::cpu0.data 3069.037039 # Average occupied blocks per requestor 2356system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34559.641433 # Average occupied blocks per requestor 2357system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.516745 # Average occupied blocks per requestor 2358system.l2c.tags.occ_blocks::cpu1.inst 1816.838650 # Average occupied blocks per requestor 2359system.l2c.tags.occ_blocks::cpu1.data 555.114204 # Average occupied blocks per requestor 2360system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2192.374249 # Average occupied blocks per requestor 2361system.l2c.tags.occ_percent::writebacks 0.183227 # Average percentage of cache occupancy 2362system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001252 # Average percentage of cache occupancy 2363system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2364system.l2c.tags.occ_percent::cpu0.inst 0.148353 # Average percentage of cache occupancy 2365system.l2c.tags.occ_percent::cpu0.data 0.046830 # Average percentage of cache occupancy 2366system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.527338 # Average percentage of cache occupancy 2367system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000145 # Average percentage of cache occupancy 2368system.l2c.tags.occ_percent::cpu1.inst 0.027723 # Average percentage of cache occupancy 2369system.l2c.tags.occ_percent::cpu1.data 0.008470 # Average percentage of cache occupancy 2370system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033453 # Average percentage of cache occupancy 2371system.l2c.tags.occ_percent::total 0.976791 # Average percentage of cache occupancy 2372system.l2c.tags.occ_task_id_blocks::1022 30866 # Occupied blocks per task id 2373system.l2c.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id 2374system.l2c.tags.occ_task_id_blocks::1024 33781 # Occupied blocks per task id 2375system.l2c.tags.age_task_id_blocks_1022::2 78 # Occupied blocks per task id 2376system.l2c.tags.age_task_id_blocks_1022::3 5648 # Occupied blocks per task id 2377system.l2c.tags.age_task_id_blocks_1022::4 25140 # Occupied blocks per task id 2378system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2379system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id 2380system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 2381system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 2382system.l2c.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id 2383system.l2c.tags.age_task_id_blocks_1024::3 2821 # Occupied blocks per task id 2384system.l2c.tags.age_task_id_blocks_1024::4 30623 # Occupied blocks per task id 2385system.l2c.tags.occ_task_id_percent::1022 0.470978 # Percentage of cache occupancy per task id 2386system.l2c.tags.occ_task_id_percent::1023 0.001251 # Percentage of cache occupancy per task id 2387system.l2c.tags.occ_task_id_percent::1024 0.515457 # Percentage of cache occupancy per task id 2388system.l2c.tags.tag_accesses 5802831 # Number of tag accesses 2389system.l2c.tags.data_accesses 5802831 # Number of data accesses 2390system.l2c.Writeback_hits::writebacks 230256 # number of Writeback hits 2391system.l2c.Writeback_hits::total 230256 # number of Writeback hits 2392system.l2c.UpgradeReq_hits::cpu0.data 3083 # number of UpgradeReq hits 2393system.l2c.UpgradeReq_hits::cpu1.data 464 # number of UpgradeReq hits 2394system.l2c.UpgradeReq_hits::total 3547 # number of UpgradeReq hits 2395system.l2c.SCUpgradeReq_hits::cpu0.data 148 # number of SCUpgradeReq hits 2396system.l2c.SCUpgradeReq_hits::cpu1.data 197 # number of SCUpgradeReq hits 2397system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits 2398system.l2c.ReadExReq_hits::cpu0.data 4599 # number of ReadExReq hits 2399system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits 2400system.l2c.ReadExReq_hits::total 5978 # number of ReadExReq hits 2401system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 467 # number of ReadSharedReq hits 2402system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits 2403system.l2c.ReadSharedReq_hits::cpu0.inst 52086 # number of ReadSharedReq hits 2404system.l2c.ReadSharedReq_hits::cpu0.data 51828 # number of ReadSharedReq hits 2405system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 50532 # number of ReadSharedReq hits 2406system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 70 # number of ReadSharedReq hits 2407system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits 2408system.l2c.ReadSharedReq_hits::cpu1.inst 10095 # number of ReadSharedReq hits 2409system.l2c.ReadSharedReq_hits::cpu1.data 4893 # number of ReadSharedReq hits 2410system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3282 # number of ReadSharedReq hits 2411system.l2c.ReadSharedReq_hits::total 173352 # number of ReadSharedReq hits 2412system.l2c.demand_hits::cpu0.dtb.walker 467 # number of demand (read+write) hits 2413system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits 2414system.l2c.demand_hits::cpu0.inst 52086 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.data 56427 # number of demand (read+write) hits 2416system.l2c.demand_hits::cpu0.l2cache.prefetcher 50532 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu1.dtb.walker 70 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu1.inst 10095 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu1.data 6272 # number of demand (read+write) hits 2421system.l2c.demand_hits::cpu1.l2cache.prefetcher 3282 # number of demand (read+write) hits 2422system.l2c.demand_hits::total 179330 # number of demand (read+write) hits 2423system.l2c.overall_hits::cpu0.dtb.walker 467 # number of overall hits 2424system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits 2425system.l2c.overall_hits::cpu0.inst 52086 # number of overall hits 2426system.l2c.overall_hits::cpu0.data 56427 # number of overall hits 2427system.l2c.overall_hits::cpu0.l2cache.prefetcher 50532 # number of overall hits 2428system.l2c.overall_hits::cpu1.dtb.walker 70 # number of overall hits 2429system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits 2430system.l2c.overall_hits::cpu1.inst 10095 # number of overall hits 2431system.l2c.overall_hits::cpu1.data 6272 # number of overall hits 2432system.l2c.overall_hits::cpu1.l2cache.prefetcher 3282 # number of overall hits 2433system.l2c.overall_hits::total 179330 # number of overall hits 2434system.l2c.UpgradeReq_misses::cpu0.data 9481 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::cpu1.data 2162 # number of UpgradeReq misses 2436system.l2c.UpgradeReq_misses::total 11643 # number of UpgradeReq misses 2437system.l2c.SCUpgradeReq_misses::cpu0.data 497 # number of SCUpgradeReq misses 2438system.l2c.SCUpgradeReq_misses::cpu1.data 1197 # number of SCUpgradeReq misses 2439system.l2c.SCUpgradeReq_misses::total 1694 # number of SCUpgradeReq misses 2440system.l2c.ReadExReq_misses::cpu0.data 11009 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::cpu1.data 7938 # number of ReadExReq misses 2442system.l2c.ReadExReq_misses::total 18947 # number of ReadExReq misses 2443system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 137 # number of ReadSharedReq misses 2444system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2445system.l2c.ReadSharedReq_misses::cpu0.inst 22412 # number of ReadSharedReq misses 2446system.l2c.ReadSharedReq_misses::cpu0.data 9738 # number of ReadSharedReq misses 2447system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133466 # number of ReadSharedReq misses 2448system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 16 # number of ReadSharedReq misses 2449system.l2c.ReadSharedReq_misses::cpu1.inst 3021 # number of ReadSharedReq misses 2450system.l2c.ReadSharedReq_misses::cpu1.data 1593 # number of ReadSharedReq misses 2451system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5720 # number of ReadSharedReq misses 2452system.l2c.ReadSharedReq_misses::total 176104 # number of ReadSharedReq misses 2453system.l2c.demand_misses::cpu0.dtb.walker 137 # number of demand (read+write) misses 2454system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2455system.l2c.demand_misses::cpu0.inst 22412 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu0.data 20747 # number of demand (read+write) misses 2457system.l2c.demand_misses::cpu0.l2cache.prefetcher 133466 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu1.inst 3021 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu1.data 9531 # number of demand (read+write) misses 2461system.l2c.demand_misses::cpu1.l2cache.prefetcher 5720 # number of demand (read+write) misses 2462system.l2c.demand_misses::total 195051 # number of demand (read+write) misses 2463system.l2c.overall_misses::cpu0.dtb.walker 137 # number of overall misses 2464system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2465system.l2c.overall_misses::cpu0.inst 22412 # number of overall misses 2466system.l2c.overall_misses::cpu0.data 20747 # number of overall misses 2467system.l2c.overall_misses::cpu0.l2cache.prefetcher 133466 # number of overall misses 2468system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses 2469system.l2c.overall_misses::cpu1.inst 3021 # number of overall misses 2470system.l2c.overall_misses::cpu1.data 9531 # number of overall misses 2471system.l2c.overall_misses::cpu1.l2cache.prefetcher 5720 # number of overall misses 2472system.l2c.overall_misses::total 195051 # number of overall misses 2473system.l2c.UpgradeReq_miss_latency::cpu0.data 34581000 # number of UpgradeReq miss cycles 2474system.l2c.UpgradeReq_miss_latency::cpu1.data 5348500 # number of UpgradeReq miss cycles 2475system.l2c.UpgradeReq_miss_latency::total 39929500 # number of UpgradeReq miss cycles 2476system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3790500 # number of SCUpgradeReq miss cycles 2477system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2694500 # number of SCUpgradeReq miss cycles 2478system.l2c.SCUpgradeReq_miss_latency::total 6485000 # number of SCUpgradeReq miss cycles 2479system.l2c.ReadExReq_miss_latency::cpu0.data 1642305000 # number of ReadExReq miss cycles 2480system.l2c.ReadExReq_miss_latency::cpu1.data 1048460500 # number of ReadExReq miss cycles 2481system.l2c.ReadExReq_miss_latency::total 2690765500 # number of ReadExReq miss cycles 2482system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 19306500 # number of ReadSharedReq miss cycles 2483system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles 2484system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2926929000 # number of ReadSharedReq miss cycles 2485system.l2c.ReadSharedReq_miss_latency::cpu0.data 1335340500 # number of ReadSharedReq miss cycles 2486system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20225428758 # number of ReadSharedReq miss cycles 2487system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 2276000 # number of ReadSharedReq miss cycles 2488system.l2c.ReadSharedReq_miss_latency::cpu1.inst 405795500 # number of ReadSharedReq miss cycles 2489system.l2c.ReadSharedReq_miss_latency::cpu1.data 223263000 # number of ReadSharedReq miss cycles 2490system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 972266423 # number of ReadSharedReq miss cycles 2491system.l2c.ReadSharedReq_miss_latency::total 26110738681 # number of ReadSharedReq miss cycles 2492system.l2c.demand_miss_latency::cpu0.dtb.walker 19306500 # number of demand (read+write) miss cycles 2493system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles 2494system.l2c.demand_miss_latency::cpu0.inst 2926929000 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::cpu0.data 2977645500 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20225428758 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu1.dtb.walker 2276000 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu1.inst 405795500 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::cpu1.data 1271723500 # number of demand (read+write) miss cycles 2500system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 972266423 # number of demand (read+write) miss cycles 2501system.l2c.demand_miss_latency::total 28801504181 # number of demand (read+write) miss cycles 2502system.l2c.overall_miss_latency::cpu0.dtb.walker 19306500 # number of overall miss cycles 2503system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles 2504system.l2c.overall_miss_latency::cpu0.inst 2926929000 # number of overall miss cycles 2505system.l2c.overall_miss_latency::cpu0.data 2977645500 # number of overall miss cycles 2506system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20225428758 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu1.dtb.walker 2276000 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu1.inst 405795500 # number of overall miss cycles 2509system.l2c.overall_miss_latency::cpu1.data 1271723500 # number of overall miss cycles 2510system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 972266423 # number of overall miss cycles 2511system.l2c.overall_miss_latency::total 28801504181 # number of overall miss cycles 2512system.l2c.Writeback_accesses::writebacks 230256 # number of Writeback accesses(hits+misses) 2513system.l2c.Writeback_accesses::total 230256 # number of Writeback accesses(hits+misses) 2514system.l2c.UpgradeReq_accesses::cpu0.data 12564 # number of UpgradeReq accesses(hits+misses) 2515system.l2c.UpgradeReq_accesses::cpu1.data 2626 # number of UpgradeReq accesses(hits+misses) 2516system.l2c.UpgradeReq_accesses::total 15190 # number of UpgradeReq accesses(hits+misses) 2517system.l2c.SCUpgradeReq_accesses::cpu0.data 645 # number of SCUpgradeReq accesses(hits+misses) 2518system.l2c.SCUpgradeReq_accesses::cpu1.data 1394 # number of SCUpgradeReq accesses(hits+misses) 2519system.l2c.SCUpgradeReq_accesses::total 2039 # number of SCUpgradeReq accesses(hits+misses) 2520system.l2c.ReadExReq_accesses::cpu0.data 15608 # number of ReadExReq accesses(hits+misses) 2521system.l2c.ReadExReq_accesses::cpu1.data 9317 # number of ReadExReq accesses(hits+misses) 2522system.l2c.ReadExReq_accesses::total 24925 # number of ReadExReq accesses(hits+misses) 2523system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 604 # number of ReadSharedReq accesses(hits+misses) 2524system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses) 2525system.l2c.ReadSharedReq_accesses::cpu0.inst 74498 # number of ReadSharedReq accesses(hits+misses) 2526system.l2c.ReadSharedReq_accesses::cpu0.data 61566 # number of ReadSharedReq accesses(hits+misses) 2527system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183998 # number of ReadSharedReq accesses(hits+misses) 2528system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 86 # number of ReadSharedReq accesses(hits+misses) 2529system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 13 # number of ReadSharedReq accesses(hits+misses) 2530system.l2c.ReadSharedReq_accesses::cpu1.inst 13116 # number of ReadSharedReq accesses(hits+misses) 2531system.l2c.ReadSharedReq_accesses::cpu1.data 6486 # number of ReadSharedReq accesses(hits+misses) 2532system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 9002 # number of ReadSharedReq accesses(hits+misses) 2533system.l2c.ReadSharedReq_accesses::total 349456 # number of ReadSharedReq accesses(hits+misses) 2534system.l2c.demand_accesses::cpu0.dtb.walker 604 # number of demand (read+write) accesses 2535system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses 2536system.l2c.demand_accesses::cpu0.inst 74498 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::cpu0.data 77174 # number of demand (read+write) accesses 2538system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183998 # number of demand (read+write) accesses 2539system.l2c.demand_accesses::cpu1.dtb.walker 86 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu1.itb.walker 13 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu1.inst 13116 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::cpu1.data 15803 # number of demand (read+write) accesses 2543system.l2c.demand_accesses::cpu1.l2cache.prefetcher 9002 # number of demand (read+write) accesses 2544system.l2c.demand_accesses::total 374381 # number of demand (read+write) accesses 2545system.l2c.overall_accesses::cpu0.dtb.walker 604 # number of overall (read+write) accesses 2546system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses 2547system.l2c.overall_accesses::cpu0.inst 74498 # number of overall (read+write) accesses 2548system.l2c.overall_accesses::cpu0.data 77174 # number of overall (read+write) accesses 2549system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183998 # number of overall (read+write) accesses 2550system.l2c.overall_accesses::cpu1.dtb.walker 86 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::cpu1.itb.walker 13 # number of overall (read+write) accesses 2552system.l2c.overall_accesses::cpu1.inst 13116 # number of overall (read+write) accesses 2553system.l2c.overall_accesses::cpu1.data 15803 # number of overall (read+write) accesses 2554system.l2c.overall_accesses::cpu1.l2cache.prefetcher 9002 # number of overall (read+write) accesses 2555system.l2c.overall_accesses::total 374381 # number of overall (read+write) accesses 2556system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754616 # miss rate for UpgradeReq accesses 2557system.l2c.UpgradeReq_miss_rate::cpu1.data 0.823305 # miss rate for UpgradeReq accesses 2558system.l2c.UpgradeReq_miss_rate::total 0.766491 # miss rate for UpgradeReq accesses 2559system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.770543 # miss rate for SCUpgradeReq accesses 2560system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.858680 # miss rate for SCUpgradeReq accesses 2561system.l2c.SCUpgradeReq_miss_rate::total 0.830799 # miss rate for SCUpgradeReq accesses 2562system.l2c.ReadExReq_miss_rate::cpu0.data 0.705343 # miss rate for ReadExReq accesses 2563system.l2c.ReadExReq_miss_rate::cpu1.data 0.851991 # miss rate for ReadExReq accesses 2564system.l2c.ReadExReq_miss_rate::total 0.760160 # miss rate for ReadExReq accesses 2565system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.226821 # miss rate for ReadSharedReq accesses 2566system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011494 # miss rate for ReadSharedReq accesses 2567system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.300840 # miss rate for ReadSharedReq accesses 2568system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158172 # miss rate for ReadSharedReq accesses 2569system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.725367 # miss rate for ReadSharedReq accesses 2570system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.186047 # miss rate for ReadSharedReq accesses 2571system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.230329 # miss rate for ReadSharedReq accesses 2572system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.245606 # miss rate for ReadSharedReq accesses 2573system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.635414 # miss rate for ReadSharedReq accesses 2574system.l2c.ReadSharedReq_miss_rate::total 0.503938 # miss rate for ReadSharedReq accesses 2575system.l2c.demand_miss_rate::cpu0.dtb.walker 0.226821 # miss rate for demand accesses 2576system.l2c.demand_miss_rate::cpu0.itb.walker 0.011494 # miss rate for demand accesses 2577system.l2c.demand_miss_rate::cpu0.inst 0.300840 # miss rate for demand accesses 2578system.l2c.demand_miss_rate::cpu0.data 0.268834 # miss rate for demand accesses 2579system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.725367 # miss rate for demand accesses 2580system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186047 # miss rate for demand accesses 2581system.l2c.demand_miss_rate::cpu1.inst 0.230329 # miss rate for demand accesses 2582system.l2c.demand_miss_rate::cpu1.data 0.603113 # miss rate for demand accesses 2583system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.635414 # miss rate for demand accesses 2584system.l2c.demand_miss_rate::total 0.520996 # miss rate for demand accesses 2585system.l2c.overall_miss_rate::cpu0.dtb.walker 0.226821 # miss rate for overall accesses 2586system.l2c.overall_miss_rate::cpu0.itb.walker 0.011494 # miss rate for overall accesses 2587system.l2c.overall_miss_rate::cpu0.inst 0.300840 # miss rate for overall accesses 2588system.l2c.overall_miss_rate::cpu0.data 0.268834 # miss rate for overall accesses 2589system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.725367 # miss rate for overall accesses 2590system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186047 # miss rate for overall accesses 2591system.l2c.overall_miss_rate::cpu1.inst 0.230329 # miss rate for overall accesses 2592system.l2c.overall_miss_rate::cpu1.data 0.603113 # miss rate for overall accesses 2593system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.635414 # miss rate for overall accesses 2594system.l2c.overall_miss_rate::total 0.520996 # miss rate for overall accesses 2595system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3647.400063 # average UpgradeReq miss latency 2596system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2473.866790 # average UpgradeReq miss latency 2597system.l2c.UpgradeReq_avg_miss_latency::total 3429.485528 # average UpgradeReq miss latency 2598system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7626.760563 # average SCUpgradeReq miss latency 2599system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2251.044277 # average SCUpgradeReq miss latency 2600system.l2c.SCUpgradeReq_avg_miss_latency::total 3828.217237 # average SCUpgradeReq miss latency 2601system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149178.399491 # average ReadExReq miss latency 2602system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132081.191736 # average ReadExReq miss latency 2603system.l2c.ReadExReq_avg_miss_latency::total 142015.385021 # average ReadExReq miss latency 2604system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140923.357664 # average ReadSharedReq miss latency 2605system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency 2606system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130596.510798 # average ReadSharedReq miss latency 2607system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137126.771411 # average ReadSharedReq miss latency 2608system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451 # average ReadSharedReq miss latency 2609system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142250 # average ReadSharedReq miss latency 2610system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134324.892420 # average ReadSharedReq miss latency 2611system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140152.542373 # average ReadSharedReq miss latency 2612system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378 # average ReadSharedReq miss latency 2613system.l2c.ReadSharedReq_avg_miss_latency::total 148268.856363 # average ReadSharedReq miss latency 2614system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140923.357664 # average overall miss latency 2615system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2616system.l2c.demand_avg_miss_latency::cpu0.inst 130596.510798 # average overall miss latency 2617system.l2c.demand_avg_miss_latency::cpu0.data 143521.738083 # average overall miss latency 2618system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451 # average overall miss latency 2619system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142250 # average overall miss latency 2620system.l2c.demand_avg_miss_latency::cpu1.inst 134324.892420 # average overall miss latency 2621system.l2c.demand_avg_miss_latency::cpu1.data 133430.227678 # average overall miss latency 2622system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378 # average overall miss latency 2623system.l2c.demand_avg_miss_latency::total 147661.402305 # average overall miss latency 2624system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140923.357664 # average overall miss latency 2625system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency 2626system.l2c.overall_avg_miss_latency::cpu0.inst 130596.510798 # average overall miss latency 2627system.l2c.overall_avg_miss_latency::cpu0.data 143521.738083 # average overall miss latency 2628system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451 # average overall miss latency 2629system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142250 # average overall miss latency 2630system.l2c.overall_avg_miss_latency::cpu1.inst 134324.892420 # average overall miss latency 2631system.l2c.overall_avg_miss_latency::cpu1.data 133430.227678 # average overall miss latency 2632system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378 # average overall miss latency 2633system.l2c.overall_avg_miss_latency::total 147661.402305 # average overall miss latency 2634system.l2c.blocked_cycles::no_mshrs 687 # number of cycles access was blocked 2635system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2636system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 2637system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2638system.l2c.avg_blocked_cycles::no_mshrs 229 # average number of cycles each access was blocked 2639system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2640system.l2c.fast_writes 0 # number of fast writes performed 2641system.l2c.cache_copies 0 # number of cache copies performed 2642system.l2c.writebacks::writebacks 102021 # number of writebacks 2643system.l2c.writebacks::total 102021 # number of writebacks 2644system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 6 # number of ReadSharedReq MSHR hits 2645system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits 2646system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 # number of ReadSharedReq MSHR hits 2647system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 2648system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits 2649system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 2650system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 2651system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits 2652system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits 2653system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 2654system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 2655system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits 2656system.l2c.CleanEvict_mshr_misses::writebacks 3105 # number of CleanEvict MSHR misses 2657system.l2c.CleanEvict_mshr_misses::total 3105 # number of CleanEvict MSHR misses 2658system.l2c.UpgradeReq_mshr_misses::cpu0.data 9481 # number of UpgradeReq MSHR misses 2659system.l2c.UpgradeReq_mshr_misses::cpu1.data 2162 # number of UpgradeReq MSHR misses 2660system.l2c.UpgradeReq_mshr_misses::total 11643 # number of UpgradeReq MSHR misses 2661system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 497 # number of SCUpgradeReq MSHR misses 2662system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1197 # number of SCUpgradeReq MSHR misses 2663system.l2c.SCUpgradeReq_mshr_misses::total 1694 # number of SCUpgradeReq MSHR misses 2664system.l2c.ReadExReq_mshr_misses::cpu0.data 11009 # number of ReadExReq MSHR misses 2665system.l2c.ReadExReq_mshr_misses::cpu1.data 7938 # number of ReadExReq MSHR misses 2666system.l2c.ReadExReq_mshr_misses::total 18947 # number of ReadExReq MSHR misses 2667system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 137 # number of ReadSharedReq MSHR misses 2668system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2669system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22406 # number of ReadSharedReq MSHR misses 2670system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9737 # number of ReadSharedReq MSHR misses 2671system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133466 # number of ReadSharedReq MSHR misses 2672system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadSharedReq MSHR misses 2673system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3015 # number of ReadSharedReq MSHR misses 2674system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1593 # number of ReadSharedReq MSHR misses 2675system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5720 # number of ReadSharedReq MSHR misses 2676system.l2c.ReadSharedReq_mshr_misses::total 176091 # number of ReadSharedReq MSHR misses 2677system.l2c.demand_mshr_misses::cpu0.dtb.walker 137 # number of demand (read+write) MSHR misses 2678system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2679system.l2c.demand_mshr_misses::cpu0.inst 22406 # number of demand (read+write) MSHR misses 2680system.l2c.demand_mshr_misses::cpu0.data 20746 # number of demand (read+write) MSHR misses 2681system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133466 # number of demand (read+write) MSHR misses 2682system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses 2683system.l2c.demand_mshr_misses::cpu1.inst 3015 # number of demand (read+write) MSHR misses 2684system.l2c.demand_mshr_misses::cpu1.data 9531 # number of demand (read+write) MSHR misses 2685system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5720 # number of demand (read+write) MSHR misses 2686system.l2c.demand_mshr_misses::total 195038 # number of demand (read+write) MSHR misses 2687system.l2c.overall_mshr_misses::cpu0.dtb.walker 137 # number of overall MSHR misses 2688system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2689system.l2c.overall_mshr_misses::cpu0.inst 22406 # number of overall MSHR misses 2690system.l2c.overall_mshr_misses::cpu0.data 20746 # number of overall MSHR misses 2691system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133466 # number of overall MSHR misses 2692system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses 2693system.l2c.overall_mshr_misses::cpu1.inst 3015 # number of overall MSHR misses 2694system.l2c.overall_mshr_misses::cpu1.data 9531 # number of overall MSHR misses 2695system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5720 # number of overall MSHR misses 2696system.l2c.overall_mshr_misses::total 195038 # number of overall MSHR misses 2697system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable 2698system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable 2699system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2700system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2841 # number of ReadReq MSHR uncacheable 2701system.l2c.ReadReq_mshr_uncacheable::total 38908 # number of ReadReq MSHR uncacheable 2702system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable 2703system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2191 # number of WriteReq MSHR uncacheable 2704system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable 2705system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses 2706system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses 2707system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2708system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5032 # number of overall MSHR uncacheable misses 2709system.l2c.overall_mshr_uncacheable_misses::total 69821 # number of overall MSHR uncacheable misses 2710system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 714754501 # number of UpgradeReq MSHR miss cycles 2711system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 161986000 # number of UpgradeReq MSHR miss cycles 2712system.l2c.UpgradeReq_mshr_miss_latency::total 876740501 # number of UpgradeReq MSHR miss cycles 2713system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 38415000 # number of SCUpgradeReq MSHR miss cycles 2714system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 91799500 # number of SCUpgradeReq MSHR miss cycles 2715system.l2c.SCUpgradeReq_mshr_miss_latency::total 130214500 # number of SCUpgradeReq MSHR miss cycles 2716system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1532215000 # number of ReadExReq MSHR miss cycles 2717system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 969080500 # number of ReadExReq MSHR miss cycles 2718system.l2c.ReadExReq_mshr_miss_latency::total 2501295500 # number of ReadExReq MSHR miss cycles 2719system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 17936500 # number of ReadSharedReq MSHR miss cycles 2720system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles 2721system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2702366000 # number of ReadSharedReq MSHR miss cycles 2722system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1237877500 # number of ReadSharedReq MSHR miss cycles 2723system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18890768758 # number of ReadSharedReq MSHR miss cycles 2724system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 2116000 # number of ReadSharedReq MSHR miss cycles 2725system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 375139500 # number of ReadSharedReq MSHR miss cycles 2726system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 207333000 # number of ReadSharedReq MSHR miss cycles 2727system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 915066423 # number of ReadSharedReq MSHR miss cycles 2728system.l2c.ReadSharedReq_mshr_miss_latency::total 24348726681 # number of ReadSharedReq MSHR miss cycles 2729system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 17936500 # number of demand (read+write) MSHR miss cycles 2730system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles 2731system.l2c.demand_mshr_miss_latency::cpu0.inst 2702366000 # number of demand (read+write) MSHR miss cycles 2732system.l2c.demand_mshr_miss_latency::cpu0.data 2770092500 # number of demand (read+write) MSHR miss cycles 2733system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18890768758 # number of demand (read+write) MSHR miss cycles 2734system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2116000 # number of demand (read+write) MSHR miss cycles 2735system.l2c.demand_mshr_miss_latency::cpu1.inst 375139500 # number of demand (read+write) MSHR miss cycles 2736system.l2c.demand_mshr_miss_latency::cpu1.data 1176413500 # number of demand (read+write) MSHR miss cycles 2737system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 915066423 # number of demand (read+write) MSHR miss cycles 2738system.l2c.demand_mshr_miss_latency::total 26850022181 # number of demand (read+write) MSHR miss cycles 2739system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 17936500 # number of overall MSHR miss cycles 2740system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles 2741system.l2c.overall_mshr_miss_latency::cpu0.inst 2702366000 # number of overall MSHR miss cycles 2742system.l2c.overall_mshr_miss_latency::cpu0.data 2770092500 # number of overall MSHR miss cycles 2743system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18890768758 # number of overall MSHR miss cycles 2744system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2116000 # number of overall MSHR miss cycles 2745system.l2c.overall_mshr_miss_latency::cpu1.inst 375139500 # number of overall MSHR miss cycles 2746system.l2c.overall_mshr_miss_latency::cpu1.data 1176413500 # number of overall MSHR miss cycles 2747system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 915066423 # number of overall MSHR miss cycles 2748system.l2c.overall_mshr_miss_latency::total 26850022181 # number of overall MSHR miss cycles 2749system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443682000 # number of ReadReq MSHR uncacheable cycles 2750system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5515186000 # number of ReadReq MSHR uncacheable cycles 2751system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11878500 # number of ReadReq MSHR uncacheable cycles 2752system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 282299000 # number of ReadReq MSHR uncacheable cycles 2753system.l2c.ReadReq_mshr_uncacheable_latency::total 6253045500 # number of ReadReq MSHR uncacheable cycles 2754system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4452219000 # number of WriteReq MSHR uncacheable cycles 2755system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 171006500 # number of WriteReq MSHR uncacheable cycles 2756system.l2c.WriteReq_mshr_uncacheable_latency::total 4623225500 # number of WriteReq MSHR uncacheable cycles 2757system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443682000 # number of overall MSHR uncacheable cycles 2758system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9967405000 # number of overall MSHR uncacheable cycles 2759system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11878500 # number of overall MSHR uncacheable cycles 2760system.l2c.overall_mshr_uncacheable_latency::cpu1.data 453305500 # number of overall MSHR uncacheable cycles 2761system.l2c.overall_mshr_uncacheable_latency::total 10876271000 # number of overall MSHR uncacheable cycles 2762system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2763system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2764system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754616 # mshr miss rate for UpgradeReq accesses 2765system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823305 # mshr miss rate for UpgradeReq accesses 2766system.l2c.UpgradeReq_mshr_miss_rate::total 0.766491 # mshr miss rate for UpgradeReq accesses 2767system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.770543 # mshr miss rate for SCUpgradeReq accesses 2768system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.858680 # mshr miss rate for SCUpgradeReq accesses 2769system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.830799 # mshr miss rate for SCUpgradeReq accesses 2770system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.705343 # mshr miss rate for ReadExReq accesses 2771system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851991 # mshr miss rate for ReadExReq accesses 2772system.l2c.ReadExReq_mshr_miss_rate::total 0.760160 # mshr miss rate for ReadExReq accesses 2773system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for ReadSharedReq accesses 2774system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses 2775system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for ReadSharedReq accesses 2776system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158155 # mshr miss rate for ReadSharedReq accesses 2777system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for ReadSharedReq accesses 2778system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for ReadSharedReq accesses 2779system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for ReadSharedReq accesses 2780system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245606 # mshr miss rate for ReadSharedReq accesses 2781system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for ReadSharedReq accesses 2782system.l2c.ReadSharedReq_mshr_miss_rate::total 0.503900 # mshr miss rate for ReadSharedReq accesses 2783system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for demand accesses 2784system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses 2785system.l2c.demand_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for demand accesses 2786system.l2c.demand_mshr_miss_rate::cpu0.data 0.268821 # mshr miss rate for demand accesses 2787system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for demand accesses 2788system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for demand accesses 2789system.l2c.demand_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for demand accesses 2790system.l2c.demand_mshr_miss_rate::cpu1.data 0.603113 # mshr miss rate for demand accesses 2791system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for demand accesses 2792system.l2c.demand_mshr_miss_rate::total 0.520961 # mshr miss rate for demand accesses 2793system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for overall accesses 2794system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses 2795system.l2c.overall_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for overall accesses 2796system.l2c.overall_mshr_miss_rate::cpu0.data 0.268821 # mshr miss rate for overall accesses 2797system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for overall accesses 2798system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for overall accesses 2799system.l2c.overall_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for overall accesses 2800system.l2c.overall_mshr_miss_rate::cpu1.data 0.603113 # mshr miss rate for overall accesses 2801system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for overall accesses 2802system.l2c.overall_mshr_miss_rate::total 0.520961 # mshr miss rate for overall accesses 2803system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75388.092079 # average UpgradeReq mshr miss latency 2804system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 74924.144311 # average UpgradeReq mshr miss latency 2805system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75301.941166 # average UpgradeReq mshr miss latency 2806system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77293.762575 # average SCUpgradeReq mshr miss latency 2807system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76691.311612 # average SCUpgradeReq mshr miss latency 2808system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76868.063754 # average SCUpgradeReq mshr miss latency 2809system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139178.399491 # average ReadExReq mshr miss latency 2810system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122081.191736 # average ReadExReq mshr miss latency 2811system.l2c.ReadExReq_avg_mshr_miss_latency::total 132015.385021 # average ReadExReq mshr miss latency 2812system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average ReadSharedReq mshr miss latency 2813system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency 2814system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average ReadSharedReq mshr miss latency 2815system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127131.303276 # average ReadSharedReq mshr miss latency 2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average ReadSharedReq mshr miss latency 2817system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average ReadSharedReq mshr miss latency 2818system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average ReadSharedReq mshr miss latency 2819system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130152.542373 # average ReadSharedReq mshr miss latency 2820system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average ReadSharedReq mshr miss latency 2821system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 138273.544253 # average ReadSharedReq mshr miss latency 2822system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency 2823system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2824system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency 2825system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency 2826system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency 2827system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency 2828system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency 2829system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency 2830system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency 2831system.l2c.demand_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency 2832system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency 2833system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency 2834system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency 2835system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency 2836system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency 2837system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency 2838system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency 2839system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency 2840system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency 2841system.l2c.overall_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency 2842system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average ReadReq mshr uncacheable latency 2843system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172134.394507 # average ReadReq mshr uncacheable latency 2844system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average ReadReq mshr uncacheable latency 2845system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99366.068286 # average ReadReq mshr uncacheable latency 2846system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160713.619307 # average ReadReq mshr uncacheable latency 2847system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155010.758304 # average WriteReq mshr uncacheable latency 2848system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 78049.520767 # average WriteReq mshr uncacheable latency 2849system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149556.028208 # average WriteReq mshr uncacheable latency 2850system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average overall mshr uncacheable latency 2851system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164040.107304 # average overall mshr uncacheable latency 2852system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average overall mshr uncacheable latency 2853system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90084.558824 # average overall mshr uncacheable latency 2854system.l2c.overall_avg_mshr_uncacheable_latency::total 155773.635439 # average overall mshr uncacheable latency 2855system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2856system.membus.trans_dist::ReadReq 38908 # Transaction distribution 2857system.membus.trans_dist::ReadResp 215242 # Transaction distribution 2858system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2859system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2860system.membus.trans_dist::Writeback 138211 # Transaction distribution 2861system.membus.trans_dist::CleanEvict 17281 # Transaction distribution 2862system.membus.trans_dist::UpgradeReq 73717 # Transaction distribution 2863system.membus.trans_dist::SCUpgradeReq 40307 # Transaction distribution 2864system.membus.trans_dist::UpgradeResp 13440 # Transaction distribution 2865system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 2866system.membus.trans_dist::ReadExReq 39445 # Transaction distribution 2867system.membus.trans_dist::ReadExResp 18844 # Transaction distribution 2868system.membus.trans_dist::ReadSharedReq 176334 # Transaction distribution 2869system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2870system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 2871system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) 2872system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2873system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13712 # Packet count per connected master and slave (bytes) 2874system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 674810 # Packet count per connected master and slave (bytes) 2875system.membus.pkt_count_system.l2c.mem_side::total 796498 # Packet count per connected master and slave (bytes) 2876system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) 2877system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) 2878system.membus.pkt_count::total 905407 # Packet count per connected master and slave (bytes) 2879system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) 2880system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2881system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27424 # Cumulative packet size per connected master and slave (bytes) 2882system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19258908 # Cumulative packet size per connected master and slave (bytes) 2883system.membus.pkt_size_system.l2c.mem_side::total 19450490 # Cumulative packet size per connected master and slave (bytes) 2884system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2885system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2886system.membus.pkt_size::total 21767610 # Cumulative packet size per connected master and slave (bytes) 2887system.membus.snoops 121785 # Total snoops (count) 2888system.membus.snoop_fanout::samples 591590 # Request fanout histogram 2889system.membus.snoop_fanout::mean 1 # Request fanout histogram 2890system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2891system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2892system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2893system.membus.snoop_fanout::1 591590 100.00% 100.00% # Request fanout histogram 2894system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2895system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2896system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2897system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2898system.membus.snoop_fanout::total 591590 # Request fanout histogram 2899system.membus.reqLayer0.occupancy 91392000 # Layer occupancy (ticks) 2900system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2901system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) 2902system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2903system.membus.reqLayer2.occupancy 11844500 # Layer occupancy (ticks) 2904system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2905system.membus.reqLayer5.occupancy 1004304747 # Layer occupancy (ticks) 2906system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2907system.membus.respLayer2.occupancy 1168943229 # Layer occupancy (ticks) 2908system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2909system.membus.respLayer3.occupancy 64602498 # Layer occupancy (ticks) 2910system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2911system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2912system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2913system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2914system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2915system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2916system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2917system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2918system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2919system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2920system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2921system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2922system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2923system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2924system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2925system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2926system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2927system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2928system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2929system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2930system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2931system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2932system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2933system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2934system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2935system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2936system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2937system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2938system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2939system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2940system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2941system.realview.ethernet.droppedPackets 0 # number of packets dropped 2942system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 2943system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 2944system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 2945system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 2946system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 2947system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 2948system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 2949system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 2950system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 2951system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 2952system.toL2Bus.snoop_filter.tot_requests 982687 # Total number of requests made to the snoop filter. 2953system.toL2Bus.snoop_filter.hit_single_requests 493902 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2954system.toL2Bus.snoop_filter.hit_multi_requests 158313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2955system.toL2Bus.snoop_filter.tot_snoops 22110 # Total number of snoops made to the snoop filter. 2956system.toL2Bus.snoop_filter.hit_single_snoops 21385 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2957system.toL2Bus.snoop_filter.hit_multi_snoops 725 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2958system.toL2Bus.trans_dist::ReadReq 38912 # Transaction distribution 2959system.toL2Bus.trans_dist::ReadResp 507516 # Transaction distribution 2960system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 2961system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 2962system.toL2Bus.trans_dist::Writeback 368484 # Transaction distribution 2963system.toL2Bus.trans_dist::CleanEvict 106099 # Transaction distribution 2964system.toL2Bus.trans_dist::UpgradeReq 77161 # Transaction distribution 2965system.toL2Bus.trans_dist::SCUpgradeReq 40652 # Transaction distribution 2966system.toL2Bus.trans_dist::UpgradeResp 117813 # Transaction distribution 2967system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution 2968system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution 2969system.toL2Bus.trans_dist::ReadExReq 51062 # Transaction distribution 2970system.toL2Bus.trans_dist::ReadExResp 51062 # Transaction distribution 2971system.toL2Bus.trans_dist::ReadSharedReq 468619 # Transaction distribution 2972system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2973system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1216476 # Packet count per connected master and slave (bytes) 2974system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 257070 # Packet count per connected master and slave (bytes) 2975system.toL2Bus.pkt_count::total 1473546 # Packet count per connected master and slave (bytes) 2976system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35115318 # Cumulative packet size per connected master and slave (bytes) 2977system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4064004 # Cumulative packet size per connected master and slave (bytes) 2978system.toL2Bus.pkt_size::total 39179322 # Cumulative packet size per connected master and slave (bytes) 2979system.toL2Bus.snoops 452154 # Total snoops (count) 2980system.toL2Bus.snoop_fanout::samples 1258731 # Request fanout histogram 2981system.toL2Bus.snoop_fanout::mean 0.293892 # Request fanout histogram 2982system.toL2Bus.snoop_fanout::stdev 0.456806 # Request fanout histogram 2983system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2984system.toL2Bus.snoop_fanout::0 889525 70.67% 70.67% # Request fanout histogram 2985system.toL2Bus.snoop_fanout::1 368481 29.27% 99.94% # Request fanout histogram 2986system.toL2Bus.snoop_fanout::2 725 0.06% 100.00% # Request fanout histogram 2987system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2988system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2989system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2990system.toL2Bus.snoop_fanout::total 1258731 # Request fanout histogram 2991system.toL2Bus.reqLayer0.occupancy 836264644 # Layer occupancy (ticks) 2992system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2993system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) 2994system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2995system.toL2Bus.respLayer0.occupancy 685711951 # Layer occupancy (ticks) 2996system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2997system.toL2Bus.respLayer1.occupancy 211221475 # Layer occupancy (ticks) 2998system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2999 3000---------- End Simulation Statistics ---------- 3001