stats.txt revision 11103:38f6188421e0
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.846117 # Number of seconds simulated 4sim_ticks 2846117015000 # Number of ticks simulated 5final_tick 2846117015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 113156 # Simulator instruction rate (inst/s) 8host_op_rate 137057 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2513496102 # Simulator tick rate (ticks/s) 10host_mem_usage 647580 # Number of bytes of host memory used 11host_seconds 1132.33 # Real time elapsed on the host 12sim_insts 128130877 # Number of instructions simulated 13sim_ops 155193960 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 7296 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1474816 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1242668 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8247680 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 2432 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 378112 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 721620 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 564672 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12640384 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1474816 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 378112 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1852928 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8933696 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8951260 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 114 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 23044 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 19938 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 128870 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 38 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 5908 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 11296 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 8823 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 198048 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 139589 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 143980 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2563 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 518185 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 436619 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 2897871 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 854 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 132852 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 253545 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 198401 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 4441273 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 518185 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 132852 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 651037 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3138907 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 3145078 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3138907 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2563 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 518185 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 442776 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 2897871 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 854 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 132852 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 253559 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 198401 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7586351 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 198048 # Number of read requests accepted 84system.physmem.writeReqs 143980 # Number of write requests accepted 85system.physmem.readBursts 198048 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 143980 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12666176 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue 89system.physmem.bytesWritten 8963584 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12640384 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 8951260 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 51245 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12439 # Per bank write bursts 96system.physmem.perBankRdBursts::1 12567 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12508 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12584 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14823 # Per bank write bursts 100system.physmem.perBankRdBursts::5 11920 # Per bank write bursts 101system.physmem.perBankRdBursts::6 13135 # Per bank write bursts 102system.physmem.perBankRdBursts::7 13383 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12319 # Per bank write bursts 104system.physmem.perBankRdBursts::9 12338 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11698 # Per bank write bursts 106system.physmem.perBankRdBursts::11 11134 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11462 # Per bank write bursts 108system.physmem.perBankRdBursts::13 11917 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11661 # Per bank write bursts 110system.physmem.perBankRdBursts::15 12021 # Per bank write bursts 111system.physmem.perBankWrBursts::0 8771 # Per bank write bursts 112system.physmem.perBankWrBursts::1 9038 # Per bank write bursts 113system.physmem.perBankWrBursts::2 9230 # Per bank write bursts 114system.physmem.perBankWrBursts::3 8945 # Per bank write bursts 115system.physmem.perBankWrBursts::4 8307 # Per bank write bursts 116system.physmem.perBankWrBursts::5 8620 # Per bank write bursts 117system.physmem.perBankWrBursts::6 9591 # Per bank write bursts 118system.physmem.perBankWrBursts::7 9703 # Per bank write bursts 119system.physmem.perBankWrBursts::8 8875 # Per bank write bursts 120system.physmem.perBankWrBursts::9 8727 # Per bank write bursts 121system.physmem.perBankWrBursts::10 8430 # Per bank write bursts 122system.physmem.perBankWrBursts::11 8199 # Per bank write bursts 123system.physmem.perBankWrBursts::12 8380 # Per bank write bursts 124system.physmem.perBankWrBursts::13 8472 # Per bank write bursts 125system.physmem.perBankWrBursts::14 8531 # Per bank write bursts 126system.physmem.perBankWrBursts::15 8237 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 129system.physmem.totGap 2846116455500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 552 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 0 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 197468 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 139589 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 85140 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 62378 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 11568 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 9695 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 6201 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 5246 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 4552 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 3838 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 263 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 234 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 161 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 2706 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 3163 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 4888 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 5603 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 6092 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 6675 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 7058 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 8476 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 9015 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 10231 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 9841 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 9581 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 8847 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 9302 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 10565 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 8547 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 7994 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 7600 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 353 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 201 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 133 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 95 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 88 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 68 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 40 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 91138 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 237.329061 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 134.886171 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 298.768529 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 49038 53.81% 53.81% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 17709 19.43% 73.24% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 6298 6.91% 80.15% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3704 4.06% 84.21% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2913 3.20% 87.41% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1386 1.52% 88.93% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 897 0.98% 89.91% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 1023 1.12% 91.04% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 8170 8.96% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 91138 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6991 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 28.308683 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 556.324450 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6990 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::total 6991 # Reads before turning the bus around for writes 260system.physmem.wrPerTurnAround::samples 6991 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::mean 20.033758 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::gmean 18.625060 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::stdev 11.557866 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::16-19 5837 83.49% 83.49% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::20-23 357 5.11% 88.60% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::24-27 222 3.18% 91.78% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::28-31 60 0.86% 92.63% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::32-35 64 0.92% 93.55% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::36-39 166 2.37% 95.92% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::40-43 20 0.29% 96.21% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::44-47 6 0.09% 96.30% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::48-51 14 0.20% 96.50% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::52-55 10 0.14% 96.64% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::56-59 5 0.07% 96.71% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::60-63 9 0.13% 96.84% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::64-67 167 2.39% 99.23% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::68-71 8 0.11% 99.34% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::72-75 8 0.11% 99.46% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::76-79 7 0.10% 99.56% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::80-83 3 0.04% 99.60% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::92-95 3 0.04% 99.64% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::96-99 3 0.04% 99.69% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::108-111 1 0.01% 99.71% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::116-119 1 0.01% 99.73% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::128-131 14 0.20% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::148-151 2 0.03% 99.96% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::total 6991 # Writes before turning the bus around for reads 291system.physmem.totQLat 5451252873 # Total ticks spent queuing 292system.physmem.totMemAccLat 9162046623 # Total ticks spent from burst creation until serviced by the DRAM 293system.physmem.totBusLat 989545000 # Total ticks spent in databus transfers 294system.physmem.avgQLat 27544.24 # Average queueing delay per DRAM burst 295system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 296system.physmem.avgMemAccLat 46294.24 # Average memory access latency per DRAM burst 297system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s 298system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s 299system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s 300system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s 301system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 302system.physmem.busUtil 0.06 # Data bus utilization in percentage 303system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 304system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 305system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 306system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing 307system.physmem.readRowHits 164305 # Number of row buffer hits during reads 308system.physmem.writeRowHits 82521 # Number of row buffer hits during writes 309system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads 310system.physmem.writeRowHitRate 58.91 # Row buffer hit rate for writes 311system.physmem.avgGap 8321296.66 # Average gap between requests 312system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined 313system.physmem_0.actEnergy 359440200 # Energy for activate commands per rank (pJ) 314system.physmem_0.preEnergy 196123125 # Energy for precharge commands per rank (pJ) 315system.physmem_0.readEnergy 806200200 # Energy for read commands per rank (pJ) 316system.physmem_0.writeEnergy 467888400 # Energy for write commands per rank (pJ) 317system.physmem_0.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ) 318system.physmem_0.actBackEnergy 83210904225 # Energy for active background per rank (pJ) 319system.physmem_0.preBackEnergy 1634677575750 # Energy for precharge background per rank (pJ) 320system.physmem_0.totalEnergy 1905612577260 # Total energy per rank (pJ) 321system.physmem_0.averagePower 669.548459 # Core power per rank (mW) 322system.physmem_0.memoryStateTime::IDLE 2719308511052 # Time in different power states 323system.physmem_0.memoryStateTime::REF 95038060000 # Time in different power states 324system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 325system.physmem_0.memoryStateTime::ACT 31769437698 # Time in different power states 326system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 327system.physmem_1.actEnergy 329563080 # Energy for activate commands per rank (pJ) 328system.physmem_1.preEnergy 179821125 # Energy for precharge commands per rank (pJ) 329system.physmem_1.readEnergy 737482200 # Energy for read commands per rank (pJ) 330system.physmem_1.writeEnergy 439674480 # Energy for write commands per rank (pJ) 331system.physmem_1.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ) 332system.physmem_1.actBackEnergy 82251132525 # Energy for active background per rank (pJ) 333system.physmem_1.preBackEnergy 1635519480750 # Energy for precharge background per rank (pJ) 334system.physmem_1.totalEnergy 1905351599520 # Total energy per rank (pJ) 335system.physmem_1.averagePower 669.456762 # Core power per rank (mW) 336system.physmem_1.memoryStateTime::IDLE 2720714979061 # Time in different power states 337system.physmem_1.memoryStateTime::REF 95038060000 # Time in different power states 338system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 339system.physmem_1.memoryStateTime::ACT 30363879439 # Time in different power states 340system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 341system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 347system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 350system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 359system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 360system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 361system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 362system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 363system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 364system.cf0.dma_write_txs 631 # Number of DMA write transactions. 365system.cpu0.branchPred.lookups 34784409 # Number of BP lookups 366system.cpu0.branchPred.condPredicted 16478031 # Number of conditional branches predicted 367system.cpu0.branchPred.condIncorrect 1480168 # Number of conditional branches incorrect 368system.cpu0.branchPred.BTBLookups 19725615 # Number of BTB lookups 369system.cpu0.branchPred.BTBHits 14342133 # Number of BTB hits 370system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 371system.cpu0.branchPred.BTBHitPct 72.708167 # BTB Hit Percentage 372system.cpu0.branchPred.usedRAS 11162624 # Number of times the RAS was used to get a target. 373system.cpu0.branchPred.RASInCorrect 702720 # Number of incorrect RAS predictions. 374system.cpu_clk_domain.clock 500 # Clock period in ticks 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 384system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 385system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 386system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 387system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 388system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 389system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 390system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 391system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 392system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 393system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 394system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 396system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 397system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 399system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 400system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 401system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 402system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 403system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 404system.cpu0.dtb.walker.walks 65972 # Table walker walks requested 405system.cpu0.dtb.walker.walksShort 65972 # Table walker walks initiated with short descriptors 406system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 43486 # Level at which table walker walks with short descriptors terminate 407system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22486 # Level at which table walker walks with short descriptors terminate 408system.cpu0.dtb.walker.walkWaitTime::samples 65972 # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::0 65972 100.00% 100.00% # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::total 65972 # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkCompletionTime::samples 6612 # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::mean 10372.504537 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::gmean 9312.931281 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::stdev 6218.139441 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::0-16383 6425 97.17% 97.17% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::16384-32767 170 2.57% 99.74% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.85% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.08% 99.92% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.98% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::total 6612 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution 423system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution 424system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution 425system.cpu0.dtb.walker.walkPageSizes::4K 5105 77.21% 77.21% # Table walker page sizes translated 426system.cpu0.dtb.walker.walkPageSizes::1M 1507 22.79% 100.00% # Table walker page sizes translated 427system.cpu0.dtb.walker.walkPageSizes::total 6612 # Table walker page sizes translated 428system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65972 # Table walker requests started/completed, data/inst 429system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65972 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6612 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6612 # Table walker requests started/completed, data/inst 434system.cpu0.dtb.walker.walkRequestOrigin::total 72584 # Table walker requests started/completed, data/inst 435system.cpu0.dtb.inst_hits 0 # ITB inst hits 436system.cpu0.dtb.inst_misses 0 # ITB inst misses 437system.cpu0.dtb.read_hits 23562231 # DTB read hits 438system.cpu0.dtb.read_misses 59962 # DTB read misses 439system.cpu0.dtb.write_hits 17431474 # DTB write hits 440system.cpu0.dtb.write_misses 6010 # DTB write misses 441system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 442system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 443system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 444system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 445system.cpu0.dtb.flush_entries 3494 # Number of entries that have been flushed from TLB 446system.cpu0.dtb.align_faults 1076 # Number of TLB faults due to alignment restrictions 447system.cpu0.dtb.prefetch_faults 1600 # Number of TLB faults due to prefetch 448system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 449system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions 450system.cpu0.dtb.read_accesses 23622193 # DTB read accesses 451system.cpu0.dtb.write_accesses 17437484 # DTB write accesses 452system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 453system.cpu0.dtb.hits 40993705 # DTB hits 454system.cpu0.dtb.misses 65972 # DTB misses 455system.cpu0.dtb.accesses 41059677 # DTB accesses 456system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 465system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 466system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 467system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 468system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 469system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 470system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 471system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 474system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 475system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 476system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 477system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 479system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 480system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 481system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 482system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 483system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 484system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 485system.cpu0.itb.walker.walks 3855 # Table walker walks requested 486system.cpu0.itb.walker.walksShort 3855 # Table walker walks initiated with short descriptors 487system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate 488system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3550 # Level at which table walker walks with short descriptors terminate 489system.cpu0.itb.walker.walkWaitTime::samples 3855 # Table walker wait (enqueue to first request) latency 490system.cpu0.itb.walker.walkWaitTime::0 3855 100.00% 100.00% # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::total 3855 # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkCompletionTime::samples 2424 # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::mean 10979.785479 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::gmean 9797.993767 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::stdev 8035.967164 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::0-32767 2422 99.92% 99.92% # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::total 2424 # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution 501system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution 502system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution 503system.cpu0.itb.walker.walkPageSizes::4K 2124 87.62% 87.62% # Table walker page sizes translated 504system.cpu0.itb.walker.walkPageSizes::1M 300 12.38% 100.00% # Table walker page sizes translated 505system.cpu0.itb.walker.walkPageSizes::total 2424 # Table walker page sizes translated 506system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 507system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3855 # Table walker requests started/completed, data/inst 508system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3855 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 510system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2424 # Table walker requests started/completed, data/inst 511system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2424 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin::total 6279 # Table walker requests started/completed, data/inst 513system.cpu0.itb.inst_hits 68397916 # ITB inst hits 514system.cpu0.itb.inst_misses 3855 # ITB inst misses 515system.cpu0.itb.read_hits 0 # DTB read hits 516system.cpu0.itb.read_misses 0 # DTB read misses 517system.cpu0.itb.write_hits 0 # DTB write hits 518system.cpu0.itb.write_misses 0 # DTB write misses 519system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 520system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 521system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 522system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 523system.cpu0.itb.flush_entries 2226 # Number of entries that have been flushed from TLB 524system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu0.itb.perms_faults 7522 # Number of TLB faults due to permissions restrictions 528system.cpu0.itb.read_accesses 0 # DTB read accesses 529system.cpu0.itb.write_accesses 0 # DTB write accesses 530system.cpu0.itb.inst_accesses 68401771 # ITB inst accesses 531system.cpu0.itb.hits 68397916 # DTB hits 532system.cpu0.itb.misses 3855 # DTB misses 533system.cpu0.itb.accesses 68401771 # DTB accesses 534system.cpu0.numCycles 225406925 # number of cpu cycles simulated 535system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 536system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 537system.cpu0.committedInsts 107236402 # Number of instructions committed 538system.cpu0.committedOps 129680129 # Number of ops (including micro ops) committed 539system.cpu0.discardedOps 8567834 # Number of ops (including micro ops) which were discarded before commit 540system.cpu0.numFetchSuspends 2087 # Number of times Execute suspended instruction fetching 541system.cpu0.quiesceCycles 5466862375 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 542system.cpu0.cpi 2.101963 # CPI: cycles per instruction 543system.cpu0.ipc 0.475746 # IPC: instructions per cycle 544system.cpu0.kern.inst.arm 0 # number of arm instructions executed 545system.cpu0.kern.inst.quiesce 2088 # number of quiesce instructions executed 546system.cpu0.tickCycles 187552407 # Number of cycles that the object actually ticked 547system.cpu0.idleCycles 37854518 # Total number of cycles that the object has spent stopped 548system.cpu0.dcache.tags.replacements 678280 # number of replacements 549system.cpu0.dcache.tags.tagsinuse 485.010035 # Cycle average of tags in use 550system.cpu0.dcache.tags.total_refs 39540240 # Total number of references to valid blocks. 551system.cpu0.dcache.tags.sampled_refs 678792 # Sample count of references to valid blocks. 552system.cpu0.dcache.tags.avg_refs 58.250893 # Average number of references to valid blocks. 553system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit. 554system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.010035 # Average occupied blocks per requestor 555system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947285 # Average percentage of cache occupancy 556system.cpu0.dcache.tags.occ_percent::total 0.947285 # Average percentage of cache occupancy 557system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 558system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 559system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 560system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 561system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 562system.cpu0.dcache.tags.tag_accesses 81933612 # Number of tag accesses 563system.cpu0.dcache.tags.data_accesses 81933612 # Number of data accesses 564system.cpu0.dcache.ReadReq_hits::cpu0.data 22071197 # number of ReadReq hits 565system.cpu0.dcache.ReadReq_hits::total 22071197 # number of ReadReq hits 566system.cpu0.dcache.WriteReq_hits::cpu0.data 16340314 # number of WriteReq hits 567system.cpu0.dcache.WriteReq_hits::total 16340314 # number of WriteReq hits 568system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307086 # number of SoftPFReq hits 569system.cpu0.dcache.SoftPFReq_hits::total 307086 # number of SoftPFReq hits 570system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357744 # number of LoadLockedReq hits 571system.cpu0.dcache.LoadLockedReq_hits::total 357744 # number of LoadLockedReq hits 572system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352756 # number of StoreCondReq hits 573system.cpu0.dcache.StoreCondReq_hits::total 352756 # number of StoreCondReq hits 574system.cpu0.dcache.demand_hits::cpu0.data 38411511 # number of demand (read+write) hits 575system.cpu0.dcache.demand_hits::total 38411511 # number of demand (read+write) hits 576system.cpu0.dcache.overall_hits::cpu0.data 38718597 # number of overall hits 577system.cpu0.dcache.overall_hits::total 38718597 # number of overall hits 578system.cpu0.dcache.ReadReq_misses::cpu0.data 442022 # number of ReadReq misses 579system.cpu0.dcache.ReadReq_misses::total 442022 # number of ReadReq misses 580system.cpu0.dcache.WriteReq_misses::cpu0.data 555005 # number of WriteReq misses 581system.cpu0.dcache.WriteReq_misses::total 555005 # number of WriteReq misses 582system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131972 # number of SoftPFReq misses 583system.cpu0.dcache.SoftPFReq_misses::total 131972 # number of SoftPFReq misses 584system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20768 # number of LoadLockedReq misses 585system.cpu0.dcache.LoadLockedReq_misses::total 20768 # number of LoadLockedReq misses 586system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21303 # number of StoreCondReq misses 587system.cpu0.dcache.StoreCondReq_misses::total 21303 # number of StoreCondReq misses 588system.cpu0.dcache.demand_misses::cpu0.data 997027 # number of demand (read+write) misses 589system.cpu0.dcache.demand_misses::total 997027 # number of demand (read+write) misses 590system.cpu0.dcache.overall_misses::cpu0.data 1128999 # number of overall misses 591system.cpu0.dcache.overall_misses::total 1128999 # number of overall misses 592system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5846536500 # number of ReadReq miss cycles 593system.cpu0.dcache.ReadReq_miss_latency::total 5846536500 # number of ReadReq miss cycles 594system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8888918500 # number of WriteReq miss cycles 595system.cpu0.dcache.WriteReq_miss_latency::total 8888918500 # number of WriteReq miss cycles 596system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319234500 # number of LoadLockedReq miss cycles 597system.cpu0.dcache.LoadLockedReq_miss_latency::total 319234500 # number of LoadLockedReq miss cycles 598system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481221000 # number of StoreCondReq miss cycles 599system.cpu0.dcache.StoreCondReq_miss_latency::total 481221000 # number of StoreCondReq miss cycles 600system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 684000 # number of StoreCondFailReq miss cycles 601system.cpu0.dcache.StoreCondFailReq_miss_latency::total 684000 # number of StoreCondFailReq miss cycles 602system.cpu0.dcache.demand_miss_latency::cpu0.data 14735455000 # number of demand (read+write) miss cycles 603system.cpu0.dcache.demand_miss_latency::total 14735455000 # number of demand (read+write) miss cycles 604system.cpu0.dcache.overall_miss_latency::cpu0.data 14735455000 # number of overall miss cycles 605system.cpu0.dcache.overall_miss_latency::total 14735455000 # number of overall miss cycles 606system.cpu0.dcache.ReadReq_accesses::cpu0.data 22513219 # number of ReadReq accesses(hits+misses) 607system.cpu0.dcache.ReadReq_accesses::total 22513219 # number of ReadReq accesses(hits+misses) 608system.cpu0.dcache.WriteReq_accesses::cpu0.data 16895319 # number of WriteReq accesses(hits+misses) 609system.cpu0.dcache.WriteReq_accesses::total 16895319 # number of WriteReq accesses(hits+misses) 610system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439058 # number of SoftPFReq accesses(hits+misses) 611system.cpu0.dcache.SoftPFReq_accesses::total 439058 # number of SoftPFReq accesses(hits+misses) 612system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378512 # number of LoadLockedReq accesses(hits+misses) 613system.cpu0.dcache.LoadLockedReq_accesses::total 378512 # number of LoadLockedReq accesses(hits+misses) 614system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) 615system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) 616system.cpu0.dcache.demand_accesses::cpu0.data 39408538 # number of demand (read+write) accesses 617system.cpu0.dcache.demand_accesses::total 39408538 # number of demand (read+write) accesses 618system.cpu0.dcache.overall_accesses::cpu0.data 39847596 # number of overall (read+write) accesses 619system.cpu0.dcache.overall_accesses::total 39847596 # number of overall (read+write) accesses 620system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019634 # miss rate for ReadReq accesses 621system.cpu0.dcache.ReadReq_miss_rate::total 0.019634 # miss rate for ReadReq accesses 622system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032850 # miss rate for WriteReq accesses 623system.cpu0.dcache.WriteReq_miss_rate::total 0.032850 # miss rate for WriteReq accesses 624system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300580 # miss rate for SoftPFReq accesses 625system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300580 # miss rate for SoftPFReq accesses 626system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054867 # miss rate for LoadLockedReq accesses 627system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054867 # miss rate for LoadLockedReq accesses 628system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses 629system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses 630system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025300 # miss rate for demand accesses 631system.cpu0.dcache.demand_miss_rate::total 0.025300 # miss rate for demand accesses 632system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028333 # miss rate for overall accesses 633system.cpu0.dcache.overall_miss_rate::total 0.028333 # miss rate for overall accesses 634system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13226.799797 # average ReadReq miss latency 635system.cpu0.dcache.ReadReq_avg_miss_latency::total 13226.799797 # average ReadReq miss latency 636system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16015.925082 # average WriteReq miss latency 637system.cpu0.dcache.WriteReq_avg_miss_latency::total 16015.925082 # average WriteReq miss latency 638system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15371.460901 # average LoadLockedReq miss latency 639system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15371.460901 # average LoadLockedReq miss latency 640system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22589.353612 # average StoreCondReq miss latency 641system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22589.353612 # average StoreCondReq miss latency 642system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 643system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 644system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14779.394139 # average overall miss latency 645system.cpu0.dcache.demand_avg_miss_latency::total 14779.394139 # average overall miss latency 646system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.787468 # average overall miss latency 647system.cpu0.dcache.overall_avg_miss_latency::total 13051.787468 # average overall miss latency 648system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 649system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 651system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 653system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 654system.cpu0.dcache.fast_writes 0 # number of fast writes performed 655system.cpu0.dcache.cache_copies 0 # number of cache copies performed 656system.cpu0.dcache.writebacks::writebacks 490245 # number of writebacks 657system.cpu0.dcache.writebacks::total 490245 # number of writebacks 658system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69954 # number of ReadReq MSHR hits 659system.cpu0.dcache.ReadReq_mshr_hits::total 69954 # number of ReadReq MSHR hits 660system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243081 # number of WriteReq MSHR hits 661system.cpu0.dcache.WriteReq_mshr_hits::total 243081 # number of WriteReq MSHR hits 662system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14749 # number of LoadLockedReq MSHR hits 663system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14749 # number of LoadLockedReq MSHR hits 664system.cpu0.dcache.demand_mshr_hits::cpu0.data 313035 # number of demand (read+write) MSHR hits 665system.cpu0.dcache.demand_mshr_hits::total 313035 # number of demand (read+write) MSHR hits 666system.cpu0.dcache.overall_mshr_hits::cpu0.data 313035 # number of overall MSHR hits 667system.cpu0.dcache.overall_mshr_hits::total 313035 # number of overall MSHR hits 668system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372068 # number of ReadReq MSHR misses 669system.cpu0.dcache.ReadReq_mshr_misses::total 372068 # number of ReadReq MSHR misses 670system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 311924 # number of WriteReq MSHR misses 671system.cpu0.dcache.WriteReq_mshr_misses::total 311924 # number of WriteReq MSHR misses 672system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99410 # number of SoftPFReq MSHR misses 673system.cpu0.dcache.SoftPFReq_mshr_misses::total 99410 # number of SoftPFReq MSHR misses 674system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6019 # number of LoadLockedReq MSHR misses 675system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6019 # number of LoadLockedReq MSHR misses 676system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21303 # number of StoreCondReq MSHR misses 677system.cpu0.dcache.StoreCondReq_mshr_misses::total 21303 # number of StoreCondReq MSHR misses 678system.cpu0.dcache.demand_mshr_misses::cpu0.data 683992 # number of demand (read+write) MSHR misses 679system.cpu0.dcache.demand_mshr_misses::total 683992 # number of demand (read+write) MSHR misses 680system.cpu0.dcache.overall_mshr_misses::cpu0.data 783402 # number of overall MSHR misses 681system.cpu0.dcache.overall_mshr_misses::total 783402 # number of overall MSHR misses 682system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29426 # number of ReadReq MSHR uncacheable 683system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29426 # number of ReadReq MSHR uncacheable 684system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26162 # number of WriteReq MSHR uncacheable 685system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26162 # number of WriteReq MSHR uncacheable 686system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55588 # number of overall MSHR uncacheable misses 687system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55588 # number of overall MSHR uncacheable misses 688system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4399139000 # number of ReadReq MSHR miss cycles 689system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4399139000 # number of ReadReq MSHR miss cycles 690system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4959161000 # number of WriteReq MSHR miss cycles 691system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4959161000 # number of WriteReq MSHR miss cycles 692system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1608557500 # number of SoftPFReq MSHR miss cycles 693system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1608557500 # number of SoftPFReq MSHR miss cycles 694system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 92509500 # number of LoadLockedReq MSHR miss cycles 695system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92509500 # number of LoadLockedReq MSHR miss cycles 696system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459936000 # number of StoreCondReq MSHR miss cycles 697system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459936000 # number of StoreCondReq MSHR miss cycles 698system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 666000 # number of StoreCondFailReq MSHR miss cycles 699system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 666000 # number of StoreCondFailReq MSHR miss cycles 700system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9358300000 # number of demand (read+write) MSHR miss cycles 701system.cpu0.dcache.demand_mshr_miss_latency::total 9358300000 # number of demand (read+write) MSHR miss cycles 702system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10966857500 # number of overall MSHR miss cycles 703system.cpu0.dcache.overall_mshr_miss_latency::total 10966857500 # number of overall MSHR miss cycles 704system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5696567000 # number of ReadReq MSHR uncacheable cycles 705system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5696567000 # number of ReadReq MSHR uncacheable cycles 706system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4315116500 # number of WriteReq MSHR uncacheable cycles 707system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4315116500 # number of WriteReq MSHR uncacheable cycles 708system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10011683500 # number of overall MSHR uncacheable cycles 709system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10011683500 # number of overall MSHR uncacheable cycles 710system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016527 # mshr miss rate for ReadReq accesses 711system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses 712system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018462 # mshr miss rate for WriteReq accesses 713system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018462 # mshr miss rate for WriteReq accesses 714system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226417 # mshr miss rate for SoftPFReq accesses 715system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226417 # mshr miss rate for SoftPFReq accesses 716system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015902 # mshr miss rate for LoadLockedReq accesses 717system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015902 # mshr miss rate for LoadLockedReq accesses 718system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056951 # mshr miss rate for StoreCondReq accesses 719system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056951 # mshr miss rate for StoreCondReq accesses 720system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017356 # mshr miss rate for demand accesses 721system.cpu0.dcache.demand_mshr_miss_rate::total 0.017356 # mshr miss rate for demand accesses 722system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019660 # mshr miss rate for overall accesses 723system.cpu0.dcache.overall_mshr_miss_rate::total 0.019660 # mshr miss rate for overall accesses 724system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11823.481192 # average ReadReq mshr miss latency 725system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11823.481192 # average ReadReq mshr miss latency 726system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15898.619536 # average WriteReq mshr miss latency 727system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15898.619536 # average WriteReq mshr miss latency 728system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16181.043155 # average SoftPFReq mshr miss latency 729system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16181.043155 # average SoftPFReq mshr miss latency 730system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15369.579664 # average LoadLockedReq mshr miss latency 731system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15369.579664 # average LoadLockedReq mshr miss latency 732system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21590.198564 # average StoreCondReq mshr miss latency 733system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21590.198564 # average StoreCondReq mshr miss latency 734system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 735system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 736system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13681.885168 # average overall mshr miss latency 737system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13681.885168 # average overall mshr miss latency 738system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13999.016469 # average overall mshr miss latency 739system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13999.016469 # average overall mshr miss latency 740system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193589.580643 # average ReadReq mshr uncacheable latency 741system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193589.580643 # average ReadReq mshr uncacheable latency 742system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164938.326581 # average WriteReq mshr uncacheable latency 743system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 164938.326581 # average WriteReq mshr uncacheable latency 744system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180105.121609 # average overall mshr uncacheable latency 745system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 180105.121609 # average overall mshr uncacheable latency 746system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 747system.cpu0.icache.tags.replacements 1886353 # number of replacements 748system.cpu0.icache.tags.tagsinuse 511.780174 # Cycle average of tags in use 749system.cpu0.icache.tags.total_refs 66503170 # Total number of references to valid blocks. 750system.cpu0.icache.tags.sampled_refs 1886865 # Sample count of references to valid blocks. 751system.cpu0.icache.tags.avg_refs 35.245325 # Average number of references to valid blocks. 752system.cpu0.icache.tags.warmup_cycle 6541312000 # Cycle when the warmup percentage was hit. 753system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780174 # Average occupied blocks per requestor 754system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy 755system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy 756system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 757system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 758system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id 759system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id 760system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 761system.cpu0.icache.tags.tag_accesses 138666991 # Number of tag accesses 762system.cpu0.icache.tags.data_accesses 138666991 # Number of data accesses 763system.cpu0.icache.ReadReq_hits::cpu0.inst 66503170 # number of ReadReq hits 764system.cpu0.icache.ReadReq_hits::total 66503170 # number of ReadReq hits 765system.cpu0.icache.demand_hits::cpu0.inst 66503170 # number of demand (read+write) hits 766system.cpu0.icache.demand_hits::total 66503170 # number of demand (read+write) hits 767system.cpu0.icache.overall_hits::cpu0.inst 66503170 # number of overall hits 768system.cpu0.icache.overall_hits::total 66503170 # number of overall hits 769system.cpu0.icache.ReadReq_misses::cpu0.inst 1886884 # number of ReadReq misses 770system.cpu0.icache.ReadReq_misses::total 1886884 # number of ReadReq misses 771system.cpu0.icache.demand_misses::cpu0.inst 1886884 # number of demand (read+write) misses 772system.cpu0.icache.demand_misses::total 1886884 # number of demand (read+write) misses 773system.cpu0.icache.overall_misses::cpu0.inst 1886884 # number of overall misses 774system.cpu0.icache.overall_misses::total 1886884 # number of overall misses 775system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17552107500 # number of ReadReq miss cycles 776system.cpu0.icache.ReadReq_miss_latency::total 17552107500 # number of ReadReq miss cycles 777system.cpu0.icache.demand_miss_latency::cpu0.inst 17552107500 # number of demand (read+write) miss cycles 778system.cpu0.icache.demand_miss_latency::total 17552107500 # number of demand (read+write) miss cycles 779system.cpu0.icache.overall_miss_latency::cpu0.inst 17552107500 # number of overall miss cycles 780system.cpu0.icache.overall_miss_latency::total 17552107500 # number of overall miss cycles 781system.cpu0.icache.ReadReq_accesses::cpu0.inst 68390054 # number of ReadReq accesses(hits+misses) 782system.cpu0.icache.ReadReq_accesses::total 68390054 # number of ReadReq accesses(hits+misses) 783system.cpu0.icache.demand_accesses::cpu0.inst 68390054 # number of demand (read+write) accesses 784system.cpu0.icache.demand_accesses::total 68390054 # number of demand (read+write) accesses 785system.cpu0.icache.overall_accesses::cpu0.inst 68390054 # number of overall (read+write) accesses 786system.cpu0.icache.overall_accesses::total 68390054 # number of overall (read+write) accesses 787system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027590 # miss rate for ReadReq accesses 788system.cpu0.icache.ReadReq_miss_rate::total 0.027590 # miss rate for ReadReq accesses 789system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027590 # miss rate for demand accesses 790system.cpu0.icache.demand_miss_rate::total 0.027590 # miss rate for demand accesses 791system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027590 # miss rate for overall accesses 792system.cpu0.icache.overall_miss_rate::total 0.027590 # miss rate for overall accesses 793system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9302.165634 # average ReadReq miss latency 794system.cpu0.icache.ReadReq_avg_miss_latency::total 9302.165634 # average ReadReq miss latency 795system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9302.165634 # average overall miss latency 796system.cpu0.icache.demand_avg_miss_latency::total 9302.165634 # average overall miss latency 797system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9302.165634 # average overall miss latency 798system.cpu0.icache.overall_avg_miss_latency::total 9302.165634 # average overall miss latency 799system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu0.icache.fast_writes 0 # number of fast writes performed 806system.cpu0.icache.cache_copies 0 # number of cache copies performed 807system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1886884 # number of ReadReq MSHR misses 808system.cpu0.icache.ReadReq_mshr_misses::total 1886884 # number of ReadReq MSHR misses 809system.cpu0.icache.demand_mshr_misses::cpu0.inst 1886884 # number of demand (read+write) MSHR misses 810system.cpu0.icache.demand_mshr_misses::total 1886884 # number of demand (read+write) MSHR misses 811system.cpu0.icache.overall_mshr_misses::cpu0.inst 1886884 # number of overall MSHR misses 812system.cpu0.icache.overall_mshr_misses::total 1886884 # number of overall MSHR misses 813system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable 814system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable 815system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses 816system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses 817system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16608666000 # number of ReadReq MSHR miss cycles 818system.cpu0.icache.ReadReq_mshr_miss_latency::total 16608666000 # number of ReadReq MSHR miss cycles 819system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16608666000 # number of demand (read+write) MSHR miss cycles 820system.cpu0.icache.demand_mshr_miss_latency::total 16608666000 # number of demand (read+write) MSHR miss cycles 821system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16608666000 # number of overall MSHR miss cycles 822system.cpu0.icache.overall_mshr_miss_latency::total 16608666000 # number of overall MSHR miss cycles 823system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles 824system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles 825system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles 826system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles 827system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for ReadReq accesses 828system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027590 # mshr miss rate for ReadReq accesses 829system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for demand accesses 830system.cpu0.icache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses 831system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for overall accesses 832system.cpu0.icache.overall_mshr_miss_rate::total 0.027590 # mshr miss rate for overall accesses 833system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average ReadReq mshr miss latency 834system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8802.165899 # average ReadReq mshr miss latency 835system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency 836system.cpu0.icache.demand_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency 837system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency 838system.cpu0.icache.overall_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency 839system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency 840system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency 841system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency 842system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency 843system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 844system.cpu0.l2cache.prefetcher.num_hwpf_issued 1753692 # number of hwpf issued 845system.cpu0.l2cache.prefetcher.pfIdentified 1753724 # number of prefetch candidates identified 846system.cpu0.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue 847system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 848system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 849system.cpu0.l2cache.prefetcher.pfSpanPage 222140 # number of prefetches not generated due to page crossing 850system.cpu0.l2cache.tags.replacements 284631 # number of replacements 851system.cpu0.l2cache.tags.tagsinuse 16080.562269 # Cycle average of tags in use 852system.cpu0.l2cache.tags.total_refs 4811395 # Total number of references to valid blocks. 853system.cpu0.l2cache.tags.sampled_refs 300867 # Sample count of references to valid blocks. 854system.cpu0.l2cache.tags.avg_refs 15.991767 # Average number of references to valid blocks. 855system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 856system.cpu0.l2cache.tags.occ_blocks::writebacks 8557.843574 # Average occupied blocks per requestor 857system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.688699 # Average occupied blocks per requestor 858system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065125 # Average occupied blocks per requestor 859system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4677.760567 # Average occupied blocks per requestor 860system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1660.845415 # Average occupied blocks per requestor 861system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1126.358889 # Average occupied blocks per requestor 862system.cpu0.l2cache.tags.occ_percent::writebacks 0.522329 # Average percentage of cache occupancy 863system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003521 # Average percentage of cache occupancy 864system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 865system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285508 # Average percentage of cache occupancy 866system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.101370 # Average percentage of cache occupancy 867system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068747 # Average percentage of cache occupancy 868system.cpu0.l2cache.tags.occ_percent::total 0.981480 # Average percentage of cache occupancy 869system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1014 # Occupied blocks per task id 870system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 871system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15208 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 351 # Occupied blocks per task id 874system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 393 # Occupied blocks per task id 875system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 881system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4117 # Occupied blocks per task id 882system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7919 # Occupied blocks per task id 883system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2851 # Occupied blocks per task id 884system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061890 # Percentage of cache occupancy per task id 885system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 886system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928223 # Percentage of cache occupancy per task id 887system.cpu0.l2cache.tags.tag_accesses 85529410 # Number of tag accesses 888system.cpu0.l2cache.tags.data_accesses 85529410 # Number of data accesses 889system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77804 # number of ReadReq hits 890system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4292 # number of ReadReq hits 891system.cpu0.l2cache.ReadReq_hits::total 82096 # number of ReadReq hits 892system.cpu0.l2cache.Writeback_hits::writebacks 490243 # number of Writeback hits 893system.cpu0.l2cache.Writeback_hits::total 490243 # number of Writeback hits 894system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28207 # number of UpgradeReq hits 895system.cpu0.l2cache.UpgradeReq_hits::total 28207 # number of UpgradeReq hits 896system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1765 # number of SCUpgradeReq hits 897system.cpu0.l2cache.SCUpgradeReq_hits::total 1765 # number of SCUpgradeReq hits 898system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212310 # number of ReadExReq hits 899system.cpu0.l2cache.ReadExReq_hits::total 212310 # number of ReadExReq hits 900system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1823174 # number of ReadCleanReq hits 901system.cpu0.l2cache.ReadCleanReq_hits::total 1823174 # number of ReadCleanReq hits 902system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376441 # number of ReadSharedReq hits 903system.cpu0.l2cache.ReadSharedReq_hits::total 376441 # number of ReadSharedReq hits 904system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77804 # number of demand (read+write) hits 905system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4292 # number of demand (read+write) hits 906system.cpu0.l2cache.demand_hits::cpu0.inst 1823174 # number of demand (read+write) hits 907system.cpu0.l2cache.demand_hits::cpu0.data 588751 # number of demand (read+write) hits 908system.cpu0.l2cache.demand_hits::total 2494021 # number of demand (read+write) hits 909system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77804 # number of overall hits 910system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4292 # number of overall hits 911system.cpu0.l2cache.overall_hits::cpu0.inst 1823174 # number of overall hits 912system.cpu0.l2cache.overall_hits::cpu0.data 588751 # number of overall hits 913system.cpu0.l2cache.overall_hits::total 2494021 # number of overall hits 914system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 777 # number of ReadReq misses 915system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 131 # number of ReadReq misses 916system.cpu0.l2cache.ReadReq_misses::total 908 # number of ReadReq misses 917system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27955 # number of UpgradeReq misses 918system.cpu0.l2cache.UpgradeReq_misses::total 27955 # number of UpgradeReq misses 919system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19533 # number of SCUpgradeReq misses 920system.cpu0.l2cache.SCUpgradeReq_misses::total 19533 # number of SCUpgradeReq misses 921system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 922system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 923system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43457 # number of ReadExReq misses 924system.cpu0.l2cache.ReadExReq_misses::total 43457 # number of ReadExReq misses 925system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 63710 # number of ReadCleanReq misses 926system.cpu0.l2cache.ReadCleanReq_misses::total 63710 # number of ReadCleanReq misses 927system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101052 # number of ReadSharedReq misses 928system.cpu0.l2cache.ReadSharedReq_misses::total 101052 # number of ReadSharedReq misses 929system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 777 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::cpu0.itb.walker 131 # number of demand (read+write) misses 931system.cpu0.l2cache.demand_misses::cpu0.inst 63710 # number of demand (read+write) misses 932system.cpu0.l2cache.demand_misses::cpu0.data 144509 # number of demand (read+write) misses 933system.cpu0.l2cache.demand_misses::total 209127 # number of demand (read+write) misses 934system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 777 # number of overall misses 935system.cpu0.l2cache.overall_misses::cpu0.itb.walker 131 # number of overall misses 936system.cpu0.l2cache.overall_misses::cpu0.inst 63710 # number of overall misses 937system.cpu0.l2cache.overall_misses::cpu0.data 144509 # number of overall misses 938system.cpu0.l2cache.overall_misses::total 209127 # number of overall misses 939system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 26295000 # number of ReadReq miss cycles 940system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3189000 # number of ReadReq miss cycles 941system.cpu0.l2cache.ReadReq_miss_latency::total 29484000 # number of ReadReq miss cycles 942system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 514165000 # number of UpgradeReq miss cycles 943system.cpu0.l2cache.UpgradeReq_miss_latency::total 514165000 # number of UpgradeReq miss cycles 944system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396282000 # number of SCUpgradeReq miss cycles 945system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396282000 # number of SCUpgradeReq miss cycles 946system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 637497 # number of SCUpgradeFailReq miss cycles 947system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 637497 # number of SCUpgradeFailReq miss cycles 948system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2195149500 # number of ReadExReq miss cycles 949system.cpu0.l2cache.ReadExReq_miss_latency::total 2195149500 # number of ReadExReq miss cycles 950system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2860433500 # number of ReadCleanReq miss cycles 951system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2860433500 # number of ReadCleanReq miss cycles 952system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2915473994 # number of ReadSharedReq miss cycles 953system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2915473994 # number of ReadSharedReq miss cycles 954system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 26295000 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3189000 # number of demand (read+write) miss cycles 956system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2860433500 # number of demand (read+write) miss cycles 957system.cpu0.l2cache.demand_miss_latency::cpu0.data 5110623494 # number of demand (read+write) miss cycles 958system.cpu0.l2cache.demand_miss_latency::total 8000540994 # number of demand (read+write) miss cycles 959system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 26295000 # number of overall miss cycles 960system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3189000 # number of overall miss cycles 961system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2860433500 # number of overall miss cycles 962system.cpu0.l2cache.overall_miss_latency::cpu0.data 5110623494 # number of overall miss cycles 963system.cpu0.l2cache.overall_miss_latency::total 8000540994 # number of overall miss cycles 964system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78581 # number of ReadReq accesses(hits+misses) 965system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4423 # number of ReadReq accesses(hits+misses) 966system.cpu0.l2cache.ReadReq_accesses::total 83004 # number of ReadReq accesses(hits+misses) 967system.cpu0.l2cache.Writeback_accesses::writebacks 490243 # number of Writeback accesses(hits+misses) 968system.cpu0.l2cache.Writeback_accesses::total 490243 # number of Writeback accesses(hits+misses) 969system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56162 # number of UpgradeReq accesses(hits+misses) 970system.cpu0.l2cache.UpgradeReq_accesses::total 56162 # number of UpgradeReq accesses(hits+misses) 971system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21298 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu0.l2cache.SCUpgradeReq_accesses::total 21298 # number of SCUpgradeReq accesses(hits+misses) 973system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 974system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 975system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 255767 # number of ReadExReq accesses(hits+misses) 976system.cpu0.l2cache.ReadExReq_accesses::total 255767 # number of ReadExReq accesses(hits+misses) 977system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1886884 # number of ReadCleanReq accesses(hits+misses) 978system.cpu0.l2cache.ReadCleanReq_accesses::total 1886884 # number of ReadCleanReq accesses(hits+misses) 979system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477493 # number of ReadSharedReq accesses(hits+misses) 980system.cpu0.l2cache.ReadSharedReq_accesses::total 477493 # number of ReadSharedReq accesses(hits+misses) 981system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78581 # number of demand (read+write) accesses 982system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4423 # number of demand (read+write) accesses 983system.cpu0.l2cache.demand_accesses::cpu0.inst 1886884 # number of demand (read+write) accesses 984system.cpu0.l2cache.demand_accesses::cpu0.data 733260 # number of demand (read+write) accesses 985system.cpu0.l2cache.demand_accesses::total 2703148 # number of demand (read+write) accesses 986system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78581 # number of overall (read+write) accesses 987system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4423 # number of overall (read+write) accesses 988system.cpu0.l2cache.overall_accesses::cpu0.inst 1886884 # number of overall (read+write) accesses 989system.cpu0.l2cache.overall_accesses::cpu0.data 733260 # number of overall (read+write) accesses 990system.cpu0.l2cache.overall_accesses::total 2703148 # number of overall (read+write) accesses 991system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009888 # miss rate for ReadReq accesses 992system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029618 # miss rate for ReadReq accesses 993system.cpu0.l2cache.ReadReq_miss_rate::total 0.010939 # miss rate for ReadReq accesses 994system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.497756 # miss rate for UpgradeReq accesses 995system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.497756 # miss rate for UpgradeReq accesses 996system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.917128 # miss rate for SCUpgradeReq accesses 997system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.917128 # miss rate for SCUpgradeReq accesses 998system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 999system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1000system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169909 # miss rate for ReadExReq accesses 1001system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169909 # miss rate for ReadExReq accesses 1002system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.033765 # miss rate for ReadCleanReq accesses 1003system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.033765 # miss rate for ReadCleanReq accesses 1004system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211630 # miss rate for ReadSharedReq accesses 1005system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211630 # miss rate for ReadSharedReq accesses 1006system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009888 # miss rate for demand accesses 1007system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029618 # miss rate for demand accesses 1008system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033765 # miss rate for demand accesses 1009system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197077 # miss rate for demand accesses 1010system.cpu0.l2cache.demand_miss_rate::total 0.077364 # miss rate for demand accesses 1011system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009888 # miss rate for overall accesses 1012system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029618 # miss rate for overall accesses 1013system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033765 # miss rate for overall accesses 1014system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197077 # miss rate for overall accesses 1015system.cpu0.l2cache.overall_miss_rate::total 0.077364 # miss rate for overall accesses 1016system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.698842 # average ReadReq miss latency 1017system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24343.511450 # average ReadReq miss latency 1018system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32471.365639 # average ReadReq miss latency 1019system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18392.595242 # average UpgradeReq miss latency 1020system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18392.595242 # average UpgradeReq miss latency 1021system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20287.820611 # average SCUpgradeReq miss latency 1022system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20287.820611 # average SCUpgradeReq miss latency 1023system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 127499.400000 # average SCUpgradeFailReq miss latency 1024system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 127499.400000 # average SCUpgradeFailReq miss latency 1025system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50513.139425 # average ReadExReq miss latency 1026system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50513.139425 # average ReadExReq miss latency 1027system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44897.716214 # average ReadCleanReq miss latency 1028system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44897.716214 # average ReadCleanReq miss latency 1029system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28851.225052 # average ReadSharedReq miss latency 1030system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28851.225052 # average ReadSharedReq miss latency 1031system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.698842 # average overall miss latency 1032system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24343.511450 # average overall miss latency 1033system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44897.716214 # average overall miss latency 1034system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35365.433945 # average overall miss latency 1035system.cpu0.l2cache.demand_avg_miss_latency::total 38256.853462 # average overall miss latency 1036system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.698842 # average overall miss latency 1037system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24343.511450 # average overall miss latency 1038system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44897.716214 # average overall miss latency 1039system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35365.433945 # average overall miss latency 1040system.cpu0.l2cache.overall_avg_miss_latency::total 38256.853462 # average overall miss latency 1041system.cpu0.l2cache.blocked_cycles::no_mshrs 59 # number of cycles access was blocked 1042system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1043system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1044system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1045system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked 1046system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1047system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1048system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1049system.cpu0.l2cache.writebacks::writebacks 195819 # number of writebacks 1050system.cpu0.l2cache.writebacks::total 195819 # number of writebacks 1051system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2770 # number of ReadExReq MSHR hits 1052system.cpu0.l2cache.ReadExReq_mshr_hits::total 2770 # number of ReadExReq MSHR hits 1053system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 71 # number of ReadCleanReq MSHR hits 1054system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 71 # number of ReadCleanReq MSHR hits 1055system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 354 # number of ReadSharedReq MSHR hits 1056system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 354 # number of ReadSharedReq MSHR hits 1057system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 71 # number of demand (read+write) MSHR hits 1058system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3124 # number of demand (read+write) MSHR hits 1059system.cpu0.l2cache.demand_mshr_hits::total 3195 # number of demand (read+write) MSHR hits 1060system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 71 # number of overall MSHR hits 1061system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3124 # number of overall MSHR hits 1062system.cpu0.l2cache.overall_mshr_hits::total 3195 # number of overall MSHR hits 1063system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 777 # number of ReadReq MSHR misses 1064system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 131 # number of ReadReq MSHR misses 1065system.cpu0.l2cache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses 1066system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9247 # number of CleanEvict MSHR misses 1067system.cpu0.l2cache.CleanEvict_mshr_misses::total 9247 # number of CleanEvict MSHR misses 1068system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232905 # number of HardPFReq MSHR misses 1069system.cpu0.l2cache.HardPFReq_mshr_misses::total 232905 # number of HardPFReq MSHR misses 1070system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27955 # number of UpgradeReq MSHR misses 1071system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27955 # number of UpgradeReq MSHR misses 1072system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19533 # number of SCUpgradeReq MSHR misses 1073system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19533 # number of SCUpgradeReq MSHR misses 1074system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1075system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1076system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40687 # number of ReadExReq MSHR misses 1077system.cpu0.l2cache.ReadExReq_mshr_misses::total 40687 # number of ReadExReq MSHR misses 1078system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 63639 # number of ReadCleanReq MSHR misses 1079system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 63639 # number of ReadCleanReq MSHR misses 1080system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100698 # number of ReadSharedReq MSHR misses 1081system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100698 # number of ReadSharedReq MSHR misses 1082system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 777 # number of demand (read+write) MSHR misses 1083system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 131 # number of demand (read+write) MSHR misses 1084system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63639 # number of demand (read+write) MSHR misses 1085system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141385 # number of demand (read+write) MSHR misses 1086system.cpu0.l2cache.demand_mshr_misses::total 205932 # number of demand (read+write) MSHR misses 1087system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 777 # number of overall MSHR misses 1088system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 131 # number of overall MSHR misses 1089system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63639 # number of overall MSHR misses 1090system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141385 # number of overall MSHR misses 1091system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232905 # number of overall MSHR misses 1092system.cpu0.l2cache.overall_mshr_misses::total 438837 # number of overall MSHR misses 1093system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable 1094system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29426 # number of ReadReq MSHR uncacheable 1095system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32852 # number of ReadReq MSHR uncacheable 1096system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26162 # number of WriteReq MSHR uncacheable 1097system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26162 # number of WriteReq MSHR uncacheable 1098system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses 1099system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55588 # number of overall MSHR uncacheable misses 1100system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 59014 # number of overall MSHR uncacheable misses 1101system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21633000 # number of ReadReq MSHR miss cycles 1102system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2403000 # number of ReadReq MSHR miss cycles 1103system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 24036000 # number of ReadReq MSHR miss cycles 1104system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13888716397 # number of HardPFReq MSHR miss cycles 1105system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13888716397 # number of HardPFReq MSHR miss cycles 1106system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 558509999 # number of UpgradeReq MSHR miss cycles 1107system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 558509999 # number of UpgradeReq MSHR miss cycles 1108system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298853000 # number of SCUpgradeReq MSHR miss cycles 1109system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298853000 # number of SCUpgradeReq MSHR miss cycles 1110system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 529497 # number of SCUpgradeFailReq MSHR miss cycles 1111system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 529497 # number of SCUpgradeFailReq MSHR miss cycles 1112system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1645934000 # number of ReadExReq MSHR miss cycles 1113system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1645934000 # number of ReadExReq MSHR miss cycles 1114system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2476915500 # number of ReadCleanReq MSHR miss cycles 1115system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2476915500 # number of ReadCleanReq MSHR miss cycles 1116system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2292009994 # number of ReadSharedReq MSHR miss cycles 1117system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2292009994 # number of ReadSharedReq MSHR miss cycles 1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21633000 # number of demand (read+write) MSHR miss cycles 1119system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2403000 # number of demand (read+write) MSHR miss cycles 1120system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2476915500 # number of demand (read+write) MSHR miss cycles 1121system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3937943994 # number of demand (read+write) MSHR miss cycles 1122system.cpu0.l2cache.demand_mshr_miss_latency::total 6438895494 # number of demand (read+write) MSHR miss cycles 1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21633000 # number of overall MSHR miss cycles 1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2403000 # number of overall MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2476915500 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3937943994 # number of overall MSHR miss cycles 1127system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13888716397 # number of overall MSHR miss cycles 1128system.cpu0.l2cache.overall_mshr_miss_latency::total 20327611891 # number of overall MSHR miss cycles 1129system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 286870500 # number of ReadReq MSHR uncacheable cycles 1130system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5461072000 # number of ReadReq MSHR uncacheable cycles 1131system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5747942500 # number of ReadReq MSHR uncacheable cycles 1132system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4118636500 # number of WriteReq MSHR uncacheable cycles 1133system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4118636500 # number of WriteReq MSHR uncacheable cycles 1134system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 286870500 # number of overall MSHR uncacheable cycles 1135system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9579708500 # number of overall MSHR uncacheable cycles 1136system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9866579000 # number of overall MSHR uncacheable cycles 1137system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009888 # mshr miss rate for ReadReq accesses 1138system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029618 # mshr miss rate for ReadReq accesses 1139system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010939 # mshr miss rate for ReadReq accesses 1140system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1141system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1142system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1143system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1144system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.497756 # mshr miss rate for UpgradeReq accesses 1145system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.497756 # mshr miss rate for UpgradeReq accesses 1146system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.917128 # mshr miss rate for SCUpgradeReq accesses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.917128 # mshr miss rate for SCUpgradeReq accesses 1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1150system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159078 # mshr miss rate for ReadExReq accesses 1151system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159078 # mshr miss rate for ReadExReq accesses 1152system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.033727 # mshr miss rate for ReadCleanReq accesses 1153system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033727 # mshr miss rate for ReadCleanReq accesses 1154system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210889 # mshr miss rate for ReadSharedReq accesses 1155system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.210889 # mshr miss rate for ReadSharedReq accesses 1156system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009888 # mshr miss rate for demand accesses 1157system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029618 # mshr miss rate for demand accesses 1158system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033727 # mshr miss rate for demand accesses 1159system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for demand accesses 1160system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076182 # mshr miss rate for demand accesses 1161system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009888 # mshr miss rate for overall accesses 1162system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029618 # mshr miss rate for overall accesses 1163system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033727 # mshr miss rate for overall accesses 1164system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses 1165system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1166system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162343 # mshr miss rate for overall accesses 1167system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average ReadReq mshr miss latency 1168system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average ReadReq mshr miss latency 1169system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26471.365639 # average ReadReq mshr miss latency 1170system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average HardPFReq mshr miss latency 1171system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59632.538576 # average HardPFReq mshr miss latency 1172system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19978.894616 # average UpgradeReq mshr miss latency 1173system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19978.894616 # average UpgradeReq mshr miss latency 1174system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15299.902729 # average SCUpgradeReq mshr miss latency 1175system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15299.902729 # average SCUpgradeReq mshr miss latency 1176system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 105899.400000 # average SCUpgradeFailReq mshr miss latency 1177system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 105899.400000 # average SCUpgradeFailReq mshr miss latency 1178system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40453.560105 # average ReadExReq mshr miss latency 1179system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40453.560105 # average ReadExReq mshr miss latency 1180system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average ReadCleanReq mshr miss latency 1181system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38921.345401 # average ReadCleanReq mshr miss latency 1182system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22761.226578 # average ReadSharedReq mshr miss latency 1183system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22761.226578 # average ReadSharedReq mshr miss latency 1184system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency 1185system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency 1186system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency 1187system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency 1188system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31267.095420 # average overall mshr miss latency 1189system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency 1190system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency 1191system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency 1192system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency 1193system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average overall mshr miss latency 1194system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46321.554224 # average overall mshr miss latency 1195system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency 1196system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185586.624074 # average ReadReq mshr uncacheable latency 1197system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174964.766224 # average ReadReq mshr uncacheable latency 1198system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157428.197386 # average WriteReq mshr uncacheable latency 1199system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157428.197386 # average WriteReq mshr uncacheable latency 1200system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency 1201system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172334.109880 # average overall mshr uncacheable latency 1202system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167190.480225 # average overall mshr uncacheable latency 1203system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1204system.cpu0.toL2Bus.trans_dist::ReadReq 134550 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::ReadResp 2542059 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::WriteResp 26162 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::Writeback 862676 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::CleanEvict 2186135 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::HardPFReq 279695 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::UpgradeReq 92964 # Transaction distribution 1212system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43745 # Transaction distribution 1213system.cpu0.toL2Bus.trans_dist::UpgradeResp 114531 # Transaction distribution 1214system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 1215system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution 1216system.cpu0.toL2Bus.trans_dist::ReadExReq 284097 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::ReadExResp 270085 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1886884 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603437 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1221system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5633887 # Packet count per connected master and slave (bytes) 1222system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2503276 # Packet count per connected master and slave (bytes) 1223system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11828 # Packet count per connected master and slave (bytes) 1224system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167039 # Packet count per connected master and slave (bytes) 1225system.cpu0.toL2Bus.pkt_count::total 8316030 # Packet count per connected master and slave (bytes) 1226system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120979776 # Cumulative packet size per connected master and slave (bytes) 1227system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82538715 # Cumulative packet size per connected master and slave (bytes) 1228system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17692 # Cumulative packet size per connected master and slave (bytes) 1229system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314324 # Cumulative packet size per connected master and slave (bytes) 1230system.cpu0.toL2Bus.pkt_size::total 203850507 # Cumulative packet size per connected master and slave (bytes) 1231system.cpu0.toL2Bus.snoops 1178802 # Total snoops (count) 1232system.cpu0.toL2Bus.snoop_fanout::samples 6482684 # Request fanout histogram 1233system.cpu0.toL2Bus.snoop_fanout::mean 1.179159 # Request fanout histogram 1234system.cpu0.toL2Bus.snoop_fanout::stdev 0.383485 # Request fanout histogram 1235system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1236system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1237system.cpu0.toL2Bus.snoop_fanout::1 5321256 82.08% 82.08% # Request fanout histogram 1238system.cpu0.toL2Bus.snoop_fanout::2 1161428 17.92% 100.00% # Request fanout histogram 1239system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1240system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1241system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::total 6482684 # Request fanout histogram 1243system.cpu0.toL2Bus.reqLayer0.occupancy 3211889987 # Layer occupancy (ticks) 1244system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1245system.cpu0.toL2Bus.snoopLayer0.occupancy 113481999 # Layer occupancy (ticks) 1246system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1247system.cpu0.toL2Bus.respLayer0.occupancy 2835744437 # Layer occupancy (ticks) 1248system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1249system.cpu0.toL2Bus.respLayer1.occupancy 1181675942 # Layer occupancy (ticks) 1250system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1251system.cpu0.toL2Bus.respLayer2.occupancy 7408493 # Layer occupancy (ticks) 1252system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1253system.cpu0.toL2Bus.respLayer3.occupancy 88460994 # Layer occupancy (ticks) 1254system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1255system.cpu1.branchPred.lookups 5445699 # Number of BP lookups 1256system.cpu1.branchPred.condPredicted 3358034 # Number of conditional branches predicted 1257system.cpu1.branchPred.condIncorrect 328537 # Number of conditional branches incorrect 1258system.cpu1.branchPred.BTBLookups 3334781 # Number of BTB lookups 1259system.cpu1.branchPred.BTBHits 2260975 # Number of BTB hits 1260system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1261system.cpu1.branchPred.BTBHitPct 67.799805 # BTB Hit Percentage 1262system.cpu1.branchPred.usedRAS 969415 # Number of times the RAS was used to get a target. 1263system.cpu1.branchPred.RASInCorrect 68088 # Number of incorrect RAS predictions. 1264system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1265system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1266system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1267system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1273system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1274system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1275system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1276system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1277system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1278system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1279system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1280system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1281system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1282system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1283system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1284system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1285system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1286system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1287system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1288system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1289system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1290system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1291system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1292system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1293system.cpu1.dtb.walker.walks 29420 # Table walker walks requested 1294system.cpu1.dtb.walker.walksShort 29420 # Table walker walks initiated with short descriptors 1295system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21788 # Level at which table walker walks with short descriptors terminate 1296system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7632 # Level at which table walker walks with short descriptors terminate 1297system.cpu1.dtb.walker.walkWaitTime::samples 29420 # Table walker wait (enqueue to first request) latency 1298system.cpu1.dtb.walker.walkWaitTime::0 29420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1299system.cpu1.dtb.walker.walkWaitTime::total 29420 # Table walker wait (enqueue to first request) latency 1300system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency 1301system.cpu1.dtb.walker.walkCompletionTime::mean 10739.844904 # Table walker service (enqueue to completion) latency 1302system.cpu1.dtb.walker.walkCompletionTime::gmean 9761.358244 # Table walker service (enqueue to completion) latency 1303system.cpu1.dtb.walker.walkCompletionTime::stdev 6619.660152 # Table walker service (enqueue to completion) latency 1304system.cpu1.dtb.walker.walkCompletionTime::0-16383 2565 94.72% 94.72% # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::16384-32767 128 4.73% 99.45% # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.30% 99.74% # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.04% 99.78% # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::81920-98303 4 0.15% 99.93% # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walksPending::samples 1720699264 # Table walker pending requests distribution 1313system.cpu1.dtb.walker.walksPending::0 1720699264 100.00% 100.00% # Table walker pending requests distribution 1314system.cpu1.dtb.walker.walksPending::total 1720699264 # Table walker pending requests distribution 1315system.cpu1.dtb.walker.walkPageSizes::4K 2021 74.63% 74.63% # Table walker page sizes translated 1316system.cpu1.dtb.walker.walkPageSizes::1M 687 25.37% 100.00% # Table walker page sizes translated 1317system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated 1318system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 29420 # Table walker requests started/completed, data/inst 1319system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1320system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 29420 # Table walker requests started/completed, data/inst 1321system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst 1322system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1323system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst 1324system.cpu1.dtb.walker.walkRequestOrigin::total 32128 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.inst_hits 0 # ITB inst hits 1326system.cpu1.dtb.inst_misses 0 # ITB inst misses 1327system.cpu1.dtb.read_hits 5163963 # DTB read hits 1328system.cpu1.dtb.read_misses 27269 # DTB read misses 1329system.cpu1.dtb.write_hits 4235498 # DTB write hits 1330system.cpu1.dtb.write_misses 2151 # DTB write misses 1331system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1332system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1333system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1334system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1335system.cpu1.dtb.flush_entries 2054 # Number of entries that have been flushed from TLB 1336system.cpu1.dtb.align_faults 296 # Number of TLB faults due to alignment restrictions 1337system.cpu1.dtb.prefetch_faults 518 # Number of TLB faults due to prefetch 1338system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1339system.cpu1.dtb.perms_faults 294 # Number of TLB faults due to permissions restrictions 1340system.cpu1.dtb.read_accesses 5191232 # DTB read accesses 1341system.cpu1.dtb.write_accesses 4237649 # DTB write accesses 1342system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1343system.cpu1.dtb.hits 9399461 # DTB hits 1344system.cpu1.dtb.misses 29420 # DTB misses 1345system.cpu1.dtb.accesses 9428881 # DTB accesses 1346system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1347system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1348system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1349system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1355system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1356system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1357system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1358system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1359system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1360system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1361system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1362system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1363system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1364system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1365system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1366system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1367system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1368system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1369system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1370system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1371system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1372system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1373system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1374system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1375system.cpu1.itb.walker.walks 2244 # Table walker walks requested 1376system.cpu1.itb.walker.walksShort 2244 # Table walker walks initiated with short descriptors 1377system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1378system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2063 # Level at which table walker walks with short descriptors terminate 1379system.cpu1.itb.walker.walkWaitTime::samples 2244 # Table walker wait (enqueue to first request) latency 1380system.cpu1.itb.walker.walkWaitTime::0 2244 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1381system.cpu1.itb.walker.walkWaitTime::total 2244 # Table walker wait (enqueue to first request) latency 1382system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency 1383system.cpu1.itb.walker.walkCompletionTime::mean 10959.928762 # Table walker service (enqueue to completion) latency 1384system.cpu1.itb.walker.walkCompletionTime::gmean 10069.580655 # Table walker service (enqueue to completion) latency 1385system.cpu1.itb.walker.walkCompletionTime::stdev 5627.290327 # Table walker service (enqueue to completion) latency 1386system.cpu1.itb.walker.walkCompletionTime::0-8191 289 25.73% 25.73% # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::8192-16383 792 70.53% 96.26% # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 96.62% # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::24576-32767 34 3.03% 99.64% # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walksPending::samples 1720133764 # Table walker pending requests distribution 1394system.cpu1.itb.walker.walksPending::0 1720133764 100.00% 100.00% # Table walker pending requests distribution 1395system.cpu1.itb.walker.walksPending::total 1720133764 # Table walker pending requests distribution 1396system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated 1397system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated 1398system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated 1399system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1400system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2244 # Table walker requests started/completed, data/inst 1401system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2244 # Table walker requests started/completed, data/inst 1402system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst 1404system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst 1405system.cpu1.itb.walker.walkRequestOrigin::total 3367 # Table walker requests started/completed, data/inst 1406system.cpu1.itb.inst_hits 10150571 # ITB inst hits 1407system.cpu1.itb.inst_misses 2244 # ITB inst misses 1408system.cpu1.itb.read_hits 0 # DTB read hits 1409system.cpu1.itb.read_misses 0 # DTB read misses 1410system.cpu1.itb.write_hits 0 # DTB write hits 1411system.cpu1.itb.write_misses 0 # DTB write misses 1412system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1413system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1414system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1415system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1416system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB 1417system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1418system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1419system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1420system.cpu1.itb.perms_faults 1947 # Number of TLB faults due to permissions restrictions 1421system.cpu1.itb.read_accesses 0 # DTB read accesses 1422system.cpu1.itb.write_accesses 0 # DTB write accesses 1423system.cpu1.itb.inst_accesses 10152815 # ITB inst accesses 1424system.cpu1.itb.hits 10150571 # DTB hits 1425system.cpu1.itb.misses 2244 # DTB misses 1426system.cpu1.itb.accesses 10152815 # DTB accesses 1427system.cpu1.numCycles 54273174 # number of cpu cycles simulated 1428system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1429system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1430system.cpu1.committedInsts 20894475 # Number of instructions committed 1431system.cpu1.committedOps 25513831 # Number of ops (including micro ops) committed 1432system.cpu1.discardedOps 1850967 # Number of ops (including micro ops) which were discarded before commit 1433system.cpu1.numFetchSuspends 2736 # Number of times Execute suspended instruction fetching 1434system.cpu1.quiesceCycles 5637336830 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1435system.cpu1.cpi 2.597489 # CPI: cycles per instruction 1436system.cpu1.ipc 0.384987 # IPC: instructions per cycle 1437system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1438system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed 1439system.cpu1.tickCycles 38589177 # Number of cycles that the object actually ticked 1440system.cpu1.idleCycles 15683997 # Total number of cycles that the object has spent stopped 1441system.cpu1.dcache.tags.replacements 232297 # number of replacements 1442system.cpu1.dcache.tags.tagsinuse 482.192292 # Cycle average of tags in use 1443system.cpu1.dcache.tags.total_refs 8906174 # Total number of references to valid blocks. 1444system.cpu1.dcache.tags.sampled_refs 232671 # Sample count of references to valid blocks. 1445system.cpu1.dcache.tags.avg_refs 38.277972 # Average number of references to valid blocks. 1446system.cpu1.dcache.tags.warmup_cycle 90623150500 # Cycle when the warmup percentage was hit. 1447system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.192292 # Average occupied blocks per requestor 1448system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941782 # Average percentage of cache occupancy 1449system.cpu1.dcache.tags.occ_percent::total 0.941782 # Average percentage of cache occupancy 1450system.cpu1.dcache.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id 1451system.cpu1.dcache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id 1452system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id 1453system.cpu1.dcache.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id 1454system.cpu1.dcache.tags.tag_accesses 18859700 # Number of tag accesses 1455system.cpu1.dcache.tags.data_accesses 18859700 # Number of data accesses 1456system.cpu1.dcache.ReadReq_hits::cpu1.data 4719301 # number of ReadReq hits 1457system.cpu1.dcache.ReadReq_hits::total 4719301 # number of ReadReq hits 1458system.cpu1.dcache.WriteReq_hits::cpu1.data 3908024 # number of WriteReq hits 1459system.cpu1.dcache.WriteReq_hits::total 3908024 # number of WriteReq hits 1460system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65371 # number of SoftPFReq hits 1461system.cpu1.dcache.SoftPFReq_hits::total 65371 # number of SoftPFReq hits 1462system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88156 # number of LoadLockedReq hits 1463system.cpu1.dcache.LoadLockedReq_hits::total 88156 # number of LoadLockedReq hits 1464system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80067 # number of StoreCondReq hits 1465system.cpu1.dcache.StoreCondReq_hits::total 80067 # number of StoreCondReq hits 1466system.cpu1.dcache.demand_hits::cpu1.data 8627325 # number of demand (read+write) hits 1467system.cpu1.dcache.demand_hits::total 8627325 # number of demand (read+write) hits 1468system.cpu1.dcache.overall_hits::cpu1.data 8692696 # number of overall hits 1469system.cpu1.dcache.overall_hits::total 8692696 # number of overall hits 1470system.cpu1.dcache.ReadReq_misses::cpu1.data 183894 # number of ReadReq misses 1471system.cpu1.dcache.ReadReq_misses::total 183894 # number of ReadReq misses 1472system.cpu1.dcache.WriteReq_misses::cpu1.data 168264 # number of WriteReq misses 1473system.cpu1.dcache.WriteReq_misses::total 168264 # number of WriteReq misses 1474system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35705 # number of SoftPFReq misses 1475system.cpu1.dcache.SoftPFReq_misses::total 35705 # number of SoftPFReq misses 1476system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17716 # number of LoadLockedReq misses 1477system.cpu1.dcache.LoadLockedReq_misses::total 17716 # number of LoadLockedReq misses 1478system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23526 # number of StoreCondReq misses 1479system.cpu1.dcache.StoreCondReq_misses::total 23526 # number of StoreCondReq misses 1480system.cpu1.dcache.demand_misses::cpu1.data 352158 # number of demand (read+write) misses 1481system.cpu1.dcache.demand_misses::total 352158 # number of demand (read+write) misses 1482system.cpu1.dcache.overall_misses::cpu1.data 387863 # number of overall misses 1483system.cpu1.dcache.overall_misses::total 387863 # number of overall misses 1484system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2718275000 # number of ReadReq miss cycles 1485system.cpu1.dcache.ReadReq_miss_latency::total 2718275000 # number of ReadReq miss cycles 1486system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4151672000 # number of WriteReq miss cycles 1487system.cpu1.dcache.WriteReq_miss_latency::total 4151672000 # number of WriteReq miss cycles 1488system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326404500 # number of LoadLockedReq miss cycles 1489system.cpu1.dcache.LoadLockedReq_miss_latency::total 326404500 # number of LoadLockedReq miss cycles 1490system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549519500 # number of StoreCondReq miss cycles 1491system.cpu1.dcache.StoreCondReq_miss_latency::total 549519500 # number of StoreCondReq miss cycles 1492system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 392000 # number of StoreCondFailReq miss cycles 1493system.cpu1.dcache.StoreCondFailReq_miss_latency::total 392000 # number of StoreCondFailReq miss cycles 1494system.cpu1.dcache.demand_miss_latency::cpu1.data 6869947000 # number of demand (read+write) miss cycles 1495system.cpu1.dcache.demand_miss_latency::total 6869947000 # number of demand (read+write) miss cycles 1496system.cpu1.dcache.overall_miss_latency::cpu1.data 6869947000 # number of overall miss cycles 1497system.cpu1.dcache.overall_miss_latency::total 6869947000 # number of overall miss cycles 1498system.cpu1.dcache.ReadReq_accesses::cpu1.data 4903195 # number of ReadReq accesses(hits+misses) 1499system.cpu1.dcache.ReadReq_accesses::total 4903195 # number of ReadReq accesses(hits+misses) 1500system.cpu1.dcache.WriteReq_accesses::cpu1.data 4076288 # number of WriteReq accesses(hits+misses) 1501system.cpu1.dcache.WriteReq_accesses::total 4076288 # number of WriteReq accesses(hits+misses) 1502system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101076 # number of SoftPFReq accesses(hits+misses) 1503system.cpu1.dcache.SoftPFReq_accesses::total 101076 # number of SoftPFReq accesses(hits+misses) 1504system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105872 # number of LoadLockedReq accesses(hits+misses) 1505system.cpu1.dcache.LoadLockedReq_accesses::total 105872 # number of LoadLockedReq accesses(hits+misses) 1506system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103593 # number of StoreCondReq accesses(hits+misses) 1507system.cpu1.dcache.StoreCondReq_accesses::total 103593 # number of StoreCondReq accesses(hits+misses) 1508system.cpu1.dcache.demand_accesses::cpu1.data 8979483 # number of demand (read+write) accesses 1509system.cpu1.dcache.demand_accesses::total 8979483 # number of demand (read+write) accesses 1510system.cpu1.dcache.overall_accesses::cpu1.data 9080559 # number of overall (read+write) accesses 1511system.cpu1.dcache.overall_accesses::total 9080559 # number of overall (read+write) accesses 1512system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037505 # miss rate for ReadReq accesses 1513system.cpu1.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses 1514system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041279 # miss rate for WriteReq accesses 1515system.cpu1.dcache.WriteReq_miss_rate::total 0.041279 # miss rate for WriteReq accesses 1516system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353249 # miss rate for SoftPFReq accesses 1517system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353249 # miss rate for SoftPFReq accesses 1518system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167334 # miss rate for LoadLockedReq accesses 1519system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167334 # miss rate for LoadLockedReq accesses 1520system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227100 # miss rate for StoreCondReq accesses 1521system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227100 # miss rate for StoreCondReq accesses 1522system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039218 # miss rate for demand accesses 1523system.cpu1.dcache.demand_miss_rate::total 0.039218 # miss rate for demand accesses 1524system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042714 # miss rate for overall accesses 1525system.cpu1.dcache.overall_miss_rate::total 0.042714 # miss rate for overall accesses 1526system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14781.749269 # average ReadReq miss latency 1527system.cpu1.dcache.ReadReq_avg_miss_latency::total 14781.749269 # average ReadReq miss latency 1528system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24673.560595 # average WriteReq miss latency 1529system.cpu1.dcache.WriteReq_avg_miss_latency::total 24673.560595 # average WriteReq miss latency 1530system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18424.277489 # average LoadLockedReq miss latency 1531system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18424.277489 # average LoadLockedReq miss latency 1532system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23357.965655 # average StoreCondReq miss latency 1533system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23357.965655 # average StoreCondReq miss latency 1534system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1535system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1536system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19508.138392 # average overall miss latency 1537system.cpu1.dcache.demand_avg_miss_latency::total 19508.138392 # average overall miss latency 1538system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17712.303055 # average overall miss latency 1539system.cpu1.dcache.overall_avg_miss_latency::total 17712.303055 # average overall miss latency 1540system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1541system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1542system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1543system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1544system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1545system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1546system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1547system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1548system.cpu1.dcache.writebacks::writebacks 139329 # number of writebacks 1549system.cpu1.dcache.writebacks::total 139329 # number of writebacks 1550system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18066 # number of ReadReq MSHR hits 1551system.cpu1.dcache.ReadReq_mshr_hits::total 18066 # number of ReadReq MSHR hits 1552system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62670 # number of WriteReq MSHR hits 1553system.cpu1.dcache.WriteReq_mshr_hits::total 62670 # number of WriteReq MSHR hits 1554system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # number of LoadLockedReq MSHR hits 1555system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12262 # number of LoadLockedReq MSHR hits 1556system.cpu1.dcache.demand_mshr_hits::cpu1.data 80736 # number of demand (read+write) MSHR hits 1557system.cpu1.dcache.demand_mshr_hits::total 80736 # number of demand (read+write) MSHR hits 1558system.cpu1.dcache.overall_mshr_hits::cpu1.data 80736 # number of overall MSHR hits 1559system.cpu1.dcache.overall_mshr_hits::total 80736 # number of overall MSHR hits 1560system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165828 # number of ReadReq MSHR misses 1561system.cpu1.dcache.ReadReq_mshr_misses::total 165828 # number of ReadReq MSHR misses 1562system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105594 # number of WriteReq MSHR misses 1563system.cpu1.dcache.WriteReq_mshr_misses::total 105594 # number of WriteReq MSHR misses 1564system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 34258 # number of SoftPFReq MSHR misses 1565system.cpu1.dcache.SoftPFReq_mshr_misses::total 34258 # number of SoftPFReq MSHR misses 1566system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5454 # number of LoadLockedReq MSHR misses 1567system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5454 # number of LoadLockedReq MSHR misses 1568system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23526 # number of StoreCondReq MSHR misses 1569system.cpu1.dcache.StoreCondReq_mshr_misses::total 23526 # number of StoreCondReq MSHR misses 1570system.cpu1.dcache.demand_mshr_misses::cpu1.data 271422 # number of demand (read+write) MSHR misses 1571system.cpu1.dcache.demand_mshr_misses::total 271422 # number of demand (read+write) MSHR misses 1572system.cpu1.dcache.overall_mshr_misses::cpu1.data 305680 # number of overall MSHR misses 1573system.cpu1.dcache.overall_mshr_misses::total 305680 # number of overall MSHR misses 1574system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5722 # number of ReadReq MSHR uncacheable 1575system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5722 # number of ReadReq MSHR uncacheable 1576system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5009 # number of WriteReq MSHR uncacheable 1577system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5009 # number of WriteReq MSHR uncacheable 1578system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10731 # number of overall MSHR uncacheable misses 1579system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10731 # number of overall MSHR uncacheable misses 1580system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2294657000 # number of ReadReq MSHR miss cycles 1581system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2294657000 # number of ReadReq MSHR miss cycles 1582system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2511298500 # number of WriteReq MSHR miss cycles 1583system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2511298500 # number of WriteReq MSHR miss cycles 1584system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 559951000 # number of SoftPFReq MSHR miss cycles 1585system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 559951000 # number of SoftPFReq MSHR miss cycles 1586system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93173500 # number of LoadLockedReq MSHR miss cycles 1587system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93173500 # number of LoadLockedReq MSHR miss cycles 1588system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 526001500 # number of StoreCondReq MSHR miss cycles 1589system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 526001500 # number of StoreCondReq MSHR miss cycles 1590system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 384000 # number of StoreCondFailReq MSHR miss cycles 1591system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 384000 # number of StoreCondFailReq MSHR miss cycles 1592system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4805955500 # number of demand (read+write) MSHR miss cycles 1593system.cpu1.dcache.demand_mshr_miss_latency::total 4805955500 # number of demand (read+write) MSHR miss cycles 1594system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5365906500 # number of overall MSHR miss cycles 1595system.cpu1.dcache.overall_mshr_miss_latency::total 5365906500 # number of overall MSHR miss cycles 1596system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 990469500 # number of ReadReq MSHR uncacheable cycles 1597system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 990469500 # number of ReadReq MSHR uncacheable cycles 1598system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857774500 # number of WriteReq MSHR uncacheable cycles 1599system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857774500 # number of WriteReq MSHR uncacheable cycles 1600system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1848244000 # number of overall MSHR uncacheable cycles 1601system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1848244000 # number of overall MSHR uncacheable cycles 1602system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses 1603system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033820 # mshr miss rate for ReadReq accesses 1604system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025904 # mshr miss rate for WriteReq accesses 1605system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025904 # mshr miss rate for WriteReq accesses 1606system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.338933 # mshr miss rate for SoftPFReq accesses 1607system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.338933 # mshr miss rate for SoftPFReq accesses 1608system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051515 # mshr miss rate for LoadLockedReq accesses 1609system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051515 # mshr miss rate for LoadLockedReq accesses 1610system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227100 # mshr miss rate for StoreCondReq accesses 1611system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227100 # mshr miss rate for StoreCondReq accesses 1612system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030227 # mshr miss rate for demand accesses 1613system.cpu1.dcache.demand_mshr_miss_rate::total 0.030227 # mshr miss rate for demand accesses 1614system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033663 # mshr miss rate for overall accesses 1615system.cpu1.dcache.overall_mshr_miss_rate::total 0.033663 # mshr miss rate for overall accesses 1616system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13837.572666 # average ReadReq mshr miss latency 1617system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13837.572666 # average ReadReq mshr miss latency 1618system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23782.587079 # average WriteReq mshr miss latency 1619system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23782.587079 # average WriteReq mshr miss latency 1620system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16345.116469 # average SoftPFReq mshr miss latency 1621system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16345.116469 # average SoftPFReq mshr miss latency 1622system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17083.516685 # average LoadLockedReq mshr miss latency 1623system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17083.516685 # average LoadLockedReq mshr miss latency 1624system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22358.305704 # average StoreCondReq mshr miss latency 1625system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22358.305704 # average StoreCondReq mshr miss latency 1626system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1627system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1628system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17706.580528 # average overall mshr miss latency 1629system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17706.580528 # average overall mshr miss latency 1630system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17553.999280 # average overall mshr miss latency 1631system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17553.999280 # average overall mshr miss latency 1632system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173098.479553 # average ReadReq mshr uncacheable latency 1633system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173098.479553 # average ReadReq mshr uncacheable latency 1634system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171246.656019 # average WriteReq mshr uncacheable latency 1635system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171246.656019 # average WriteReq mshr uncacheable latency 1636system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172234.088156 # average overall mshr uncacheable latency 1637system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 172234.088156 # average overall mshr uncacheable latency 1638system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1639system.cpu1.icache.tags.replacements 1036067 # number of replacements 1640system.cpu1.icache.tags.tagsinuse 499.306675 # Cycle average of tags in use 1641system.cpu1.icache.tags.total_refs 9111880 # Total number of references to valid blocks. 1642system.cpu1.icache.tags.sampled_refs 1036579 # Sample count of references to valid blocks. 1643system.cpu1.icache.tags.avg_refs 8.790338 # Average number of references to valid blocks. 1644system.cpu1.icache.tags.warmup_cycle 72226761500 # Cycle when the warmup percentage was hit. 1645system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.306675 # Average occupied blocks per requestor 1646system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975208 # Average percentage of cache occupancy 1647system.cpu1.icache.tags.occ_percent::total 0.975208 # Average percentage of cache occupancy 1648system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1649system.cpu1.icache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id 1650system.cpu1.icache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id 1651system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1652system.cpu1.icache.tags.tag_accesses 21333497 # Number of tag accesses 1653system.cpu1.icache.tags.data_accesses 21333497 # Number of data accesses 1654system.cpu1.icache.ReadReq_hits::cpu1.inst 9111880 # number of ReadReq hits 1655system.cpu1.icache.ReadReq_hits::total 9111880 # number of ReadReq hits 1656system.cpu1.icache.demand_hits::cpu1.inst 9111880 # number of demand (read+write) hits 1657system.cpu1.icache.demand_hits::total 9111880 # number of demand (read+write) hits 1658system.cpu1.icache.overall_hits::cpu1.inst 9111880 # number of overall hits 1659system.cpu1.icache.overall_hits::total 9111880 # number of overall hits 1660system.cpu1.icache.ReadReq_misses::cpu1.inst 1036579 # number of ReadReq misses 1661system.cpu1.icache.ReadReq_misses::total 1036579 # number of ReadReq misses 1662system.cpu1.icache.demand_misses::cpu1.inst 1036579 # number of demand (read+write) misses 1663system.cpu1.icache.demand_misses::total 1036579 # number of demand (read+write) misses 1664system.cpu1.icache.overall_misses::cpu1.inst 1036579 # number of overall misses 1665system.cpu1.icache.overall_misses::total 1036579 # number of overall misses 1666system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9180202500 # number of ReadReq miss cycles 1667system.cpu1.icache.ReadReq_miss_latency::total 9180202500 # number of ReadReq miss cycles 1668system.cpu1.icache.demand_miss_latency::cpu1.inst 9180202500 # number of demand (read+write) miss cycles 1669system.cpu1.icache.demand_miss_latency::total 9180202500 # number of demand (read+write) miss cycles 1670system.cpu1.icache.overall_miss_latency::cpu1.inst 9180202500 # number of overall miss cycles 1671system.cpu1.icache.overall_miss_latency::total 9180202500 # number of overall miss cycles 1672system.cpu1.icache.ReadReq_accesses::cpu1.inst 10148459 # number of ReadReq accesses(hits+misses) 1673system.cpu1.icache.ReadReq_accesses::total 10148459 # number of ReadReq accesses(hits+misses) 1674system.cpu1.icache.demand_accesses::cpu1.inst 10148459 # number of demand (read+write) accesses 1675system.cpu1.icache.demand_accesses::total 10148459 # number of demand (read+write) accesses 1676system.cpu1.icache.overall_accesses::cpu1.inst 10148459 # number of overall (read+write) accesses 1677system.cpu1.icache.overall_accesses::total 10148459 # number of overall (read+write) accesses 1678system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.102142 # miss rate for ReadReq accesses 1679system.cpu1.icache.ReadReq_miss_rate::total 0.102142 # miss rate for ReadReq accesses 1680system.cpu1.icache.demand_miss_rate::cpu1.inst 0.102142 # miss rate for demand accesses 1681system.cpu1.icache.demand_miss_rate::total 0.102142 # miss rate for demand accesses 1682system.cpu1.icache.overall_miss_rate::cpu1.inst 0.102142 # miss rate for overall accesses 1683system.cpu1.icache.overall_miss_rate::total 0.102142 # miss rate for overall accesses 1684system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.249741 # average ReadReq miss latency 1685system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.249741 # average ReadReq miss latency 1686system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.249741 # average overall miss latency 1687system.cpu1.icache.demand_avg_miss_latency::total 8856.249741 # average overall miss latency 1688system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.249741 # average overall miss latency 1689system.cpu1.icache.overall_avg_miss_latency::total 8856.249741 # average overall miss latency 1690system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1691system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1692system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1693system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1694system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1695system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1696system.cpu1.icache.fast_writes 0 # number of fast writes performed 1697system.cpu1.icache.cache_copies 0 # number of cache copies performed 1698system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1036579 # number of ReadReq MSHR misses 1699system.cpu1.icache.ReadReq_mshr_misses::total 1036579 # number of ReadReq MSHR misses 1700system.cpu1.icache.demand_mshr_misses::cpu1.inst 1036579 # number of demand (read+write) MSHR misses 1701system.cpu1.icache.demand_mshr_misses::total 1036579 # number of demand (read+write) MSHR misses 1702system.cpu1.icache.overall_mshr_misses::cpu1.inst 1036579 # number of overall MSHR misses 1703system.cpu1.icache.overall_mshr_misses::total 1036579 # number of overall MSHR misses 1704system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable 1705system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable 1706system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses 1707system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses 1708system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8661913000 # number of ReadReq MSHR miss cycles 1709system.cpu1.icache.ReadReq_mshr_miss_latency::total 8661913000 # number of ReadReq MSHR miss cycles 1710system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8661913000 # number of demand (read+write) MSHR miss cycles 1711system.cpu1.icache.demand_mshr_miss_latency::total 8661913000 # number of demand (read+write) MSHR miss cycles 1712system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8661913000 # number of overall MSHR miss cycles 1713system.cpu1.icache.overall_mshr_miss_latency::total 8661913000 # number of overall MSHR miss cycles 1714system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10059500 # number of ReadReq MSHR uncacheable cycles 1715system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10059500 # number of ReadReq MSHR uncacheable cycles 1716system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10059500 # number of overall MSHR uncacheable cycles 1717system.cpu1.icache.overall_mshr_uncacheable_latency::total 10059500 # number of overall MSHR uncacheable cycles 1718system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for ReadReq accesses 1719system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102142 # mshr miss rate for ReadReq accesses 1720system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for demand accesses 1721system.cpu1.icache.demand_mshr_miss_rate::total 0.102142 # mshr miss rate for demand accesses 1722system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for overall accesses 1723system.cpu1.icache.overall_mshr_miss_rate::total 0.102142 # mshr miss rate for overall accesses 1724system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average ReadReq mshr miss latency 1725system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8356.249741 # average ReadReq mshr miss latency 1726system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average overall mshr miss latency 1727system.cpu1.icache.demand_avg_mshr_miss_latency::total 8356.249741 # average overall mshr miss latency 1728system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average overall mshr miss latency 1729system.cpu1.icache.overall_avg_mshr_miss_latency::total 8356.249741 # average overall mshr miss latency 1730system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894 # average ReadReq mshr uncacheable latency 1731system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89022.123894 # average ReadReq mshr uncacheable latency 1732system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894 # average overall mshr uncacheable latency 1733system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89022.123894 # average overall mshr uncacheable latency 1734system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1735system.cpu1.l2cache.prefetcher.num_hwpf_issued 272165 # number of hwpf issued 1736system.cpu1.l2cache.prefetcher.pfIdentified 272190 # number of prefetch candidates identified 1737system.cpu1.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue 1738system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1739system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1740system.cpu1.l2cache.prefetcher.pfSpanPage 68922 # number of prefetches not generated due to page crossing 1741system.cpu1.l2cache.tags.replacements 69326 # number of replacements 1742system.cpu1.l2cache.tags.tagsinuse 15661.573061 # Cycle average of tags in use 1743system.cpu1.l2cache.tags.total_refs 2410564 # Total number of references to valid blocks. 1744system.cpu1.l2cache.tags.sampled_refs 84006 # Sample count of references to valid blocks. 1745system.cpu1.l2cache.tags.avg_refs 28.695141 # Average number of references to valid blocks. 1746system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1747system.cpu1.l2cache.tags.occ_blocks::writebacks 6188.157881 # Average occupied blocks per requestor 1748system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.165341 # Average occupied blocks per requestor 1749system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100614 # Average occupied blocks per requestor 1750system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5579.436781 # Average occupied blocks per requestor 1751system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2277.975966 # Average occupied blocks per requestor 1752system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1563.736478 # Average occupied blocks per requestor 1753system.cpu1.l2cache.tags.occ_percent::writebacks 0.377695 # Average percentage of cache occupancy 1754system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003184 # Average percentage of cache occupancy 1755system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1756system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.340542 # Average percentage of cache occupancy 1757system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.139037 # Average percentage of cache occupancy 1758system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.095443 # Average percentage of cache occupancy 1759system.cpu1.l2cache.tags.occ_percent::total 0.955907 # Average percentage of cache occupancy 1760system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1195 # Occupied blocks per task id 1761system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id 1762system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13435 # Occupied blocks per task id 1763system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 1764system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id 1765system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 525 # Occupied blocks per task id 1766system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1767system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id 1768system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 1769system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id 1770system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5728 # Occupied blocks per task id 1771system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7406 # Occupied blocks per task id 1772system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072937 # Percentage of cache occupancy per task id 1773system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id 1774system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.820007 # Percentage of cache occupancy per task id 1775system.cpu1.l2cache.tags.tag_accesses 42699170 # Number of tag accesses 1776system.cpu1.l2cache.tags.data_accesses 42699170 # Number of data accesses 1777system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32497 # number of ReadReq hits 1778system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2653 # number of ReadReq hits 1779system.cpu1.l2cache.ReadReq_hits::total 35150 # number of ReadReq hits 1780system.cpu1.l2cache.Writeback_hits::writebacks 139329 # number of Writeback hits 1781system.cpu1.l2cache.Writeback_hits::total 139329 # number of Writeback hits 1782system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2011 # number of UpgradeReq hits 1783system.cpu1.l2cache.UpgradeReq_hits::total 2011 # number of UpgradeReq hits 1784system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1071 # number of SCUpgradeReq hits 1785system.cpu1.l2cache.SCUpgradeReq_hits::total 1071 # number of SCUpgradeReq hits 1786system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38166 # number of ReadExReq hits 1787system.cpu1.l2cache.ReadExReq_hits::total 38166 # number of ReadExReq hits 1788system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1009291 # number of ReadCleanReq hits 1789system.cpu1.l2cache.ReadCleanReq_hits::total 1009291 # number of ReadCleanReq hits 1790system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131481 # number of ReadSharedReq hits 1791system.cpu1.l2cache.ReadSharedReq_hits::total 131481 # number of ReadSharedReq hits 1792system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 32497 # number of demand (read+write) hits 1793system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2653 # number of demand (read+write) hits 1794system.cpu1.l2cache.demand_hits::cpu1.inst 1009291 # number of demand (read+write) hits 1795system.cpu1.l2cache.demand_hits::cpu1.data 169647 # number of demand (read+write) hits 1796system.cpu1.l2cache.demand_hits::total 1214088 # number of demand (read+write) hits 1797system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 32497 # number of overall hits 1798system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2653 # number of overall hits 1799system.cpu1.l2cache.overall_hits::cpu1.inst 1009291 # number of overall hits 1800system.cpu1.l2cache.overall_hits::cpu1.data 169647 # number of overall hits 1801system.cpu1.l2cache.overall_hits::total 1214088 # number of overall hits 1802system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 719 # number of ReadReq misses 1803system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 229 # number of ReadReq misses 1804system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses 1805system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29485 # number of UpgradeReq misses 1806system.cpu1.l2cache.UpgradeReq_misses::total 29485 # number of UpgradeReq misses 1807system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22454 # number of SCUpgradeReq misses 1808system.cpu1.l2cache.SCUpgradeReq_misses::total 22454 # number of SCUpgradeReq misses 1809system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 1810system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1811system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35935 # number of ReadExReq misses 1812system.cpu1.l2cache.ReadExReq_misses::total 35935 # number of ReadExReq misses 1813system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27288 # number of ReadCleanReq misses 1814system.cpu1.l2cache.ReadCleanReq_misses::total 27288 # number of ReadCleanReq misses 1815system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74058 # number of ReadSharedReq misses 1816system.cpu1.l2cache.ReadSharedReq_misses::total 74058 # number of ReadSharedReq misses 1817system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 719 # number of demand (read+write) misses 1818system.cpu1.l2cache.demand_misses::cpu1.itb.walker 229 # number of demand (read+write) misses 1819system.cpu1.l2cache.demand_misses::cpu1.inst 27288 # number of demand (read+write) misses 1820system.cpu1.l2cache.demand_misses::cpu1.data 109993 # number of demand (read+write) misses 1821system.cpu1.l2cache.demand_misses::total 138229 # number of demand (read+write) misses 1822system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 719 # number of overall misses 1823system.cpu1.l2cache.overall_misses::cpu1.itb.walker 229 # number of overall misses 1824system.cpu1.l2cache.overall_misses::cpu1.inst 27288 # number of overall misses 1825system.cpu1.l2cache.overall_misses::cpu1.data 109993 # number of overall misses 1826system.cpu1.l2cache.overall_misses::total 138229 # number of overall misses 1827system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17830000 # number of ReadReq miss cycles 1828system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4703000 # number of ReadReq miss cycles 1829system.cpu1.l2cache.ReadReq_miss_latency::total 22533000 # number of ReadReq miss cycles 1830system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 557854000 # number of UpgradeReq miss cycles 1831system.cpu1.l2cache.UpgradeReq_miss_latency::total 557854000 # number of UpgradeReq miss cycles 1832system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449261000 # number of SCUpgradeReq miss cycles 1833system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449261000 # number of SCUpgradeReq miss cycles 1834system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 372000 # number of SCUpgradeFailReq miss cycles 1835system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 372000 # number of SCUpgradeFailReq miss cycles 1836system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1407590499 # number of ReadExReq miss cycles 1837system.cpu1.l2cache.ReadExReq_miss_latency::total 1407590499 # number of ReadExReq miss cycles 1838system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1060250500 # number of ReadCleanReq miss cycles 1839system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1060250500 # number of ReadCleanReq miss cycles 1840system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1775396994 # number of ReadSharedReq miss cycles 1841system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1775396994 # number of ReadSharedReq miss cycles 1842system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17830000 # number of demand (read+write) miss cycles 1843system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4703000 # number of demand (read+write) miss cycles 1844system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1060250500 # number of demand (read+write) miss cycles 1845system.cpu1.l2cache.demand_miss_latency::cpu1.data 3182987493 # number of demand (read+write) miss cycles 1846system.cpu1.l2cache.demand_miss_latency::total 4265770993 # number of demand (read+write) miss cycles 1847system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17830000 # number of overall miss cycles 1848system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4703000 # number of overall miss cycles 1849system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1060250500 # number of overall miss cycles 1850system.cpu1.l2cache.overall_miss_latency::cpu1.data 3182987493 # number of overall miss cycles 1851system.cpu1.l2cache.overall_miss_latency::total 4265770993 # number of overall miss cycles 1852system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33216 # number of ReadReq accesses(hits+misses) 1853system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2882 # number of ReadReq accesses(hits+misses) 1854system.cpu1.l2cache.ReadReq_accesses::total 36098 # number of ReadReq accesses(hits+misses) 1855system.cpu1.l2cache.Writeback_accesses::writebacks 139329 # number of Writeback accesses(hits+misses) 1856system.cpu1.l2cache.Writeback_accesses::total 139329 # number of Writeback accesses(hits+misses) 1857system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31496 # number of UpgradeReq accesses(hits+misses) 1858system.cpu1.l2cache.UpgradeReq_accesses::total 31496 # number of UpgradeReq accesses(hits+misses) 1859system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23525 # number of SCUpgradeReq accesses(hits+misses) 1860system.cpu1.l2cache.SCUpgradeReq_accesses::total 23525 # number of SCUpgradeReq accesses(hits+misses) 1861system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1862system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1863system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74101 # number of ReadExReq accesses(hits+misses) 1864system.cpu1.l2cache.ReadExReq_accesses::total 74101 # number of ReadExReq accesses(hits+misses) 1865system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1036579 # number of ReadCleanReq accesses(hits+misses) 1866system.cpu1.l2cache.ReadCleanReq_accesses::total 1036579 # number of ReadCleanReq accesses(hits+misses) 1867system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205539 # number of ReadSharedReq accesses(hits+misses) 1868system.cpu1.l2cache.ReadSharedReq_accesses::total 205539 # number of ReadSharedReq accesses(hits+misses) 1869system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33216 # number of demand (read+write) accesses 1870system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2882 # number of demand (read+write) accesses 1871system.cpu1.l2cache.demand_accesses::cpu1.inst 1036579 # number of demand (read+write) accesses 1872system.cpu1.l2cache.demand_accesses::cpu1.data 279640 # number of demand (read+write) accesses 1873system.cpu1.l2cache.demand_accesses::total 1352317 # number of demand (read+write) accesses 1874system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33216 # number of overall (read+write) accesses 1875system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2882 # number of overall (read+write) accesses 1876system.cpu1.l2cache.overall_accesses::cpu1.inst 1036579 # number of overall (read+write) accesses 1877system.cpu1.l2cache.overall_accesses::cpu1.data 279640 # number of overall (read+write) accesses 1878system.cpu1.l2cache.overall_accesses::total 1352317 # number of overall (read+write) accesses 1879system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for ReadReq accesses 1880system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079459 # miss rate for ReadReq accesses 1881system.cpu1.l2cache.ReadReq_miss_rate::total 0.026262 # miss rate for ReadReq accesses 1882system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936151 # miss rate for UpgradeReq accesses 1883system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936151 # miss rate for UpgradeReq accesses 1884system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.954474 # miss rate for SCUpgradeReq accesses 1885system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.954474 # miss rate for SCUpgradeReq accesses 1886system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1887system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1888system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484946 # miss rate for ReadExReq accesses 1889system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484946 # miss rate for ReadExReq accesses 1890system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026325 # miss rate for ReadCleanReq accesses 1891system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026325 # miss rate for ReadCleanReq accesses 1892system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360311 # miss rate for ReadSharedReq accesses 1893system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.360311 # miss rate for ReadSharedReq accesses 1894system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for demand accesses 1895system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079459 # miss rate for demand accesses 1896system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026325 # miss rate for demand accesses 1897system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.393338 # miss rate for demand accesses 1898system.cpu1.l2cache.demand_miss_rate::total 0.102216 # miss rate for demand accesses 1899system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for overall accesses 1900system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079459 # miss rate for overall accesses 1901system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026325 # miss rate for overall accesses 1902system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.393338 # miss rate for overall accesses 1903system.cpu1.l2cache.overall_miss_rate::total 0.102216 # miss rate for overall accesses 1904system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average ReadReq miss latency 1905system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20537.117904 # average ReadReq miss latency 1906system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23768.987342 # average ReadReq miss latency 1907system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18919.925386 # average UpgradeReq miss latency 1908system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18919.925386 # average UpgradeReq miss latency 1909system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20008.060925 # average SCUpgradeReq miss latency 1910system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20008.060925 # average SCUpgradeReq miss latency 1911system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372000 # average SCUpgradeFailReq miss latency 1912system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372000 # average SCUpgradeFailReq miss latency 1913system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39170.460526 # average ReadExReq miss latency 1914system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39170.460526 # average ReadExReq miss latency 1915system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38854.093374 # average ReadCleanReq miss latency 1916system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38854.093374 # average ReadCleanReq miss latency 1917system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23973.061573 # average ReadSharedReq miss latency 1918system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23973.061573 # average ReadSharedReq miss latency 1919system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average overall miss latency 1920system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20537.117904 # average overall miss latency 1921system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38854.093374 # average overall miss latency 1922system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28938.091451 # average overall miss latency 1923system.cpu1.l2cache.demand_avg_miss_latency::total 30860.174008 # average overall miss latency 1924system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average overall miss latency 1925system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20537.117904 # average overall miss latency 1926system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38854.093374 # average overall miss latency 1927system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28938.091451 # average overall miss latency 1928system.cpu1.l2cache.overall_avg_miss_latency::total 30860.174008 # average overall miss latency 1929system.cpu1.l2cache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked 1930system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1931system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1932system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1933system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked 1934system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1935system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1936system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1937system.cpu1.l2cache.writebacks::writebacks 37014 # number of writebacks 1938system.cpu1.l2cache.writebacks::total 37014 # number of writebacks 1939system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 288 # number of ReadExReq MSHR hits 1940system.cpu1.l2cache.ReadExReq_mshr_hits::total 288 # number of ReadExReq MSHR hits 1941system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 20 # number of ReadCleanReq MSHR hits 1942system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 1943system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 127 # number of ReadSharedReq MSHR hits 1944system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 127 # number of ReadSharedReq MSHR hits 1945system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 20 # number of demand (read+write) MSHR hits 1946system.cpu1.l2cache.demand_mshr_hits::cpu1.data 415 # number of demand (read+write) MSHR hits 1947system.cpu1.l2cache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits 1948system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 20 # number of overall MSHR hits 1949system.cpu1.l2cache.overall_mshr_hits::cpu1.data 415 # number of overall MSHR hits 1950system.cpu1.l2cache.overall_mshr_hits::total 435 # number of overall MSHR hits 1951system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 719 # number of ReadReq MSHR misses 1952system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 229 # number of ReadReq MSHR misses 1953system.cpu1.l2cache.ReadReq_mshr_misses::total 948 # number of ReadReq MSHR misses 1954system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3215 # number of CleanEvict MSHR misses 1955system.cpu1.l2cache.CleanEvict_mshr_misses::total 3215 # number of CleanEvict MSHR misses 1956system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35422 # number of HardPFReq MSHR misses 1957system.cpu1.l2cache.HardPFReq_mshr_misses::total 35422 # number of HardPFReq MSHR misses 1958system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29485 # number of UpgradeReq MSHR misses 1959system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29485 # number of UpgradeReq MSHR misses 1960system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22454 # number of SCUpgradeReq MSHR misses 1961system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22454 # number of SCUpgradeReq MSHR misses 1962system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 1963system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1964system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35647 # number of ReadExReq MSHR misses 1965system.cpu1.l2cache.ReadExReq_mshr_misses::total 35647 # number of ReadExReq MSHR misses 1966system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27268 # number of ReadCleanReq MSHR misses 1967system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27268 # number of ReadCleanReq MSHR misses 1968system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73931 # number of ReadSharedReq MSHR misses 1969system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73931 # number of ReadSharedReq MSHR misses 1970system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 719 # number of demand (read+write) MSHR misses 1971system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 229 # number of demand (read+write) MSHR misses 1972system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27268 # number of demand (read+write) MSHR misses 1973system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109578 # number of demand (read+write) MSHR misses 1974system.cpu1.l2cache.demand_mshr_misses::total 137794 # number of demand (read+write) MSHR misses 1975system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 719 # number of overall MSHR misses 1976system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 229 # number of overall MSHR misses 1977system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27268 # number of overall MSHR misses 1978system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109578 # number of overall MSHR misses 1979system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35422 # number of overall MSHR misses 1980system.cpu1.l2cache.overall_mshr_misses::total 173216 # number of overall MSHR misses 1981system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable 1982system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5722 # number of ReadReq MSHR uncacheable 1983system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5835 # number of ReadReq MSHR uncacheable 1984system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5009 # number of WriteReq MSHR uncacheable 1985system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5009 # number of WriteReq MSHR uncacheable 1986system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses 1987system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10731 # number of overall MSHR uncacheable misses 1988system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10844 # number of overall MSHR uncacheable misses 1989system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13516000 # number of ReadReq MSHR miss cycles 1990system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3329000 # number of ReadReq MSHR miss cycles 1991system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 16845000 # number of ReadReq MSHR miss cycles 1992system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1189902692 # number of HardPFReq MSHR miss cycles 1993system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1189902692 # number of HardPFReq MSHR miss cycles 1994system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 503727499 # number of UpgradeReq MSHR miss cycles 1995system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 503727499 # number of UpgradeReq MSHR miss cycles 1996system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348590500 # number of SCUpgradeReq MSHR miss cycles 1997system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348590500 # number of SCUpgradeReq MSHR miss cycles 1998system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 324000 # number of SCUpgradeFailReq MSHR miss cycles 1999system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 324000 # number of SCUpgradeFailReq MSHR miss cycles 2000system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1162178500 # number of ReadExReq MSHR miss cycles 2001system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1162178500 # number of ReadExReq MSHR miss cycles 2002system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 895970500 # number of ReadCleanReq MSHR miss cycles 2003system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 895970500 # number of ReadCleanReq MSHR miss cycles 2004system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1327142494 # number of ReadSharedReq MSHR miss cycles 2005system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1327142494 # number of ReadSharedReq MSHR miss cycles 2006system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13516000 # number of demand (read+write) MSHR miss cycles 2007system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3329000 # number of demand (read+write) MSHR miss cycles 2008system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 895970500 # number of demand (read+write) MSHR miss cycles 2009system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2489320994 # number of demand (read+write) MSHR miss cycles 2010system.cpu1.l2cache.demand_mshr_miss_latency::total 3402136494 # number of demand (read+write) MSHR miss cycles 2011system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13516000 # number of overall MSHR miss cycles 2012system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3329000 # number of overall MSHR miss cycles 2013system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 895970500 # number of overall MSHR miss cycles 2014system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2489320994 # number of overall MSHR miss cycles 2015system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1189902692 # number of overall MSHR miss cycles 2016system.cpu1.l2cache.overall_mshr_miss_latency::total 4592039186 # number of overall MSHR miss cycles 2017system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9155500 # number of ReadReq MSHR uncacheable cycles 2018system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 944653500 # number of ReadReq MSHR uncacheable cycles 2019system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 953809000 # number of ReadReq MSHR uncacheable cycles 2020system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 820084500 # number of WriteReq MSHR uncacheable cycles 2021system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 820084500 # number of WriteReq MSHR uncacheable cycles 2022system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9155500 # number of overall MSHR uncacheable cycles 2023system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1764738000 # number of overall MSHR uncacheable cycles 2024system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1773893500 # number of overall MSHR uncacheable cycles 2025system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for ReadReq accesses 2026system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for ReadReq accesses 2027system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026262 # mshr miss rate for ReadReq accesses 2028system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2029system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2030system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2031system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2032system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936151 # mshr miss rate for UpgradeReq accesses 2033system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936151 # mshr miss rate for UpgradeReq accesses 2034system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954474 # mshr miss rate for SCUpgradeReq accesses 2035system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954474 # mshr miss rate for SCUpgradeReq accesses 2036system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2037system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2038system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.481060 # mshr miss rate for ReadExReq accesses 2039system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.481060 # mshr miss rate for ReadExReq accesses 2040system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for ReadCleanReq accesses 2041system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026306 # mshr miss rate for ReadCleanReq accesses 2042system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359693 # mshr miss rate for ReadSharedReq accesses 2043system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359693 # mshr miss rate for ReadSharedReq accesses 2044system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for demand accesses 2045system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for demand accesses 2046system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for demand accesses 2047system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391854 # mshr miss rate for demand accesses 2048system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101895 # mshr miss rate for demand accesses 2049system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for overall accesses 2050system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for overall accesses 2051system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for overall accesses 2052system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391854 # mshr miss rate for overall accesses 2053system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2054system.cpu1.l2cache.overall_mshr_miss_rate::total 0.128088 # mshr miss rate for overall accesses 2055system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average ReadReq mshr miss latency 2056system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average ReadReq mshr miss latency 2057system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17768.987342 # average ReadReq mshr miss latency 2058system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average HardPFReq mshr miss latency 2059system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33592.193891 # average HardPFReq mshr miss latency 2060system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17084.195320 # average UpgradeReq mshr miss latency 2061system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17084.195320 # average UpgradeReq mshr miss latency 2062system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15524.650396 # average SCUpgradeReq mshr miss latency 2063system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15524.650396 # average SCUpgradeReq mshr miss latency 2064system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 324000 # average SCUpgradeFailReq mshr miss latency 2065system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 324000 # average SCUpgradeFailReq mshr miss latency 2066system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32602.420961 # average ReadExReq mshr miss latency 2067system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32602.420961 # average ReadExReq mshr miss latency 2068system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average ReadCleanReq mshr miss latency 2069system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32857.947044 # average ReadCleanReq mshr miss latency 2070system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17951.096211 # average ReadSharedReq mshr miss latency 2071system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17951.096211 # average ReadSharedReq mshr miss latency 2072system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency 2073system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency 2074system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency 2075system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency 2076system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24690.019115 # average overall mshr miss latency 2077system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency 2078system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency 2079system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency 2080system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency 2081system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average overall mshr miss latency 2082system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26510.479321 # average overall mshr miss latency 2083system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average ReadReq mshr uncacheable latency 2084system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165091.488990 # average ReadReq mshr uncacheable latency 2085system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163463.410454 # average ReadReq mshr uncacheable latency 2086system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163722.200040 # average WriteReq mshr uncacheable latency 2087system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163722.200040 # average WriteReq mshr uncacheable latency 2088system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average overall mshr uncacheable latency 2089system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164452.334358 # average overall mshr uncacheable latency 2090system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163582.949096 # average overall mshr uncacheable latency 2091system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2092system.cpu1.toL2Bus.trans_dist::ReadReq 80046 # Transaction distribution 2093system.cpu1.toL2Bus.trans_dist::ReadResp 1329975 # Transaction distribution 2094system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution 2095system.cpu1.toL2Bus.trans_dist::WriteResp 5009 # Transaction distribution 2096system.cpu1.toL2Bus.trans_dist::Writeback 511761 # Transaction distribution 2097system.cpu1.toL2Bus.trans_dist::CleanEvict 1258534 # Transaction distribution 2098system.cpu1.toL2Bus.trans_dist::HardPFReq 43565 # Transaction distribution 2099system.cpu1.toL2Bus.trans_dist::UpgradeReq 76909 # Transaction distribution 2100system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43045 # Transaction distribution 2101system.cpu1.toL2Bus.trans_dist::UpgradeResp 89356 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::ReadExReq 97332 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::ReadExResp 80052 # Transaction distribution 2106system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1036579 # Transaction distribution 2107system.cpu1.toL2Bus.trans_dist::ReadSharedReq 560078 # Transaction distribution 2108system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2109system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3090316 # Packet count per connected master and slave (bytes) 2110system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1000986 # Packet count per connected master and slave (bytes) 2111system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7189 # Packet count per connected master and slave (bytes) 2112system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70268 # Packet count per connected master and slave (bytes) 2113system.cpu1.toL2Bus.pkt_count::total 4168759 # Packet count per connected master and slave (bytes) 2114system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66348288 # Cumulative packet size per connected master and slave (bytes) 2115system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29828599 # Cumulative packet size per connected master and slave (bytes) 2116system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11528 # Cumulative packet size per connected master and slave (bytes) 2117system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 132864 # Cumulative packet size per connected master and slave (bytes) 2118system.cpu1.toL2Bus.pkt_size::total 96321279 # Cumulative packet size per connected master and slave (bytes) 2119system.cpu1.toL2Bus.snoops 1191896 # Total snoops (count) 2120system.cpu1.toL2Bus.snoop_fanout::samples 3797471 # Request fanout histogram 2121system.cpu1.toL2Bus.snoop_fanout::mean 1.302048 # Request fanout histogram 2122system.cpu1.toL2Bus.snoop_fanout::stdev 0.459146 # Request fanout histogram 2123system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2124system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2125system.cpu1.toL2Bus.snoop_fanout::1 2650451 69.80% 69.80% # Request fanout histogram 2126system.cpu1.toL2Bus.snoop_fanout::2 1147020 30.20% 100.00% # Request fanout histogram 2127system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2128system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2129system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2130system.cpu1.toL2Bus.snoop_fanout::total 3797471 # Request fanout histogram 2131system.cpu1.toL2Bus.reqLayer0.occupancy 1487742991 # Layer occupancy (ticks) 2132system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2133system.cpu1.toL2Bus.snoopLayer0.occupancy 87115499 # Layer occupancy (ticks) 2134system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2135system.cpu1.toL2Bus.respLayer0.occupancy 1555110854 # Layer occupancy (ticks) 2136system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2137system.cpu1.toL2Bus.respLayer1.occupancy 456039835 # Layer occupancy (ticks) 2138system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2139system.cpu1.toL2Bus.respLayer2.occupancy 4307000 # Layer occupancy (ticks) 2140system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2141system.cpu1.toL2Bus.respLayer3.occupancy 37064974 # Layer occupancy (ticks) 2142system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2143system.iobus.trans_dist::ReadReq 30994 # Transaction distribution 2144system.iobus.trans_dist::ReadResp 30994 # Transaction distribution 2145system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2146system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2147system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2148system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2149system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2150system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2151system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2152system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) 2153system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2154system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2157system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2162system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2163system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2164system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2165system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2166system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2168system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) 2169system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72920 # Packet count per connected master and slave (bytes) 2170system.iobus.pkt_count_system.realview.ide.dma::total 72920 # Packet count per connected master and slave (bytes) 2171system.iobus.pkt_count::total 180832 # Packet count per connected master and slave (bytes) 2172system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2173system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2174system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2175system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2176system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2177system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2179system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2187system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2188system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2189system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2190system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2191system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2192system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2193system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2194system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321120 # Cumulative packet size per connected master and slave (bytes) 2195system.iobus.pkt_size_system.realview.ide.dma::total 2321120 # Cumulative packet size per connected master and slave (bytes) 2196system.iobus.pkt_size::total 2483914 # Cumulative packet size per connected master and slave (bytes) 2197system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) 2198system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2199system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2200system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2201system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2202system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2203system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2204system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2205system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2206system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2207system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) 2208system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2209system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2210system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2211system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2212system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2213system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2214system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2215system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2216system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2217system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2218system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2219system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2220system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2221system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2222system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2223system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2224system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2225system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2226system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2227system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2228system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2229system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2230system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2231system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2232system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2233system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2234system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2235system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2236system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2237system.iobus.reqLayer27.occupancy 187482956 # Layer occupancy (ticks) 2238system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2239system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2240system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2241system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) 2242system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2243system.iobus.respLayer3.occupancy 36744000 # Layer occupancy (ticks) 2244system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2245system.iocache.tags.replacements 36426 # number of replacements 2246system.iocache.tags.tagsinuse 1.010803 # Cycle average of tags in use 2247system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2248system.iocache.tags.sampled_refs 36442 # Sample count of references to valid blocks. 2249system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2250system.iocache.tags.warmup_cycle 270452648000 # Cycle when the warmup percentage was hit. 2251system.iocache.tags.occ_blocks::realview.ide 1.010803 # Average occupied blocks per requestor 2252system.iocache.tags.occ_percent::realview.ide 0.063175 # Average percentage of cache occupancy 2253system.iocache.tags.occ_percent::total 0.063175 # Average percentage of cache occupancy 2254system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2255system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2256system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2257system.iocache.tags.tag_accesses 328140 # Number of tag accesses 2258system.iocache.tags.data_accesses 328140 # Number of data accesses 2259system.iocache.ReadReq_misses::realview.ide 236 # number of ReadReq misses 2260system.iocache.ReadReq_misses::total 236 # number of ReadReq misses 2261system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2262system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2263system.iocache.demand_misses::realview.ide 236 # number of demand (read+write) misses 2264system.iocache.demand_misses::total 236 # number of demand (read+write) misses 2265system.iocache.overall_misses::realview.ide 236 # number of overall misses 2266system.iocache.overall_misses::total 236 # number of overall misses 2267system.iocache.ReadReq_miss_latency::realview.ide 30330877 # number of ReadReq miss cycles 2268system.iocache.ReadReq_miss_latency::total 30330877 # number of ReadReq miss cycles 2269system.iocache.WriteLineReq_miss_latency::realview.ide 4273955079 # number of WriteLineReq miss cycles 2270system.iocache.WriteLineReq_miss_latency::total 4273955079 # number of WriteLineReq miss cycles 2271system.iocache.demand_miss_latency::realview.ide 30330877 # number of demand (read+write) miss cycles 2272system.iocache.demand_miss_latency::total 30330877 # number of demand (read+write) miss cycles 2273system.iocache.overall_miss_latency::realview.ide 30330877 # number of overall miss cycles 2274system.iocache.overall_miss_latency::total 30330877 # number of overall miss cycles 2275system.iocache.ReadReq_accesses::realview.ide 236 # number of ReadReq accesses(hits+misses) 2276system.iocache.ReadReq_accesses::total 236 # number of ReadReq accesses(hits+misses) 2277system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2278system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2279system.iocache.demand_accesses::realview.ide 236 # number of demand (read+write) accesses 2280system.iocache.demand_accesses::total 236 # number of demand (read+write) accesses 2281system.iocache.overall_accesses::realview.ide 236 # number of overall (read+write) accesses 2282system.iocache.overall_accesses::total 236 # number of overall (read+write) accesses 2283system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2284system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2285system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2286system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2287system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2288system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2289system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2290system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2291system.iocache.ReadReq_avg_miss_latency::realview.ide 128520.665254 # average ReadReq miss latency 2292system.iocache.ReadReq_avg_miss_latency::total 128520.665254 # average ReadReq miss latency 2293system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117986.834116 # average WriteLineReq miss latency 2294system.iocache.WriteLineReq_avg_miss_latency::total 117986.834116 # average WriteLineReq miss latency 2295system.iocache.demand_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency 2296system.iocache.demand_avg_miss_latency::total 128520.665254 # average overall miss latency 2297system.iocache.overall_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency 2298system.iocache.overall_avg_miss_latency::total 128520.665254 # average overall miss latency 2299system.iocache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked 2300system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2301system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 2302system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2303system.iocache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked 2304system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2305system.iocache.fast_writes 0 # number of fast writes performed 2306system.iocache.cache_copies 0 # number of cache copies performed 2307system.iocache.writebacks::writebacks 36190 # number of writebacks 2308system.iocache.writebacks::total 36190 # number of writebacks 2309system.iocache.ReadReq_mshr_misses::realview.ide 236 # number of ReadReq MSHR misses 2310system.iocache.ReadReq_mshr_misses::total 236 # number of ReadReq MSHR misses 2311system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2312system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2313system.iocache.demand_mshr_misses::realview.ide 236 # number of demand (read+write) MSHR misses 2314system.iocache.demand_mshr_misses::total 236 # number of demand (read+write) MSHR misses 2315system.iocache.overall_mshr_misses::realview.ide 236 # number of overall MSHR misses 2316system.iocache.overall_mshr_misses::total 236 # number of overall MSHR misses 2317system.iocache.ReadReq_mshr_miss_latency::realview.ide 18530877 # number of ReadReq MSHR miss cycles 2318system.iocache.ReadReq_mshr_miss_latency::total 18530877 # number of ReadReq MSHR miss cycles 2319system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462755079 # number of WriteLineReq MSHR miss cycles 2320system.iocache.WriteLineReq_mshr_miss_latency::total 2462755079 # number of WriteLineReq MSHR miss cycles 2321system.iocache.demand_mshr_miss_latency::realview.ide 18530877 # number of demand (read+write) MSHR miss cycles 2322system.iocache.demand_mshr_miss_latency::total 18530877 # number of demand (read+write) MSHR miss cycles 2323system.iocache.overall_mshr_miss_latency::realview.ide 18530877 # number of overall MSHR miss cycles 2324system.iocache.overall_mshr_miss_latency::total 18530877 # number of overall MSHR miss cycles 2325system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2326system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2327system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2328system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2329system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2330system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2331system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2332system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2333system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78520.665254 # average ReadReq mshr miss latency 2334system.iocache.ReadReq_avg_mshr_miss_latency::total 78520.665254 # average ReadReq mshr miss latency 2335system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67986.834116 # average WriteLineReq mshr miss latency 2336system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67986.834116 # average WriteLineReq mshr miss latency 2337system.iocache.demand_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency 2338system.iocache.demand_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency 2339system.iocache.overall_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency 2340system.iocache.overall_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency 2341system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2342system.l2c.tags.replacements 135428 # number of replacements 2343system.l2c.tags.tagsinuse 64138.208301 # Cycle average of tags in use 2344system.l2c.tags.total_refs 442739 # Total number of references to valid blocks. 2345system.l2c.tags.sampled_refs 199807 # Sample count of references to valid blocks. 2346system.l2c.tags.avg_refs 2.215833 # Average number of references to valid blocks. 2347system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2348system.l2c.tags.occ_blocks::writebacks 12941.285088 # Average occupied blocks per requestor 2349system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.276334 # Average occupied blocks per requestor 2350system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031468 # Average occupied blocks per requestor 2351system.l2c.tags.occ_blocks::cpu0.inst 7274.373268 # Average occupied blocks per requestor 2352system.l2c.tags.occ_blocks::cpu0.data 2166.846690 # Average occupied blocks per requestor 2353system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 31945.045858 # Average occupied blocks per requestor 2354system.l2c.tags.occ_blocks::cpu1.dtb.walker 24.318023 # Average occupied blocks per requestor 2355system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851962 # Average occupied blocks per requestor 2356system.l2c.tags.occ_blocks::cpu1.inst 4022.114049 # Average occupied blocks per requestor 2357system.l2c.tags.occ_blocks::cpu1.data 1496.265741 # Average occupied blocks per requestor 2358system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4197.799819 # Average occupied blocks per requestor 2359system.l2c.tags.occ_percent::writebacks 0.197468 # Average percentage of cache occupancy 2360system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001057 # Average percentage of cache occupancy 2361system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2362system.l2c.tags.occ_percent::cpu0.inst 0.110998 # Average percentage of cache occupancy 2363system.l2c.tags.occ_percent::cpu0.data 0.033063 # Average percentage of cache occupancy 2364system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.487443 # Average percentage of cache occupancy 2365system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000371 # Average percentage of cache occupancy 2366system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy 2367system.l2c.tags.occ_percent::cpu1.inst 0.061373 # Average percentage of cache occupancy 2368system.l2c.tags.occ_percent::cpu1.data 0.022831 # Average percentage of cache occupancy 2369system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064053 # Average percentage of cache occupancy 2370system.l2c.tags.occ_percent::total 0.978671 # Average percentage of cache occupancy 2371system.l2c.tags.occ_task_id_blocks::1022 29250 # Occupied blocks per task id 2372system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id 2373system.l2c.tags.occ_task_id_blocks::1024 35037 # Occupied blocks per task id 2374system.l2c.tags.age_task_id_blocks_1022::2 144 # Occupied blocks per task id 2375system.l2c.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id 2376system.l2c.tags.age_task_id_blocks_1022::4 23842 # Occupied blocks per task id 2377system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2378system.l2c.tags.age_task_id_blocks_1023::4 91 # Occupied blocks per task id 2379system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2380system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 2381system.l2c.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id 2382system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id 2383system.l2c.tags.age_task_id_blocks_1024::4 31679 # Occupied blocks per task id 2384system.l2c.tags.occ_task_id_percent::1022 0.446320 # Percentage of cache occupancy per task id 2385system.l2c.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id 2386system.l2c.tags.occ_task_id_percent::1024 0.534622 # Percentage of cache occupancy per task id 2387system.l2c.tags.tag_accesses 5824693 # Number of tag accesses 2388system.l2c.tags.data_accesses 5824693 # Number of data accesses 2389system.l2c.Writeback_hits::writebacks 232832 # number of Writeback hits 2390system.l2c.Writeback_hits::total 232832 # number of Writeback hits 2391system.l2c.UpgradeReq_hits::cpu0.data 3079 # number of UpgradeReq hits 2392system.l2c.UpgradeReq_hits::cpu1.data 930 # number of UpgradeReq hits 2393system.l2c.UpgradeReq_hits::total 4009 # number of UpgradeReq hits 2394system.l2c.SCUpgradeReq_hits::cpu0.data 233 # number of SCUpgradeReq hits 2395system.l2c.SCUpgradeReq_hits::cpu1.data 92 # number of SCUpgradeReq hits 2396system.l2c.SCUpgradeReq_hits::total 325 # number of SCUpgradeReq hits 2397system.l2c.ReadExReq_hits::cpu0.data 4022 # number of ReadExReq hits 2398system.l2c.ReadExReq_hits::cpu1.data 2114 # number of ReadExReq hits 2399system.l2c.ReadExReq_hits::total 6136 # number of ReadExReq hits 2400system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 393 # number of ReadSharedReq hits 2401system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits 2402system.l2c.ReadSharedReq_hits::cpu0.inst 44006 # number of ReadSharedReq hits 2403system.l2c.ReadSharedReq_hits::cpu0.data 47229 # number of ReadSharedReq hits 2404system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46346 # number of ReadSharedReq hits 2405system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 166 # number of ReadSharedReq hits 2406system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits 2407system.l2c.ReadSharedReq_hits::cpu1.inst 21446 # number of ReadSharedReq hits 2408system.l2c.ReadSharedReq_hits::cpu1.data 11079 # number of ReadSharedReq hits 2409system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8110 # number of ReadSharedReq hits 2410system.l2c.ReadSharedReq_hits::total 178893 # number of ReadSharedReq hits 2411system.l2c.demand_hits::cpu0.dtb.walker 393 # number of demand (read+write) hits 2412system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits 2413system.l2c.demand_hits::cpu0.inst 44006 # number of demand (read+write) hits 2414system.l2c.demand_hits::cpu0.data 51251 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.l2cache.prefetcher 46346 # number of demand (read+write) hits 2416system.l2c.demand_hits::cpu1.dtb.walker 166 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu1.inst 21446 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu1.data 13193 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu1.l2cache.prefetcher 8110 # number of demand (read+write) hits 2421system.l2c.demand_hits::total 185029 # number of demand (read+write) hits 2422system.l2c.overall_hits::cpu0.dtb.walker 393 # number of overall hits 2423system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits 2424system.l2c.overall_hits::cpu0.inst 44006 # number of overall hits 2425system.l2c.overall_hits::cpu0.data 51251 # number of overall hits 2426system.l2c.overall_hits::cpu0.l2cache.prefetcher 46346 # number of overall hits 2427system.l2c.overall_hits::cpu1.dtb.walker 166 # number of overall hits 2428system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits 2429system.l2c.overall_hits::cpu1.inst 21446 # number of overall hits 2430system.l2c.overall_hits::cpu1.data 13193 # number of overall hits 2431system.l2c.overall_hits::cpu1.l2cache.prefetcher 8110 # number of overall hits 2432system.l2c.overall_hits::total 185029 # number of overall hits 2433system.l2c.UpgradeReq_misses::cpu0.data 8747 # number of UpgradeReq misses 2434system.l2c.UpgradeReq_misses::cpu1.data 4112 # number of UpgradeReq misses 2435system.l2c.UpgradeReq_misses::total 12859 # number of UpgradeReq misses 2436system.l2c.SCUpgradeReq_misses::cpu0.data 835 # number of SCUpgradeReq misses 2437system.l2c.SCUpgradeReq_misses::cpu1.data 1227 # number of SCUpgradeReq misses 2438system.l2c.SCUpgradeReq_misses::total 2062 # number of SCUpgradeReq misses 2439system.l2c.ReadExReq_misses::cpu0.data 10918 # number of ReadExReq misses 2440system.l2c.ReadExReq_misses::cpu1.data 8428 # number of ReadExReq misses 2441system.l2c.ReadExReq_misses::total 19346 # number of ReadExReq misses 2442system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 114 # number of ReadSharedReq misses 2443system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2444system.l2c.ReadSharedReq_misses::cpu0.inst 19630 # number of ReadSharedReq misses 2445system.l2c.ReadSharedReq_misses::cpu0.data 8718 # number of ReadSharedReq misses 2446system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 129027 # number of ReadSharedReq misses 2447system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 38 # number of ReadSharedReq misses 2448system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 2449system.l2c.ReadSharedReq_misses::cpu1.inst 5812 # number of ReadSharedReq misses 2450system.l2c.ReadSharedReq_misses::cpu1.data 2889 # number of ReadSharedReq misses 2451system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8839 # number of ReadSharedReq misses 2452system.l2c.ReadSharedReq_misses::total 175069 # number of ReadSharedReq misses 2453system.l2c.demand_misses::cpu0.dtb.walker 114 # number of demand (read+write) misses 2454system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2455system.l2c.demand_misses::cpu0.inst 19630 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu0.data 19636 # number of demand (read+write) misses 2457system.l2c.demand_misses::cpu0.l2cache.prefetcher 129027 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu1.dtb.walker 38 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu1.inst 5812 # number of demand (read+write) misses 2461system.l2c.demand_misses::cpu1.data 11317 # number of demand (read+write) misses 2462system.l2c.demand_misses::cpu1.l2cache.prefetcher 8839 # number of demand (read+write) misses 2463system.l2c.demand_misses::total 194415 # number of demand (read+write) misses 2464system.l2c.overall_misses::cpu0.dtb.walker 114 # number of overall misses 2465system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2466system.l2c.overall_misses::cpu0.inst 19630 # number of overall misses 2467system.l2c.overall_misses::cpu0.data 19636 # number of overall misses 2468system.l2c.overall_misses::cpu0.l2cache.prefetcher 129027 # number of overall misses 2469system.l2c.overall_misses::cpu1.dtb.walker 38 # number of overall misses 2470system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 2471system.l2c.overall_misses::cpu1.inst 5812 # number of overall misses 2472system.l2c.overall_misses::cpu1.data 11317 # number of overall misses 2473system.l2c.overall_misses::cpu1.l2cache.prefetcher 8839 # number of overall misses 2474system.l2c.overall_misses::total 194415 # number of overall misses 2475system.l2c.UpgradeReq_miss_latency::cpu0.data 8346500 # number of UpgradeReq miss cycles 2476system.l2c.UpgradeReq_miss_latency::cpu1.data 5785000 # number of UpgradeReq miss cycles 2477system.l2c.UpgradeReq_miss_latency::total 14131500 # number of UpgradeReq miss cycles 2478system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1392500 # number of SCUpgradeReq miss cycles 2479system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1414500 # number of SCUpgradeReq miss cycles 2480system.l2c.SCUpgradeReq_miss_latency::total 2807000 # number of SCUpgradeReq miss cycles 2481system.l2c.ReadExReq_miss_latency::cpu0.data 1077000000 # number of ReadExReq miss cycles 2482system.l2c.ReadExReq_miss_latency::cpu1.data 690485000 # number of ReadExReq miss cycles 2483system.l2c.ReadExReq_miss_latency::total 1767485000 # number of ReadExReq miss cycles 2484system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10253000 # number of ReadSharedReq miss cycles 2485system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 303000 # number of ReadSharedReq miss cycles 2486system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1569061500 # number of ReadSharedReq miss cycles 2487system.l2c.ReadSharedReq_miss_latency::cpu0.data 759147500 # number of ReadSharedReq miss cycles 2488system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13107894109 # number of ReadSharedReq miss cycles 2489system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3343000 # number of ReadSharedReq miss cycles 2490system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 83000 # number of ReadSharedReq miss cycles 2491system.l2c.ReadSharedReq_miss_latency::cpu1.inst 479575000 # number of ReadSharedReq miss cycles 2492system.l2c.ReadSharedReq_miss_latency::cpu1.data 252543500 # number of ReadSharedReq miss cycles 2493system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1024779080 # number of ReadSharedReq miss cycles 2494system.l2c.ReadSharedReq_miss_latency::total 17206982689 # number of ReadSharedReq miss cycles 2495system.l2c.demand_miss_latency::cpu0.dtb.walker 10253000 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu0.itb.walker 303000 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu0.inst 1569061500 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu0.data 1836147500 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13107894109 # number of demand (read+write) miss cycles 2500system.l2c.demand_miss_latency::cpu1.dtb.walker 3343000 # number of demand (read+write) miss cycles 2501system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles 2502system.l2c.demand_miss_latency::cpu1.inst 479575000 # number of demand (read+write) miss cycles 2503system.l2c.demand_miss_latency::cpu1.data 943028500 # number of demand (read+write) miss cycles 2504system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1024779080 # number of demand (read+write) miss cycles 2505system.l2c.demand_miss_latency::total 18974467689 # number of demand (read+write) miss cycles 2506system.l2c.overall_miss_latency::cpu0.dtb.walker 10253000 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu0.itb.walker 303000 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu0.inst 1569061500 # number of overall miss cycles 2509system.l2c.overall_miss_latency::cpu0.data 1836147500 # number of overall miss cycles 2510system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13107894109 # number of overall miss cycles 2511system.l2c.overall_miss_latency::cpu1.dtb.walker 3343000 # number of overall miss cycles 2512system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles 2513system.l2c.overall_miss_latency::cpu1.inst 479575000 # number of overall miss cycles 2514system.l2c.overall_miss_latency::cpu1.data 943028500 # number of overall miss cycles 2515system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1024779080 # number of overall miss cycles 2516system.l2c.overall_miss_latency::total 18974467689 # number of overall miss cycles 2517system.l2c.Writeback_accesses::writebacks 232832 # number of Writeback accesses(hits+misses) 2518system.l2c.Writeback_accesses::total 232832 # number of Writeback accesses(hits+misses) 2519system.l2c.UpgradeReq_accesses::cpu0.data 11826 # number of UpgradeReq accesses(hits+misses) 2520system.l2c.UpgradeReq_accesses::cpu1.data 5042 # number of UpgradeReq accesses(hits+misses) 2521system.l2c.UpgradeReq_accesses::total 16868 # number of UpgradeReq accesses(hits+misses) 2522system.l2c.SCUpgradeReq_accesses::cpu0.data 1068 # number of SCUpgradeReq accesses(hits+misses) 2523system.l2c.SCUpgradeReq_accesses::cpu1.data 1319 # number of SCUpgradeReq accesses(hits+misses) 2524system.l2c.SCUpgradeReq_accesses::total 2387 # number of SCUpgradeReq accesses(hits+misses) 2525system.l2c.ReadExReq_accesses::cpu0.data 14940 # number of ReadExReq accesses(hits+misses) 2526system.l2c.ReadExReq_accesses::cpu1.data 10542 # number of ReadExReq accesses(hits+misses) 2527system.l2c.ReadExReq_accesses::total 25482 # number of ReadExReq accesses(hits+misses) 2528system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 507 # number of ReadSharedReq accesses(hits+misses) 2529system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 82 # number of ReadSharedReq accesses(hits+misses) 2530system.l2c.ReadSharedReq_accesses::cpu0.inst 63636 # number of ReadSharedReq accesses(hits+misses) 2531system.l2c.ReadSharedReq_accesses::cpu0.data 55947 # number of ReadSharedReq accesses(hits+misses) 2532system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 175373 # number of ReadSharedReq accesses(hits+misses) 2533system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 204 # number of ReadSharedReq accesses(hits+misses) 2534system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses) 2535system.l2c.ReadSharedReq_accesses::cpu1.inst 27258 # number of ReadSharedReq accesses(hits+misses) 2536system.l2c.ReadSharedReq_accesses::cpu1.data 13968 # number of ReadSharedReq accesses(hits+misses) 2537system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 16949 # number of ReadSharedReq accesses(hits+misses) 2538system.l2c.ReadSharedReq_accesses::total 353962 # number of ReadSharedReq accesses(hits+misses) 2539system.l2c.demand_accesses::cpu0.dtb.walker 507 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu0.itb.walker 82 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu0.inst 63636 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::cpu0.data 70887 # number of demand (read+write) accesses 2543system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175373 # number of demand (read+write) accesses 2544system.l2c.demand_accesses::cpu1.dtb.walker 204 # number of demand (read+write) accesses 2545system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 2546system.l2c.demand_accesses::cpu1.inst 27258 # number of demand (read+write) accesses 2547system.l2c.demand_accesses::cpu1.data 24510 # number of demand (read+write) accesses 2548system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16949 # number of demand (read+write) accesses 2549system.l2c.demand_accesses::total 379444 # number of demand (read+write) accesses 2550system.l2c.overall_accesses::cpu0.dtb.walker 507 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::cpu0.itb.walker 82 # number of overall (read+write) accesses 2552system.l2c.overall_accesses::cpu0.inst 63636 # number of overall (read+write) accesses 2553system.l2c.overall_accesses::cpu0.data 70887 # number of overall (read+write) accesses 2554system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175373 # number of overall (read+write) accesses 2555system.l2c.overall_accesses::cpu1.dtb.walker 204 # number of overall (read+write) accesses 2556system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 2557system.l2c.overall_accesses::cpu1.inst 27258 # number of overall (read+write) accesses 2558system.l2c.overall_accesses::cpu1.data 24510 # number of overall (read+write) accesses 2559system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16949 # number of overall (read+write) accesses 2560system.l2c.overall_accesses::total 379444 # number of overall (read+write) accesses 2561system.l2c.UpgradeReq_miss_rate::cpu0.data 0.739641 # miss rate for UpgradeReq accesses 2562system.l2c.UpgradeReq_miss_rate::cpu1.data 0.815549 # miss rate for UpgradeReq accesses 2563system.l2c.UpgradeReq_miss_rate::total 0.762331 # miss rate for UpgradeReq accesses 2564system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.781835 # miss rate for SCUpgradeReq accesses 2565system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.930250 # miss rate for SCUpgradeReq accesses 2566system.l2c.SCUpgradeReq_miss_rate::total 0.863846 # miss rate for SCUpgradeReq accesses 2567system.l2c.ReadExReq_miss_rate::cpu0.data 0.730790 # miss rate for ReadExReq accesses 2568system.l2c.ReadExReq_miss_rate::cpu1.data 0.799469 # miss rate for ReadExReq accesses 2569system.l2c.ReadExReq_miss_rate::total 0.759203 # miss rate for ReadExReq accesses 2570system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.224852 # miss rate for ReadSharedReq accesses 2571system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.012195 # miss rate for ReadSharedReq accesses 2572system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.308473 # miss rate for ReadSharedReq accesses 2573system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.155826 # miss rate for ReadSharedReq accesses 2574system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735729 # miss rate for ReadSharedReq accesses 2575system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.186275 # miss rate for ReadSharedReq accesses 2576system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.026316 # miss rate for ReadSharedReq accesses 2577system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.213222 # miss rate for ReadSharedReq accesses 2578system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.206830 # miss rate for ReadSharedReq accesses 2579system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521506 # miss rate for ReadSharedReq accesses 2580system.l2c.ReadSharedReq_miss_rate::total 0.494598 # miss rate for ReadSharedReq accesses 2581system.l2c.demand_miss_rate::cpu0.dtb.walker 0.224852 # miss rate for demand accesses 2582system.l2c.demand_miss_rate::cpu0.itb.walker 0.012195 # miss rate for demand accesses 2583system.l2c.demand_miss_rate::cpu0.inst 0.308473 # miss rate for demand accesses 2584system.l2c.demand_miss_rate::cpu0.data 0.277004 # miss rate for demand accesses 2585system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735729 # miss rate for demand accesses 2586system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186275 # miss rate for demand accesses 2587system.l2c.demand_miss_rate::cpu1.itb.walker 0.026316 # miss rate for demand accesses 2588system.l2c.demand_miss_rate::cpu1.inst 0.213222 # miss rate for demand accesses 2589system.l2c.demand_miss_rate::cpu1.data 0.461730 # miss rate for demand accesses 2590system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521506 # miss rate for demand accesses 2591system.l2c.demand_miss_rate::total 0.512368 # miss rate for demand accesses 2592system.l2c.overall_miss_rate::cpu0.dtb.walker 0.224852 # miss rate for overall accesses 2593system.l2c.overall_miss_rate::cpu0.itb.walker 0.012195 # miss rate for overall accesses 2594system.l2c.overall_miss_rate::cpu0.inst 0.308473 # miss rate for overall accesses 2595system.l2c.overall_miss_rate::cpu0.data 0.277004 # miss rate for overall accesses 2596system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735729 # miss rate for overall accesses 2597system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186275 # miss rate for overall accesses 2598system.l2c.overall_miss_rate::cpu1.itb.walker 0.026316 # miss rate for overall accesses 2599system.l2c.overall_miss_rate::cpu1.inst 0.213222 # miss rate for overall accesses 2600system.l2c.overall_miss_rate::cpu1.data 0.461730 # miss rate for overall accesses 2601system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521506 # miss rate for overall accesses 2602system.l2c.overall_miss_rate::total 0.512368 # miss rate for overall accesses 2603system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 954.212873 # average UpgradeReq miss latency 2604system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1406.857977 # average UpgradeReq miss latency 2605system.l2c.UpgradeReq_avg_miss_latency::total 1098.957928 # average UpgradeReq miss latency 2606system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1667.664671 # average SCUpgradeReq miss latency 2607system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1152.811736 # average SCUpgradeReq miss latency 2608system.l2c.SCUpgradeReq_avg_miss_latency::total 1361.299709 # average SCUpgradeReq miss latency 2609system.l2c.ReadExReq_avg_miss_latency::cpu0.data 98644.440374 # average ReadExReq miss latency 2610system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81927.503560 # average ReadExReq miss latency 2611system.l2c.ReadExReq_avg_miss_latency::total 91361.780213 # average ReadExReq miss latency 2612system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89938.596491 # average ReadSharedReq miss latency 2613system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 303000 # average ReadSharedReq miss latency 2614system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79931.813551 # average ReadSharedReq miss latency 2615system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87078.171599 # average ReadSharedReq miss latency 2616system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150 # average ReadSharedReq miss latency 2617system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87973.684211 # average ReadSharedReq miss latency 2618system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadSharedReq miss latency 2619system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82514.624914 # average ReadSharedReq miss latency 2620system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 87415.541710 # average ReadSharedReq miss latency 2621system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492 # average ReadSharedReq miss latency 2622system.l2c.ReadSharedReq_avg_miss_latency::total 98286.862260 # average ReadSharedReq miss latency 2623system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89938.596491 # average overall miss latency 2624system.l2c.demand_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency 2625system.l2c.demand_avg_miss_latency::cpu0.inst 79931.813551 # average overall miss latency 2626system.l2c.demand_avg_miss_latency::cpu0.data 93509.243227 # average overall miss latency 2627system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150 # average overall miss latency 2628system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87973.684211 # average overall miss latency 2629system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency 2630system.l2c.demand_avg_miss_latency::cpu1.inst 82514.624914 # average overall miss latency 2631system.l2c.demand_avg_miss_latency::cpu1.data 83328.488115 # average overall miss latency 2632system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492 # average overall miss latency 2633system.l2c.demand_avg_miss_latency::total 97597.755775 # average overall miss latency 2634system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89938.596491 # average overall miss latency 2635system.l2c.overall_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency 2636system.l2c.overall_avg_miss_latency::cpu0.inst 79931.813551 # average overall miss latency 2637system.l2c.overall_avg_miss_latency::cpu0.data 93509.243227 # average overall miss latency 2638system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150 # average overall miss latency 2639system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87973.684211 # average overall miss latency 2640system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency 2641system.l2c.overall_avg_miss_latency::cpu1.inst 82514.624914 # average overall miss latency 2642system.l2c.overall_avg_miss_latency::cpu1.data 83328.488115 # average overall miss latency 2643system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492 # average overall miss latency 2644system.l2c.overall_avg_miss_latency::total 97597.755775 # average overall miss latency 2645system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2646system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2647system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2648system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2649system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2650system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2651system.l2c.fast_writes 0 # number of fast writes performed 2652system.l2c.cache_copies 0 # number of cache copies performed 2653system.l2c.writebacks::writebacks 103399 # number of writebacks 2654system.l2c.writebacks::total 103399 # number of writebacks 2655system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits 2656system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits 2657system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 2658system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2659system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2660system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 2661system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2662system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2663system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits 2664system.l2c.CleanEvict_mshr_misses::writebacks 3802 # number of CleanEvict MSHR misses 2665system.l2c.CleanEvict_mshr_misses::total 3802 # number of CleanEvict MSHR misses 2666system.l2c.UpgradeReq_mshr_misses::cpu0.data 8747 # number of UpgradeReq MSHR misses 2667system.l2c.UpgradeReq_mshr_misses::cpu1.data 4112 # number of UpgradeReq MSHR misses 2668system.l2c.UpgradeReq_mshr_misses::total 12859 # number of UpgradeReq MSHR misses 2669system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 835 # number of SCUpgradeReq MSHR misses 2670system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1227 # number of SCUpgradeReq MSHR misses 2671system.l2c.SCUpgradeReq_mshr_misses::total 2062 # number of SCUpgradeReq MSHR misses 2672system.l2c.ReadExReq_mshr_misses::cpu0.data 10918 # number of ReadExReq MSHR misses 2673system.l2c.ReadExReq_mshr_misses::cpu1.data 8428 # number of ReadExReq MSHR misses 2674system.l2c.ReadExReq_mshr_misses::total 19346 # number of ReadExReq MSHR misses 2675system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 114 # number of ReadSharedReq MSHR misses 2676system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2677system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19629 # number of ReadSharedReq MSHR misses 2678system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8718 # number of ReadSharedReq MSHR misses 2679system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 129027 # number of ReadSharedReq MSHR misses 2680system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 38 # number of ReadSharedReq MSHR misses 2681system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses 2682system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5808 # number of ReadSharedReq MSHR misses 2683system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2889 # number of ReadSharedReq MSHR misses 2684system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8839 # number of ReadSharedReq MSHR misses 2685system.l2c.ReadSharedReq_mshr_misses::total 175064 # number of ReadSharedReq MSHR misses 2686system.l2c.demand_mshr_misses::cpu0.dtb.walker 114 # number of demand (read+write) MSHR misses 2687system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2688system.l2c.demand_mshr_misses::cpu0.inst 19629 # number of demand (read+write) MSHR misses 2689system.l2c.demand_mshr_misses::cpu0.data 19636 # number of demand (read+write) MSHR misses 2690system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129027 # number of demand (read+write) MSHR misses 2691system.l2c.demand_mshr_misses::cpu1.dtb.walker 38 # number of demand (read+write) MSHR misses 2692system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 2693system.l2c.demand_mshr_misses::cpu1.inst 5808 # number of demand (read+write) MSHR misses 2694system.l2c.demand_mshr_misses::cpu1.data 11317 # number of demand (read+write) MSHR misses 2695system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8839 # number of demand (read+write) MSHR misses 2696system.l2c.demand_mshr_misses::total 194410 # number of demand (read+write) MSHR misses 2697system.l2c.overall_mshr_misses::cpu0.dtb.walker 114 # number of overall MSHR misses 2698system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2699system.l2c.overall_mshr_misses::cpu0.inst 19629 # number of overall MSHR misses 2700system.l2c.overall_mshr_misses::cpu0.data 19636 # number of overall MSHR misses 2701system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129027 # number of overall MSHR misses 2702system.l2c.overall_mshr_misses::cpu1.dtb.walker 38 # number of overall MSHR misses 2703system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 2704system.l2c.overall_mshr_misses::cpu1.inst 5808 # number of overall MSHR misses 2705system.l2c.overall_mshr_misses::cpu1.data 11317 # number of overall MSHR misses 2706system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8839 # number of overall MSHR misses 2707system.l2c.overall_mshr_misses::total 194410 # number of overall MSHR misses 2708system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable 2709system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29426 # number of ReadReq MSHR uncacheable 2710system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable 2711system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5718 # number of ReadReq MSHR uncacheable 2712system.l2c.ReadReq_mshr_uncacheable::total 38683 # number of ReadReq MSHR uncacheable 2713system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26162 # number of WriteReq MSHR uncacheable 2714system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5009 # number of WriteReq MSHR uncacheable 2715system.l2c.WriteReq_mshr_uncacheable::total 31171 # number of WriteReq MSHR uncacheable 2716system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses 2717system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55588 # number of overall MSHR uncacheable misses 2718system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses 2719system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10727 # number of overall MSHR uncacheable misses 2720system.l2c.overall_mshr_uncacheable_misses::total 69854 # number of overall MSHR uncacheable misses 2721system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 181705001 # number of UpgradeReq MSHR miss cycles 2722system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 86116001 # number of UpgradeReq MSHR miss cycles 2723system.l2c.UpgradeReq_mshr_miss_latency::total 267821002 # number of UpgradeReq MSHR miss cycles 2724system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17444000 # number of SCUpgradeReq MSHR miss cycles 2725system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25472500 # number of SCUpgradeReq MSHR miss cycles 2726system.l2c.SCUpgradeReq_mshr_miss_latency::total 42916500 # number of SCUpgradeReq MSHR miss cycles 2727system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 967820000 # number of ReadExReq MSHR miss cycles 2728system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606205000 # number of ReadExReq MSHR miss cycles 2729system.l2c.ReadExReq_mshr_miss_latency::total 1574025000 # number of ReadExReq MSHR miss cycles 2730system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 9113000 # number of ReadSharedReq MSHR miss cycles 2731system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 293000 # number of ReadSharedReq MSHR miss cycles 2732system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1372734500 # number of ReadSharedReq MSHR miss cycles 2733system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 671967500 # number of ReadSharedReq MSHR miss cycles 2734system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11817624109 # number of ReadSharedReq MSHR miss cycles 2735system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 2963000 # number of ReadSharedReq MSHR miss cycles 2736system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 73000 # number of ReadSharedReq MSHR miss cycles 2737system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 421007000 # number of ReadSharedReq MSHR miss cycles 2738system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 223653500 # number of ReadSharedReq MSHR miss cycles 2739system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 936389080 # number of ReadSharedReq MSHR miss cycles 2740system.l2c.ReadSharedReq_mshr_miss_latency::total 15455817689 # number of ReadSharedReq MSHR miss cycles 2741system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9113000 # number of demand (read+write) MSHR miss cycles 2742system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) MSHR miss cycles 2743system.l2c.demand_mshr_miss_latency::cpu0.inst 1372734500 # number of demand (read+write) MSHR miss cycles 2744system.l2c.demand_mshr_miss_latency::cpu0.data 1639787500 # number of demand (read+write) MSHR miss cycles 2745system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11817624109 # number of demand (read+write) MSHR miss cycles 2746system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2963000 # number of demand (read+write) MSHR miss cycles 2747system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73000 # number of demand (read+write) MSHR miss cycles 2748system.l2c.demand_mshr_miss_latency::cpu1.inst 421007000 # number of demand (read+write) MSHR miss cycles 2749system.l2c.demand_mshr_miss_latency::cpu1.data 829858500 # number of demand (read+write) MSHR miss cycles 2750system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 936389080 # number of demand (read+write) MSHR miss cycles 2751system.l2c.demand_mshr_miss_latency::total 17029842689 # number of demand (read+write) MSHR miss cycles 2752system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9113000 # number of overall MSHR miss cycles 2753system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 293000 # number of overall MSHR miss cycles 2754system.l2c.overall_mshr_miss_latency::cpu0.inst 1372734500 # number of overall MSHR miss cycles 2755system.l2c.overall_mshr_miss_latency::cpu0.data 1639787500 # number of overall MSHR miss cycles 2756system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11817624109 # number of overall MSHR miss cycles 2757system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2963000 # number of overall MSHR miss cycles 2758system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73000 # number of overall MSHR miss cycles 2759system.l2c.overall_mshr_miss_latency::cpu1.inst 421007000 # number of overall MSHR miss cycles 2760system.l2c.overall_mshr_miss_latency::cpu1.data 829858500 # number of overall MSHR miss cycles 2761system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 936389080 # number of overall MSHR miss cycles 2762system.l2c.overall_mshr_miss_latency::total 17029842689 # number of overall MSHR miss cycles 2763system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 214924500 # number of ReadReq MSHR uncacheable cycles 2764system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4931392500 # number of ReadReq MSHR uncacheable cycles 2765system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6782000 # number of ReadReq MSHR uncacheable cycles 2766system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 841666000 # number of ReadReq MSHR uncacheable cycles 2767system.l2c.ReadReq_mshr_uncacheable_latency::total 5994765000 # number of ReadReq MSHR uncacheable cycles 2768system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3673788500 # number of WriteReq MSHR uncacheable cycles 2769system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 734928500 # number of WriteReq MSHR uncacheable cycles 2770system.l2c.WriteReq_mshr_uncacheable_latency::total 4408717000 # number of WriteReq MSHR uncacheable cycles 2771system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 214924500 # number of overall MSHR uncacheable cycles 2772system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8605181000 # number of overall MSHR uncacheable cycles 2773system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6782000 # number of overall MSHR uncacheable cycles 2774system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1576594500 # number of overall MSHR uncacheable cycles 2775system.l2c.overall_mshr_uncacheable_latency::total 10403482000 # number of overall MSHR uncacheable cycles 2776system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2777system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2778system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.739641 # mshr miss rate for UpgradeReq accesses 2779system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.815549 # mshr miss rate for UpgradeReq accesses 2780system.l2c.UpgradeReq_mshr_miss_rate::total 0.762331 # mshr miss rate for UpgradeReq accesses 2781system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.781835 # mshr miss rate for SCUpgradeReq accesses 2782system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.930250 # mshr miss rate for SCUpgradeReq accesses 2783system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.863846 # mshr miss rate for SCUpgradeReq accesses 2784system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.730790 # mshr miss rate for ReadExReq accesses 2785system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.799469 # mshr miss rate for ReadExReq accesses 2786system.l2c.ReadExReq_mshr_miss_rate::total 0.759203 # mshr miss rate for ReadExReq accesses 2787system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.224852 # mshr miss rate for ReadSharedReq accesses 2788system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.012195 # mshr miss rate for ReadSharedReq accesses 2789system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.308457 # mshr miss rate for ReadSharedReq accesses 2790system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.155826 # mshr miss rate for ReadSharedReq accesses 2791system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735729 # mshr miss rate for ReadSharedReq accesses 2792system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.186275 # mshr miss rate for ReadSharedReq accesses 2793system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.026316 # mshr miss rate for ReadSharedReq accesses 2794system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.213075 # mshr miss rate for ReadSharedReq accesses 2795system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.206830 # mshr miss rate for ReadSharedReq accesses 2796system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521506 # mshr miss rate for ReadSharedReq accesses 2797system.l2c.ReadSharedReq_mshr_miss_rate::total 0.494584 # mshr miss rate for ReadSharedReq accesses 2798system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.224852 # mshr miss rate for demand accesses 2799system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012195 # mshr miss rate for demand accesses 2800system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308457 # mshr miss rate for demand accesses 2801system.l2c.demand_mshr_miss_rate::cpu0.data 0.277004 # mshr miss rate for demand accesses 2802system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735729 # mshr miss rate for demand accesses 2803system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186275 # mshr miss rate for demand accesses 2804system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.026316 # mshr miss rate for demand accesses 2805system.l2c.demand_mshr_miss_rate::cpu1.inst 0.213075 # mshr miss rate for demand accesses 2806system.l2c.demand_mshr_miss_rate::cpu1.data 0.461730 # mshr miss rate for demand accesses 2807system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521506 # mshr miss rate for demand accesses 2808system.l2c.demand_mshr_miss_rate::total 0.512355 # mshr miss rate for demand accesses 2809system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.224852 # mshr miss rate for overall accesses 2810system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012195 # mshr miss rate for overall accesses 2811system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308457 # mshr miss rate for overall accesses 2812system.l2c.overall_mshr_miss_rate::cpu0.data 0.277004 # mshr miss rate for overall accesses 2813system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735729 # mshr miss rate for overall accesses 2814system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186275 # mshr miss rate for overall accesses 2815system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.026316 # mshr miss rate for overall accesses 2816system.l2c.overall_mshr_miss_rate::cpu1.inst 0.213075 # mshr miss rate for overall accesses 2817system.l2c.overall_mshr_miss_rate::cpu1.data 0.461730 # mshr miss rate for overall accesses 2818system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521506 # mshr miss rate for overall accesses 2819system.l2c.overall_mshr_miss_rate::total 0.512355 # mshr miss rate for overall accesses 2820system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.408140 # average UpgradeReq mshr miss latency 2821system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20942.607247 # average UpgradeReq mshr miss latency 2822system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20827.513959 # average UpgradeReq mshr miss latency 2823system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20891.017964 # average SCUpgradeReq mshr miss latency 2824system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.983700 # average SCUpgradeReq mshr miss latency 2825system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20813.045587 # average SCUpgradeReq mshr miss latency 2826system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 88644.440374 # average ReadExReq mshr miss latency 2827system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71927.503560 # average ReadExReq mshr miss latency 2828system.l2c.ReadExReq_avg_mshr_miss_latency::total 81361.780213 # average ReadExReq mshr miss latency 2829system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average ReadSharedReq mshr miss latency 2830system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency 2831system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average ReadSharedReq mshr miss latency 2832system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77078.171599 # average ReadSharedReq mshr miss latency 2833system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average ReadSharedReq mshr miss latency 2834system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average ReadSharedReq mshr miss latency 2835system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average ReadSharedReq mshr miss latency 2836system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average ReadSharedReq mshr miss latency 2837system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 77415.541710 # average ReadSharedReq mshr miss latency 2838system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average ReadSharedReq mshr miss latency 2839system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88286.670526 # average ReadSharedReq mshr miss latency 2840system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average overall mshr miss latency 2841system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency 2842system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average overall mshr miss latency 2843system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83509.243227 # average overall mshr miss latency 2844system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average overall mshr miss latency 2845system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average overall mshr miss latency 2846system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average overall mshr miss latency 2847system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average overall mshr miss latency 2848system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73328.488115 # average overall mshr miss latency 2849system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average overall mshr miss latency 2850system.l2c.demand_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency 2851system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average overall mshr miss latency 2852system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency 2853system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average overall mshr miss latency 2854system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83509.243227 # average overall mshr miss latency 2855system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average overall mshr miss latency 2856system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average overall mshr miss latency 2857system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average overall mshr miss latency 2858system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average overall mshr miss latency 2859system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73328.488115 # average overall mshr miss latency 2860system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average overall mshr miss latency 2861system.l2c.overall_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency 2862system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency 2863system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167586.233263 # average ReadReq mshr uncacheable latency 2864system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average ReadReq mshr uncacheable latency 2865system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147195.872683 # average ReadReq mshr uncacheable latency 2866system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154971.563736 # average ReadReq mshr uncacheable latency 2867system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140424.604388 # average WriteReq mshr uncacheable latency 2868system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146721.601118 # average WriteReq mshr uncacheable latency 2869system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141436.495461 # average WriteReq mshr uncacheable latency 2870system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency 2871system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154802.853134 # average overall mshr uncacheable latency 2872system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average overall mshr uncacheable latency 2873system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146974.410366 # average overall mshr uncacheable latency 2874system.l2c.overall_avg_mshr_uncacheable_latency::total 148931.800613 # average overall mshr uncacheable latency 2875system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2876system.membus.trans_dist::ReadReq 38683 # Transaction distribution 2877system.membus.trans_dist::ReadResp 213983 # Transaction distribution 2878system.membus.trans_dist::WriteReq 31171 # Transaction distribution 2879system.membus.trans_dist::WriteResp 31171 # Transaction distribution 2880system.membus.trans_dist::Writeback 139589 # Transaction distribution 2881system.membus.trans_dist::CleanEvict 18226 # Transaction distribution 2882system.membus.trans_dist::UpgradeReq 78324 # Transaction distribution 2883system.membus.trans_dist::SCUpgradeReq 41642 # Transaction distribution 2884system.membus.trans_dist::UpgradeResp 15039 # Transaction distribution 2885system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 2886system.membus.trans_dist::ReadExReq 39751 # Transaction distribution 2887system.membus.trans_dist::ReadExResp 19228 # Transaction distribution 2888system.membus.trans_dist::ReadSharedReq 175300 # Transaction distribution 2889system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2890system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 2891system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) 2892system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2893system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14776 # Packet count per connected master and slave (bytes) 2894system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682330 # Packet count per connected master and slave (bytes) 2895system.membus.pkt_count_system.l2c.mem_side::total 805060 # Packet count per connected master and slave (bytes) 2896system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108902 # Packet count per connected master and slave (bytes) 2897system.membus.pkt_count_system.iocache.mem_side::total 108902 # Packet count per connected master and slave (bytes) 2898system.membus.pkt_count::total 913962 # Packet count per connected master and slave (bytes) 2899system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) 2900system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2901system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29552 # Cumulative packet size per connected master and slave (bytes) 2902system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19274524 # Cumulative packet size per connected master and slave (bytes) 2903system.membus.pkt_size_system.l2c.mem_side::total 19468214 # Cumulative packet size per connected master and slave (bytes) 2904system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2905system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2906system.membus.pkt_size::total 21785334 # Cumulative packet size per connected master and slave (bytes) 2907system.membus.snoops 126049 # Total snoops (count) 2908system.membus.snoop_fanout::samples 599148 # Request fanout histogram 2909system.membus.snoop_fanout::mean 1 # Request fanout histogram 2910system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2911system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2912system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2913system.membus.snoop_fanout::1 599148 100.00% 100.00% # Request fanout histogram 2914system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2915system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2916system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2917system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2918system.membus.snoop_fanout::total 599148 # Request fanout histogram 2919system.membus.reqLayer0.occupancy 91414000 # Layer occupancy (ticks) 2920system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2921system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) 2922system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2923system.membus.reqLayer2.occupancy 12977999 # Layer occupancy (ticks) 2924system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2925system.membus.reqLayer5.occupancy 1005422091 # Layer occupancy (ticks) 2926system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2927system.membus.respLayer2.occupancy 1166590180 # Layer occupancy (ticks) 2928system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2929system.membus.respLayer3.occupancy 64371509 # Layer occupancy (ticks) 2930system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2931system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2932system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2933system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2934system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2935system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2936system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2937system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2938system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2939system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2940system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2941system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2942system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2943system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2944system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2945system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2946system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2947system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2948system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2949system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2950system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2951system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2952system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2953system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2954system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2955system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2956system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2957system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2958system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2959system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2960system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2961system.realview.ethernet.droppedPackets 0 # number of packets dropped 2962system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 2963system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 2964system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 2965system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 2966system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 2967system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 2968system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 2969system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 2970system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 2971system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 2972system.toL2Bus.trans_dist::ReadReq 38687 # Transaction distribution 2973system.toL2Bus.trans_dist::ReadResp 518927 # Transaction distribution 2974system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution 2975system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution 2976system.toL2Bus.trans_dist::Writeback 372432 # Transaction distribution 2977system.toL2Bus.trans_dist::CleanEvict 99547 # Transaction distribution 2978system.toL2Bus.trans_dist::UpgradeReq 82215 # Transaction distribution 2979system.toL2Bus.trans_dist::SCUpgradeReq 41967 # Transaction distribution 2980system.toL2Bus.trans_dist::UpgradeResp 124182 # Transaction distribution 2981system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution 2982system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution 2983system.toL2Bus.trans_dist::ReadExReq 51561 # Transaction distribution 2984system.toL2Bus.trans_dist::ReadExResp 51561 # Transaction distribution 2985system.toL2Bus.trans_dist::ReadSharedReq 480255 # Transaction distribution 2986system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2987system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1133004 # Packet count per connected master and slave (bytes) 2988system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 361504 # Packet count per connected master and slave (bytes) 2989system.toL2Bus.pkt_count::total 1494508 # Packet count per connected master and slave (bytes) 2990system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32818575 # Cumulative packet size per connected master and slave (bytes) 2991system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6820071 # Cumulative packet size per connected master and slave (bytes) 2992system.toL2Bus.pkt_size::total 39638646 # Cumulative packet size per connected master and slave (bytes) 2993system.toL2Bus.snoops 465665 # Total snoops (count) 2994system.toL2Bus.snoop_fanout::samples 1285667 # Request fanout histogram 2995system.toL2Bus.snoop_fanout::mean 1.162057 # Request fanout histogram 2996system.toL2Bus.snoop_fanout::stdev 0.368503 # Request fanout histogram 2997system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2998system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2999system.toL2Bus.snoop_fanout::1 1077316 83.79% 83.79% # Request fanout histogram 3000system.toL2Bus.snoop_fanout::2 208351 16.21% 100.00% # Request fanout histogram 3001system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3002system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3003system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3004system.toL2Bus.snoop_fanout::total 1285667 # Request fanout histogram 3005system.toL2Bus.reqLayer0.occupancy 860205550 # Layer occupancy (ticks) 3006system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3007system.toL2Bus.snoopLayer0.occupancy 331500 # Layer occupancy (ticks) 3008system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3009system.toL2Bus.respLayer0.occupancy 646726661 # Layer occupancy (ticks) 3010system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3011system.toL2Bus.respLayer1.occupancy 269148617 # Layer occupancy (ticks) 3012system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3013 3014---------- End Simulation Statistics ---------- 3015