stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.658500 # Number of seconds simulated 4sim_ticks 2658500429500 # Number of ticks simulated 5final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 100914 # Simulator instruction rate (inst/s) 8host_op_rate 121517 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4256503307 # Simulator tick rate (ticks/s) 10host_mem_usage 437672 # Number of bytes of host memory used 11host_seconds 624.57 # Real time elapsed on the host 12sim_insts 63028509 # Number of instructions simulated 13sim_ops 75896503 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory 25system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory 32system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory 33system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 825078 # Number of write requests responded to by this memory 47system.physmem.bw_read::realview.clcd 46147592 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.dtb.walker 120 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 252267 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 1885334 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 241 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.inst 189481 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.l2cache.prefetcher 1942075 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 50417182 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 82597 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 23255 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 105852 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 1632054 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.inst 1133021 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 2771469 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 1632054 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.clcd 46147592 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 120 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 258662 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 1885334 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 241 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 1322502 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.l2cache.prefetcher 1942075 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 53188651 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 15512856 # Number of read requests accepted 76system.physmem.writeReqs 825078 # Number of write requests accepted 77system.physmem.readBursts 15512856 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 825078 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 992706816 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 115968 # Total number of bytes read from write queue 81system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 134034100 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 7367952 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 1812 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 709689 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 15707 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 969471 # Per bank write bursts 88system.physmem.perBankRdBursts::1 969246 # Per bank write bursts 89system.physmem.perBankRdBursts::2 969043 # Per bank write bursts 90system.physmem.perBankRdBursts::3 969564 # Per bank write bursts 91system.physmem.perBankRdBursts::4 971813 # Per bank write bursts 92system.physmem.perBankRdBursts::5 969510 # Per bank write bursts 93system.physmem.perBankRdBursts::6 969103 # Per bank write bursts 94system.physmem.perBankRdBursts::7 968972 # Per bank write bursts 95system.physmem.perBankRdBursts::8 969597 # Per bank write bursts 96system.physmem.perBankRdBursts::9 969588 # Per bank write bursts 97system.physmem.perBankRdBursts::10 969467 # Per bank write bursts 98system.physmem.perBankRdBursts::11 968939 # Per bank write bursts 99system.physmem.perBankRdBursts::12 969138 # Per bank write bursts 100system.physmem.perBankRdBursts::13 969444 # Per bank write bursts 101system.physmem.perBankRdBursts::14 969295 # Per bank write bursts 102system.physmem.perBankRdBursts::15 968854 # Per bank write bursts 103system.physmem.perBankWrBursts::0 7363 # Per bank write bursts 104system.physmem.perBankWrBursts::1 7345 # Per bank write bursts 105system.physmem.perBankWrBursts::2 6989 # Per bank write bursts 106system.physmem.perBankWrBursts::3 7254 # Per bank write bursts 107system.physmem.perBankWrBursts::4 7419 # Per bank write bursts 108system.physmem.perBankWrBursts::5 7425 # Per bank write bursts 109system.physmem.perBankWrBursts::6 7374 # Per bank write bursts 110system.physmem.perBankWrBursts::7 7152 # Per bank write bursts 111system.physmem.perBankWrBursts::8 7408 # Per bank write bursts 112system.physmem.perBankWrBursts::9 7360 # Per bank write bursts 113system.physmem.perBankWrBursts::10 7357 # Per bank write bursts 114system.physmem.perBankWrBursts::11 7062 # Per bank write bursts 115system.physmem.perBankWrBursts::12 6947 # Per bank write bursts 116system.physmem.perBankWrBursts::13 7077 # Per bank write bursts 117system.physmem.perBankWrBursts::14 7057 # Per bank write bursts 118system.physmem.perBankWrBursts::15 6784 # Per bank write bursts 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 120system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 121system.physmem.totGap 2658500409000 # Total gap between requests 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 59 # Read request sizes (log2) 125system.physmem.readPktSize::3 15335449 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) 128system.physmem.readPktSize::6 177348 # Read request sizes (log2) 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 757284 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) 135system.physmem.writePktSize::6 67794 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 1046196 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 1019688 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 986842 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 1094338 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 993106 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 1055542 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 2738032 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 2641383 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 3439999 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 128528 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 110050 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 101603 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 98027 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 19641 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 18942 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 18731 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 149 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 20 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 18 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 9 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 7 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 8 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::15 4053 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 4092 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 4702 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 5210 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 5835 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 6326 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 6634 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 6762 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 6877 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 7053 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 7199 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 7335 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 7285 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 7275 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 7348 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 7039 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 185 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 28 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 232system.physmem.bytesPerActivate::samples 1037696 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 963.760762 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 885.523874 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 219.463963 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 32040 3.09% 3.09% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 21332 2.06% 5.14% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 9404 0.91% 6.05% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 2470 0.24% 6.29% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 3075 0.30% 6.58% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 2164 0.21% 6.79% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 8825 0.85% 7.64% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 1075 0.10% 7.75% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 957311 92.25% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 1037696 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 6640 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 2336.000602 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 97357.467769 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-262143 6632 99.88% 99.88% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.91% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::524288-786431 3 0.05% 99.95% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.97% # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::total 6640 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6640 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 17.375452 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 17.330517 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 1.281391 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16 2518 37.92% 37.92% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::17 36 0.54% 38.46% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::18 3683 55.47% 93.93% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads 274system.physmem.totQLat 403478953250 # Total ticks spent queuing 275system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 279system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 2.94 # Data bus utilization in percentage 286system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing 289system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing 290system.physmem.readRowHits 14503444 # Number of row buffer hits during reads 291system.physmem.writeRowHits 85277 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes 294system.physmem.avgGap 162719.50 # Average gap between requests 295system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined 296system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states 297system.physmem.memoryStateTime::REF 88773100000 # Time in different power states 298system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states 300system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory 302system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 303system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory 304system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory 305system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 306system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 307system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory 308system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 309system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 310system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s) 311system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s) 312system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s) 313system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s) 314system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s) 315system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s) 316system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) 317system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) 318system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) 319system.membus.trans_dist::ReadReq 16692425 # Transaction distribution 320system.membus.trans_dist::ReadResp 16692425 # Transaction distribution 321system.membus.trans_dist::WriteReq 768873 # Transaction distribution 322system.membus.trans_dist::WriteResp 768873 # Transaction distribution 323system.membus.trans_dist::Writeback 67794 # Transaction distribution 324system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution 325system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution 326system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution 327system.membus.trans_dist::ReadExReq 15268 # Transaction distribution 328system.membus.trans_dist::ReadExResp 8420 # Transaction distribution 329system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) 334system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes) 335system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes) 339system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes) 340system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) 341system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes) 342system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 343system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) 344system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes) 345system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes) 349system.membus.snoops 68805 # Total snoops (count) 350system.membus.snoop_fanout::samples 327203 # Request fanout histogram 351system.membus.snoop_fanout::mean 1 # Request fanout histogram 352system.membus.snoop_fanout::stdev 0 # Request fanout histogram 353system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 354system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 355system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram 356system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 357system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 358system.membus.snoop_fanout::min_value 1 # Request fanout histogram 359system.membus.snoop_fanout::max_value 1 # Request fanout histogram 360system.membus.snoop_fanout::total 327203 # Request fanout histogram 361system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks) 362system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 363system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 364system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 365system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks) 366system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 367system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 368system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 369system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks) 370system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 371system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks) 372system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 373system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks) 374system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 375system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks) 376system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 377system.cpu_clk_domain.clock 500 # Clock period in ticks 378system.l2c.tags.replacements 92212 # number of replacements 379system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use 380system.l2c.tags.total_refs 396364 # Total number of references to valid blocks. 381system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks. 382system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks. 383system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 384system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor 385system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor 386system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor 387system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor 388system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor 389system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor 390system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor 391system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor 392system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor 393system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy 394system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy 395system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 396system.l2c.tags.occ_percent::cpu0.inst 0.038184 # Average percentage of cache occupancy 397system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.449355 # Average percentage of cache occupancy 398system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000086 # Average percentage of cache occupancy 399system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 400system.l2c.tags.occ_percent::cpu1.inst 0.031121 # Average percentage of cache occupancy 401system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200258 # Average percentage of cache occupancy 402system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy 403system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id 404system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 405system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id 406system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 407system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id 408system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id 409system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id 410system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 411system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 412system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 413system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 414system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id 415system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id 416system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id 417system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id 418system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id 419system.l2c.tags.occ_task_id_percent::1024 0.174408 # Percentage of cache occupancy per task id 420system.l2c.tags.tag_accesses 5122526 # Number of tag accesses 421system.l2c.tags.data_accesses 5122526 # Number of data accesses 422system.l2c.ReadReq_hits::cpu0.dtb.walker 183 # number of ReadReq hits 423system.l2c.ReadReq_hits::cpu0.itb.walker 37 # number of ReadReq hits 424system.l2c.ReadReq_hits::cpu0.inst 15214 # number of ReadReq hits 425system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88074 # number of ReadReq hits 426system.l2c.ReadReq_hits::cpu1.dtb.walker 233 # number of ReadReq hits 427system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits 428system.l2c.ReadReq_hits::cpu1.inst 19471 # number of ReadReq hits 429system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76181 # number of ReadReq hits 430system.l2c.ReadReq_hits::total 199443 # number of ReadReq hits 431system.l2c.Writeback_hits::writebacks 215065 # number of Writeback hits 432system.l2c.Writeback_hits::total 215065 # number of Writeback hits 433system.l2c.UpgradeReq_hits::cpu0.inst 3153 # number of UpgradeReq hits 434system.l2c.UpgradeReq_hits::cpu1.inst 2020 # number of UpgradeReq hits 435system.l2c.UpgradeReq_hits::total 5173 # number of UpgradeReq hits 436system.l2c.SCUpgradeReq_hits::cpu0.inst 94 # number of SCUpgradeReq hits 437system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits 438system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits 439system.l2c.ReadExReq_hits::cpu0.inst 2198 # number of ReadExReq hits 440system.l2c.ReadExReq_hits::cpu1.inst 2398 # number of ReadExReq hits 441system.l2c.ReadExReq_hits::total 4596 # number of ReadExReq hits 442system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits 443system.l2c.demand_hits::cpu0.itb.walker 37 # number of demand (read+write) hits 444system.l2c.demand_hits::cpu0.inst 17412 # number of demand (read+write) hits 445system.l2c.demand_hits::cpu0.l2cache.prefetcher 88074 # number of demand (read+write) hits 446system.l2c.demand_hits::cpu1.dtb.walker 233 # number of demand (read+write) hits 447system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits 448system.l2c.demand_hits::cpu1.inst 21869 # number of demand (read+write) hits 449system.l2c.demand_hits::cpu1.l2cache.prefetcher 76181 # number of demand (read+write) hits 450system.l2c.demand_hits::total 204039 # number of demand (read+write) hits 451system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits 452system.l2c.overall_hits::cpu0.itb.walker 37 # number of overall hits 453system.l2c.overall_hits::cpu0.inst 17412 # number of overall hits 454system.l2c.overall_hits::cpu0.l2cache.prefetcher 88074 # number of overall hits 455system.l2c.overall_hits::cpu1.dtb.walker 233 # number of overall hits 456system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits 457system.l2c.overall_hits::cpu1.inst 21869 # number of overall hits 458system.l2c.overall_hits::cpu1.l2cache.prefetcher 76181 # number of overall hits 459system.l2c.overall_hits::total 204039 # number of overall hits 460system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses 461system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 462system.l2c.ReadReq_misses::cpu0.inst 4198 # number of ReadReq misses 463system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq misses 464system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 465system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 466system.l2c.ReadReq_misses::cpu1.inst 3275 # number of ReadReq misses 467system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq misses 468system.l2c.ReadReq_misses::total 166478 # number of ReadReq misses 469system.l2c.UpgradeReq_misses::cpu0.inst 7866 # number of UpgradeReq misses 470system.l2c.UpgradeReq_misses::cpu1.inst 5570 # number of UpgradeReq misses 471system.l2c.UpgradeReq_misses::total 13436 # number of UpgradeReq misses 472system.l2c.SCUpgradeReq_misses::cpu0.inst 1047 # number of SCUpgradeReq misses 473system.l2c.SCUpgradeReq_misses::cpu1.inst 1097 # number of SCUpgradeReq misses 474system.l2c.SCUpgradeReq_misses::total 2144 # number of SCUpgradeReq misses 475system.l2c.ReadExReq_misses::cpu0.inst 3980 # number of ReadExReq misses 476system.l2c.ReadExReq_misses::cpu1.inst 4567 # number of ReadExReq misses 477system.l2c.ReadExReq_misses::total 8547 # number of ReadExReq misses 478system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses 479system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 480system.l2c.demand_misses::cpu0.inst 8178 # number of demand (read+write) misses 481system.l2c.demand_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) misses 482system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 483system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 484system.l2c.demand_misses::cpu1.inst 7842 # number of demand (read+write) misses 485system.l2c.demand_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) misses 486system.l2c.demand_misses::total 175025 # number of demand (read+write) misses 487system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses 488system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 489system.l2c.overall_misses::cpu0.inst 8178 # number of overall misses 490system.l2c.overall_misses::cpu0.l2cache.prefetcher 78315 # number of overall misses 491system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 492system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 493system.l2c.overall_misses::cpu1.inst 7842 # number of overall misses 494system.l2c.overall_misses::cpu1.l2cache.prefetcher 80672 # number of overall misses 495system.l2c.overall_misses::total 175025 # number of overall misses 496system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 332000 # number of ReadReq miss cycles 497system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles 498system.l2c.ReadReq_miss_latency::cpu0.inst 326103000 # number of ReadReq miss cycles 499system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of ReadReq miss cycles 500system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 790750 # number of ReadReq miss cycles 501system.l2c.ReadReq_miss_latency::cpu1.itb.walker 142500 # number of ReadReq miss cycles 502system.l2c.ReadReq_miss_latency::cpu1.inst 265072000 # number of ReadReq miss cycles 503system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of ReadReq miss cycles 504system.l2c.ReadReq_miss_latency::total 16470995078 # number of ReadReq miss cycles 505system.l2c.UpgradeReq_miss_latency::cpu0.inst 13809412 # number of UpgradeReq miss cycles 506system.l2c.UpgradeReq_miss_latency::cpu1.inst 6376729 # number of UpgradeReq miss cycles 507system.l2c.UpgradeReq_miss_latency::total 20186141 # number of UpgradeReq miss cycles 508system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 656474 # number of SCUpgradeReq miss cycles 509system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4281316 # number of SCUpgradeReq miss cycles 510system.l2c.SCUpgradeReq_miss_latency::total 4937790 # number of SCUpgradeReq miss cycles 511system.l2c.ReadExReq_miss_latency::cpu0.inst 283206167 # number of ReadExReq miss cycles 512system.l2c.ReadExReq_miss_latency::cpu1.inst 338006954 # number of ReadExReq miss cycles 513system.l2c.ReadExReq_miss_latency::total 621213121 # number of ReadExReq miss cycles 514system.l2c.demand_miss_latency::cpu0.dtb.walker 332000 # number of demand (read+write) miss cycles 515system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles 516system.l2c.demand_miss_latency::cpu0.inst 609309167 # number of demand (read+write) miss cycles 517system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of demand (read+write) miss cycles 518system.l2c.demand_miss_latency::cpu1.dtb.walker 790750 # number of demand (read+write) miss cycles 519system.l2c.demand_miss_latency::cpu1.itb.walker 142500 # number of demand (read+write) miss cycles 520system.l2c.demand_miss_latency::cpu1.inst 603078954 # number of demand (read+write) miss cycles 521system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of demand (read+write) miss cycles 522system.l2c.demand_miss_latency::total 17092208199 # number of demand (read+write) miss cycles 523system.l2c.overall_miss_latency::cpu0.dtb.walker 332000 # number of overall miss cycles 524system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles 525system.l2c.overall_miss_latency::cpu0.inst 609309167 # number of overall miss cycles 526system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of overall miss cycles 527system.l2c.overall_miss_latency::cpu1.dtb.walker 790750 # number of overall miss cycles 528system.l2c.overall_miss_latency::cpu1.itb.walker 142500 # number of overall miss cycles 529system.l2c.overall_miss_latency::cpu1.inst 603078954 # number of overall miss cycles 530system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of overall miss cycles 531system.l2c.overall_miss_latency::total 17092208199 # number of overall miss cycles 532system.l2c.ReadReq_accesses::cpu0.dtb.walker 188 # number of ReadReq accesses(hits+misses) 533system.l2c.ReadReq_accesses::cpu0.itb.walker 39 # number of ReadReq accesses(hits+misses) 534system.l2c.ReadReq_accesses::cpu0.inst 19412 # number of ReadReq accesses(hits+misses) 535system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166389 # number of ReadReq accesses(hits+misses) 536system.l2c.ReadReq_accesses::cpu1.dtb.walker 243 # number of ReadReq accesses(hits+misses) 537system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) 538system.l2c.ReadReq_accesses::cpu1.inst 22746 # number of ReadReq accesses(hits+misses) 539system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156853 # number of ReadReq accesses(hits+misses) 540system.l2c.ReadReq_accesses::total 365921 # number of ReadReq accesses(hits+misses) 541system.l2c.Writeback_accesses::writebacks 215065 # number of Writeback accesses(hits+misses) 542system.l2c.Writeback_accesses::total 215065 # number of Writeback accesses(hits+misses) 543system.l2c.UpgradeReq_accesses::cpu0.inst 11019 # number of UpgradeReq accesses(hits+misses) 544system.l2c.UpgradeReq_accesses::cpu1.inst 7590 # number of UpgradeReq accesses(hits+misses) 545system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses) 546system.l2c.SCUpgradeReq_accesses::cpu0.inst 1141 # number of SCUpgradeReq accesses(hits+misses) 547system.l2c.SCUpgradeReq_accesses::cpu1.inst 1310 # number of SCUpgradeReq accesses(hits+misses) 548system.l2c.SCUpgradeReq_accesses::total 2451 # number of SCUpgradeReq accesses(hits+misses) 549system.l2c.ReadExReq_accesses::cpu0.inst 6178 # number of ReadExReq accesses(hits+misses) 550system.l2c.ReadExReq_accesses::cpu1.inst 6965 # number of ReadExReq accesses(hits+misses) 551system.l2c.ReadExReq_accesses::total 13143 # number of ReadExReq accesses(hits+misses) 552system.l2c.demand_accesses::cpu0.dtb.walker 188 # number of demand (read+write) accesses 553system.l2c.demand_accesses::cpu0.itb.walker 39 # number of demand (read+write) accesses 554system.l2c.demand_accesses::cpu0.inst 25590 # number of demand (read+write) accesses 555system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166389 # number of demand (read+write) accesses 556system.l2c.demand_accesses::cpu1.dtb.walker 243 # number of demand (read+write) accesses 557system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses 558system.l2c.demand_accesses::cpu1.inst 29711 # number of demand (read+write) accesses 559system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156853 # number of demand (read+write) accesses 560system.l2c.demand_accesses::total 379064 # number of demand (read+write) accesses 561system.l2c.overall_accesses::cpu0.dtb.walker 188 # number of overall (read+write) accesses 562system.l2c.overall_accesses::cpu0.itb.walker 39 # number of overall (read+write) accesses 563system.l2c.overall_accesses::cpu0.inst 25590 # number of overall (read+write) accesses 564system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166389 # number of overall (read+write) accesses 565system.l2c.overall_accesses::cpu1.dtb.walker 243 # number of overall (read+write) accesses 566system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses 567system.l2c.overall_accesses::cpu1.inst 29711 # number of overall (read+write) accesses 568system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156853 # number of overall (read+write) accesses 569system.l2c.overall_accesses::total 379064 # number of overall (read+write) accesses 570system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for ReadReq accesses 571system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.051282 # miss rate for ReadReq accesses 572system.l2c.ReadReq_miss_rate::cpu0.inst 0.216258 # miss rate for ReadReq accesses 573system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for ReadReq accesses 574system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for ReadReq accesses 575system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses 576system.l2c.ReadReq_miss_rate::cpu1.inst 0.143981 # miss rate for ReadReq accesses 577system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for ReadReq accesses 578system.l2c.ReadReq_miss_rate::total 0.454956 # miss rate for ReadReq accesses 579system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.713858 # miss rate for UpgradeReq accesses 580system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.733860 # miss rate for UpgradeReq accesses 581system.l2c.UpgradeReq_miss_rate::total 0.722016 # miss rate for UpgradeReq accesses 582system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.917616 # miss rate for SCUpgradeReq accesses 583system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837405 # miss rate for SCUpgradeReq accesses 584system.l2c.SCUpgradeReq_miss_rate::total 0.874745 # miss rate for SCUpgradeReq accesses 585system.l2c.ReadExReq_miss_rate::cpu0.inst 0.644221 # miss rate for ReadExReq accesses 586system.l2c.ReadExReq_miss_rate::cpu1.inst 0.655707 # miss rate for ReadExReq accesses 587system.l2c.ReadExReq_miss_rate::total 0.650308 # miss rate for ReadExReq accesses 588system.l2c.demand_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for demand accesses 589system.l2c.demand_miss_rate::cpu0.itb.walker 0.051282 # miss rate for demand accesses 590system.l2c.demand_miss_rate::cpu0.inst 0.319578 # miss rate for demand accesses 591system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for demand accesses 592system.l2c.demand_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for demand accesses 593system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses 594system.l2c.demand_miss_rate::cpu1.inst 0.263943 # miss rate for demand accesses 595system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for demand accesses 596system.l2c.demand_miss_rate::total 0.461729 # miss rate for demand accesses 597system.l2c.overall_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for overall accesses 598system.l2c.overall_miss_rate::cpu0.itb.walker 0.051282 # miss rate for overall accesses 599system.l2c.overall_miss_rate::cpu0.inst 0.319578 # miss rate for overall accesses 600system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for overall accesses 601system.l2c.overall_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for overall accesses 602system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses 603system.l2c.overall_miss_rate::cpu1.inst 0.263943 # miss rate for overall accesses 604system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for overall accesses 605system.l2c.overall_miss_rate::total 0.461729 # miss rate for overall accesses 606system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66400 # average ReadReq miss latency 607system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 608system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77680.562172 # average ReadReq miss latency 609system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average ReadReq miss latency 610system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79075 # average ReadReq miss latency 611system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 142500 # average ReadReq miss latency 612system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80938.015267 # average ReadReq miss latency 613system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average ReadReq miss latency 614system.l2c.ReadReq_avg_miss_latency::total 98937.968248 # average ReadReq miss latency 615system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1755.582507 # average UpgradeReq miss latency 616system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1144.834650 # average UpgradeReq miss latency 617system.l2c.UpgradeReq_avg_miss_latency::total 1502.392155 # average UpgradeReq miss latency 618system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 627.004776 # average SCUpgradeReq miss latency 619system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 3902.749316 # average SCUpgradeReq miss latency 620system.l2c.SCUpgradeReq_avg_miss_latency::total 2303.073694 # average SCUpgradeReq miss latency 621system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 71157.328392 # average ReadExReq miss latency 622system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74010.719072 # average ReadExReq miss latency 623system.l2c.ReadExReq_avg_miss_latency::total 72682.007839 # average ReadExReq miss latency 624system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency 625system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 626system.l2c.demand_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency 627system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency 628system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency 629system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency 630system.l2c.demand_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency 631system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency 632system.l2c.demand_avg_miss_latency::total 97655.810307 # average overall miss latency 633system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency 634system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 635system.l2c.overall_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency 636system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency 637system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency 638system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency 639system.l2c.overall_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency 640system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency 641system.l2c.overall_avg_miss_latency::total 97655.810307 # average overall miss latency 642system.l2c.blocked_cycles::no_mshrs 174 # number of cycles access was blocked 643system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked 645system.l2c.blocked::no_targets 0 # number of cycles access was blocked 646system.l2c.avg_blocked_cycles::no_mshrs 34.800000 # average number of cycles each access was blocked 647system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.l2c.fast_writes 0 # number of fast writes performed 649system.l2c.cache_copies 0 # number of cache copies performed 650system.l2c.writebacks::writebacks 67795 # number of writebacks 651system.l2c.writebacks::total 67795 # number of writebacks 652system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 653system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 654system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 655system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 656system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 657system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 658system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5 # number of ReadReq MSHR misses 659system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 660system.l2c.ReadReq_mshr_misses::cpu0.inst 4198 # number of ReadReq MSHR misses 661system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq MSHR misses 662system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses 663system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 664system.l2c.ReadReq_mshr_misses::cpu1.inst 3274 # number of ReadReq MSHR misses 665system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq MSHR misses 666system.l2c.ReadReq_mshr_misses::total 166477 # number of ReadReq MSHR misses 667system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7866 # number of UpgradeReq MSHR misses 668system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5570 # number of UpgradeReq MSHR misses 669system.l2c.UpgradeReq_mshr_misses::total 13436 # number of UpgradeReq MSHR misses 670system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1047 # number of SCUpgradeReq MSHR misses 671system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1097 # number of SCUpgradeReq MSHR misses 672system.l2c.SCUpgradeReq_mshr_misses::total 2144 # number of SCUpgradeReq MSHR misses 673system.l2c.ReadExReq_mshr_misses::cpu0.inst 3980 # number of ReadExReq MSHR misses 674system.l2c.ReadExReq_mshr_misses::cpu1.inst 4567 # number of ReadExReq MSHR misses 675system.l2c.ReadExReq_mshr_misses::total 8547 # number of ReadExReq MSHR misses 676system.l2c.demand_mshr_misses::cpu0.dtb.walker 5 # number of demand (read+write) MSHR misses 677system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 678system.l2c.demand_mshr_misses::cpu0.inst 8178 # number of demand (read+write) MSHR misses 679system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) MSHR misses 680system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses 681system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 682system.l2c.demand_mshr_misses::cpu1.inst 7841 # number of demand (read+write) MSHR misses 683system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) MSHR misses 684system.l2c.demand_mshr_misses::total 175024 # number of demand (read+write) MSHR misses 685system.l2c.overall_mshr_misses::cpu0.dtb.walker 5 # number of overall MSHR misses 686system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 687system.l2c.overall_mshr_misses::cpu0.inst 8178 # number of overall MSHR misses 688system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of overall MSHR misses 689system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses 690system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 691system.l2c.overall_mshr_misses::cpu1.inst 7841 # number of overall MSHR misses 692system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of overall MSHR misses 693system.l2c.overall_mshr_misses::total 175024 # number of overall MSHR misses 694system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 270000 # number of ReadReq MSHR miss cycles 695system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 696system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273844500 # number of ReadReq MSHR miss cycles 697system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of ReadReq MSHR miss cycles 698system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 666250 # number of ReadReq MSHR miss cycles 699system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 130500 # number of ReadReq MSHR miss cycles 700system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 224380000 # number of ReadReq MSHR miss cycles 701system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of ReadReq MSHR miss cycles 702system.l2c.ReadReq_mshr_miss_latency::total 14413044080 # number of ReadReq MSHR miss cycles 703system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 79216804 # number of UpgradeReq MSHR miss cycles 704system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 56126525 # number of UpgradeReq MSHR miss cycles 705system.l2c.UpgradeReq_mshr_miss_latency::total 135343329 # number of UpgradeReq MSHR miss cycles 706system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10623534 # number of SCUpgradeReq MSHR miss cycles 707system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 10994091 # number of SCUpgradeReq MSHR miss cycles 708system.l2c.SCUpgradeReq_mshr_miss_latency::total 21617625 # number of SCUpgradeReq MSHR miss cycles 709system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 233127823 # number of ReadExReq MSHR miss cycles 710system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 280625546 # number of ReadExReq MSHR miss cycles 711system.l2c.ReadExReq_mshr_miss_latency::total 513753369 # number of ReadExReq MSHR miss cycles 712system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 270000 # number of demand (read+write) MSHR miss cycles 713system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 714system.l2c.demand_mshr_miss_latency::cpu0.inst 506972323 # number of demand (read+write) MSHR miss cycles 715system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of demand (read+write) MSHR miss cycles 716system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 666250 # number of demand (read+write) MSHR miss cycles 717system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 130500 # number of demand (read+write) MSHR miss cycles 718system.l2c.demand_mshr_miss_latency::cpu1.inst 505005546 # number of demand (read+write) MSHR miss cycles 719system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of demand (read+write) MSHR miss cycles 720system.l2c.demand_mshr_miss_latency::total 14926797449 # number of demand (read+write) MSHR miss cycles 721system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 270000 # number of overall MSHR miss cycles 722system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 723system.l2c.overall_mshr_miss_latency::cpu0.inst 506972323 # number of overall MSHR miss cycles 724system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of overall MSHR miss cycles 725system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 666250 # number of overall MSHR miss cycles 726system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 130500 # number of overall MSHR miss cycles 727system.l2c.overall_mshr_miss_latency::cpu1.inst 505005546 # number of overall MSHR miss cycles 728system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of overall MSHR miss cycles 729system.l2c.overall_mshr_miss_latency::total 14926797449 # number of overall MSHR miss cycles 730system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12572348996 # number of ReadReq MSHR uncacheable cycles 731system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155062093246 # number of ReadReq MSHR uncacheable cycles 732system.l2c.ReadReq_mshr_uncacheable_latency::total 167634442242 # number of ReadReq MSHR uncacheable cycles 733system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125655500 # number of WriteReq MSHR uncacheable cycles 734system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721437217 # number of WriteReq MSHR uncacheable cycles 735system.l2c.WriteReq_mshr_uncacheable_latency::total 16847092717 # number of WriteReq MSHR uncacheable cycles 736system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13698004496 # number of overall MSHR uncacheable cycles 737system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170783530463 # number of overall MSHR uncacheable cycles 738system.l2c.overall_mshr_uncacheable_latency::total 184481534959 # number of overall MSHR uncacheable cycles 739system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for ReadReq accesses 740system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for ReadReq accesses 741system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.216258 # mshr miss rate for ReadReq accesses 742system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for ReadReq accesses 743system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for ReadReq accesses 744system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses 745system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.143937 # mshr miss rate for ReadReq accesses 746system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for ReadReq accesses 747system.l2c.ReadReq_mshr_miss_rate::total 0.454953 # mshr miss rate for ReadReq accesses 748system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.713858 # mshr miss rate for UpgradeReq accesses 749system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.733860 # mshr miss rate for UpgradeReq accesses 750system.l2c.UpgradeReq_mshr_miss_rate::total 0.722016 # mshr miss rate for UpgradeReq accesses 751system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.917616 # mshr miss rate for SCUpgradeReq accesses 752system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837405 # mshr miss rate for SCUpgradeReq accesses 753system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.874745 # mshr miss rate for SCUpgradeReq accesses 754system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.644221 # mshr miss rate for ReadExReq accesses 755system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.655707 # mshr miss rate for ReadExReq accesses 756system.l2c.ReadExReq_mshr_miss_rate::total 0.650308 # mshr miss rate for ReadExReq accesses 757system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for demand accesses 758system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for demand accesses 759system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for demand accesses 760system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for demand accesses 761system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for demand accesses 762system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses 763system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses 764system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for demand accesses 765system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses 766system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses 767system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses 768system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses 769system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses 770system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses 771system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses 772system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses 773system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses 774system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses 775system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency 776system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 777system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency 778system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency 779system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency 780system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency 781system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency 782system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency 783system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency 784system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency 785system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency 786system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency 787system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency 788system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency 789system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency 790system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency 791system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency 792system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency 793system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency 794system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 795system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency 796system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency 797system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency 798system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency 799system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency 800system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency 801system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency 802system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency 803system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 804system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency 805system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency 806system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency 807system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency 808system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency 809system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency 810system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency 811system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 812system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 813system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 814system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 815system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 816system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 817system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 818system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 819system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 820system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 821system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 822system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 823system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 824system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 825system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 826system.cf0.dma_write_txs 0 # Number of DMA write transactions. 827system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution 828system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution 829system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution 830system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution 831system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution 832system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution 833system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution 834system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution 835system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 836system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution 837system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution 838system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution 839system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes) 840system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes) 841system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes) 842system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes) 843system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes) 844system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes) 845system.toL2Bus.snoops 171019 # Total snoops (count) 846system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram 847system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 848system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 849system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 850system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 851system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram 852system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 853system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 854system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 855system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 856system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram 857system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks) 858system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 859system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks) 860system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 861system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks) 862system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 863system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution 864system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution 865system.iobus.trans_dist::WriteReq 8084 # Transaction distribution 866system.iobus.trans_dist::WriteResp 8084 # Transaction distribution 867system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) 868system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes) 869system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 871system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 872system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 873system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) 874system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 878system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 879system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 880system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 881system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 882system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 883system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 884system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 885system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 886system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 887system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 888system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 889system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 890system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes) 891system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 892system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) 893system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes) 894system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) 895system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 900system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 906system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 907system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 908system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 910system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 911system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 912system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 913system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 914system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 915system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 916system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 917system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes) 918system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 919system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) 920system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes) 921system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) 922system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 923system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks) 924system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 925system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 926system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 927system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) 928system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 929system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 930system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 931system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 932system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 933system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) 934system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 935system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 936system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 937system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 938system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 939system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 940system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 941system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 942system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 943system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 944system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 945system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 946system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 947system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 948system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 949system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 950system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 951system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 952system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 953system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 954system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 955system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 956system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 957system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 958system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 959system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 960system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 961system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 962system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 963system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 964system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 965system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 966system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 967system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) 968system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 969system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks) 970system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 971system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks) 972system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 973system.cpu0.branchPred.lookups 7247667 # Number of BP lookups 974system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted 975system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect 976system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups 977system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits 978system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 979system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage 980system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target. 981system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions. 982system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 983system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 984system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 985system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 986system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 987system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 988system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 989system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 990system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 991system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 992system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 993system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 994system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 995system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 996system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 997system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 998system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 999system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1000system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1001system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1002system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1003system.cpu0.dtb.inst_hits 0 # ITB inst hits 1004system.cpu0.dtb.inst_misses 0 # ITB inst misses 1005system.cpu0.dtb.read_hits 6449421 # DTB read hits 1006system.cpu0.dtb.read_misses 22629 # DTB read misses 1007system.cpu0.dtb.write_hits 5803237 # DTB write hits 1008system.cpu0.dtb.write_misses 1880 # DTB write misses 1009system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1010system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1011system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1012system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1013system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB 1014system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions 1015system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch 1016system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1017system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions 1018system.cpu0.dtb.read_accesses 6472050 # DTB read accesses 1019system.cpu0.dtb.write_accesses 5805117 # DTB write accesses 1020system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1021system.cpu0.dtb.hits 12252658 # DTB hits 1022system.cpu0.dtb.misses 24509 # DTB misses 1023system.cpu0.dtb.accesses 12277167 # DTB accesses 1024system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1025system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1026system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1027system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1028system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1029system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1030system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1031system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1032system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1033system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1034system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1035system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1036system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1037system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1038system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1039system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1040system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1041system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1042system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1043system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1044system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1045system.cpu0.itb.inst_hits 13306402 # ITB inst hits 1046system.cpu0.itb.inst_misses 3981 # ITB inst misses 1047system.cpu0.itb.read_hits 0 # DTB read hits 1048system.cpu0.itb.read_misses 0 # DTB read misses 1049system.cpu0.itb.write_hits 0 # DTB write hits 1050system.cpu0.itb.write_misses 0 # DTB write misses 1051system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1052system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1053system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1054system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1055system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB 1056system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1057system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1058system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1059system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions 1060system.cpu0.itb.read_accesses 0 # DTB read accesses 1061system.cpu0.itb.write_accesses 0 # DTB write accesses 1062system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses 1063system.cpu0.itb.hits 13306402 # DTB hits 1064system.cpu0.itb.misses 3981 # DTB misses 1065system.cpu0.itb.accesses 13310383 # DTB accesses 1066system.cpu0.numCycles 86779776 # number of cpu cycles simulated 1067system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1068system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1069system.cpu0.committedInsts 29469177 # Number of instructions committed 1070system.cpu0.committedOps 35692469 # Number of ops (including micro ops) committed 1071system.cpu0.discardedOps 1968048 # Number of ops (including micro ops) which were discarded before commit 1072system.cpu0.numFetchSuspends 41085 # Number of times Execute suspended instruction fetching 1073system.cpu0.quiesceCycles 5234632408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1074system.cpu0.cpi 2.944764 # CPI: cycles per instruction 1075system.cpu0.ipc 0.339586 # IPC: instructions per cycle 1076system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1077system.cpu0.kern.inst.quiesce 47499 # number of quiesce instructions executed 1078system.cpu0.tickCycles 68210329 # Number of cycles that the object actually ticked 1079system.cpu0.idleCycles 18569447 # Total number of cycles that the object has spent stopped 1080system.cpu0.icache.tags.replacements 669895 # number of replacements 1081system.cpu0.icache.tags.tagsinuse 511.780265 # Cycle average of tags in use 1082system.cpu0.icache.tags.total_refs 12632215 # Total number of references to valid blocks. 1083system.cpu0.icache.tags.sampled_refs 670407 # Sample count of references to valid blocks. 1084system.cpu0.icache.tags.avg_refs 18.842606 # Average number of references to valid blocks. 1085system.cpu0.icache.tags.warmup_cycle 6077782000 # Cycle when the warmup percentage was hit. 1086system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780265 # Average occupied blocks per requestor 1087system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy 1088system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy 1089system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1090system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 1091system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id 1092system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id 1093system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1094system.cpu0.icache.tags.tag_accesses 27275662 # Number of tag accesses 1095system.cpu0.icache.tags.data_accesses 27275662 # Number of data accesses 1096system.cpu0.icache.ReadReq_hits::cpu0.inst 12632215 # number of ReadReq hits 1097system.cpu0.icache.ReadReq_hits::total 12632215 # number of ReadReq hits 1098system.cpu0.icache.demand_hits::cpu0.inst 12632215 # number of demand (read+write) hits 1099system.cpu0.icache.demand_hits::total 12632215 # number of demand (read+write) hits 1100system.cpu0.icache.overall_hits::cpu0.inst 12632215 # number of overall hits 1101system.cpu0.icache.overall_hits::total 12632215 # number of overall hits 1102system.cpu0.icache.ReadReq_misses::cpu0.inst 670411 # number of ReadReq misses 1103system.cpu0.icache.ReadReq_misses::total 670411 # number of ReadReq misses 1104system.cpu0.icache.demand_misses::cpu0.inst 670411 # number of demand (read+write) misses 1105system.cpu0.icache.demand_misses::total 670411 # number of demand (read+write) misses 1106system.cpu0.icache.overall_misses::cpu0.inst 670411 # number of overall misses 1107system.cpu0.icache.overall_misses::total 670411 # number of overall misses 1108system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5588337897 # number of ReadReq miss cycles 1109system.cpu0.icache.ReadReq_miss_latency::total 5588337897 # number of ReadReq miss cycles 1110system.cpu0.icache.demand_miss_latency::cpu0.inst 5588337897 # number of demand (read+write) miss cycles 1111system.cpu0.icache.demand_miss_latency::total 5588337897 # number of demand (read+write) miss cycles 1112system.cpu0.icache.overall_miss_latency::cpu0.inst 5588337897 # number of overall miss cycles 1113system.cpu0.icache.overall_miss_latency::total 5588337897 # number of overall miss cycles 1114system.cpu0.icache.ReadReq_accesses::cpu0.inst 13302626 # number of ReadReq accesses(hits+misses) 1115system.cpu0.icache.ReadReq_accesses::total 13302626 # number of ReadReq accesses(hits+misses) 1116system.cpu0.icache.demand_accesses::cpu0.inst 13302626 # number of demand (read+write) accesses 1117system.cpu0.icache.demand_accesses::total 13302626 # number of demand (read+write) accesses 1118system.cpu0.icache.overall_accesses::cpu0.inst 13302626 # number of overall (read+write) accesses 1119system.cpu0.icache.overall_accesses::total 13302626 # number of overall (read+write) accesses 1120system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050397 # miss rate for ReadReq accesses 1121system.cpu0.icache.ReadReq_miss_rate::total 0.050397 # miss rate for ReadReq accesses 1122system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050397 # miss rate for demand accesses 1123system.cpu0.icache.demand_miss_rate::total 0.050397 # miss rate for demand accesses 1124system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050397 # miss rate for overall accesses 1125system.cpu0.icache.overall_miss_rate::total 0.050397 # miss rate for overall accesses 1126system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8335.689446 # average ReadReq miss latency 1127system.cpu0.icache.ReadReq_avg_miss_latency::total 8335.689446 # average ReadReq miss latency 1128system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency 1129system.cpu0.icache.demand_avg_miss_latency::total 8335.689446 # average overall miss latency 1130system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency 1131system.cpu0.icache.overall_avg_miss_latency::total 8335.689446 # average overall miss latency 1132system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1133system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1134system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1135system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1136system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1137system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1138system.cpu0.icache.fast_writes 0 # number of fast writes performed 1139system.cpu0.icache.cache_copies 0 # number of cache copies performed 1140system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 670411 # number of ReadReq MSHR misses 1141system.cpu0.icache.ReadReq_mshr_misses::total 670411 # number of ReadReq MSHR misses 1142system.cpu0.icache.demand_mshr_misses::cpu0.inst 670411 # number of demand (read+write) MSHR misses 1143system.cpu0.icache.demand_mshr_misses::total 670411 # number of demand (read+write) MSHR misses 1144system.cpu0.icache.overall_mshr_misses::cpu0.inst 670411 # number of overall MSHR misses 1145system.cpu0.icache.overall_mshr_misses::total 670411 # number of overall MSHR misses 1146system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4581839103 # number of ReadReq MSHR miss cycles 1147system.cpu0.icache.ReadReq_mshr_miss_latency::total 4581839103 # number of ReadReq MSHR miss cycles 1148system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4581839103 # number of demand (read+write) MSHR miss cycles 1149system.cpu0.icache.demand_mshr_miss_latency::total 4581839103 # number of demand (read+write) MSHR miss cycles 1150system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4581839103 # number of overall MSHR miss cycles 1151system.cpu0.icache.overall_mshr_miss_latency::total 4581839103 # number of overall MSHR miss cycles 1152system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 215199250 # number of ReadReq MSHR uncacheable cycles 1153system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 215199250 # number of ReadReq MSHR uncacheable cycles 1154system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 215199250 # number of overall MSHR uncacheable cycles 1155system.cpu0.icache.overall_mshr_uncacheable_latency::total 215199250 # number of overall MSHR uncacheable cycles 1156system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for ReadReq accesses 1157system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050397 # mshr miss rate for ReadReq accesses 1158system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for demand accesses 1159system.cpu0.icache.demand_mshr_miss_rate::total 0.050397 # mshr miss rate for demand accesses 1160system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for overall accesses 1161system.cpu0.icache.overall_mshr_miss_rate::total 0.050397 # mshr miss rate for overall accesses 1162system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average ReadReq mshr miss latency 1163system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6834.373396 # average ReadReq mshr miss latency 1164system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency 1165system.cpu0.icache.demand_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency 1166system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency 1167system.cpu0.icache.overall_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency 1168system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1169system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1170system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1171system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1172system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1173system.cpu0.toL2Bus.trans_dist::ReadReq 1297449 # Transaction distribution 1174system.cpu0.toL2Bus.trans_dist::ReadResp 1098949 # Transaction distribution 1175system.cpu0.toL2Bus.trans_dist::WriteReq 10915 # Transaction distribution 1176system.cpu0.toL2Bus.trans_dist::WriteResp 10915 # Transaction distribution 1177system.cpu0.toL2Bus.trans_dist::Writeback 277394 # Transaction distribution 1178system.cpu0.toL2Bus.trans_dist::HardPFReq 309853 # Transaction distribution 1179system.cpu0.toL2Bus.trans_dist::UpgradeReq 48681 # Transaction distribution 1180system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23393 # Transaction distribution 1181system.cpu0.toL2Bus.trans_dist::UpgradeResp 54656 # Transaction distribution 1182system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution 1183system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution 1184system.cpu0.toL2Bus.trans_dist::ReadExReq 145161 # Transaction distribution 1185system.cpu0.toL2Bus.trans_dist::ReadExResp 136933 # Transaction distribution 1186system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1345495 # Packet count per connected master and slave (bytes) 1187system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1384854 # Packet count per connected master and slave (bytes) 1188system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13521 # Packet count per connected master and slave (bytes) 1189system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 67392 # Packet count per connected master and slave (bytes) 1190system.cpu0.toL2Bus.pkt_count::total 2811262 # Packet count per connected master and slave (bytes) 1191system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43053120 # Cumulative packet size per connected master and slave (bytes) 1192system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45712112 # Cumulative packet size per connected master and slave (bytes) 1193system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22348 # Cumulative packet size per connected master and slave (bytes) 1194system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 121316 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu0.toL2Bus.pkt_size::total 88908896 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu0.toL2Bus.snoops 663093 # Total snoops (count) 1197system.cpu0.toL2Bus.snoop_fanout::samples 2014813 # Request fanout histogram 1198system.cpu0.toL2Bus.snoop_fanout::mean 5.294791 # Request fanout histogram 1199system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram 1200system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1201system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1202system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1203system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1204system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1205system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1206system.cpu0.toL2Bus.snoop_fanout::5 1420865 70.52% 70.52% # Request fanout histogram 1207system.cpu0.toL2Bus.snoop_fanout::6 593948 29.48% 100.00% # Request fanout histogram 1208system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1209system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1210system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1211system.cpu0.toL2Bus.snoop_fanout::total 2014813 # Request fanout histogram 1212system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks) 1213system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1214system.cpu0.toL2Bus.snoopLayer0.occupancy 66915000 # Layer occupancy (ticks) 1215system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1216system.cpu0.toL2Bus.respLayer0.occupancy 1010138647 # Layer occupancy (ticks) 1217system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1218system.cpu0.toL2Bus.respLayer1.occupancy 706064108 # Layer occupancy (ticks) 1219system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1220system.cpu0.toL2Bus.respLayer2.occupancy 7935497 # Layer occupancy (ticks) 1221system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1222system.cpu0.toL2Bus.respLayer3.occupancy 37067990 # Layer occupancy (ticks) 1223system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1224system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6505286 # number of hwpf identified 1225system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 197873 # number of hwpf that were already in mshr 1226system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6075585 # number of hwpf that were already in the cache 1227system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2087 # number of hwpf that were already in the prefetch queue 1228system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1229system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated 1230system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 227641 # number of hwpf issued 1231system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 451994 # number of hwpf spanning a virtual page 1232system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1233system.cpu0.l2cache.tags.replacements 185568 # number of replacements 1234system.cpu0.l2cache.tags.tagsinuse 16045.943959 # Cycle average of tags in use 1235system.cpu0.l2cache.tags.total_refs 1211197 # Total number of references to valid blocks. 1236system.cpu0.l2cache.tags.sampled_refs 201780 # Sample count of references to valid blocks. 1237system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks. 1238system.cpu0.l2cache.tags.warmup_cycle 5120960000 # Cycle when the warmup percentage was hit. 1239system.cpu0.l2cache.tags.occ_blocks::writebacks 4785.288649 # Average occupied blocks per requestor 1240system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 15.661304 # Average occupied blocks per requestor 1241system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.175022 # Average occupied blocks per requestor 1242system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2150.935803 # Average occupied blocks per requestor 1243system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9093.883182 # Average occupied blocks per requestor 1244system.cpu0.l2cache.tags.occ_percent::writebacks 0.292071 # Average percentage of cache occupancy 1245system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000956 # Average percentage of cache occupancy 1246system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000011 # Average percentage of cache occupancy 1247system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.131283 # Average percentage of cache occupancy 1248system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.555047 # Average percentage of cache occupancy 1249system.cpu0.l2cache.tags.occ_percent::total 0.979367 # Average percentage of cache occupancy 1250system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8308 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7886 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 36 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 61 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 933 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5734 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1544 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1527 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5465 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 648 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.507080 # Percentage of cache occupancy per task id 1267system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 1268system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.481323 # Percentage of cache occupancy per task id 1269system.cpu0.l2cache.tags.tag_accesses 22965812 # Number of tag accesses 1270system.cpu0.l2cache.tags.data_accesses 22965812 # Number of data accesses 1271system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29822 # number of ReadReq hits 1272system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5414 # number of ReadReq hits 1273system.cpu0.l2cache.ReadReq_hits::cpu0.inst 885726 # number of ReadReq hits 1274system.cpu0.l2cache.ReadReq_hits::total 920962 # number of ReadReq hits 1275system.cpu0.l2cache.Writeback_hits::writebacks 277394 # number of Writeback hits 1276system.cpu0.l2cache.Writeback_hits::total 277394 # number of Writeback hits 1277system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1852 # number of UpgradeReq hits 1278system.cpu0.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits 1279system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 771 # number of SCUpgradeReq hits 1280system.cpu0.l2cache.SCUpgradeReq_hits::total 771 # number of SCUpgradeReq hits 1281system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107990 # number of ReadExReq hits 1282system.cpu0.l2cache.ReadExReq_hits::total 107990 # number of ReadExReq hits 1283system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29822 # number of demand (read+write) hits 1284system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5414 # number of demand (read+write) hits 1285system.cpu0.l2cache.demand_hits::cpu0.inst 993716 # number of demand (read+write) hits 1286system.cpu0.l2cache.demand_hits::total 1028952 # number of demand (read+write) hits 1287system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29822 # number of overall hits 1288system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5414 # number of overall hits 1289system.cpu0.l2cache.overall_hits::cpu0.inst 993716 # number of overall hits 1290system.cpu0.l2cache.overall_hits::total 1028952 # number of overall hits 1291system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses 1292system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses 1293system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49350 # number of ReadReq misses 1294system.cpu0.l2cache.ReadReq_misses::total 50030 # number of ReadReq misses 1295system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18889 # number of UpgradeReq misses 1296system.cpu0.l2cache.UpgradeReq_misses::total 18889 # number of UpgradeReq misses 1297system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10120 # number of SCUpgradeReq misses 1298system.cpu0.l2cache.SCUpgradeReq_misses::total 10120 # number of SCUpgradeReq misses 1299system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23685 # number of ReadExReq misses 1300system.cpu0.l2cache.ReadExReq_misses::total 23685 # number of ReadExReq misses 1301system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses 1302system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses 1303system.cpu0.l2cache.demand_misses::cpu0.inst 73035 # number of demand (read+write) misses 1304system.cpu0.l2cache.demand_misses::total 73715 # number of demand (read+write) misses 1305system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses 1306system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses 1307system.cpu0.l2cache.overall_misses::cpu0.inst 73035 # number of overall misses 1308system.cpu0.l2cache.overall_misses::total 73715 # number of overall misses 1309system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10873500 # number of ReadReq miss cycles 1310system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3613500 # number of ReadReq miss cycles 1311system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1326942681 # number of ReadReq miss cycles 1312system.cpu0.l2cache.ReadReq_miss_latency::total 1341429681 # number of ReadReq miss cycles 1313system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312233020 # number of UpgradeReq miss cycles 1314system.cpu0.l2cache.UpgradeReq_miss_latency::total 312233020 # number of UpgradeReq miss cycles 1315system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 200699599 # number of SCUpgradeReq miss cycles 1316system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 200699599 # number of SCUpgradeReq miss cycles 1317system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1269500 # number of SCUpgradeFailReq miss cycles 1318system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1269500 # number of SCUpgradeFailReq miss cycles 1319system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 847496588 # number of ReadExReq miss cycles 1320system.cpu0.l2cache.ReadExReq_miss_latency::total 847496588 # number of ReadExReq miss cycles 1321system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10873500 # number of demand (read+write) miss cycles 1322system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3613500 # number of demand (read+write) miss cycles 1323system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2174439269 # number of demand (read+write) miss cycles 1324system.cpu0.l2cache.demand_miss_latency::total 2188926269 # number of demand (read+write) miss cycles 1325system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10873500 # number of overall miss cycles 1326system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3613500 # number of overall miss cycles 1327system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2174439269 # number of overall miss cycles 1328system.cpu0.l2cache.overall_miss_latency::total 2188926269 # number of overall miss cycles 1329system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 30329 # number of ReadReq accesses(hits+misses) 1330system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5587 # number of ReadReq accesses(hits+misses) 1331system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935076 # number of ReadReq accesses(hits+misses) 1332system.cpu0.l2cache.ReadReq_accesses::total 970992 # number of ReadReq accesses(hits+misses) 1333system.cpu0.l2cache.Writeback_accesses::writebacks 277394 # number of Writeback accesses(hits+misses) 1334system.cpu0.l2cache.Writeback_accesses::total 277394 # number of Writeback accesses(hits+misses) 1335system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20741 # number of UpgradeReq accesses(hits+misses) 1336system.cpu0.l2cache.UpgradeReq_accesses::total 20741 # number of UpgradeReq accesses(hits+misses) 1337system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10891 # number of SCUpgradeReq accesses(hits+misses) 1338system.cpu0.l2cache.SCUpgradeReq_accesses::total 10891 # number of SCUpgradeReq accesses(hits+misses) 1339system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131675 # number of ReadExReq accesses(hits+misses) 1340system.cpu0.l2cache.ReadExReq_accesses::total 131675 # number of ReadExReq accesses(hits+misses) 1341system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 30329 # number of demand (read+write) accesses 1342system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5587 # number of demand (read+write) accesses 1343system.cpu0.l2cache.demand_accesses::cpu0.inst 1066751 # number of demand (read+write) accesses 1344system.cpu0.l2cache.demand_accesses::total 1102667 # number of demand (read+write) accesses 1345system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 30329 # number of overall (read+write) accesses 1346system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5587 # number of overall (read+write) accesses 1347system.cpu0.l2cache.overall_accesses::cpu0.inst 1066751 # number of overall (read+write) accesses 1348system.cpu0.l2cache.overall_accesses::total 1102667 # number of overall (read+write) accesses 1349system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for ReadReq accesses 1350system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030965 # miss rate for ReadReq accesses 1351system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052776 # miss rate for ReadReq accesses 1352system.cpu0.l2cache.ReadReq_miss_rate::total 0.051525 # miss rate for ReadReq accesses 1353system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.910708 # miss rate for UpgradeReq accesses 1354system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.910708 # miss rate for UpgradeReq accesses 1355system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.929208 # miss rate for SCUpgradeReq accesses 1356system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.929208 # miss rate for SCUpgradeReq accesses 1357system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179875 # miss rate for ReadExReq accesses 1358system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179875 # miss rate for ReadExReq accesses 1359system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for demand accesses 1360system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030965 # miss rate for demand accesses 1361system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068465 # miss rate for demand accesses 1362system.cpu0.l2cache.demand_miss_rate::total 0.066852 # miss rate for demand accesses 1363system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for overall accesses 1364system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030965 # miss rate for overall accesses 1365system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068465 # miss rate for overall accesses 1366system.cpu0.l2cache.overall_miss_rate::total 0.066852 # miss rate for overall accesses 1367system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average ReadReq miss latency 1368system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20887.283237 # average ReadReq miss latency 1369system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26888.402857 # average ReadReq miss latency 1370system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26812.506116 # average ReadReq miss latency 1371system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16529.886177 # average UpgradeReq miss latency 1372system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16529.886177 # average UpgradeReq miss latency 1373system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19831.976186 # average SCUpgradeReq miss latency 1374system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19831.976186 # average SCUpgradeReq miss latency 1375system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency 1376system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1377system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 35781.996538 # average ReadExReq miss latency 1378system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35781.996538 # average ReadExReq miss latency 1379system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency 1380system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency 1381system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency 1382system.cpu0.l2cache.demand_avg_miss_latency::total 29694.448470 # average overall miss latency 1383system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency 1384system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency 1385system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency 1386system.cpu0.l2cache.overall_avg_miss_latency::total 29694.448470 # average overall miss latency 1387system.cpu0.l2cache.blocked_cycles::no_mshrs 1346 # number of cycles access was blocked 1388system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1389system.cpu0.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked 1390system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1391system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 39.588235 # average number of cycles each access was blocked 1392system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1393system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1394system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1395system.cpu0.l2cache.writebacks::writebacks 114944 # number of writebacks 1396system.cpu0.l2cache.writebacks::total 114944 # number of writebacks 1397system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2945 # number of ReadReq MSHR hits 1398system.cpu0.l2cache.ReadReq_mshr_hits::total 2945 # number of ReadReq MSHR hits 1399system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 748 # number of ReadExReq MSHR hits 1400system.cpu0.l2cache.ReadExReq_mshr_hits::total 748 # number of ReadExReq MSHR hits 1401system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3693 # number of demand (read+write) MSHR hits 1402system.cpu0.l2cache.demand_mshr_hits::total 3693 # number of demand (read+write) MSHR hits 1403system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3693 # number of overall MSHR hits 1404system.cpu0.l2cache.overall_mshr_hits::total 3693 # number of overall MSHR hits 1405system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 507 # number of ReadReq MSHR misses 1406system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses 1407system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46405 # number of ReadReq MSHR misses 1408system.cpu0.l2cache.ReadReq_mshr_misses::total 47085 # number of ReadReq MSHR misses 1409system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of HardPFReq MSHR misses 1410system.cpu0.l2cache.HardPFReq_mshr_misses::total 227640 # number of HardPFReq MSHR misses 1411system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18889 # number of UpgradeReq MSHR misses 1412system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18889 # number of UpgradeReq MSHR misses 1413system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10120 # number of SCUpgradeReq MSHR misses 1414system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10120 # number of SCUpgradeReq MSHR misses 1415system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22937 # number of ReadExReq MSHR misses 1416system.cpu0.l2cache.ReadExReq_mshr_misses::total 22937 # number of ReadExReq MSHR misses 1417system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 507 # number of demand (read+write) MSHR misses 1418system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses 1419system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69342 # number of demand (read+write) MSHR misses 1420system.cpu0.l2cache.demand_mshr_misses::total 70022 # number of demand (read+write) MSHR misses 1421system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 507 # number of overall MSHR misses 1422system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses 1423system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69342 # number of overall MSHR misses 1424system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of overall MSHR misses 1425system.cpu0.l2cache.overall_mshr_misses::total 297662 # number of overall MSHR misses 1426system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of ReadReq MSHR miss cycles 1427system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2402500 # number of ReadReq MSHR miss cycles 1428system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 949940475 # number of ReadReq MSHR miss cycles 1429system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 959667475 # number of ReadReq MSHR miss cycles 1430system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of HardPFReq MSHR miss cycles 1431system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8587835748 # number of HardPFReq MSHR miss cycles 1432system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 341053600 # number of UpgradeReq MSHR miss cycles 1433system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 341053600 # number of UpgradeReq MSHR miss cycles 1434system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 145849953 # number of SCUpgradeReq MSHR miss cycles 1435system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 145849953 # number of SCUpgradeReq MSHR miss cycles 1436system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1059500 # number of SCUpgradeFailReq MSHR miss cycles 1437system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1059500 # number of SCUpgradeFailReq MSHR miss cycles 1438system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 592786901 # number of ReadExReq MSHR miss cycles 1439system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 592786901 # number of ReadExReq MSHR miss cycles 1440system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of demand (read+write) MSHR miss cycles 1441system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2402500 # number of demand (read+write) MSHR miss cycles 1442system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1542727376 # number of demand (read+write) MSHR miss cycles 1443system.cpu0.l2cache.demand_mshr_miss_latency::total 1552454376 # number of demand (read+write) MSHR miss cycles 1444system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of overall MSHR miss cycles 1445system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2402500 # number of overall MSHR miss cycles 1446system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1542727376 # number of overall MSHR miss cycles 1447system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of overall MSHR miss cycles 1448system.cpu0.l2cache.overall_mshr_miss_latency::total 10140290124 # number of overall MSHR miss cycles 1449system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14160332496 # number of ReadReq MSHR uncacheable cycles 1450system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14160332496 # number of ReadReq MSHR uncacheable cycles 1451system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312896000 # number of WriteReq MSHR uncacheable cycles 1452system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312896000 # number of WriteReq MSHR uncacheable cycles 1453system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15473228496 # number of overall MSHR uncacheable cycles 1454system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15473228496 # number of overall MSHR uncacheable cycles 1455system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for ReadReq accesses 1456system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for ReadReq accesses 1457system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049627 # mshr miss rate for ReadReq accesses 1458system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048492 # mshr miss rate for ReadReq accesses 1459system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1460system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1461system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.910708 # mshr miss rate for UpgradeReq accesses 1462system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.910708 # mshr miss rate for UpgradeReq accesses 1463system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.929208 # mshr miss rate for SCUpgradeReq accesses 1464system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.929208 # mshr miss rate for SCUpgradeReq accesses 1465system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.174194 # mshr miss rate for ReadExReq accesses 1466system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.174194 # mshr miss rate for ReadExReq accesses 1467system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for demand accesses 1468system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for demand accesses 1469system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for demand accesses 1470system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063502 # mshr miss rate for demand accesses 1471system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for overall accesses 1472system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for overall accesses 1473system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for overall accesses 1474system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1475system.cpu0.l2cache.overall_mshr_miss_rate::total 0.269947 # mshr miss rate for overall accesses 1476system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average ReadReq mshr miss latency 1477system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average ReadReq mshr miss latency 1478system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20470.649176 # average ReadReq mshr miss latency 1479system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20381.596581 # average ReadReq mshr miss latency 1480system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average HardPFReq mshr miss latency 1481system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37725.512862 # average HardPFReq mshr miss latency 1482system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18055.672614 # average UpgradeReq mshr miss latency 1483system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18055.672614 # average UpgradeReq mshr miss latency 1484system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14412.050692 # average SCUpgradeReq mshr miss latency 1485system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14412.050692 # average SCUpgradeReq mshr miss latency 1486system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency 1487system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1488system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 25844.133976 # average ReadExReq mshr miss latency 1489system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25844.133976 # average ReadExReq mshr miss latency 1490system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency 1491system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency 1492system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency 1493system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22170.951644 # average overall mshr miss latency 1494system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency 1495system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency 1496system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency 1497system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average overall mshr miss latency 1498system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34066.458345 # average overall mshr miss latency 1499system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1500system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1501system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1502system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1503system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1504system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1505system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1506system.cpu0.dcache.tags.replacements 363620 # number of replacements 1507system.cpu0.dcache.tags.tagsinuse 473.092728 # Cycle average of tags in use 1508system.cpu0.dcache.tags.total_refs 11412864 # Total number of references to valid blocks. 1509system.cpu0.dcache.tags.sampled_refs 364132 # Sample count of references to valid blocks. 1510system.cpu0.dcache.tags.avg_refs 31.342656 # Average number of references to valid blocks. 1511system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. 1512system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.092728 # Average occupied blocks per requestor 1513system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924009 # Average percentage of cache occupancy 1514system.cpu0.dcache.tags.occ_percent::total 0.924009 # Average percentage of cache occupancy 1515system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1516system.cpu0.dcache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 1517system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id 1518system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 1519system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1520system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1521system.cpu0.dcache.tags.tag_accesses 24359055 # Number of tag accesses 1522system.cpu0.dcache.tags.data_accesses 24359055 # Number of data accesses 1523system.cpu0.dcache.ReadReq_hits::cpu0.inst 5804369 # number of ReadReq hits 1524system.cpu0.dcache.ReadReq_hits::total 5804369 # number of ReadReq hits 1525system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275244 # number of WriteReq hits 1526system.cpu0.dcache.WriteReq_hits::total 5275244 # number of WriteReq hits 1527system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147463 # number of LoadLockedReq hits 1528system.cpu0.dcache.LoadLockedReq_hits::total 147463 # number of LoadLockedReq hits 1529system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146615 # number of StoreCondReq hits 1530system.cpu0.dcache.StoreCondReq_hits::total 146615 # number of StoreCondReq hits 1531system.cpu0.dcache.demand_hits::cpu0.inst 11079613 # number of demand (read+write) hits 1532system.cpu0.dcache.demand_hits::total 11079613 # number of demand (read+write) hits 1533system.cpu0.dcache.overall_hits::cpu0.inst 11079613 # number of overall hits 1534system.cpu0.dcache.overall_hits::total 11079613 # number of overall hits 1535system.cpu0.dcache.ReadReq_misses::cpu0.inst 309599 # number of ReadReq misses 1536system.cpu0.dcache.ReadReq_misses::total 309599 # number of ReadReq misses 1537system.cpu0.dcache.WriteReq_misses::cpu0.inst 276951 # number of WriteReq misses 1538system.cpu0.dcache.WriteReq_misses::total 276951 # number of WriteReq misses 1539system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10168 # number of LoadLockedReq misses 1540system.cpu0.dcache.LoadLockedReq_misses::total 10168 # number of LoadLockedReq misses 1541system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10891 # number of StoreCondReq misses 1542system.cpu0.dcache.StoreCondReq_misses::total 10891 # number of StoreCondReq misses 1543system.cpu0.dcache.demand_misses::cpu0.inst 586550 # number of demand (read+write) misses 1544system.cpu0.dcache.demand_misses::total 586550 # number of demand (read+write) misses 1545system.cpu0.dcache.overall_misses::cpu0.inst 586550 # number of overall misses 1546system.cpu0.dcache.overall_misses::total 586550 # number of overall misses 1547system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3701357617 # number of ReadReq miss cycles 1548system.cpu0.dcache.ReadReq_miss_latency::total 3701357617 # number of ReadReq miss cycles 1549system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4193199790 # number of WriteReq miss cycles 1550system.cpu0.dcache.WriteReq_miss_latency::total 4193199790 # number of WriteReq miss cycles 1551system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 166675501 # number of LoadLockedReq miss cycles 1552system.cpu0.dcache.LoadLockedReq_miss_latency::total 166675501 # number of LoadLockedReq miss cycles 1553system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254636964 # number of StoreCondReq miss cycles 1554system.cpu0.dcache.StoreCondReq_miss_latency::total 254636964 # number of StoreCondReq miss cycles 1555system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1359500 # number of StoreCondFailReq miss cycles 1556system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1359500 # number of StoreCondFailReq miss cycles 1557system.cpu0.dcache.demand_miss_latency::cpu0.inst 7894557407 # number of demand (read+write) miss cycles 1558system.cpu0.dcache.demand_miss_latency::total 7894557407 # number of demand (read+write) miss cycles 1559system.cpu0.dcache.overall_miss_latency::cpu0.inst 7894557407 # number of overall miss cycles 1560system.cpu0.dcache.overall_miss_latency::total 7894557407 # number of overall miss cycles 1561system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113968 # number of ReadReq accesses(hits+misses) 1562system.cpu0.dcache.ReadReq_accesses::total 6113968 # number of ReadReq accesses(hits+misses) 1563system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5552195 # number of WriteReq accesses(hits+misses) 1564system.cpu0.dcache.WriteReq_accesses::total 5552195 # number of WriteReq accesses(hits+misses) 1565system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157631 # number of LoadLockedReq accesses(hits+misses) 1566system.cpu0.dcache.LoadLockedReq_accesses::total 157631 # number of LoadLockedReq accesses(hits+misses) 1567system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157506 # number of StoreCondReq accesses(hits+misses) 1568system.cpu0.dcache.StoreCondReq_accesses::total 157506 # number of StoreCondReq accesses(hits+misses) 1569system.cpu0.dcache.demand_accesses::cpu0.inst 11666163 # number of demand (read+write) accesses 1570system.cpu0.dcache.demand_accesses::total 11666163 # number of demand (read+write) accesses 1571system.cpu0.dcache.overall_accesses::cpu0.inst 11666163 # number of overall (read+write) accesses 1572system.cpu0.dcache.overall_accesses::total 11666163 # number of overall (read+write) accesses 1573system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050638 # miss rate for ReadReq accesses 1574system.cpu0.dcache.ReadReq_miss_rate::total 0.050638 # miss rate for ReadReq accesses 1575system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049881 # miss rate for WriteReq accesses 1576system.cpu0.dcache.WriteReq_miss_rate::total 0.049881 # miss rate for WriteReq accesses 1577system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064505 # miss rate for LoadLockedReq accesses 1578system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064505 # miss rate for LoadLockedReq accesses 1579system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069147 # miss rate for StoreCondReq accesses 1580system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069147 # miss rate for StoreCondReq accesses 1581system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050278 # miss rate for demand accesses 1582system.cpu0.dcache.demand_miss_rate::total 0.050278 # miss rate for demand accesses 1583system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050278 # miss rate for overall accesses 1584system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses 1585system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11955.328076 # average ReadReq miss latency 1586system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency 1587system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15140.583677 # average WriteReq miss latency 1588system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency 1589system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency 1590system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency 1591system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23380.494353 # average StoreCondReq miss latency 1592system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23380.494353 # average StoreCondReq miss latency 1593system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 1594system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1595system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency 1596system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency 1597system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency 1598system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency 1599system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1600system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1601system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1602system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1603system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1604system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1605system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1606system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1607system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks 1608system.cpu0.dcache.writebacks::total 277395 # number of writebacks 1609system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits 1610system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits 1611system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits 1612system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits 1613system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits 1614system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits 1615system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits 1616system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits 1617system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits 1618system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits 1619system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses 1620system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses 1621system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses 1622system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses 1623system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses 1624system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses 1625system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses 1626system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses 1627system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses 1628system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses 1629system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses 1630system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses 1631system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles 1632system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles 1633system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles 1634system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles 1635system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles 1636system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles 1637system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles 1638system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles 1639system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles 1640system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles 1641system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles 1642system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles 1643system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles 1644system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles 1645system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles 1646system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles 1647system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles 1648system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles 1649system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles 1650system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles 1651system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses 1652system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses 1653system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses 1654system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses 1655system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses 1656system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses 1657system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses 1658system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses 1659system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses 1660system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses 1661system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses 1662system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses 1663system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency 1664system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency 1665system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency 1666system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency 1667system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency 1668system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency 1669system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency 1670system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency 1671system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 1672system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1673system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency 1674system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency 1675system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency 1676system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency 1677system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1678system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1679system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1680system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1681system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1682system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1683system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1684system.cpu1.branchPred.lookups 7015971 # Number of BP lookups 1685system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted 1686system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect 1687system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups 1688system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits 1689system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1690system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage 1691system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target. 1692system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions. 1693system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1694system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1695system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1696system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1697system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1698system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1699system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1700system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1701system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1702system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1703system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1704system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1705system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1706system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1707system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1708system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1709system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1710system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1711system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1712system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1713system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1714system.cpu1.dtb.inst_hits 0 # ITB inst hits 1715system.cpu1.dtb.inst_misses 0 # ITB inst misses 1716system.cpu1.dtb.read_hits 7897430 # DTB read hits 1717system.cpu1.dtb.read_misses 21135 # DTB read misses 1718system.cpu1.dtb.write_hits 6047519 # DTB write hits 1719system.cpu1.dtb.write_misses 2176 # DTB write misses 1720system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1721system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1722system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1723system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1724system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB 1725system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions 1726system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch 1727system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1728system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions 1729system.cpu1.dtb.read_accesses 7918565 # DTB read accesses 1730system.cpu1.dtb.write_accesses 6049695 # DTB write accesses 1731system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1732system.cpu1.dtb.hits 13944949 # DTB hits 1733system.cpu1.dtb.misses 23311 # DTB misses 1734system.cpu1.dtb.accesses 13968260 # DTB accesses 1735system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1736system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1737system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1738system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1739system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1740system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1741system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1742system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1743system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1744system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1745system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1746system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1747system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1748system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1749system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1750system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1751system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1752system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1753system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1754system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1755system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1756system.cpu1.itb.inst_hits 14225149 # ITB inst hits 1757system.cpu1.itb.inst_misses 5020 # ITB inst misses 1758system.cpu1.itb.read_hits 0 # DTB read hits 1759system.cpu1.itb.read_misses 0 # DTB read misses 1760system.cpu1.itb.write_hits 0 # DTB write hits 1761system.cpu1.itb.write_misses 0 # DTB write misses 1762system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1763system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1764system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1765system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1766system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB 1767system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1768system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1769system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1770system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions 1771system.cpu1.itb.read_accesses 0 # DTB read accesses 1772system.cpu1.itb.write_accesses 0 # DTB write accesses 1773system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses 1774system.cpu1.itb.hits 14225149 # DTB hits 1775system.cpu1.itb.misses 5020 # DTB misses 1776system.cpu1.itb.accesses 14230169 # DTB accesses 1777system.cpu1.numCycles 502333604 # number of cpu cycles simulated 1778system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1779system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1780system.cpu1.committedInsts 33559332 # Number of instructions committed 1781system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed 1782system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit 1783system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching 1784system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1785system.cpu1.cpi 14.968522 # CPI: cycles per instruction 1786system.cpu1.ipc 0.066807 # IPC: instructions per cycle 1787system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1788system.cpu1.kern.inst.quiesce 45430 # number of quiesce instructions executed 1789system.cpu1.tickCycles 438569606 # Number of cycles that the object actually ticked 1790system.cpu1.idleCycles 63763998 # Total number of cycles that the object has spent stopped 1791system.cpu1.icache.tags.replacements 776883 # number of replacements 1792system.cpu1.icache.tags.tagsinuse 499.132911 # Cycle average of tags in use 1793system.cpu1.icache.tags.total_refs 13444222 # Total number of references to valid blocks. 1794system.cpu1.icache.tags.sampled_refs 777395 # Sample count of references to valid blocks. 1795system.cpu1.icache.tags.avg_refs 17.293939 # Average number of references to valid blocks. 1796system.cpu1.icache.tags.warmup_cycle 68940011500 # Cycle when the warmup percentage was hit. 1797system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.132911 # Average occupied blocks per requestor 1798system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974869 # Average percentage of cache occupancy 1799system.cpu1.icache.tags.occ_percent::total 0.974869 # Average percentage of cache occupancy 1800system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1801system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 1802system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1803system.cpu1.icache.tags.tag_accesses 29220629 # Number of tag accesses 1804system.cpu1.icache.tags.data_accesses 29220629 # Number of data accesses 1805system.cpu1.icache.ReadReq_hits::cpu1.inst 13444222 # number of ReadReq hits 1806system.cpu1.icache.ReadReq_hits::total 13444222 # number of ReadReq hits 1807system.cpu1.icache.demand_hits::cpu1.inst 13444222 # number of demand (read+write) hits 1808system.cpu1.icache.demand_hits::total 13444222 # number of demand (read+write) hits 1809system.cpu1.icache.overall_hits::cpu1.inst 13444222 # number of overall hits 1810system.cpu1.icache.overall_hits::total 13444222 # number of overall hits 1811system.cpu1.icache.ReadReq_misses::cpu1.inst 777395 # number of ReadReq misses 1812system.cpu1.icache.ReadReq_misses::total 777395 # number of ReadReq misses 1813system.cpu1.icache.demand_misses::cpu1.inst 777395 # number of demand (read+write) misses 1814system.cpu1.icache.demand_misses::total 777395 # number of demand (read+write) misses 1815system.cpu1.icache.overall_misses::cpu1.inst 777395 # number of overall misses 1816system.cpu1.icache.overall_misses::total 777395 # number of overall misses 1817system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6473834509 # number of ReadReq miss cycles 1818system.cpu1.icache.ReadReq_miss_latency::total 6473834509 # number of ReadReq miss cycles 1819system.cpu1.icache.demand_miss_latency::cpu1.inst 6473834509 # number of demand (read+write) miss cycles 1820system.cpu1.icache.demand_miss_latency::total 6473834509 # number of demand (read+write) miss cycles 1821system.cpu1.icache.overall_miss_latency::cpu1.inst 6473834509 # number of overall miss cycles 1822system.cpu1.icache.overall_miss_latency::total 6473834509 # number of overall miss cycles 1823system.cpu1.icache.ReadReq_accesses::cpu1.inst 14221617 # number of ReadReq accesses(hits+misses) 1824system.cpu1.icache.ReadReq_accesses::total 14221617 # number of ReadReq accesses(hits+misses) 1825system.cpu1.icache.demand_accesses::cpu1.inst 14221617 # number of demand (read+write) accesses 1826system.cpu1.icache.demand_accesses::total 14221617 # number of demand (read+write) accesses 1827system.cpu1.icache.overall_accesses::cpu1.inst 14221617 # number of overall (read+write) accesses 1828system.cpu1.icache.overall_accesses::total 14221617 # number of overall (read+write) accesses 1829system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054663 # miss rate for ReadReq accesses 1830system.cpu1.icache.ReadReq_miss_rate::total 0.054663 # miss rate for ReadReq accesses 1831system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054663 # miss rate for demand accesses 1832system.cpu1.icache.demand_miss_rate::total 0.054663 # miss rate for demand accesses 1833system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054663 # miss rate for overall accesses 1834system.cpu1.icache.overall_miss_rate::total 0.054663 # miss rate for overall accesses 1835system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8327.599880 # average ReadReq miss latency 1836system.cpu1.icache.ReadReq_avg_miss_latency::total 8327.599880 # average ReadReq miss latency 1837system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency 1838system.cpu1.icache.demand_avg_miss_latency::total 8327.599880 # average overall miss latency 1839system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency 1840system.cpu1.icache.overall_avg_miss_latency::total 8327.599880 # average overall miss latency 1841system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1842system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1843system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1844system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1845system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1846system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1847system.cpu1.icache.fast_writes 0 # number of fast writes performed 1848system.cpu1.icache.cache_copies 0 # number of cache copies performed 1849system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 777395 # number of ReadReq MSHR misses 1850system.cpu1.icache.ReadReq_mshr_misses::total 777395 # number of ReadReq MSHR misses 1851system.cpu1.icache.demand_mshr_misses::cpu1.inst 777395 # number of demand (read+write) MSHR misses 1852system.cpu1.icache.demand_mshr_misses::total 777395 # number of demand (read+write) MSHR misses 1853system.cpu1.icache.overall_mshr_misses::cpu1.inst 777395 # number of overall MSHR misses 1854system.cpu1.icache.overall_mshr_misses::total 777395 # number of overall MSHR misses 1855system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5306001991 # number of ReadReq MSHR miss cycles 1856system.cpu1.icache.ReadReq_mshr_miss_latency::total 5306001991 # number of ReadReq MSHR miss cycles 1857system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5306001991 # number of demand (read+write) MSHR miss cycles 1858system.cpu1.icache.demand_mshr_miss_latency::total 5306001991 # number of demand (read+write) MSHR miss cycles 1859system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5306001991 # number of overall MSHR miss cycles 1860system.cpu1.icache.overall_mshr_miss_latency::total 5306001991 # number of overall MSHR miss cycles 1861system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7443500 # number of ReadReq MSHR uncacheable cycles 1862system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7443500 # number of ReadReq MSHR uncacheable cycles 1863system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7443500 # number of overall MSHR uncacheable cycles 1864system.cpu1.icache.overall_mshr_uncacheable_latency::total 7443500 # number of overall MSHR uncacheable cycles 1865system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for ReadReq accesses 1866system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054663 # mshr miss rate for ReadReq accesses 1867system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for demand accesses 1868system.cpu1.icache.demand_mshr_miss_rate::total 0.054663 # mshr miss rate for demand accesses 1869system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for overall accesses 1870system.cpu1.icache.overall_mshr_miss_rate::total 0.054663 # mshr miss rate for overall accesses 1871system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average ReadReq mshr miss latency 1872system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6825.361613 # average ReadReq mshr miss latency 1873system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency 1874system.cpu1.icache.demand_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency 1875system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency 1876system.cpu1.icache.overall_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency 1877system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1878system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1879system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1880system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1881system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1882system.cpu1.toL2Bus.trans_dist::ReadReq 2372884 # Transaction distribution 1883system.cpu1.toL2Bus.trans_dist::ReadResp 2161619 # Transaction distribution 1884system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1885system.cpu1.toL2Bus.trans_dist::WriteReq 757958 # Transaction distribution 1886system.cpu1.toL2Bus.trans_dist::WriteResp 757958 # Transaction distribution 1887system.cpu1.toL2Bus.trans_dist::Writeback 242023 # Transaction distribution 1888system.cpu1.toL2Bus.trans_dist::HardPFReq 269237 # Transaction distribution 1889system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution 1890system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution 1891system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution 1892system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution 1893system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution 1894system.cpu1.toL2Bus.trans_dist::ReadExReq 145739 # Transaction distribution 1895system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution 1896system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1554692 # Packet count per connected master and slave (bytes) 1897system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4766762 # Packet count per connected master and slave (bytes) 1898system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17488 # Packet count per connected master and slave (bytes) 1899system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67601 # Packet count per connected master and slave (bytes) 1900system.cpu1.toL2Bus.pkt_count::total 6406543 # Packet count per connected master and slave (bytes) 1901system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49741696 # Cumulative packet size per connected master and slave (bytes) 1902system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44501144 # Cumulative packet size per connected master and slave (bytes) 1903system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30140 # Cumulative packet size per connected master and slave (bytes) 1904system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 121260 # Cumulative packet size per connected master and slave (bytes) 1905system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes) 1906system.cpu1.toL2Bus.snoops 607829 # Total snoops (count) 1907system.cpu1.toL2Bus.snoop_fanout::samples 2003123 # Request fanout histogram 1908system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram 1909system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram 1910system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1911system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1912system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1913system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1914system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1915system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1916system.cpu1.toL2Bus.snoop_fanout::5 1446836 72.23% 72.23% # Request fanout histogram 1917system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram 1918system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1919system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1920system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1921system.cpu1.toL2Bus.snoop_fanout::total 2003123 # Request fanout histogram 1922system.cpu1.toL2Bus.reqLayer0.occupancy 2275243689 # Layer occupancy (ticks) 1923system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1924system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks) 1925system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1926system.cpu1.toL2Bus.respLayer0.occupancy 1167104009 # Layer occupancy (ticks) 1927system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1928system.cpu1.toL2Bus.respLayer1.occupancy 2025335762 # Layer occupancy (ticks) 1929system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1930system.cpu1.toL2Bus.respLayer2.occupancy 9955994 # Layer occupancy (ticks) 1931system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1932system.cpu1.toL2Bus.respLayer3.occupancy 37292239 # Layer occupancy (ticks) 1933system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1934system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6843055 # number of hwpf identified 1935system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163843 # number of hwpf that were already in mshr 1936system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6478033 # number of hwpf that were already in the cache 1937system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2741 # number of hwpf that were already in the prefetch queue 1938system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1939system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated 1940system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 196423 # number of hwpf issued 1941system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 563857 # number of hwpf spanning a virtual page 1942system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1943system.cpu1.l2cache.tags.replacements 179577 # number of replacements 1944system.cpu1.l2cache.tags.tagsinuse 15624.309787 # Cycle average of tags in use 1945system.cpu1.l2cache.tags.total_refs 1195829 # Total number of references to valid blocks. 1946system.cpu1.l2cache.tags.sampled_refs 195022 # Sample count of references to valid blocks. 1947system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks. 1948system.cpu1.l2cache.tags.warmup_cycle 2581358397500 # Cycle when the warmup percentage was hit. 1949system.cpu1.l2cache.tags.occ_blocks::writebacks 4477.438103 # Average occupied blocks per requestor 1950system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.594175 # Average occupied blocks per requestor 1951system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.081575 # Average occupied blocks per requestor 1952system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2724.649779 # Average occupied blocks per requestor 1953system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8398.546154 # Average occupied blocks per requestor 1954system.cpu1.l2cache.tags.occ_percent::writebacks 0.273281 # Average percentage of cache occupancy 1955system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001379 # Average percentage of cache occupancy 1956system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000066 # Average percentage of cache occupancy 1957system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.166299 # Average percentage of cache occupancy 1958system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.512607 # Average percentage of cache occupancy 1959system.cpu1.l2cache.tags.occ_percent::total 0.953632 # Average percentage of cache occupancy 1960system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9457 # Occupied blocks per task id 1961system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1962system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5975 # Occupied blocks per task id 1963system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2071 # Occupied blocks per task id 1964system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1611 # Occupied blocks per task id 1965system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5775 # Occupied blocks per task id 1966system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id 1967system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1968system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2329 # Occupied blocks per task id 1969system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 929 # Occupied blocks per task id 1970system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2717 # Occupied blocks per task id 1971system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.577209 # Percentage of cache occupancy per task id 1972system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 1973system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364685 # Percentage of cache occupancy per task id 1974system.cpu1.l2cache.tags.tag_accesses 23391503 # Number of tag accesses 1975system.cpu1.l2cache.tags.data_accesses 23391503 # Number of data accesses 1976system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29831 # number of ReadReq hits 1977system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7391 # number of ReadReq hits 1978system.cpu1.l2cache.ReadReq_hits::cpu1.inst 925413 # number of ReadReq hits 1979system.cpu1.l2cache.ReadReq_hits::total 962635 # number of ReadReq hits 1980system.cpu1.l2cache.Writeback_hits::writebacks 242023 # number of Writeback hits 1981system.cpu1.l2cache.Writeback_hits::total 242023 # number of Writeback hits 1982system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits 1983system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits 1984system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1118 # number of SCUpgradeReq hits 1985system.cpu1.l2cache.SCUpgradeReq_hits::total 1118 # number of SCUpgradeReq hits 1986system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112181 # number of ReadExReq hits 1987system.cpu1.l2cache.ReadExReq_hits::total 112181 # number of ReadExReq hits 1988system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29831 # number of demand (read+write) hits 1989system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7391 # number of demand (read+write) hits 1990system.cpu1.l2cache.demand_hits::cpu1.inst 1037594 # number of demand (read+write) hits 1991system.cpu1.l2cache.demand_hits::total 1074816 # number of demand (read+write) hits 1992system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29831 # number of overall hits 1993system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7391 # number of overall hits 1994system.cpu1.l2cache.overall_hits::cpu1.inst 1037594 # number of overall hits 1995system.cpu1.l2cache.overall_hits::total 1074816 # number of overall hits 1996system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 484 # number of ReadReq misses 1997system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 144 # number of ReadReq misses 1998system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61489 # number of ReadReq misses 1999system.cpu1.l2cache.ReadReq_misses::total 62117 # number of ReadReq misses 2000system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18553 # number of UpgradeReq misses 2001system.cpu1.l2cache.UpgradeReq_misses::total 18553 # number of UpgradeReq misses 2002system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12524 # number of SCUpgradeReq misses 2003system.cpu1.l2cache.SCUpgradeReq_misses::total 12524 # number of SCUpgradeReq misses 2004system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses 2005system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 2006system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 24216 # number of ReadExReq misses 2007system.cpu1.l2cache.ReadExReq_misses::total 24216 # number of ReadExReq misses 2008system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 484 # number of demand (read+write) misses 2009system.cpu1.l2cache.demand_misses::cpu1.itb.walker 144 # number of demand (read+write) misses 2010system.cpu1.l2cache.demand_misses::cpu1.inst 85705 # number of demand (read+write) misses 2011system.cpu1.l2cache.demand_misses::total 86333 # number of demand (read+write) misses 2012system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 484 # number of overall misses 2013system.cpu1.l2cache.overall_misses::cpu1.itb.walker 144 # number of overall misses 2014system.cpu1.l2cache.overall_misses::cpu1.inst 85705 # number of overall misses 2015system.cpu1.l2cache.overall_misses::total 86333 # number of overall misses 2016system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10993750 # number of ReadReq miss cycles 2017system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3129500 # number of ReadReq miss cycles 2018system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1532483424 # number of ReadReq miss cycles 2019system.cpu1.l2cache.ReadReq_miss_latency::total 1546606674 # number of ReadReq miss cycles 2020system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 310148223 # number of UpgradeReq miss cycles 2021system.cpu1.l2cache.UpgradeReq_miss_latency::total 310148223 # number of UpgradeReq miss cycles 2022system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 250854673 # number of SCUpgradeReq miss cycles 2023system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 250854673 # number of SCUpgradeReq miss cycles 2024system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 743500 # number of SCUpgradeFailReq miss cycles 2025system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 743500 # number of SCUpgradeFailReq miss cycles 2026system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1014040211 # number of ReadExReq miss cycles 2027system.cpu1.l2cache.ReadExReq_miss_latency::total 1014040211 # number of ReadExReq miss cycles 2028system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10993750 # number of demand (read+write) miss cycles 2029system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3129500 # number of demand (read+write) miss cycles 2030system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2546523635 # number of demand (read+write) miss cycles 2031system.cpu1.l2cache.demand_miss_latency::total 2560646885 # number of demand (read+write) miss cycles 2032system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10993750 # number of overall miss cycles 2033system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3129500 # number of overall miss cycles 2034system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2546523635 # number of overall miss cycles 2035system.cpu1.l2cache.overall_miss_latency::total 2560646885 # number of overall miss cycles 2036system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30315 # number of ReadReq accesses(hits+misses) 2037system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7535 # number of ReadReq accesses(hits+misses) 2038system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 986902 # number of ReadReq accesses(hits+misses) 2039system.cpu1.l2cache.ReadReq_accesses::total 1024752 # number of ReadReq accesses(hits+misses) 2040system.cpu1.l2cache.Writeback_accesses::writebacks 242023 # number of Writeback accesses(hits+misses) 2041system.cpu1.l2cache.Writeback_accesses::total 242023 # number of Writeback accesses(hits+misses) 2042system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20363 # number of UpgradeReq accesses(hits+misses) 2043system.cpu1.l2cache.UpgradeReq_accesses::total 20363 # number of UpgradeReq accesses(hits+misses) 2044system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13642 # number of SCUpgradeReq accesses(hits+misses) 2045system.cpu1.l2cache.SCUpgradeReq_accesses::total 13642 # number of SCUpgradeReq accesses(hits+misses) 2046system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) 2047system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2048system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136397 # number of ReadExReq accesses(hits+misses) 2049system.cpu1.l2cache.ReadExReq_accesses::total 136397 # number of ReadExReq accesses(hits+misses) 2050system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30315 # number of demand (read+write) accesses 2051system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7535 # number of demand (read+write) accesses 2052system.cpu1.l2cache.demand_accesses::cpu1.inst 1123299 # number of demand (read+write) accesses 2053system.cpu1.l2cache.demand_accesses::total 1161149 # number of demand (read+write) accesses 2054system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30315 # number of overall (read+write) accesses 2055system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7535 # number of overall (read+write) accesses 2056system.cpu1.l2cache.overall_accesses::cpu1.inst 1123299 # number of overall (read+write) accesses 2057system.cpu1.l2cache.overall_accesses::total 1161149 # number of overall (read+write) accesses 2058system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for ReadReq accesses 2059system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019111 # miss rate for ReadReq accesses 2060system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062305 # miss rate for ReadReq accesses 2061system.cpu1.l2cache.ReadReq_miss_rate::total 0.060617 # miss rate for ReadReq accesses 2062system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.911113 # miss rate for UpgradeReq accesses 2063system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.911113 # miss rate for UpgradeReq accesses 2064system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.918047 # miss rate for SCUpgradeReq accesses 2065system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.918047 # miss rate for SCUpgradeReq accesses 2066system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses 2067system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2068system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.177541 # miss rate for ReadExReq accesses 2069system.cpu1.l2cache.ReadExReq_miss_rate::total 0.177541 # miss rate for ReadExReq accesses 2070system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for demand accesses 2071system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019111 # miss rate for demand accesses 2072system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076298 # miss rate for demand accesses 2073system.cpu1.l2cache.demand_miss_rate::total 0.074351 # miss rate for demand accesses 2074system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for overall accesses 2075system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019111 # miss rate for overall accesses 2076system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076298 # miss rate for overall accesses 2077system.cpu1.l2cache.overall_miss_rate::total 0.074351 # miss rate for overall accesses 2078system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average ReadReq miss latency 2079system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21732.638889 # average ReadReq miss latency 2080system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24922.887411 # average ReadReq miss latency 2081system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24898.283465 # average ReadReq miss latency 2082system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16716.877217 # average UpgradeReq miss latency 2083system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16716.877217 # average UpgradeReq miss latency 2084system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20029.916401 # average SCUpgradeReq miss latency 2085system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20029.916401 # average SCUpgradeReq miss latency 2086system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 743500 # average SCUpgradeFailReq miss latency 2087system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743500 # average SCUpgradeFailReq miss latency 2088system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41874.802238 # average ReadExReq miss latency 2089system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41874.802238 # average ReadExReq miss latency 2090system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency 2091system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency 2092system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency 2093system.cpu1.l2cache.demand_avg_miss_latency::total 29660.117047 # average overall miss latency 2094system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency 2095system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency 2096system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency 2097system.cpu1.l2cache.overall_avg_miss_latency::total 29660.117047 # average overall miss latency 2098system.cpu1.l2cache.blocked_cycles::no_mshrs 2162 # number of cycles access was blocked 2099system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2100system.cpu1.l2cache.blocked::no_mshrs 53 # number of cycles access was blocked 2101system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2102system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 40.792453 # average number of cycles each access was blocked 2103system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2104system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2105system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2106system.cpu1.l2cache.writebacks::writebacks 100121 # number of writebacks 2107system.cpu1.l2cache.writebacks::total 100121 # number of writebacks 2108system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3717 # number of ReadReq MSHR hits 2109system.cpu1.l2cache.ReadReq_mshr_hits::total 3717 # number of ReadReq MSHR hits 2110system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1346 # number of ReadExReq MSHR hits 2111system.cpu1.l2cache.ReadExReq_mshr_hits::total 1346 # number of ReadExReq MSHR hits 2112system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5063 # number of demand (read+write) MSHR hits 2113system.cpu1.l2cache.demand_mshr_hits::total 5063 # number of demand (read+write) MSHR hits 2114system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5063 # number of overall MSHR hits 2115system.cpu1.l2cache.overall_mshr_hits::total 5063 # number of overall MSHR hits 2116system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 484 # number of ReadReq MSHR misses 2117system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 144 # number of ReadReq MSHR misses 2118system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57772 # number of ReadReq MSHR misses 2119system.cpu1.l2cache.ReadReq_mshr_misses::total 58400 # number of ReadReq MSHR misses 2120system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of HardPFReq MSHR misses 2121system.cpu1.l2cache.HardPFReq_mshr_misses::total 196422 # number of HardPFReq MSHR misses 2122system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18553 # number of UpgradeReq MSHR misses 2123system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18553 # number of UpgradeReq MSHR misses 2124system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12524 # number of SCUpgradeReq MSHR misses 2125system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12524 # number of SCUpgradeReq MSHR misses 2126system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses 2127system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2128system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22870 # number of ReadExReq MSHR misses 2129system.cpu1.l2cache.ReadExReq_mshr_misses::total 22870 # number of ReadExReq MSHR misses 2130system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 484 # number of demand (read+write) MSHR misses 2131system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 144 # number of demand (read+write) MSHR misses 2132system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80642 # number of demand (read+write) MSHR misses 2133system.cpu1.l2cache.demand_mshr_misses::total 81270 # number of demand (read+write) MSHR misses 2134system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 484 # number of overall MSHR misses 2135system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 144 # number of overall MSHR misses 2136system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80642 # number of overall MSHR misses 2137system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of overall MSHR misses 2138system.cpu1.l2cache.overall_mshr_misses::total 277692 # number of overall MSHR misses 2139system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of ReadReq MSHR miss cycles 2140system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2121500 # number of ReadReq MSHR miss cycles 2141system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1060116241 # number of ReadReq MSHR miss cycles 2142system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1069841991 # number of ReadReq MSHR miss cycles 2143system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of HardPFReq MSHR miss cycles 2144system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10135528743 # number of HardPFReq MSHR miss cycles 2145system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 305752523 # number of UpgradeReq MSHR miss cycles 2146system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 305752523 # number of UpgradeReq MSHR miss cycles 2147system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178428901 # number of SCUpgradeReq MSHR miss cycles 2148system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178428901 # number of SCUpgradeReq MSHR miss cycles 2149system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 582500 # number of SCUpgradeFailReq MSHR miss cycles 2150system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 582500 # number of SCUpgradeFailReq MSHR miss cycles 2151system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 637234022 # number of ReadExReq MSHR miss cycles 2152system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 637234022 # number of ReadExReq MSHR miss cycles 2153system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of demand (read+write) MSHR miss cycles 2154system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2121500 # number of demand (read+write) MSHR miss cycles 2155system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1697350263 # number of demand (read+write) MSHR miss cycles 2156system.cpu1.l2cache.demand_mshr_miss_latency::total 1707076013 # number of demand (read+write) MSHR miss cycles 2157system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of overall MSHR miss cycles 2158system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2121500 # number of overall MSHR miss cycles 2159system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1697350263 # number of overall MSHR miss cycles 2160system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of overall MSHR miss cycles 2161system.cpu1.l2cache.overall_mshr_miss_latency::total 11842604756 # number of overall MSHR miss cycles 2162system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174928342748 # number of ReadReq MSHR uncacheable cycles 2163system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174928342748 # number of ReadReq MSHR uncacheable cycles 2164system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797063287 # number of WriteReq MSHR uncacheable cycles 2165system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797063287 # number of WriteReq MSHR uncacheable cycles 2166system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203725406035 # number of overall MSHR uncacheable cycles 2167system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203725406035 # number of overall MSHR uncacheable cycles 2168system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for ReadReq accesses 2169system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for ReadReq accesses 2170system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058539 # mshr miss rate for ReadReq accesses 2171system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.056989 # mshr miss rate for ReadReq accesses 2172system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2173system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2174system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.911113 # mshr miss rate for UpgradeReq accesses 2175system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.911113 # mshr miss rate for UpgradeReq accesses 2176system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.918047 # mshr miss rate for SCUpgradeReq accesses 2177system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.918047 # mshr miss rate for SCUpgradeReq accesses 2178system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 2179system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2180system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.167672 # mshr miss rate for ReadExReq accesses 2181system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.167672 # mshr miss rate for ReadExReq accesses 2182system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for demand accesses 2183system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for demand accesses 2184system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for demand accesses 2185system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069991 # mshr miss rate for demand accesses 2186system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for overall accesses 2187system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for overall accesses 2188system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for overall accesses 2189system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2190system.cpu1.l2cache.overall_mshr_miss_rate::total 0.239153 # mshr miss rate for overall accesses 2191system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average ReadReq mshr miss latency 2192system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average ReadReq mshr miss latency 2193system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18350.000710 # average ReadReq mshr miss latency 2194system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18319.212175 # average ReadReq mshr miss latency 2195system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average HardPFReq mshr miss latency 2196system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51600.781700 # average HardPFReq mshr miss latency 2197system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16479.950574 # average UpgradeReq mshr miss latency 2198system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16479.950574 # average UpgradeReq mshr miss latency 2199system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14246.957921 # average SCUpgradeReq mshr miss latency 2200system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14246.957921 # average SCUpgradeReq mshr miss latency 2201system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 582500 # average SCUpgradeFailReq mshr miss latency 2202system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 582500 # average SCUpgradeFailReq mshr miss latency 2203system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27863.315348 # average ReadExReq mshr miss latency 2204system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27863.315348 # average ReadExReq mshr miss latency 2205system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency 2206system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency 2207system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency 2208system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21004.995853 # average overall mshr miss latency 2209system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency 2210system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency 2211system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency 2212system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average overall mshr miss latency 2213system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42646.546375 # average overall mshr miss latency 2214system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2215system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2216system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2217system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2218system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2219system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2220system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2221system.cpu1.dcache.tags.replacements 322636 # number of replacements 2222system.cpu1.dcache.tags.tagsinuse 491.144142 # Cycle average of tags in use 2223system.cpu1.dcache.tags.total_refs 11399665 # Total number of references to valid blocks. 2224system.cpu1.dcache.tags.sampled_refs 322979 # Sample count of references to valid blocks. 2225system.cpu1.dcache.tags.avg_refs 35.295375 # Average number of references to valid blocks. 2226system.cpu1.dcache.tags.warmup_cycle 72461169500 # Cycle when the warmup percentage was hit. 2227system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.144142 # Average occupied blocks per requestor 2228system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959266 # Average percentage of cache occupancy 2229system.cpu1.dcache.tags.occ_percent::total 0.959266 # Average percentage of cache occupancy 2230system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 2231system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 2232system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 2233system.cpu1.dcache.tags.tag_accesses 24160845 # Number of tag accesses 2234system.cpu1.dcache.tags.data_accesses 24160845 # Number of data accesses 2235system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375348 # number of ReadReq hits 2236system.cpu1.dcache.ReadReq_hits::total 6375348 # number of ReadReq hits 2237system.cpu1.dcache.WriteReq_hits::cpu1.inst 4820943 # number of WriteReq hits 2238system.cpu1.dcache.WriteReq_hits::total 4820943 # number of WriteReq hits 2239system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83445 # number of LoadLockedReq hits 2240system.cpu1.dcache.LoadLockedReq_hits::total 83445 # number of LoadLockedReq hits 2241system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81578 # number of StoreCondReq hits 2242system.cpu1.dcache.StoreCondReq_hits::total 81578 # number of StoreCondReq hits 2243system.cpu1.dcache.demand_hits::cpu1.inst 11196291 # number of demand (read+write) hits 2244system.cpu1.dcache.demand_hits::total 11196291 # number of demand (read+write) hits 2245system.cpu1.dcache.overall_hits::cpu1.inst 11196291 # number of overall hits 2246system.cpu1.dcache.overall_hits::total 11196291 # number of overall hits 2247system.cpu1.dcache.ReadReq_misses::cpu1.inst 234523 # number of ReadReq misses 2248system.cpu1.dcache.ReadReq_misses::total 234523 # number of ReadReq misses 2249system.cpu1.dcache.WriteReq_misses::cpu1.inst 286003 # number of WriteReq misses 2250system.cpu1.dcache.WriteReq_misses::total 286003 # number of WriteReq misses 2251system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11843 # number of LoadLockedReq misses 2252system.cpu1.dcache.LoadLockedReq_misses::total 11843 # number of LoadLockedReq misses 2253system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13643 # number of StoreCondReq misses 2254system.cpu1.dcache.StoreCondReq_misses::total 13643 # number of StoreCondReq misses 2255system.cpu1.dcache.demand_misses::cpu1.inst 520526 # number of demand (read+write) misses 2256system.cpu1.dcache.demand_misses::total 520526 # number of demand (read+write) misses 2257system.cpu1.dcache.overall_misses::cpu1.inst 520526 # number of overall misses 2258system.cpu1.dcache.overall_misses::total 520526 # number of overall misses 2259system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3079569141 # number of ReadReq miss cycles 2260system.cpu1.dcache.ReadReq_miss_latency::total 3079569141 # number of ReadReq miss cycles 2261system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4582527620 # number of WriteReq miss cycles 2262system.cpu1.dcache.WriteReq_miss_latency::total 4582527620 # number of WriteReq miss cycles 2263system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 211610249 # number of LoadLockedReq miss cycles 2264system.cpu1.dcache.LoadLockedReq_miss_latency::total 211610249 # number of LoadLockedReq miss cycles 2265system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314496917 # number of StoreCondReq miss cycles 2266system.cpu1.dcache.StoreCondReq_miss_latency::total 314496917 # number of StoreCondReq miss cycles 2267system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 813000 # number of StoreCondFailReq miss cycles 2268system.cpu1.dcache.StoreCondFailReq_miss_latency::total 813000 # number of StoreCondFailReq miss cycles 2269system.cpu1.dcache.demand_miss_latency::cpu1.inst 7662096761 # number of demand (read+write) miss cycles 2270system.cpu1.dcache.demand_miss_latency::total 7662096761 # number of demand (read+write) miss cycles 2271system.cpu1.dcache.overall_miss_latency::cpu1.inst 7662096761 # number of overall miss cycles 2272system.cpu1.dcache.overall_miss_latency::total 7662096761 # number of overall miss cycles 2273system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6609871 # number of ReadReq accesses(hits+misses) 2274system.cpu1.dcache.ReadReq_accesses::total 6609871 # number of ReadReq accesses(hits+misses) 2275system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5106946 # number of WriteReq accesses(hits+misses) 2276system.cpu1.dcache.WriteReq_accesses::total 5106946 # number of WriteReq accesses(hits+misses) 2277system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95288 # number of LoadLockedReq accesses(hits+misses) 2278system.cpu1.dcache.LoadLockedReq_accesses::total 95288 # number of LoadLockedReq accesses(hits+misses) 2279system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95221 # number of StoreCondReq accesses(hits+misses) 2280system.cpu1.dcache.StoreCondReq_accesses::total 95221 # number of StoreCondReq accesses(hits+misses) 2281system.cpu1.dcache.demand_accesses::cpu1.inst 11716817 # number of demand (read+write) accesses 2282system.cpu1.dcache.demand_accesses::total 11716817 # number of demand (read+write) accesses 2283system.cpu1.dcache.overall_accesses::cpu1.inst 11716817 # number of overall (read+write) accesses 2284system.cpu1.dcache.overall_accesses::total 11716817 # number of overall (read+write) accesses 2285system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035481 # miss rate for ReadReq accesses 2286system.cpu1.dcache.ReadReq_miss_rate::total 0.035481 # miss rate for ReadReq accesses 2287system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056003 # miss rate for WriteReq accesses 2288system.cpu1.dcache.WriteReq_miss_rate::total 0.056003 # miss rate for WriteReq accesses 2289system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.124286 # miss rate for LoadLockedReq accesses 2290system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124286 # miss rate for LoadLockedReq accesses 2291system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143277 # miss rate for StoreCondReq accesses 2292system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143277 # miss rate for StoreCondReq accesses 2293system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044426 # miss rate for demand accesses 2294system.cpu1.dcache.demand_miss_rate::total 0.044426 # miss rate for demand accesses 2295system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044426 # miss rate for overall accesses 2296system.cpu1.dcache.overall_miss_rate::total 0.044426 # miss rate for overall accesses 2297system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13131.203085 # average ReadReq miss latency 2298system.cpu1.dcache.ReadReq_avg_miss_latency::total 13131.203085 # average ReadReq miss latency 2299system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16022.655776 # average WriteReq miss latency 2300system.cpu1.dcache.WriteReq_avg_miss_latency::total 16022.655776 # average WriteReq miss latency 2301system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17867.959892 # average LoadLockedReq miss latency 2302system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17867.959892 # average LoadLockedReq miss latency 2303system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23051.888661 # average StoreCondReq miss latency 2304system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23051.888661 # average StoreCondReq miss latency 2305system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 2306system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2307system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency 2308system.cpu1.dcache.demand_avg_miss_latency::total 14719.911707 # average overall miss latency 2309system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency 2310system.cpu1.dcache.overall_avg_miss_latency::total 14719.911707 # average overall miss latency 2311system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2312system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2313system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2314system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2315system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2316system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2317system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2318system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2319system.cpu1.dcache.writebacks::writebacks 242023 # number of writebacks 2320system.cpu1.dcache.writebacks::total 242023 # number of writebacks 2321system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36547 # number of ReadReq MSHR hits 2322system.cpu1.dcache.ReadReq_mshr_hits::total 36547 # number of ReadReq MSHR hits 2323system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129246 # number of WriteReq MSHR hits 2324system.cpu1.dcache.WriteReq_mshr_hits::total 129246 # number of WriteReq MSHR hits 2325system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 45 # number of LoadLockedReq MSHR hits 2326system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits 2327system.cpu1.dcache.demand_mshr_hits::cpu1.inst 165793 # number of demand (read+write) MSHR hits 2328system.cpu1.dcache.demand_mshr_hits::total 165793 # number of demand (read+write) MSHR hits 2329system.cpu1.dcache.overall_mshr_hits::cpu1.inst 165793 # number of overall MSHR hits 2330system.cpu1.dcache.overall_mshr_hits::total 165793 # number of overall MSHR hits 2331system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 197976 # number of ReadReq MSHR misses 2332system.cpu1.dcache.ReadReq_mshr_misses::total 197976 # number of ReadReq MSHR misses 2333system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156757 # number of WriteReq MSHR misses 2334system.cpu1.dcache.WriteReq_mshr_misses::total 156757 # number of WriteReq MSHR misses 2335system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11798 # number of LoadLockedReq MSHR misses 2336system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11798 # number of LoadLockedReq MSHR misses 2337system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13643 # number of StoreCondReq MSHR misses 2338system.cpu1.dcache.StoreCondReq_mshr_misses::total 13643 # number of StoreCondReq MSHR misses 2339system.cpu1.dcache.demand_mshr_misses::cpu1.inst 354733 # number of demand (read+write) MSHR misses 2340system.cpu1.dcache.demand_mshr_misses::total 354733 # number of demand (read+write) MSHR misses 2341system.cpu1.dcache.overall_mshr_misses::cpu1.inst 354733 # number of overall MSHR misses 2342system.cpu1.dcache.overall_mshr_misses::total 354733 # number of overall MSHR misses 2343system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204262298 # number of ReadReq MSHR miss cycles 2344system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204262298 # number of ReadReq MSHR miss cycles 2345system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2289972148 # number of WriteReq MSHR miss cycles 2346system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2289972148 # number of WriteReq MSHR miss cycles 2347system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 187457749 # number of LoadLockedReq MSHR miss cycles 2348system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 187457749 # number of LoadLockedReq MSHR miss cycles 2349system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286173083 # number of StoreCondReq MSHR miss cycles 2350system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286173083 # number of StoreCondReq MSHR miss cycles 2351system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 767000 # number of StoreCondFailReq MSHR miss cycles 2352system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 767000 # number of StoreCondFailReq MSHR miss cycles 2353system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4494234446 # number of demand (read+write) MSHR miss cycles 2354system.cpu1.dcache.demand_mshr_miss_latency::total 4494234446 # number of demand (read+write) MSHR miss cycles 2355system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4494234446 # number of overall MSHR miss cycles 2356system.cpu1.dcache.overall_mshr_miss_latency::total 4494234446 # number of overall MSHR miss cycles 2357system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183748244745 # number of ReadReq MSHR uncacheable cycles 2358system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183748244745 # number of ReadReq MSHR uncacheable cycles 2359system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481816713 # number of WriteReq MSHR uncacheable cycles 2360system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481816713 # number of WriteReq MSHR uncacheable cycles 2361system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218230061458 # number of overall MSHR uncacheable cycles 2362system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218230061458 # number of overall MSHR uncacheable cycles 2363system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029952 # mshr miss rate for ReadReq accesses 2364system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029952 # mshr miss rate for ReadReq accesses 2365system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030695 # mshr miss rate for WriteReq accesses 2366system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030695 # mshr miss rate for WriteReq accesses 2367system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.123814 # mshr miss rate for LoadLockedReq accesses 2368system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123814 # mshr miss rate for LoadLockedReq accesses 2369system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143277 # mshr miss rate for StoreCondReq accesses 2370system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143277 # mshr miss rate for StoreCondReq accesses 2371system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for demand accesses 2372system.cpu1.dcache.demand_mshr_miss_rate::total 0.030276 # mshr miss rate for demand accesses 2373system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for overall accesses 2374system.cpu1.dcache.overall_mshr_miss_rate::total 0.030276 # mshr miss rate for overall accesses 2375system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11133.987443 # average ReadReq mshr miss latency 2376system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11133.987443 # average ReadReq mshr miss latency 2377system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14608.420345 # average WriteReq mshr miss latency 2378system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14608.420345 # average WriteReq mshr miss latency 2379system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 15888.942956 # average LoadLockedReq mshr miss latency 2380system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15888.942956 # average LoadLockedReq mshr miss latency 2381system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20975.817855 # average StoreCondReq mshr miss latency 2382system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20975.817855 # average StoreCondReq mshr miss latency 2383system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 2384system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2385system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency 2386system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency 2387system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency 2388system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency 2389system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2390system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2391system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2392system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2393system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2394system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2395system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2396system.iocache.tags.replacements 0 # number of replacements 2397system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 2398system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2399system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2400system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2401system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2402system.iocache.tags.tag_accesses 0 # Number of tag accesses 2403system.iocache.tags.data_accesses 0 # Number of data accesses 2404system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2405system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2406system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2407system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2408system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2409system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2410system.iocache.fast_writes 0 # number of fast writes performed 2411system.iocache.cache_copies 0 # number of cache copies performed 2412system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles 2413system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles 2414system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles 2415system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles 2416system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2417system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2418system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2419system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2420system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2421 2422---------- End Simulation Statistics ---------- 2423