stats.txt revision 10261:dc198e224a85
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.146775 # Number of seconds simulated 4sim_ticks 1146774863500 # Number of ticks simulated 5final_tick 1146774863500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 52366 # Simulator instruction rate (inst/s) 8host_op_rate 67406 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 970268509 # Simulator tick rate (ticks/s) 10host_mem_usage 448492 # Number of bytes of host memory used 11host_seconds 1181.92 # Real time elapsed on the host 12sim_insts 61892059 # Number of instructions simulated 13sim_ops 79667620 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 2560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7022076 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 3606712 # Number of bytes read from this memory 22system.physmem.bytes_read::total 60963700 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 763904 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 275840 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 1039744 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4294592 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7321936 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 40 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 109794 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.inst 56383 # Number of read requests responded to by this memory 36system.physmem.num_reads::total 6457684 # Number of read requests responded to by this memory 37system.physmem.num_writes::writebacks 67103 # Number of write requests responded to by this memory 38system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory 39system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory 40system.physmem.num_writes::total 823939 # Number of write requests responded to by this memory 41system.physmem.bw_read::realview.clcd 43889738 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu0.dtb.walker 2232 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.inst 6123326 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu1.dtb.walker 502 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu1.inst 3145092 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::total 53161001 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_inst_read::cpu0.inst 666132 # Instruction read bandwidth from this memory (bytes/s) 49system.physmem.bw_inst_read::cpu1.inst 240535 # Instruction read bandwidth from this memory (bytes/s) 50system.physmem.bw_inst_read::total 906668 # Instruction read bandwidth from this memory (bytes/s) 51system.physmem.bw_write::writebacks 3744930 # Write bandwidth from this memory (bytes/s) 52system.physmem.bw_write::cpu0.inst 14824 # Write bandwidth from this memory (bytes/s) 53system.physmem.bw_write::cpu1.inst 2625052 # Write bandwidth from this memory (bytes/s) 54system.physmem.bw_write::total 6384807 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_total::writebacks 3744930 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::realview.clcd 43889738 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.bw_total::cpu0.dtb.walker 2232 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu0.inst 6138150 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu1.dtb.walker 502 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu1.inst 5770144 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::total 59545808 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.readReqs 6457684 # Number of read requests accepted 64system.physmem.writeReqs 823939 # Number of write requests accepted 65system.physmem.readBursts 6457684 # Number of DRAM read bursts, including those serviced by the write queue 66system.physmem.writeBursts 823939 # Number of DRAM write bursts, including those merged in the write queue 67system.physmem.bytesReadDRAM 413268352 # Total number of bytes read from DRAM 68system.physmem.bytesReadWrQ 23424 # Total number of bytes read from write queue 69system.physmem.bytesWritten 7334336 # Total number of bytes written to DRAM 70system.physmem.bytesReadSys 60963700 # Total read bytes from the system interface side 71system.physmem.bytesWrittenSys 7321936 # Total written bytes from the system interface side 72system.physmem.servicedByWrQ 366 # Number of DRAM read bursts serviced by the write queue 73system.physmem.mergedWrBursts 709320 # Number of DRAM write bursts merged with an existing one 74system.physmem.neitherReadNorWriteReqs 12375 # Number of requests that are neither read nor write 75system.physmem.perBankRdBursts::0 403317 # Per bank write bursts 76system.physmem.perBankRdBursts::1 403674 # Per bank write bursts 77system.physmem.perBankRdBursts::2 403089 # Per bank write bursts 78system.physmem.perBankRdBursts::3 403454 # Per bank write bursts 79system.physmem.perBankRdBursts::4 406236 # Per bank write bursts 80system.physmem.perBankRdBursts::5 403730 # Per bank write bursts 81system.physmem.perBankRdBursts::6 403529 # Per bank write bursts 82system.physmem.perBankRdBursts::7 403381 # Per bank write bursts 83system.physmem.perBankRdBursts::8 403672 # Per bank write bursts 84system.physmem.perBankRdBursts::9 404158 # Per bank write bursts 85system.physmem.perBankRdBursts::10 403104 # Per bank write bursts 86system.physmem.perBankRdBursts::11 402562 # Per bank write bursts 87system.physmem.perBankRdBursts::12 403651 # Per bank write bursts 88system.physmem.perBankRdBursts::13 403575 # Per bank write bursts 89system.physmem.perBankRdBursts::14 403252 # Per bank write bursts 90system.physmem.perBankRdBursts::15 402934 # Per bank write bursts 91system.physmem.perBankWrBursts::0 7008 # Per bank write bursts 92system.physmem.perBankWrBursts::1 7418 # Per bank write bursts 93system.physmem.perBankWrBursts::2 6865 # Per bank write bursts 94system.physmem.perBankWrBursts::3 7084 # Per bank write bursts 95system.physmem.perBankWrBursts::4 7615 # Per bank write bursts 96system.physmem.perBankWrBursts::5 7300 # Per bank write bursts 97system.physmem.perBankWrBursts::6 7325 # Per bank write bursts 98system.physmem.perBankWrBursts::7 7167 # Per bank write bursts 99system.physmem.perBankWrBursts::8 7323 # Per bank write bursts 100system.physmem.perBankWrBursts::9 7753 # Per bank write bursts 101system.physmem.perBankWrBursts::10 6901 # Per bank write bursts 102system.physmem.perBankWrBursts::11 6492 # Per bank write bursts 103system.physmem.perBankWrBursts::12 7387 # Per bank write bursts 104system.physmem.perBankWrBursts::13 7157 # Per bank write bursts 105system.physmem.perBankWrBursts::14 7029 # Per bank write bursts 106system.physmem.perBankWrBursts::15 6775 # Per bank write bursts 107system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 108system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 109system.physmem.totGap 1146771945000 # Total gap between requests 110system.physmem.readPktSize::0 0 # Read request sizes (log2) 111system.physmem.readPktSize::1 0 # Read request sizes (log2) 112system.physmem.readPktSize::2 109 # Read request sizes (log2) 113system.physmem.readPktSize::3 6291456 # Read request sizes (log2) 114system.physmem.readPktSize::4 0 # Read request sizes (log2) 115system.physmem.readPktSize::5 0 # Read request sizes (log2) 116system.physmem.readPktSize::6 166119 # Read request sizes (log2) 117system.physmem.writePktSize::0 0 # Write request sizes (log2) 118system.physmem.writePktSize::1 0 # Write request sizes (log2) 119system.physmem.writePktSize::2 756836 # Write request sizes (log2) 120system.physmem.writePktSize::3 0 # Write request sizes (log2) 121system.physmem.writePktSize::4 0 # Write request sizes (log2) 122system.physmem.writePktSize::5 0 # Write request sizes (log2) 123system.physmem.writePktSize::6 67103 # Write request sizes (log2) 124system.physmem.rdQLenPdf::0 558746 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::1 398674 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::2 399850 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::3 441647 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::4 404684 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::5 430598 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::6 1121698 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::7 1089151 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::8 1417401 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::9 50859 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::10 42455 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::11 39349 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::12 37752 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::13 8359 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::14 8007 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::15 7903 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::16 180 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 156system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::15 3958 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::16 3977 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::17 6613 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::18 6665 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::19 6671 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::20 6670 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::21 6668 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::22 6668 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::23 6670 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::24 6670 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::25 6677 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::26 6672 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::27 6683 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::28 6670 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::29 6668 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::30 6670 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::32 6665 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 220system.physmem.bytesPerActivate::samples 461513 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::mean 911.356100 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::gmean 779.117173 # Bytes accessed per row activation 223system.physmem.bytesPerActivate::stdev 292.189115 # Bytes accessed per row activation 224system.physmem.bytesPerActivate::0-127 24977 5.41% 5.41% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::128-255 21582 4.68% 10.09% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::256-383 5972 1.29% 11.38% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::384-511 2646 0.57% 11.96% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::512-639 2555 0.55% 12.51% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::640-767 1574 0.34% 12.85% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::768-895 4102 0.89% 13.74% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::896-1023 979 0.21% 13.95% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::1024-1151 397126 86.05% 100.00% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::total 461513 # Bytes accessed per row activation 234system.physmem.rdPerTurnAround::samples 6665 # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::mean 968.839160 # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::stdev 26148.924018 # Reads before turning the bus around for writes 237system.physmem.rdPerTurnAround::0-65535 6658 99.89% 99.89% # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes 239system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes 240system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes 241system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 242system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::total 6665 # Reads before turning the bus around for writes 244system.physmem.wrPerTurnAround::samples 6665 # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::mean 17.194149 # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::gmean 17.165520 # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::stdev 0.984786 # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::16 2686 40.30% 40.30% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::17 20 0.30% 40.60% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::18 3941 59.13% 99.73% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::19 15 0.23% 99.95% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::total 6665 # Writes before turning the bus around for reads 254system.physmem.totQLat 165007028750 # Total ticks spent queuing 255system.physmem.totMemAccLat 286081741250 # Total ticks spent from burst creation until serviced by the DRAM 256system.physmem.totBusLat 32286590000 # Total ticks spent in databus transfers 257system.physmem.avgQLat 25553.49 # Average queueing delay per DRAM burst 258system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 259system.physmem.avgMemAccLat 44303.49 # Average memory access latency per DRAM burst 260system.physmem.avgRdBW 360.37 # Average DRAM read bandwidth in MiByte/s 261system.physmem.avgWrBW 6.40 # Average achieved write bandwidth in MiByte/s 262system.physmem.avgRdBWSys 53.16 # Average system read bandwidth in MiByte/s 263system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s 264system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 265system.physmem.busUtil 2.87 # Data bus utilization in percentage 266system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads 267system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 268system.physmem.avgRdQLen 4.16 # Average read queue length when enqueuing 269system.physmem.avgWrQLen 21.54 # Average write queue length when enqueuing 270system.physmem.readRowHits 6015984 # Number of row buffer hits during reads 271system.physmem.writeRowHits 94420 # Number of row buffer hits during writes 272system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads 273system.physmem.writeRowHitRate 82.38 # Row buffer hit rate for writes 274system.physmem.avgGap 157488.51 # Average gap between requests 275system.physmem.pageHitRate 92.98 # Row buffer hit rate, read and write combined 276system.physmem.memoryStateTime::IDLE 908124290750 # Time in different power states 277system.physmem.memoryStateTime::REF 38293320000 # Time in different power states 278system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 279system.physmem.memoryStateTime::ACT 200357121750 # Time in different power states 280system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 281system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory 282system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 283system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory 284system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory 285system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 286system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 287system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory 288system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 289system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 290system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) 291system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) 292system.realview.nvmem.bw_read::total 614 # Total read bandwidth from this memory (bytes/s) 293system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) 294system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) 295system.realview.nvmem.bw_inst_read::total 614 # Instruction read bandwidth from this memory (bytes/s) 296system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) 297system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) 298system.realview.nvmem.bw_total::total 614 # Total bandwidth to/from this memory (bytes/s) 299system.membus.throughput 61651742 # Throughput (bytes/s) 300system.membus.trans_dist::ReadReq 7506663 # Transaction distribution 301system.membus.trans_dist::ReadResp 7506663 # Transaction distribution 302system.membus.trans_dist::WriteReq 767825 # Transaction distribution 303system.membus.trans_dist::WriteResp 767825 # Transaction distribution 304system.membus.trans_dist::Writeback 67103 # Transaction distribution 305system.membus.trans_dist::UpgradeReq 33483 # Transaction distribution 306system.membus.trans_dist::SCUpgradeReq 17276 # Transaction distribution 307system.membus.trans_dist::UpgradeResp 12375 # Transaction distribution 308system.membus.trans_dist::ReadExReq 137796 # Transaction distribution 309system.membus.trans_dist::ReadExResp 137454 # Transaction distribution 310system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382664 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11280 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976707 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.l2c.mem_side::total 4371551 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count::total 16954463 # Packet count per connected master and slave (bytes) 320system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390012 # Cumulative packet size per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22560 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17953988 # Cumulative packet size per connected master and slave (bytes) 326system.membus.tot_pkt_size_system.l2c.mem_side::total 20369020 # Cumulative packet size per connected master and slave (bytes) 327system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) 328system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) 329system.membus.tot_pkt_size::total 70700668 # Cumulative packet size per connected master and slave (bytes) 330system.membus.data_through_bus 70700668 # Total data (bytes) 331system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 332system.membus.reqLayer0.occupancy 1725618000 # Layer occupancy (ticks) 333system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 334system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) 335system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 336system.membus.reqLayer2.occupancy 10203000 # Layer occupancy (ticks) 337system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 338system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 339system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 340system.membus.reqLayer5.occupancy 700000 # Layer occupancy (ticks) 341system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 342system.membus.reqLayer6.occupancy 8808401000 # Layer occupancy (ticks) 343system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) 344system.membus.respLayer1.occupancy 4909176600 # Layer occupancy (ticks) 345system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 346system.membus.respLayer2.occupancy 15579623500 # Layer occupancy (ticks) 347system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 348system.cpu_clk_domain.clock 500 # Clock period in ticks 349system.l2c.tags.replacements 73595 # number of replacements 350system.l2c.tags.tagsinuse 53913.869309 # Cycle average of tags in use 351system.l2c.tags.total_refs 2430089 # Total number of references to valid blocks. 352system.l2c.tags.sampled_refs 138750 # Sample count of references to valid blocks. 353system.l2c.tags.avg_refs 17.514155 # Average number of references to valid blocks. 354system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 355system.l2c.tags.occ_blocks::writebacks 38825.506974 # Average occupied blocks per requestor 356system.l2c.tags.occ_blocks::cpu0.dtb.walker 30.840279 # Average occupied blocks per requestor 357system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001297 # Average occupied blocks per requestor 358system.l2c.tags.occ_blocks::cpu0.inst 8944.299229 # Average occupied blocks per requestor 359system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.867460 # Average occupied blocks per requestor 360system.l2c.tags.occ_blocks::cpu1.inst 6105.354070 # Average occupied blocks per requestor 361system.l2c.tags.occ_percent::writebacks 0.592430 # Average percentage of cache occupancy 362system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000471 # Average percentage of cache occupancy 363system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 364system.l2c.tags.occ_percent::cpu0.inst 0.136479 # Average percentage of cache occupancy 365system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy 366system.l2c.tags.occ_percent::cpu1.inst 0.093160 # Average percentage of cache occupancy 367system.l2c.tags.occ_percent::total 0.822660 # Average percentage of cache occupancy 368system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 369system.l2c.tags.occ_task_id_blocks::1024 65141 # Occupied blocks per task id 370system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 371system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 372system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 373system.l2c.tags.age_task_id_blocks_1024::2 2303 # Occupied blocks per task id 374system.l2c.tags.age_task_id_blocks_1024::3 8599 # Occupied blocks per task id 375system.l2c.tags.age_task_id_blocks_1024::4 54129 # Occupied blocks per task id 376system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id 377system.l2c.tags.occ_task_id_percent::1024 0.993973 # Percentage of cache occupancy per task id 378system.l2c.tags.tag_accesses 23296068 # Number of tag accesses 379system.l2c.tags.data_accesses 23296068 # Number of data accesses 380system.l2c.ReadReq_hits::cpu0.dtb.walker 29004 # number of ReadReq hits 381system.l2c.ReadReq_hits::cpu0.itb.walker 6772 # number of ReadReq hits 382system.l2c.ReadReq_hits::cpu0.inst 959141 # number of ReadReq hits 383system.l2c.ReadReq_hits::cpu1.dtb.walker 26476 # number of ReadReq hits 384system.l2c.ReadReq_hits::cpu1.itb.walker 5085 # number of ReadReq hits 385system.l2c.ReadReq_hits::cpu1.inst 968677 # number of ReadReq hits 386system.l2c.ReadReq_hits::total 1995155 # number of ReadReq hits 387system.l2c.Writeback_hits::writebacks 576981 # number of Writeback hits 388system.l2c.Writeback_hits::total 576981 # number of Writeback hits 389system.l2c.UpgradeReq_hits::cpu0.inst 913 # number of UpgradeReq hits 390system.l2c.UpgradeReq_hits::cpu1.inst 959 # number of UpgradeReq hits 391system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits 392system.l2c.SCUpgradeReq_hits::cpu0.inst 209 # number of SCUpgradeReq hits 393system.l2c.SCUpgradeReq_hits::cpu1.inst 100 # number of SCUpgradeReq hits 394system.l2c.SCUpgradeReq_hits::total 309 # number of SCUpgradeReq hits 395system.l2c.ReadExReq_hits::cpu0.inst 58748 # number of ReadExReq hits 396system.l2c.ReadExReq_hits::cpu1.inst 50778 # number of ReadExReq hits 397system.l2c.ReadExReq_hits::total 109526 # number of ReadExReq hits 398system.l2c.demand_hits::cpu0.dtb.walker 29004 # number of demand (read+write) hits 399system.l2c.demand_hits::cpu0.itb.walker 6772 # number of demand (read+write) hits 400system.l2c.demand_hits::cpu0.inst 1017889 # number of demand (read+write) hits 401system.l2c.demand_hits::cpu1.dtb.walker 26476 # number of demand (read+write) hits 402system.l2c.demand_hits::cpu1.itb.walker 5085 # number of demand (read+write) hits 403system.l2c.demand_hits::cpu1.inst 1019455 # number of demand (read+write) hits 404system.l2c.demand_hits::total 2104681 # number of demand (read+write) hits 405system.l2c.overall_hits::cpu0.dtb.walker 29004 # number of overall hits 406system.l2c.overall_hits::cpu0.itb.walker 6772 # number of overall hits 407system.l2c.overall_hits::cpu0.inst 1017889 # number of overall hits 408system.l2c.overall_hits::cpu1.dtb.walker 26476 # number of overall hits 409system.l2c.overall_hits::cpu1.itb.walker 5085 # number of overall hits 410system.l2c.overall_hits::cpu1.inst 1019455 # number of overall hits 411system.l2c.overall_hits::total 2104681 # number of overall hits 412system.l2c.ReadReq_misses::cpu0.dtb.walker 40 # number of ReadReq misses 413system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 414system.l2c.ReadReq_misses::cpu0.inst 16374 # number of ReadReq misses 415system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses 416system.l2c.ReadReq_misses::cpu1.inst 9914 # number of ReadReq misses 417system.l2c.ReadReq_misses::total 26339 # number of ReadReq misses 418system.l2c.UpgradeReq_misses::cpu0.inst 4863 # number of UpgradeReq misses 419system.l2c.UpgradeReq_misses::cpu1.inst 4102 # number of UpgradeReq misses 420system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses 421system.l2c.SCUpgradeReq_misses::cpu0.inst 683 # number of SCUpgradeReq misses 422system.l2c.SCUpgradeReq_misses::cpu1.inst 310 # number of SCUpgradeReq misses 423system.l2c.SCUpgradeReq_misses::total 993 # number of SCUpgradeReq misses 424system.l2c.ReadExReq_misses::cpu0.inst 92483 # number of ReadExReq misses 425system.l2c.ReadExReq_misses::cpu1.inst 47388 # number of ReadExReq misses 426system.l2c.ReadExReq_misses::total 139871 # number of ReadExReq misses 427system.l2c.demand_misses::cpu0.dtb.walker 40 # number of demand (read+write) misses 428system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 429system.l2c.demand_misses::cpu0.inst 108857 # number of demand (read+write) misses 430system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses 431system.l2c.demand_misses::cpu1.inst 57302 # number of demand (read+write) misses 432system.l2c.demand_misses::total 166210 # number of demand (read+write) misses 433system.l2c.overall_misses::cpu0.dtb.walker 40 # number of overall misses 434system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 435system.l2c.overall_misses::cpu0.inst 108857 # number of overall misses 436system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses 437system.l2c.overall_misses::cpu1.inst 57302 # number of overall misses 438system.l2c.overall_misses::total 166210 # number of overall misses 439system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3039250 # number of ReadReq miss cycles 440system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 441system.l2c.ReadReq_miss_latency::cpu0.inst 1157856000 # number of ReadReq miss cycles 442system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 661250 # number of ReadReq miss cycles 443system.l2c.ReadReq_miss_latency::cpu1.inst 747415749 # number of ReadReq miss cycles 444system.l2c.ReadReq_miss_latency::total 1909121749 # number of ReadReq miss cycles 445system.l2c.UpgradeReq_miss_latency::cpu0.inst 8211643 # number of UpgradeReq miss cycles 446system.l2c.UpgradeReq_miss_latency::cpu1.inst 13589417 # number of UpgradeReq miss cycles 447system.l2c.UpgradeReq_miss_latency::total 21801060 # number of UpgradeReq miss cycles 448system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 673971 # number of SCUpgradeReq miss cycles 449system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2091409 # number of SCUpgradeReq miss cycles 450system.l2c.SCUpgradeReq_miss_latency::total 2765380 # number of SCUpgradeReq miss cycles 451system.l2c.ReadExReq_miss_latency::cpu0.inst 6321431326 # number of ReadExReq miss cycles 452system.l2c.ReadExReq_miss_latency::cpu1.inst 3362017496 # number of ReadExReq miss cycles 453system.l2c.ReadExReq_miss_latency::total 9683448822 # number of ReadExReq miss cycles 454system.l2c.demand_miss_latency::cpu0.dtb.walker 3039250 # number of demand (read+write) miss cycles 455system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 456system.l2c.demand_miss_latency::cpu0.inst 7479287326 # number of demand (read+write) miss cycles 457system.l2c.demand_miss_latency::cpu1.dtb.walker 661250 # number of demand (read+write) miss cycles 458system.l2c.demand_miss_latency::cpu1.inst 4109433245 # number of demand (read+write) miss cycles 459system.l2c.demand_miss_latency::total 11592570571 # number of demand (read+write) miss cycles 460system.l2c.overall_miss_latency::cpu0.dtb.walker 3039250 # number of overall miss cycles 461system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 462system.l2c.overall_miss_latency::cpu0.inst 7479287326 # number of overall miss cycles 463system.l2c.overall_miss_latency::cpu1.dtb.walker 661250 # number of overall miss cycles 464system.l2c.overall_miss_latency::cpu1.inst 4109433245 # number of overall miss cycles 465system.l2c.overall_miss_latency::total 11592570571 # number of overall miss cycles 466system.l2c.ReadReq_accesses::cpu0.dtb.walker 29044 # number of ReadReq accesses(hits+misses) 467system.l2c.ReadReq_accesses::cpu0.itb.walker 6774 # number of ReadReq accesses(hits+misses) 468system.l2c.ReadReq_accesses::cpu0.inst 975515 # number of ReadReq accesses(hits+misses) 469system.l2c.ReadReq_accesses::cpu1.dtb.walker 26485 # number of ReadReq accesses(hits+misses) 470system.l2c.ReadReq_accesses::cpu1.itb.walker 5085 # number of ReadReq accesses(hits+misses) 471system.l2c.ReadReq_accesses::cpu1.inst 978591 # number of ReadReq accesses(hits+misses) 472system.l2c.ReadReq_accesses::total 2021494 # number of ReadReq accesses(hits+misses) 473system.l2c.Writeback_accesses::writebacks 576981 # number of Writeback accesses(hits+misses) 474system.l2c.Writeback_accesses::total 576981 # number of Writeback accesses(hits+misses) 475system.l2c.UpgradeReq_accesses::cpu0.inst 5776 # number of UpgradeReq accesses(hits+misses) 476system.l2c.UpgradeReq_accesses::cpu1.inst 5061 # number of UpgradeReq accesses(hits+misses) 477system.l2c.UpgradeReq_accesses::total 10837 # number of UpgradeReq accesses(hits+misses) 478system.l2c.SCUpgradeReq_accesses::cpu0.inst 892 # number of SCUpgradeReq accesses(hits+misses) 479system.l2c.SCUpgradeReq_accesses::cpu1.inst 410 # number of SCUpgradeReq accesses(hits+misses) 480system.l2c.SCUpgradeReq_accesses::total 1302 # number of SCUpgradeReq accesses(hits+misses) 481system.l2c.ReadExReq_accesses::cpu0.inst 151231 # number of ReadExReq accesses(hits+misses) 482system.l2c.ReadExReq_accesses::cpu1.inst 98166 # number of ReadExReq accesses(hits+misses) 483system.l2c.ReadExReq_accesses::total 249397 # number of ReadExReq accesses(hits+misses) 484system.l2c.demand_accesses::cpu0.dtb.walker 29044 # number of demand (read+write) accesses 485system.l2c.demand_accesses::cpu0.itb.walker 6774 # number of demand (read+write) accesses 486system.l2c.demand_accesses::cpu0.inst 1126746 # number of demand (read+write) accesses 487system.l2c.demand_accesses::cpu1.dtb.walker 26485 # number of demand (read+write) accesses 488system.l2c.demand_accesses::cpu1.itb.walker 5085 # number of demand (read+write) accesses 489system.l2c.demand_accesses::cpu1.inst 1076757 # number of demand (read+write) accesses 490system.l2c.demand_accesses::total 2270891 # number of demand (read+write) accesses 491system.l2c.overall_accesses::cpu0.dtb.walker 29044 # number of overall (read+write) accesses 492system.l2c.overall_accesses::cpu0.itb.walker 6774 # number of overall (read+write) accesses 493system.l2c.overall_accesses::cpu0.inst 1126746 # number of overall (read+write) accesses 494system.l2c.overall_accesses::cpu1.dtb.walker 26485 # number of overall (read+write) accesses 495system.l2c.overall_accesses::cpu1.itb.walker 5085 # number of overall (read+write) accesses 496system.l2c.overall_accesses::cpu1.inst 1076757 # number of overall (read+write) accesses 497system.l2c.overall_accesses::total 2270891 # number of overall (read+write) accesses 498system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001377 # miss rate for ReadReq accesses 499system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000295 # miss rate for ReadReq accesses 500system.l2c.ReadReq_miss_rate::cpu0.inst 0.016785 # miss rate for ReadReq accesses 501system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000340 # miss rate for ReadReq accesses 502system.l2c.ReadReq_miss_rate::cpu1.inst 0.010131 # miss rate for ReadReq accesses 503system.l2c.ReadReq_miss_rate::total 0.013029 # miss rate for ReadReq accesses 504system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.841932 # miss rate for UpgradeReq accesses 505system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.810512 # miss rate for UpgradeReq accesses 506system.l2c.UpgradeReq_miss_rate::total 0.827258 # miss rate for UpgradeReq accesses 507system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.765695 # miss rate for SCUpgradeReq accesses 508system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.756098 # miss rate for SCUpgradeReq accesses 509system.l2c.SCUpgradeReq_miss_rate::total 0.762673 # miss rate for SCUpgradeReq accesses 510system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611535 # miss rate for ReadExReq accesses 511system.l2c.ReadExReq_miss_rate::cpu1.inst 0.482733 # miss rate for ReadExReq accesses 512system.l2c.ReadExReq_miss_rate::total 0.560837 # miss rate for ReadExReq accesses 513system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001377 # miss rate for demand accesses 514system.l2c.demand_miss_rate::cpu0.itb.walker 0.000295 # miss rate for demand accesses 515system.l2c.demand_miss_rate::cpu0.inst 0.096612 # miss rate for demand accesses 516system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000340 # miss rate for demand accesses 517system.l2c.demand_miss_rate::cpu1.inst 0.053217 # miss rate for demand accesses 518system.l2c.demand_miss_rate::total 0.073192 # miss rate for demand accesses 519system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001377 # miss rate for overall accesses 520system.l2c.overall_miss_rate::cpu0.itb.walker 0.000295 # miss rate for overall accesses 521system.l2c.overall_miss_rate::cpu0.inst 0.096612 # miss rate for overall accesses 522system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000340 # miss rate for overall accesses 523system.l2c.overall_miss_rate::cpu1.inst 0.053217 # miss rate for overall accesses 524system.l2c.overall_miss_rate::total 0.073192 # miss rate for overall accesses 525system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75981.250000 # average ReadReq miss latency 526system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 527system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70713.081715 # average ReadReq miss latency 528system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 73472.222222 # average ReadReq miss latency 529system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75389.928283 # average ReadReq miss latency 530system.l2c.ReadReq_avg_miss_latency::total 72482.696723 # average ReadReq miss latency 531system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1688.596134 # average UpgradeReq miss latency 532system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3312.875914 # average UpgradeReq miss latency 533system.l2c.UpgradeReq_avg_miss_latency::total 2431.796988 # average UpgradeReq miss latency 534system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 986.780381 # average SCUpgradeReq miss latency 535system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 6746.480645 # average SCUpgradeReq miss latency 536system.l2c.SCUpgradeReq_avg_miss_latency::total 2784.874119 # average SCUpgradeReq miss latency 537system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68352.360174 # average ReadExReq miss latency 538system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70946.600321 # average ReadExReq miss latency 539system.l2c.ReadExReq_avg_miss_latency::total 69231.283268 # average ReadExReq miss latency 540system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75981.250000 # average overall miss latency 541system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 542system.l2c.demand_avg_miss_latency::cpu0.inst 68707.454054 # average overall miss latency 543system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 73472.222222 # average overall miss latency 544system.l2c.demand_avg_miss_latency::cpu1.inst 71715.354525 # average overall miss latency 545system.l2c.demand_avg_miss_latency::total 69746.528915 # average overall miss latency 546system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75981.250000 # average overall miss latency 547system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 548system.l2c.overall_avg_miss_latency::cpu0.inst 68707.454054 # average overall miss latency 549system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 73472.222222 # average overall miss latency 550system.l2c.overall_avg_miss_latency::cpu1.inst 71715.354525 # average overall miss latency 551system.l2c.overall_avg_miss_latency::total 69746.528915 # average overall miss latency 552system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 555system.l2c.blocked::no_targets 0 # number of cycles access was blocked 556system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.l2c.fast_writes 0 # number of fast writes performed 559system.l2c.cache_copies 0 # number of cache copies performed 560system.l2c.writebacks::writebacks 67103 # number of writebacks 561system.l2c.writebacks::total 67103 # number of writebacks 562system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits 563system.l2c.ReadReq_mshr_hits::cpu1.inst 19 # number of ReadReq MSHR hits 564system.l2c.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 565system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits 566system.l2c.demand_mshr_hits::cpu1.inst 19 # number of demand (read+write) MSHR hits 567system.l2c.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 568system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits 569system.l2c.overall_mshr_hits::cpu1.inst 19 # number of overall MSHR hits 570system.l2c.overall_mshr_hits::total 68 # number of overall MSHR hits 571system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 40 # number of ReadReq MSHR misses 572system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 573system.l2c.ReadReq_mshr_misses::cpu0.inst 16325 # number of ReadReq MSHR misses 574system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses 575system.l2c.ReadReq_mshr_misses::cpu1.inst 9895 # number of ReadReq MSHR misses 576system.l2c.ReadReq_mshr_misses::total 26271 # number of ReadReq MSHR misses 577system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4863 # number of UpgradeReq MSHR misses 578system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4102 # number of UpgradeReq MSHR misses 579system.l2c.UpgradeReq_mshr_misses::total 8965 # number of UpgradeReq MSHR misses 580system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 683 # number of SCUpgradeReq MSHR misses 581system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 310 # number of SCUpgradeReq MSHR misses 582system.l2c.SCUpgradeReq_mshr_misses::total 993 # number of SCUpgradeReq MSHR misses 583system.l2c.ReadExReq_mshr_misses::cpu0.inst 92483 # number of ReadExReq MSHR misses 584system.l2c.ReadExReq_mshr_misses::cpu1.inst 47388 # number of ReadExReq MSHR misses 585system.l2c.ReadExReq_mshr_misses::total 139871 # number of ReadExReq MSHR misses 586system.l2c.demand_mshr_misses::cpu0.dtb.walker 40 # number of demand (read+write) MSHR misses 587system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 588system.l2c.demand_mshr_misses::cpu0.inst 108808 # number of demand (read+write) MSHR misses 589system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses 590system.l2c.demand_mshr_misses::cpu1.inst 57283 # number of demand (read+write) MSHR misses 591system.l2c.demand_mshr_misses::total 166142 # number of demand (read+write) MSHR misses 592system.l2c.overall_mshr_misses::cpu0.dtb.walker 40 # number of overall MSHR misses 593system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 594system.l2c.overall_mshr_misses::cpu0.inst 108808 # number of overall MSHR misses 595system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses 596system.l2c.overall_mshr_misses::cpu1.inst 57283 # number of overall MSHR misses 597system.l2c.overall_mshr_misses::total 166142 # number of overall MSHR misses 598system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2549250 # number of ReadReq MSHR miss cycles 599system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 600system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 950227250 # number of ReadReq MSHR miss cycles 601system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 549750 # number of ReadReq MSHR miss cycles 602system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 622555749 # number of ReadReq MSHR miss cycles 603system.l2c.ReadReq_mshr_miss_latency::total 1576006999 # number of ReadReq MSHR miss cycles 604system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48716838 # number of UpgradeReq MSHR miss cycles 605system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 41086590 # number of UpgradeReq MSHR miss cycles 606system.l2c.UpgradeReq_mshr_miss_latency::total 89803428 # number of UpgradeReq MSHR miss cycles 607system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6847181 # number of SCUpgradeReq MSHR miss cycles 608system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3100809 # number of SCUpgradeReq MSHR miss cycles 609system.l2c.SCUpgradeReq_mshr_miss_latency::total 9947990 # number of SCUpgradeReq MSHR miss cycles 610system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5160123162 # number of ReadExReq MSHR miss cycles 611system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2766953994 # number of ReadExReq MSHR miss cycles 612system.l2c.ReadExReq_mshr_miss_latency::total 7927077156 # number of ReadExReq MSHR miss cycles 613system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2549250 # number of demand (read+write) MSHR miss cycles 614system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 615system.l2c.demand_mshr_miss_latency::cpu0.inst 6110350412 # number of demand (read+write) MSHR miss cycles 616system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 549750 # number of demand (read+write) MSHR miss cycles 617system.l2c.demand_mshr_miss_latency::cpu1.inst 3389509743 # number of demand (read+write) MSHR miss cycles 618system.l2c.demand_mshr_miss_latency::total 9503084155 # number of demand (read+write) MSHR miss cycles 619system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2549250 # number of overall MSHR miss cycles 620system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 621system.l2c.overall_mshr_miss_latency::cpu0.inst 6110350412 # number of overall MSHR miss cycles 622system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 549750 # number of overall MSHR miss cycles 623system.l2c.overall_mshr_miss_latency::cpu1.inst 3389509743 # number of overall MSHR miss cycles 624system.l2c.overall_mshr_miss_latency::total 9503084155 # number of overall MSHR miss cycles 625system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156402291235 # number of ReadReq MSHR uncacheable cycles 626system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10978060744 # number of ReadReq MSHR uncacheable cycles 627system.l2c.ReadReq_mshr_uncacheable_latency::total 167380351979 # number of ReadReq MSHR uncacheable cycles 628system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364398990 # number of WriteReq MSHR uncacheable cycles 629system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414990793 # number of WriteReq MSHR uncacheable cycles 630system.l2c.WriteReq_mshr_uncacheable_latency::total 16779389783 # number of WriteReq MSHR uncacheable cycles 631system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157766690225 # number of overall MSHR uncacheable cycles 632system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26393051537 # number of overall MSHR uncacheable cycles 633system.l2c.overall_mshr_uncacheable_latency::total 184159741762 # number of overall MSHR uncacheable cycles 634system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001377 # mshr miss rate for ReadReq accesses 635system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000295 # mshr miss rate for ReadReq accesses 636system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016735 # mshr miss rate for ReadReq accesses 637system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000340 # mshr miss rate for ReadReq accesses 638system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010111 # mshr miss rate for ReadReq accesses 639system.l2c.ReadReq_mshr_miss_rate::total 0.012996 # mshr miss rate for ReadReq accesses 640system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.841932 # mshr miss rate for UpgradeReq accesses 641system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.810512 # mshr miss rate for UpgradeReq accesses 642system.l2c.UpgradeReq_mshr_miss_rate::total 0.827258 # mshr miss rate for UpgradeReq accesses 643system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.765695 # mshr miss rate for SCUpgradeReq accesses 644system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.756098 # mshr miss rate for SCUpgradeReq accesses 645system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.762673 # mshr miss rate for SCUpgradeReq accesses 646system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611535 # mshr miss rate for ReadExReq accesses 647system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.482733 # mshr miss rate for ReadExReq accesses 648system.l2c.ReadExReq_mshr_miss_rate::total 0.560837 # mshr miss rate for ReadExReq accesses 649system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001377 # mshr miss rate for demand accesses 650system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000295 # mshr miss rate for demand accesses 651system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096568 # mshr miss rate for demand accesses 652system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000340 # mshr miss rate for demand accesses 653system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053200 # mshr miss rate for demand accesses 654system.l2c.demand_mshr_miss_rate::total 0.073162 # mshr miss rate for demand accesses 655system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001377 # mshr miss rate for overall accesses 656system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000295 # mshr miss rate for overall accesses 657system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096568 # mshr miss rate for overall accesses 658system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000340 # mshr miss rate for overall accesses 659system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053200 # mshr miss rate for overall accesses 660system.l2c.overall_mshr_miss_rate::total 0.073162 # mshr miss rate for overall accesses 661system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average ReadReq mshr miss latency 662system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 663system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58206.875957 # average ReadReq mshr miss latency 664system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average ReadReq mshr miss latency 665system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62916.194947 # average ReadReq mshr miss latency 666system.l2c.ReadReq_avg_mshr_miss_latency::total 59990.369571 # average ReadReq mshr miss latency 667system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10017.856878 # average UpgradeReq mshr miss latency 668system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10016.233545 # average UpgradeReq mshr miss latency 669system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.114110 # average UpgradeReq mshr miss latency 670system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10025.155198 # average SCUpgradeReq mshr miss latency 671system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.609677 # average SCUpgradeReq mshr miss latency 672system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10018.116818 # average SCUpgradeReq mshr miss latency 673system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55795.369549 # average ReadExReq mshr miss latency 674system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58389.338947 # average ReadExReq mshr miss latency 675system.l2c.ReadExReq_avg_mshr_miss_latency::total 56674.200914 # average ReadExReq mshr miss latency 676system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average overall mshr miss latency 677system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 678system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56157.179729 # average overall mshr miss latency 679system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average overall mshr miss latency 680system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59171.302882 # average overall mshr miss latency 681system.l2c.demand_avg_mshr_miss_latency::total 57198.566016 # average overall mshr miss latency 682system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average overall mshr miss latency 683system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 684system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56157.179729 # average overall mshr miss latency 685system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average overall mshr miss latency 686system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59171.302882 # average overall mshr miss latency 687system.l2c.overall_avg_mshr_miss_latency::total 57198.566016 # average overall mshr miss latency 688system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 689system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 690system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 691system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 692system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 693system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 694system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 695system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 696system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 697system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 699system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 700system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 701system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 702system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 703system.cf0.dma_write_txs 0 # Number of DMA write transactions. 704system.toL2Bus.throughput 164548117 # Throughput (bytes/s) 705system.toL2Bus.trans_dist::ReadReq 3298522 # Transaction distribution 706system.toL2Bus.trans_dist::ReadResp 3298521 # Transaction distribution 707system.toL2Bus.trans_dist::WriteReq 767825 # Transaction distribution 708system.toL2Bus.trans_dist::WriteResp 767825 # Transaction distribution 709system.toL2Bus.trans_dist::Writeback 576981 # Transaction distribution 710system.toL2Bus.trans_dist::UpgradeReq 32938 # Transaction distribution 711system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution 712system.toL2Bus.trans_dist::UpgradeResp 50523 # Transaction distribution 713system.toL2Bus.trans_dist::ReadExReq 260723 # Transaction distribution 714system.toL2Bus.trans_dist::ReadExResp 260723 # Transaction distribution 715system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1574360 # Packet count per connected master and slave (bytes) 716system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3288712 # Packet count per connected master and slave (bytes) 717system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16464 # Packet count per connected master and slave (bytes) 718system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 66826 # Packet count per connected master and slave (bytes) 719system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1600801 # Packet count per connected master and slave (bytes) 720system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2571055 # Packet count per connected master and slave (bytes) 721system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13478 # Packet count per connected master and slave (bytes) 722system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62668 # Packet count per connected master and slave (bytes) 723system.toL2Bus.pkt_count::total 9194364 # Packet count per connected master and slave (bytes) 724system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 50355392 # Cumulative packet size per connected master and slave (bytes) 725system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43867388 # Cumulative packet size per connected master and slave (bytes) 726system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) 727system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 116176 # Cumulative packet size per connected master and slave (bytes) 728system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 51198592 # Cumulative packet size per connected master and slave (bytes) 729system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38125568 # Cumulative packet size per connected master and slave (bytes) 730system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20340 # Cumulative packet size per connected master and slave (bytes) 731system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 105940 # Cumulative packet size per connected master and slave (bytes) 732system.toL2Bus.tot_pkt_size::total 183816492 # Cumulative packet size per connected master and slave (bytes) 733system.toL2Bus.data_through_bus 183816492 # Total data (bytes) 734system.toL2Bus.snoop_data_through_bus 4883152 # Total snoop data (bytes) 735system.toL2Bus.reqLayer0.occupancy 5169541990 # Layer occupancy (ticks) 736system.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 737system.toL2Bus.respLayer0.occupancy 3546630183 # Layer occupancy (ticks) 738system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 739system.toL2Bus.respLayer1.occupancy 2800512724 # Layer occupancy (ticks) 740system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 741system.toL2Bus.respLayer2.occupancy 9693493 # Layer occupancy (ticks) 742system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 743system.toL2Bus.respLayer3.occupancy 37783748 # Layer occupancy (ticks) 744system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 745system.toL2Bus.respLayer6.occupancy 3604679924 # Layer occupancy (ticks) 746system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) 747system.toL2Bus.respLayer7.occupancy 1938501968 # Layer occupancy (ticks) 748system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 749system.toL2Bus.respLayer8.occupancy 8396493 # Layer occupancy (ticks) 750system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 751system.toL2Bus.respLayer9.occupancy 36187242 # Layer occupancy (ticks) 752system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 753system.iobus.throughput 45973854 # Throughput (bytes/s) 754system.iobus.trans_dist::ReadReq 7474822 # Transaction distribution 755system.iobus.trans_dist::ReadResp 7474822 # Transaction distribution 756system.iobus.trans_dist::WriteReq 7966 # Transaction distribution 757system.iobus.trans_dist::WriteResp 7966 # Transaction distribution 758system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) 759system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8050 # Packet count per connected master and slave (bytes) 760system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 761system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) 762system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 763system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 764system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes) 765system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 766system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 767system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 768system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 769system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 770system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 771system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 772system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 773system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 774system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 775system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 776system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 777system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 778system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 779system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 780system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 781system.iobus.pkt_count_system.bridge.master::total 2382664 # Packet count per connected master and slave (bytes) 782system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) 783system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) 784system.iobus.pkt_count::total 14965576 # Packet count per connected master and slave (bytes) 785system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) 786system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16100 # Cumulative packet size per connected master and slave (bytes) 787system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 788system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) 789system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 790system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 791system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes) 792system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 793system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 794system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 795system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 796system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 797system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 798system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 799system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 800system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 801system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 802system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 803system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 804system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 805system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 806system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 807system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 808system.iobus.tot_pkt_size_system.bridge.master::total 2390012 # Cumulative packet size per connected master and slave (bytes) 809system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) 810system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) 811system.iobus.tot_pkt_size::total 52721660 # Cumulative packet size per connected master and slave (bytes) 812system.iobus.data_through_bus 52721660 # Total data (bytes) 813system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) 814system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 815system.iobus.reqLayer1.occupancy 4031000 # Layer occupancy (ticks) 816system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 817system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 818system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 819system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks) 820system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 821system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 822system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 823system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 824system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 825system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks) 826system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 827system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 828system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 829system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 830system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 831system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 832system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 833system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 834system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 835system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 836system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 837system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 838system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 839system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 840system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 841system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 842system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 843system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 844system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 845system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 846system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 847system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 848system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 849system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 850system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 851system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 852system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 853system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 854system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 855system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 856system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 857system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 858system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 859system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) 860system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 861system.iobus.respLayer0.occupancy 2374698000 # Layer occupancy (ticks) 862system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) 863system.iobus.respLayer1.occupancy 15850285500 # Layer occupancy (ticks) 864system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) 865system.cpu0.branchPred.lookups 6861856 # Number of BP lookups 866system.cpu0.branchPred.condPredicted 5181081 # Number of conditional branches predicted 867system.cpu0.branchPred.condIncorrect 652173 # Number of conditional branches incorrect 868system.cpu0.branchPred.BTBLookups 4714052 # Number of BTB lookups 869system.cpu0.branchPred.BTBHits 3350352 # Number of BTB hits 870system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 871system.cpu0.branchPred.BTBHitPct 71.071596 # BTB Hit Percentage 872system.cpu0.branchPred.usedRAS 844036 # Number of times the RAS was used to get a target. 873system.cpu0.branchPred.RASInCorrect 70439 # Number of incorrect RAS predictions. 874system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 875system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 876system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 877system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 878system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 879system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 880system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 881system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 882system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 883system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 884system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 885system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 886system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 887system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 888system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 889system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 890system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 891system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 892system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 893system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 894system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 895system.cpu0.dtb.inst_hits 0 # ITB inst hits 896system.cpu0.dtb.inst_misses 0 # ITB inst misses 897system.cpu0.dtb.read_hits 8249046 # DTB read hits 898system.cpu0.dtb.read_misses 22426 # DTB read misses 899system.cpu0.dtb.write_hits 6048331 # DTB write hits 900system.cpu0.dtb.write_misses 1452 # DTB write misses 901system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 902system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 903system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 904system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 905system.cpu0.dtb.flush_entries 1952 # Number of entries that have been flushed from TLB 906system.cpu0.dtb.align_faults 1134 # Number of TLB faults due to alignment restrictions 907system.cpu0.dtb.prefetch_faults 199 # Number of TLB faults due to prefetch 908system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 909system.cpu0.dtb.perms_faults 288 # Number of TLB faults due to permissions restrictions 910system.cpu0.dtb.read_accesses 8271472 # DTB read accesses 911system.cpu0.dtb.write_accesses 6049783 # DTB write accesses 912system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 913system.cpu0.dtb.hits 14297377 # DTB hits 914system.cpu0.dtb.misses 23878 # DTB misses 915system.cpu0.dtb.accesses 14321255 # DTB accesses 916system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 917system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 918system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 919system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 920system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 921system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 922system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 923system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 924system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 925system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 926system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 927system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 928system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 929system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 930system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 931system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 932system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 933system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 934system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 935system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 936system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 937system.cpu0.itb.inst_hits 12515958 # ITB inst hits 938system.cpu0.itb.inst_misses 4886 # ITB inst misses 939system.cpu0.itb.read_hits 0 # DTB read hits 940system.cpu0.itb.read_misses 0 # DTB read misses 941system.cpu0.itb.write_hits 0 # DTB write hits 942system.cpu0.itb.write_misses 0 # DTB write misses 943system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 944system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 945system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 946system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 947system.cpu0.itb.flush_entries 1295 # Number of entries that have been flushed from TLB 948system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 949system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 950system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 951system.cpu0.itb.perms_faults 2118 # Number of TLB faults due to permissions restrictions 952system.cpu0.itb.read_accesses 0 # DTB read accesses 953system.cpu0.itb.write_accesses 0 # DTB write accesses 954system.cpu0.itb.inst_accesses 12520844 # ITB inst accesses 955system.cpu0.itb.hits 12515958 # DTB hits 956system.cpu0.itb.misses 4886 # DTB misses 957system.cpu0.itb.accesses 12520844 # DTB accesses 958system.cpu0.numCycles 433909161 # number of cpu cycles simulated 959system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 960system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 961system.cpu0.committedInsts 29915294 # Number of instructions committed 962system.cpu0.committedOps 39343022 # Number of ops (including micro ops) committed 963system.cpu0.discardedOps 1900672 # Number of ops (including micro ops) which were discarded before commit 964system.cpu0.numFetchSuspends 39481 # Number of times Execute suspended instruction fetching 965system.cpu0.quiesceCycles 1859706962 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 966system.cpu0.cpi 14.504593 # CPI: cycles per instruction 967system.cpu0.ipc 0.068944 # IPC: instructions per cycle 968system.cpu0.kern.inst.arm 0 # number of arm instructions executed 969system.cpu0.kern.inst.quiesce 50347 # number of quiesce instructions executed 970system.cpu0.tickCycles 353761855 # Number of cycles that the object actually ticked 971system.cpu0.idleCycles 80147306 # Total number of cycles that the object has spent stopped 972system.cpu0.icache.tags.replacements 784713 # number of replacements 973system.cpu0.icache.tags.tagsinuse 510.784867 # Cycle average of tags in use 974system.cpu0.icache.tags.total_refs 11728456 # Total number of references to valid blocks. 975system.cpu0.icache.tags.sampled_refs 785225 # Sample count of references to valid blocks. 976system.cpu0.icache.tags.avg_refs 14.936427 # Average number of references to valid blocks. 977system.cpu0.icache.tags.warmup_cycle 10280766000 # Cycle when the warmup percentage was hit. 978system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.784867 # Average occupied blocks per requestor 979system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997627 # Average percentage of cache occupancy 980system.cpu0.icache.tags.occ_percent::total 0.997627 # Average percentage of cache occupancy 981system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 982system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id 983system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 984system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 985system.cpu0.icache.tags.tag_accesses 13298912 # Number of tag accesses 986system.cpu0.icache.tags.data_accesses 13298912 # Number of data accesses 987system.cpu0.icache.ReadReq_hits::cpu0.inst 11728456 # number of ReadReq hits 988system.cpu0.icache.ReadReq_hits::total 11728456 # number of ReadReq hits 989system.cpu0.icache.demand_hits::cpu0.inst 11728456 # number of demand (read+write) hits 990system.cpu0.icache.demand_hits::total 11728456 # number of demand (read+write) hits 991system.cpu0.icache.overall_hits::cpu0.inst 11728456 # number of overall hits 992system.cpu0.icache.overall_hits::total 11728456 # number of overall hits 993system.cpu0.icache.ReadReq_misses::cpu0.inst 785228 # number of ReadReq misses 994system.cpu0.icache.ReadReq_misses::total 785228 # number of ReadReq misses 995system.cpu0.icache.demand_misses::cpu0.inst 785228 # number of demand (read+write) misses 996system.cpu0.icache.demand_misses::total 785228 # number of demand (read+write) misses 997system.cpu0.icache.overall_misses::cpu0.inst 785228 # number of overall misses 998system.cpu0.icache.overall_misses::total 785228 # number of overall misses 999system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10819127683 # number of ReadReq miss cycles 1000system.cpu0.icache.ReadReq_miss_latency::total 10819127683 # number of ReadReq miss cycles 1001system.cpu0.icache.demand_miss_latency::cpu0.inst 10819127683 # number of demand (read+write) miss cycles 1002system.cpu0.icache.demand_miss_latency::total 10819127683 # number of demand (read+write) miss cycles 1003system.cpu0.icache.overall_miss_latency::cpu0.inst 10819127683 # number of overall miss cycles 1004system.cpu0.icache.overall_miss_latency::total 10819127683 # number of overall miss cycles 1005system.cpu0.icache.ReadReq_accesses::cpu0.inst 12513684 # number of ReadReq accesses(hits+misses) 1006system.cpu0.icache.ReadReq_accesses::total 12513684 # number of ReadReq accesses(hits+misses) 1007system.cpu0.icache.demand_accesses::cpu0.inst 12513684 # number of demand (read+write) accesses 1008system.cpu0.icache.demand_accesses::total 12513684 # number of demand (read+write) accesses 1009system.cpu0.icache.overall_accesses::cpu0.inst 12513684 # number of overall (read+write) accesses 1010system.cpu0.icache.overall_accesses::total 12513684 # number of overall (read+write) accesses 1011system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.062750 # miss rate for ReadReq accesses 1012system.cpu0.icache.ReadReq_miss_rate::total 0.062750 # miss rate for ReadReq accesses 1013system.cpu0.icache.demand_miss_rate::cpu0.inst 0.062750 # miss rate for demand accesses 1014system.cpu0.icache.demand_miss_rate::total 0.062750 # miss rate for demand accesses 1015system.cpu0.icache.overall_miss_rate::cpu0.inst 0.062750 # miss rate for overall accesses 1016system.cpu0.icache.overall_miss_rate::total 0.062750 # miss rate for overall accesses 1017system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13778.326401 # average ReadReq miss latency 1018system.cpu0.icache.ReadReq_avg_miss_latency::total 13778.326401 # average ReadReq miss latency 1019system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13778.326401 # average overall miss latency 1020system.cpu0.icache.demand_avg_miss_latency::total 13778.326401 # average overall miss latency 1021system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13778.326401 # average overall miss latency 1022system.cpu0.icache.overall_avg_miss_latency::total 13778.326401 # average overall miss latency 1023system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1024system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1025system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1026system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1027system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1028system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1029system.cpu0.icache.fast_writes 0 # number of fast writes performed 1030system.cpu0.icache.cache_copies 0 # number of cache copies performed 1031system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 785228 # number of ReadReq MSHR misses 1032system.cpu0.icache.ReadReq_mshr_misses::total 785228 # number of ReadReq MSHR misses 1033system.cpu0.icache.demand_mshr_misses::cpu0.inst 785228 # number of demand (read+write) MSHR misses 1034system.cpu0.icache.demand_mshr_misses::total 785228 # number of demand (read+write) MSHR misses 1035system.cpu0.icache.overall_mshr_misses::cpu0.inst 785228 # number of overall MSHR misses 1036system.cpu0.icache.overall_mshr_misses::total 785228 # number of overall MSHR misses 1037system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9244507317 # number of ReadReq MSHR miss cycles 1038system.cpu0.icache.ReadReq_mshr_miss_latency::total 9244507317 # number of ReadReq MSHR miss cycles 1039system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9244507317 # number of demand (read+write) MSHR miss cycles 1040system.cpu0.icache.demand_mshr_miss_latency::total 9244507317 # number of demand (read+write) MSHR miss cycles 1041system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9244507317 # number of overall MSHR miss cycles 1042system.cpu0.icache.overall_mshr_miss_latency::total 9244507317 # number of overall MSHR miss cycles 1043system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171313500 # number of ReadReq MSHR uncacheable cycles 1044system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171313500 # number of ReadReq MSHR uncacheable cycles 1045system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171313500 # number of overall MSHR uncacheable cycles 1046system.cpu0.icache.overall_mshr_uncacheable_latency::total 171313500 # number of overall MSHR uncacheable cycles 1047system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for ReadReq accesses 1048system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.062750 # mshr miss rate for ReadReq accesses 1049system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for demand accesses 1050system.cpu0.icache.demand_mshr_miss_rate::total 0.062750 # mshr miss rate for demand accesses 1051system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for overall accesses 1052system.cpu0.icache.overall_mshr_miss_rate::total 0.062750 # mshr miss rate for overall accesses 1053system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average ReadReq mshr miss latency 1054system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11773.023016 # average ReadReq mshr miss latency 1055system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average overall mshr miss latency 1056system.cpu0.icache.demand_avg_mshr_miss_latency::total 11773.023016 # average overall mshr miss latency 1057system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average overall mshr miss latency 1058system.cpu0.icache.overall_avg_mshr_miss_latency::total 11773.023016 # average overall mshr miss latency 1059system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1060system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1061system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1062system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1063system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1064system.cpu0.dcache.tags.replacements 332522 # number of replacements 1065system.cpu0.dcache.tags.tagsinuse 495.116335 # Cycle average of tags in use 1066system.cpu0.dcache.tags.total_refs 12493941 # Total number of references to valid blocks. 1067system.cpu0.dcache.tags.sampled_refs 332889 # Sample count of references to valid blocks. 1068system.cpu0.dcache.tags.avg_refs 37.531853 # Average number of references to valid blocks. 1069system.cpu0.dcache.tags.warmup_cycle 236260250 # Cycle when the warmup percentage was hit. 1070system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.116335 # Average occupied blocks per requestor 1071system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967024 # Average percentage of cache occupancy 1072system.cpu0.dcache.tags.occ_percent::total 0.967024 # Average percentage of cache occupancy 1073system.cpu0.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id 1074system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id 1075system.cpu0.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id 1076system.cpu0.dcache.tags.tag_accesses 52581205 # Number of tag accesses 1077system.cpu0.dcache.tags.data_accesses 52581205 # Number of data accesses 1078system.cpu0.dcache.ReadReq_hits::cpu0.inst 6652234 # number of ReadReq hits 1079system.cpu0.dcache.ReadReq_hits::total 6652234 # number of ReadReq hits 1080system.cpu0.dcache.WriteReq_hits::cpu0.inst 5513247 # number of WriteReq hits 1081system.cpu0.dcache.WriteReq_hits::total 5513247 # number of WriteReq hits 1082system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152467 # number of LoadLockedReq hits 1083system.cpu0.dcache.LoadLockedReq_hits::total 152467 # number of LoadLockedReq hits 1084system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153686 # number of StoreCondReq hits 1085system.cpu0.dcache.StoreCondReq_hits::total 153686 # number of StoreCondReq hits 1086system.cpu0.dcache.demand_hits::cpu0.inst 12165481 # number of demand (read+write) hits 1087system.cpu0.dcache.demand_hits::total 12165481 # number of demand (read+write) hits 1088system.cpu0.dcache.overall_hits::cpu0.inst 12165481 # number of overall hits 1089system.cpu0.dcache.overall_hits::total 12165481 # number of overall hits 1090system.cpu0.dcache.ReadReq_misses::cpu0.inst 257861 # number of ReadReq misses 1091system.cpu0.dcache.ReadReq_misses::total 257861 # number of ReadReq misses 1092system.cpu0.dcache.WriteReq_misses::cpu0.inst 307489 # number of WriteReq misses 1093system.cpu0.dcache.WriteReq_misses::total 307489 # number of WriteReq misses 1094system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8753 # number of LoadLockedReq misses 1095system.cpu0.dcache.LoadLockedReq_misses::total 8753 # number of LoadLockedReq misses 1096system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7461 # number of StoreCondReq misses 1097system.cpu0.dcache.StoreCondReq_misses::total 7461 # number of StoreCondReq misses 1098system.cpu0.dcache.demand_misses::cpu0.inst 565350 # number of demand (read+write) misses 1099system.cpu0.dcache.demand_misses::total 565350 # number of demand (read+write) misses 1100system.cpu0.dcache.overall_misses::cpu0.inst 565350 # number of overall misses 1101system.cpu0.dcache.overall_misses::total 565350 # number of overall misses 1102system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3878128215 # number of ReadReq miss cycles 1103system.cpu0.dcache.ReadReq_miss_latency::total 3878128215 # number of ReadReq miss cycles 1104system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15135680350 # number of WriteReq miss cycles 1105system.cpu0.dcache.WriteReq_miss_latency::total 15135680350 # number of WriteReq miss cycles 1106system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89040000 # number of LoadLockedReq miss cycles 1107system.cpu0.dcache.LoadLockedReq_miss_latency::total 89040000 # number of LoadLockedReq miss cycles 1108system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47241681 # number of StoreCondReq miss cycles 1109system.cpu0.dcache.StoreCondReq_miss_latency::total 47241681 # number of StoreCondReq miss cycles 1110system.cpu0.dcache.demand_miss_latency::cpu0.inst 19013808565 # number of demand (read+write) miss cycles 1111system.cpu0.dcache.demand_miss_latency::total 19013808565 # number of demand (read+write) miss cycles 1112system.cpu0.dcache.overall_miss_latency::cpu0.inst 19013808565 # number of overall miss cycles 1113system.cpu0.dcache.overall_miss_latency::total 19013808565 # number of overall miss cycles 1114system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6910095 # number of ReadReq accesses(hits+misses) 1115system.cpu0.dcache.ReadReq_accesses::total 6910095 # number of ReadReq accesses(hits+misses) 1116system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5820736 # number of WriteReq accesses(hits+misses) 1117system.cpu0.dcache.WriteReq_accesses::total 5820736 # number of WriteReq accesses(hits+misses) 1118system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161220 # number of LoadLockedReq accesses(hits+misses) 1119system.cpu0.dcache.LoadLockedReq_accesses::total 161220 # number of LoadLockedReq accesses(hits+misses) 1120system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161147 # number of StoreCondReq accesses(hits+misses) 1121system.cpu0.dcache.StoreCondReq_accesses::total 161147 # number of StoreCondReq accesses(hits+misses) 1122system.cpu0.dcache.demand_accesses::cpu0.inst 12730831 # number of demand (read+write) accesses 1123system.cpu0.dcache.demand_accesses::total 12730831 # number of demand (read+write) accesses 1124system.cpu0.dcache.overall_accesses::cpu0.inst 12730831 # number of overall (read+write) accesses 1125system.cpu0.dcache.overall_accesses::total 12730831 # number of overall (read+write) accesses 1126system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.037317 # miss rate for ReadReq accesses 1127system.cpu0.dcache.ReadReq_miss_rate::total 0.037317 # miss rate for ReadReq accesses 1128system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.052826 # miss rate for WriteReq accesses 1129system.cpu0.dcache.WriteReq_miss_rate::total 0.052826 # miss rate for WriteReq accesses 1130system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.054292 # miss rate for LoadLockedReq accesses 1131system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054292 # miss rate for LoadLockedReq accesses 1132system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046299 # miss rate for StoreCondReq accesses 1133system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046299 # miss rate for StoreCondReq accesses 1134system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.044408 # miss rate for demand accesses 1135system.cpu0.dcache.demand_miss_rate::total 0.044408 # miss rate for demand accesses 1136system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.044408 # miss rate for overall accesses 1137system.cpu0.dcache.overall_miss_rate::total 0.044408 # miss rate for overall accesses 1138system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15039.607444 # average ReadReq miss latency 1139system.cpu0.dcache.ReadReq_avg_miss_latency::total 15039.607444 # average ReadReq miss latency 1140system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49223.485556 # average WriteReq miss latency 1141system.cpu0.dcache.WriteReq_avg_miss_latency::total 49223.485556 # average WriteReq miss latency 1142system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10172.512282 # average LoadLockedReq miss latency 1143system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10172.512282 # average LoadLockedReq miss latency 1144system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6331.816244 # average StoreCondReq miss latency 1145system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6331.816244 # average StoreCondReq miss latency 1146system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33631.924587 # average overall miss latency 1147system.cpu0.dcache.demand_avg_miss_latency::total 33631.924587 # average overall miss latency 1148system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33631.924587 # average overall miss latency 1149system.cpu0.dcache.overall_avg_miss_latency::total 33631.924587 # average overall miss latency 1150system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1151system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1152system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1153system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1154system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1155system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1156system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1157system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1158system.cpu0.dcache.writebacks::writebacks 307804 # number of writebacks 1159system.cpu0.dcache.writebacks::total 307804 # number of writebacks 1160system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 51446 # number of ReadReq MSHR hits 1161system.cpu0.dcache.ReadReq_mshr_hits::total 51446 # number of ReadReq MSHR hits 1162system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 139700 # number of WriteReq MSHR hits 1163system.cpu0.dcache.WriteReq_mshr_hits::total 139700 # number of WriteReq MSHR hits 1164system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 20 # number of LoadLockedReq MSHR hits 1165system.cpu0.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits 1166system.cpu0.dcache.demand_mshr_hits::cpu0.inst 191146 # number of demand (read+write) MSHR hits 1167system.cpu0.dcache.demand_mshr_hits::total 191146 # number of demand (read+write) MSHR hits 1168system.cpu0.dcache.overall_mshr_hits::cpu0.inst 191146 # number of overall MSHR hits 1169system.cpu0.dcache.overall_mshr_hits::total 191146 # number of overall MSHR hits 1170system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 206415 # number of ReadReq MSHR misses 1171system.cpu0.dcache.ReadReq_mshr_misses::total 206415 # number of ReadReq MSHR misses 1172system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167789 # number of WriteReq MSHR misses 1173system.cpu0.dcache.WriteReq_mshr_misses::total 167789 # number of WriteReq MSHR misses 1174system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8733 # number of LoadLockedReq MSHR misses 1175system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8733 # number of LoadLockedReq MSHR misses 1176system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7461 # number of StoreCondReq MSHR misses 1177system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses 1178system.cpu0.dcache.demand_mshr_misses::cpu0.inst 374204 # number of demand (read+write) MSHR misses 1179system.cpu0.dcache.demand_mshr_misses::total 374204 # number of demand (read+write) MSHR misses 1180system.cpu0.dcache.overall_mshr_misses::cpu0.inst 374204 # number of overall MSHR misses 1181system.cpu0.dcache.overall_mshr_misses::total 374204 # number of overall MSHR misses 1182system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2545797312 # number of ReadReq MSHR miss cycles 1183system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2545797312 # number of ReadReq MSHR miss cycles 1184system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7212492893 # number of WriteReq MSHR miss cycles 1185system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7212492893 # number of WriteReq MSHR miss cycles 1186system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71207000 # number of LoadLockedReq MSHR miss cycles 1187system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71207000 # number of LoadLockedReq MSHR miss cycles 1188system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32318319 # number of StoreCondReq MSHR miss cycles 1189system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32318319 # number of StoreCondReq MSHR miss cycles 1190system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9758290205 # number of demand (read+write) MSHR miss cycles 1191system.cpu0.dcache.demand_mshr_miss_latency::total 9758290205 # number of demand (read+write) MSHR miss cycles 1192system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9758290205 # number of overall MSHR miss cycles 1193system.cpu0.dcache.overall_mshr_miss_latency::total 9758290205 # number of overall MSHR miss cycles 1194system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170750199252 # number of ReadReq MSHR uncacheable cycles 1195system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170750199252 # number of ReadReq MSHR uncacheable cycles 1196system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513150500 # number of WriteReq MSHR uncacheable cycles 1197system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513150500 # number of WriteReq MSHR uncacheable cycles 1198system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172263349752 # number of overall MSHR uncacheable cycles 1199system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172263349752 # number of overall MSHR uncacheable cycles 1200system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.029872 # mshr miss rate for ReadReq accesses 1201system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029872 # mshr miss rate for ReadReq accesses 1202system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028826 # mshr miss rate for WriteReq accesses 1203system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028826 # mshr miss rate for WriteReq accesses 1204system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.054168 # mshr miss rate for LoadLockedReq accesses 1205system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.054168 # mshr miss rate for LoadLockedReq accesses 1206system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046299 # mshr miss rate for StoreCondReq accesses 1207system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046299 # mshr miss rate for StoreCondReq accesses 1208system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.029394 # mshr miss rate for demand accesses 1209system.cpu0.dcache.demand_mshr_miss_rate::total 0.029394 # mshr miss rate for demand accesses 1210system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.029394 # mshr miss rate for overall accesses 1211system.cpu0.dcache.overall_mshr_miss_rate::total 0.029394 # mshr miss rate for overall accesses 1212system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.392980 # average ReadReq mshr miss latency 1213system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12333.392980 # average ReadReq mshr miss latency 1214system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42985.493048 # average WriteReq mshr miss latency 1215system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42985.493048 # average WriteReq mshr miss latency 1216system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8153.784496 # average LoadLockedReq mshr miss latency 1217system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8153.784496 # average LoadLockedReq mshr miss latency 1218system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4331.633695 # average StoreCondReq mshr miss latency 1219system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4331.633695 # average StoreCondReq mshr miss latency 1220system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26077.460970 # average overall mshr miss latency 1221system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26077.460970 # average overall mshr miss latency 1222system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26077.460970 # average overall mshr miss latency 1223system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26077.460970 # average overall mshr miss latency 1224system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1225system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1226system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1227system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1228system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1229system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1230system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1231system.cpu1.branchPred.lookups 6346953 # Number of BP lookups 1232system.cpu1.branchPred.condPredicted 4931527 # Number of conditional branches predicted 1233system.cpu1.branchPred.condIncorrect 433505 # Number of conditional branches incorrect 1234system.cpu1.branchPred.BTBLookups 4095605 # Number of BTB lookups 1235system.cpu1.branchPred.BTBHits 3083437 # Number of BTB hits 1236system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1237system.cpu1.branchPred.BTBHitPct 75.286484 # BTB Hit Percentage 1238system.cpu1.branchPred.usedRAS 663921 # Number of times the RAS was used to get a target. 1239system.cpu1.branchPred.RASInCorrect 63861 # Number of incorrect RAS predictions. 1240system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1241system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1242system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1243system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1244system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1245system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1246system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1247system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1248system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1249system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1250system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1251system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1252system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1253system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1254system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1255system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1256system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1257system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1258system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1259system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1260system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1261system.cpu1.dtb.inst_hits 0 # ITB inst hits 1262system.cpu1.dtb.inst_misses 0 # ITB inst misses 1263system.cpu1.dtb.read_hits 7581512 # DTB read hits 1264system.cpu1.dtb.read_misses 20239 # DTB read misses 1265system.cpu1.dtb.write_hits 5551171 # DTB write hits 1266system.cpu1.dtb.write_misses 2521 # DTB write misses 1267system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1268system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1269system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1270system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1271system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB 1272system.cpu1.dtb.align_faults 2404 # Number of TLB faults due to alignment restrictions 1273system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch 1274system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1275system.cpu1.dtb.perms_faults 237 # Number of TLB faults due to permissions restrictions 1276system.cpu1.dtb.read_accesses 7601751 # DTB read accesses 1277system.cpu1.dtb.write_accesses 5553692 # DTB write accesses 1278system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1279system.cpu1.dtb.hits 13132683 # DTB hits 1280system.cpu1.dtb.misses 22760 # DTB misses 1281system.cpu1.dtb.accesses 13155443 # DTB accesses 1282system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1283system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1284system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1285system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1286system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1287system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1288system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1289system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1290system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1291system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1292system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1293system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1294system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1295system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1296system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1297system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1298system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1299system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1300system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1301system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1302system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1303system.cpu1.itb.inst_hits 11349850 # ITB inst hits 1304system.cpu1.itb.inst_misses 4207 # ITB inst misses 1305system.cpu1.itb.read_hits 0 # DTB read hits 1306system.cpu1.itb.read_misses 0 # DTB read misses 1307system.cpu1.itb.write_hits 0 # DTB write hits 1308system.cpu1.itb.write_misses 0 # DTB write misses 1309system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1310system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1311system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1312system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1313system.cpu1.itb.flush_entries 1191 # Number of entries that have been flushed from TLB 1314system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1315system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1316system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1317system.cpu1.itb.perms_faults 2046 # Number of TLB faults due to permissions restrictions 1318system.cpu1.itb.read_accesses 0 # DTB read accesses 1319system.cpu1.itb.write_accesses 0 # DTB write accesses 1320system.cpu1.itb.inst_accesses 11354057 # ITB inst accesses 1321system.cpu1.itb.hits 11349850 # DTB hits 1322system.cpu1.itb.misses 4207 # DTB misses 1323system.cpu1.itb.accesses 11354057 # DTB accesses 1324system.cpu1.numCycles 149527233 # number of cpu cycles simulated 1325system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1326system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1327system.cpu1.committedInsts 31976765 # Number of instructions committed 1328system.cpu1.committedOps 40324598 # Number of ops (including micro ops) committed 1329system.cpu1.discardedOps 1783017 # Number of ops (including micro ops) which were discarded before commit 1330system.cpu1.numFetchSuspends 39969 # Number of times Execute suspended instruction fetching 1331system.cpu1.quiesceCycles 2144960974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1332system.cpu1.cpi 4.676121 # CPI: cycles per instruction 1333system.cpu1.ipc 0.213852 # IPC: instructions per cycle 1334system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1335system.cpu1.kern.inst.quiesce 40497 # number of quiesce instructions executed 1336system.cpu1.tickCycles 120083069 # Number of cycles that the object actually ticked 1337system.cpu1.idleCycles 29444164 # Total number of cycles that the object has spent stopped 1338system.cpu1.icache.tags.replacements 800234 # number of replacements 1339system.cpu1.icache.tags.tagsinuse 480.617194 # Cycle average of tags in use 1340system.cpu1.icache.tags.total_refs 10546899 # Total number of references to valid blocks. 1341system.cpu1.icache.tags.sampled_refs 800746 # Sample count of references to valid blocks. 1342system.cpu1.icache.tags.avg_refs 13.171341 # Average number of references to valid blocks. 1343system.cpu1.icache.tags.warmup_cycle 82063984250 # Cycle when the warmup percentage was hit. 1344system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.617194 # Average occupied blocks per requestor 1345system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938705 # Average percentage of cache occupancy 1346system.cpu1.icache.tags.occ_percent::total 0.938705 # Average percentage of cache occupancy 1347system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1348system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 1349system.cpu1.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 1350system.cpu1.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id 1351system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 1352system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1353system.cpu1.icache.tags.tag_accesses 12148392 # Number of tag accesses 1354system.cpu1.icache.tags.data_accesses 12148392 # Number of data accesses 1355system.cpu1.icache.ReadReq_hits::cpu1.inst 10546899 # number of ReadReq hits 1356system.cpu1.icache.ReadReq_hits::total 10546899 # number of ReadReq hits 1357system.cpu1.icache.demand_hits::cpu1.inst 10546899 # number of demand (read+write) hits 1358system.cpu1.icache.demand_hits::total 10546899 # number of demand (read+write) hits 1359system.cpu1.icache.overall_hits::cpu1.inst 10546899 # number of overall hits 1360system.cpu1.icache.overall_hits::total 10546899 # number of overall hits 1361system.cpu1.icache.ReadReq_misses::cpu1.inst 800747 # number of ReadReq misses 1362system.cpu1.icache.ReadReq_misses::total 800747 # number of ReadReq misses 1363system.cpu1.icache.demand_misses::cpu1.inst 800747 # number of demand (read+write) misses 1364system.cpu1.icache.demand_misses::total 800747 # number of demand (read+write) misses 1365system.cpu1.icache.overall_misses::cpu1.inst 800747 # number of overall misses 1366system.cpu1.icache.overall_misses::total 800747 # number of overall misses 1367system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10721128674 # number of ReadReq miss cycles 1368system.cpu1.icache.ReadReq_miss_latency::total 10721128674 # number of ReadReq miss cycles 1369system.cpu1.icache.demand_miss_latency::cpu1.inst 10721128674 # number of demand (read+write) miss cycles 1370system.cpu1.icache.demand_miss_latency::total 10721128674 # number of demand (read+write) miss cycles 1371system.cpu1.icache.overall_miss_latency::cpu1.inst 10721128674 # number of overall miss cycles 1372system.cpu1.icache.overall_miss_latency::total 10721128674 # number of overall miss cycles 1373system.cpu1.icache.ReadReq_accesses::cpu1.inst 11347646 # number of ReadReq accesses(hits+misses) 1374system.cpu1.icache.ReadReq_accesses::total 11347646 # number of ReadReq accesses(hits+misses) 1375system.cpu1.icache.demand_accesses::cpu1.inst 11347646 # number of demand (read+write) accesses 1376system.cpu1.icache.demand_accesses::total 11347646 # number of demand (read+write) accesses 1377system.cpu1.icache.overall_accesses::cpu1.inst 11347646 # number of overall (read+write) accesses 1378system.cpu1.icache.overall_accesses::total 11347646 # number of overall (read+write) accesses 1379system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070565 # miss rate for ReadReq accesses 1380system.cpu1.icache.ReadReq_miss_rate::total 0.070565 # miss rate for ReadReq accesses 1381system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070565 # miss rate for demand accesses 1382system.cpu1.icache.demand_miss_rate::total 0.070565 # miss rate for demand accesses 1383system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070565 # miss rate for overall accesses 1384system.cpu1.icache.overall_miss_rate::total 0.070565 # miss rate for overall accesses 1385system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13388.908949 # average ReadReq miss latency 1386system.cpu1.icache.ReadReq_avg_miss_latency::total 13388.908949 # average ReadReq miss latency 1387system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13388.908949 # average overall miss latency 1388system.cpu1.icache.demand_avg_miss_latency::total 13388.908949 # average overall miss latency 1389system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13388.908949 # average overall miss latency 1390system.cpu1.icache.overall_avg_miss_latency::total 13388.908949 # average overall miss latency 1391system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1392system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1393system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1394system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1395system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1396system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1397system.cpu1.icache.fast_writes 0 # number of fast writes performed 1398system.cpu1.icache.cache_copies 0 # number of cache copies performed 1399system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 800747 # number of ReadReq MSHR misses 1400system.cpu1.icache.ReadReq_mshr_misses::total 800747 # number of ReadReq MSHR misses 1401system.cpu1.icache.demand_mshr_misses::cpu1.inst 800747 # number of demand (read+write) MSHR misses 1402system.cpu1.icache.demand_mshr_misses::total 800747 # number of demand (read+write) MSHR misses 1403system.cpu1.icache.overall_mshr_misses::cpu1.inst 800747 # number of overall MSHR misses 1404system.cpu1.icache.overall_mshr_misses::total 800747 # number of overall MSHR misses 1405system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9117705326 # number of ReadReq MSHR miss cycles 1406system.cpu1.icache.ReadReq_mshr_miss_latency::total 9117705326 # number of ReadReq MSHR miss cycles 1407system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9117705326 # number of demand (read+write) MSHR miss cycles 1408system.cpu1.icache.demand_mshr_miss_latency::total 9117705326 # number of demand (read+write) MSHR miss cycles 1409system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9117705326 # number of overall MSHR miss cycles 1410system.cpu1.icache.overall_mshr_miss_latency::total 9117705326 # number of overall MSHR miss cycles 1411system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5654750 # number of ReadReq MSHR uncacheable cycles 1412system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5654750 # number of ReadReq MSHR uncacheable cycles 1413system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5654750 # number of overall MSHR uncacheable cycles 1414system.cpu1.icache.overall_mshr_uncacheable_latency::total 5654750 # number of overall MSHR uncacheable cycles 1415system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070565 # mshr miss rate for ReadReq accesses 1416system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070565 # mshr miss rate for ReadReq accesses 1417system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070565 # mshr miss rate for demand accesses 1418system.cpu1.icache.demand_mshr_miss_rate::total 0.070565 # mshr miss rate for demand accesses 1419system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070565 # mshr miss rate for overall accesses 1420system.cpu1.icache.overall_mshr_miss_rate::total 0.070565 # mshr miss rate for overall accesses 1421system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11386.499514 # average ReadReq mshr miss latency 1422system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11386.499514 # average ReadReq mshr miss latency 1423system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11386.499514 # average overall mshr miss latency 1424system.cpu1.icache.demand_avg_mshr_miss_latency::total 11386.499514 # average overall mshr miss latency 1425system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11386.499514 # average overall mshr miss latency 1426system.cpu1.icache.overall_avg_mshr_miss_latency::total 11386.499514 # average overall mshr miss latency 1427system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1428system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1429system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1430system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1431system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1432system.cpu1.dcache.tags.replacements 301108 # number of replacements 1433system.cpu1.dcache.tags.tagsinuse 446.775625 # Cycle average of tags in use 1434system.cpu1.dcache.tags.total_refs 11731236 # Total number of references to valid blocks. 1435system.cpu1.dcache.tags.sampled_refs 301620 # Sample count of references to valid blocks. 1436system.cpu1.dcache.tags.avg_refs 38.894092 # Average number of references to valid blocks. 1437system.cpu1.dcache.tags.warmup_cycle 76702840250 # Cycle when the warmup percentage was hit. 1438system.cpu1.dcache.tags.occ_blocks::cpu1.inst 446.775625 # Average occupied blocks per requestor 1439system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.872609 # Average percentage of cache occupancy 1440system.cpu1.dcache.tags.occ_percent::total 0.872609 # Average percentage of cache occupancy 1441system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1442system.cpu1.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 1443system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 1444system.cpu1.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id 1445system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1446system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1447system.cpu1.dcache.tags.tag_accesses 49070289 # Number of tag accesses 1448system.cpu1.dcache.tags.data_accesses 49070289 # Number of data accesses 1449system.cpu1.dcache.ReadReq_hits::cpu1.inst 7114972 # number of ReadReq hits 1450system.cpu1.dcache.ReadReq_hits::total 7114972 # number of ReadReq hits 1451system.cpu1.dcache.WriteReq_hits::cpu1.inst 4425981 # number of WriteReq hits 1452system.cpu1.dcache.WriteReq_hits::total 4425981 # number of WriteReq hits 1453system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78462 # number of LoadLockedReq hits 1454system.cpu1.dcache.LoadLockedReq_hits::total 78462 # number of LoadLockedReq hits 1455system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79072 # number of StoreCondReq hits 1456system.cpu1.dcache.StoreCondReq_hits::total 79072 # number of StoreCondReq hits 1457system.cpu1.dcache.demand_hits::cpu1.inst 11540953 # number of demand (read+write) hits 1458system.cpu1.dcache.demand_hits::total 11540953 # number of demand (read+write) hits 1459system.cpu1.dcache.overall_hits::cpu1.inst 11540953 # number of overall hits 1460system.cpu1.dcache.overall_hits::total 11540953 # number of overall hits 1461system.cpu1.dcache.ReadReq_misses::cpu1.inst 243175 # number of ReadReq misses 1462system.cpu1.dcache.ReadReq_misses::total 243175 # number of ReadReq misses 1463system.cpu1.dcache.WriteReq_misses::cpu1.inst 224036 # number of WriteReq misses 1464system.cpu1.dcache.WriteReq_misses::total 224036 # number of WriteReq misses 1465system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10782 # number of LoadLockedReq misses 1466system.cpu1.dcache.LoadLockedReq_misses::total 10782 # number of LoadLockedReq misses 1467system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10124 # number of StoreCondReq misses 1468system.cpu1.dcache.StoreCondReq_misses::total 10124 # number of StoreCondReq misses 1469system.cpu1.dcache.demand_misses::cpu1.inst 467211 # number of demand (read+write) misses 1470system.cpu1.dcache.demand_misses::total 467211 # number of demand (read+write) misses 1471system.cpu1.dcache.overall_misses::cpu1.inst 467211 # number of overall misses 1472system.cpu1.dcache.overall_misses::total 467211 # number of overall misses 1473system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3616409978 # number of ReadReq miss cycles 1474system.cpu1.dcache.ReadReq_miss_latency::total 3616409978 # number of ReadReq miss cycles 1475system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8727689439 # number of WriteReq miss cycles 1476system.cpu1.dcache.WriteReq_miss_latency::total 8727689439 # number of WriteReq miss cycles 1477system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90341500 # number of LoadLockedReq miss cycles 1478system.cpu1.dcache.LoadLockedReq_miss_latency::total 90341500 # number of LoadLockedReq miss cycles 1479system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50520310 # number of StoreCondReq miss cycles 1480system.cpu1.dcache.StoreCondReq_miss_latency::total 50520310 # number of StoreCondReq miss cycles 1481system.cpu1.dcache.demand_miss_latency::cpu1.inst 12344099417 # number of demand (read+write) miss cycles 1482system.cpu1.dcache.demand_miss_latency::total 12344099417 # number of demand (read+write) miss cycles 1483system.cpu1.dcache.overall_miss_latency::cpu1.inst 12344099417 # number of overall miss cycles 1484system.cpu1.dcache.overall_miss_latency::total 12344099417 # number of overall miss cycles 1485system.cpu1.dcache.ReadReq_accesses::cpu1.inst 7358147 # number of ReadReq accesses(hits+misses) 1486system.cpu1.dcache.ReadReq_accesses::total 7358147 # number of ReadReq accesses(hits+misses) 1487system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4650017 # number of WriteReq accesses(hits+misses) 1488system.cpu1.dcache.WriteReq_accesses::total 4650017 # number of WriteReq accesses(hits+misses) 1489system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89244 # number of LoadLockedReq accesses(hits+misses) 1490system.cpu1.dcache.LoadLockedReq_accesses::total 89244 # number of LoadLockedReq accesses(hits+misses) 1491system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89196 # number of StoreCondReq accesses(hits+misses) 1492system.cpu1.dcache.StoreCondReq_accesses::total 89196 # number of StoreCondReq accesses(hits+misses) 1493system.cpu1.dcache.demand_accesses::cpu1.inst 12008164 # number of demand (read+write) accesses 1494system.cpu1.dcache.demand_accesses::total 12008164 # number of demand (read+write) accesses 1495system.cpu1.dcache.overall_accesses::cpu1.inst 12008164 # number of overall (read+write) accesses 1496system.cpu1.dcache.overall_accesses::total 12008164 # number of overall (read+write) accesses 1497system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.033048 # miss rate for ReadReq accesses 1498system.cpu1.dcache.ReadReq_miss_rate::total 0.033048 # miss rate for ReadReq accesses 1499system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048180 # miss rate for WriteReq accesses 1500system.cpu1.dcache.WriteReq_miss_rate::total 0.048180 # miss rate for WriteReq accesses 1501system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120815 # miss rate for LoadLockedReq accesses 1502system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120815 # miss rate for LoadLockedReq accesses 1503system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113503 # miss rate for StoreCondReq accesses 1504system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113503 # miss rate for StoreCondReq accesses 1505system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038908 # miss rate for demand accesses 1506system.cpu1.dcache.demand_miss_rate::total 0.038908 # miss rate for demand accesses 1507system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038908 # miss rate for overall accesses 1508system.cpu1.dcache.overall_miss_rate::total 0.038908 # miss rate for overall accesses 1509system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.635563 # average ReadReq miss latency 1510system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.635563 # average ReadReq miss latency 1511system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38956.638393 # average WriteReq miss latency 1512system.cpu1.dcache.WriteReq_avg_miss_latency::total 38956.638393 # average WriteReq miss latency 1513system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8378.918568 # average LoadLockedReq miss latency 1514system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8378.918568 # average LoadLockedReq miss latency 1515system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4990.153102 # average StoreCondReq miss latency 1516system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4990.153102 # average StoreCondReq miss latency 1517system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26420.823604 # average overall miss latency 1518system.cpu1.dcache.demand_avg_miss_latency::total 26420.823604 # average overall miss latency 1519system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26420.823604 # average overall miss latency 1520system.cpu1.dcache.overall_avg_miss_latency::total 26420.823604 # average overall miss latency 1521system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1522system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1523system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1524system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1525system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1526system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1527system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1528system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1529system.cpu1.dcache.writebacks::writebacks 269177 # number of writebacks 1530system.cpu1.dcache.writebacks::total 269177 # number of writebacks 1531system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 37509 # number of ReadReq MSHR hits 1532system.cpu1.dcache.ReadReq_mshr_hits::total 37509 # number of ReadReq MSHR hits 1533system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98167 # number of WriteReq MSHR hits 1534system.cpu1.dcache.WriteReq_mshr_hits::total 98167 # number of WriteReq MSHR hits 1535system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 30 # number of LoadLockedReq MSHR hits 1536system.cpu1.dcache.LoadLockedReq_mshr_hits::total 30 # number of LoadLockedReq MSHR hits 1537system.cpu1.dcache.demand_mshr_hits::cpu1.inst 135676 # number of demand (read+write) MSHR hits 1538system.cpu1.dcache.demand_mshr_hits::total 135676 # number of demand (read+write) MSHR hits 1539system.cpu1.dcache.overall_mshr_hits::cpu1.inst 135676 # number of overall MSHR hits 1540system.cpu1.dcache.overall_mshr_hits::total 135676 # number of overall MSHR hits 1541system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 205666 # number of ReadReq MSHR misses 1542system.cpu1.dcache.ReadReq_mshr_misses::total 205666 # number of ReadReq MSHR misses 1543system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125869 # number of WriteReq MSHR misses 1544system.cpu1.dcache.WriteReq_mshr_misses::total 125869 # number of WriteReq MSHR misses 1545system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10752 # number of LoadLockedReq MSHR misses 1546system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10752 # number of LoadLockedReq MSHR misses 1547system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10124 # number of StoreCondReq MSHR misses 1548system.cpu1.dcache.StoreCondReq_mshr_misses::total 10124 # number of StoreCondReq MSHR misses 1549system.cpu1.dcache.demand_mshr_misses::cpu1.inst 331535 # number of demand (read+write) MSHR misses 1550system.cpu1.dcache.demand_mshr_misses::total 331535 # number of demand (read+write) MSHR misses 1551system.cpu1.dcache.overall_mshr_misses::cpu1.inst 331535 # number of overall MSHR misses 1552system.cpu1.dcache.overall_mshr_misses::total 331535 # number of overall MSHR misses 1553system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2422782037 # number of ReadReq MSHR miss cycles 1554system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2422782037 # number of ReadReq MSHR miss cycles 1555system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4131508096 # number of WriteReq MSHR miss cycles 1556system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4131508096 # number of WriteReq MSHR miss cycles 1557system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68345000 # number of LoadLockedReq MSHR miss cycles 1558system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68345000 # number of LoadLockedReq MSHR miss cycles 1559system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30271690 # number of StoreCondReq MSHR miss cycles 1560system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30271690 # number of StoreCondReq MSHR miss cycles 1561system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6554290133 # number of demand (read+write) MSHR miss cycles 1562system.cpu1.dcache.demand_mshr_miss_latency::total 6554290133 # number of demand (read+write) MSHR miss cycles 1563system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6554290133 # number of overall MSHR miss cycles 1564system.cpu1.dcache.overall_mshr_miss_latency::total 6554290133 # number of overall MSHR miss cycles 1565system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11992419500 # number of ReadReq MSHR uncacheable cycles 1566system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11992419500 # number of ReadReq MSHR uncacheable cycles 1567system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672512707 # number of WriteReq MSHR uncacheable cycles 1568system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672512707 # number of WriteReq MSHR uncacheable cycles 1569system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36664932207 # number of overall MSHR uncacheable cycles 1570system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36664932207 # number of overall MSHR uncacheable cycles 1571system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.027951 # mshr miss rate for ReadReq accesses 1572system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses 1573system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027069 # mshr miss rate for WriteReq accesses 1574system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027069 # mshr miss rate for WriteReq accesses 1575system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120479 # mshr miss rate for LoadLockedReq accesses 1576system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120479 # mshr miss rate for LoadLockedReq accesses 1577system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113503 # mshr miss rate for StoreCondReq accesses 1578system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113503 # mshr miss rate for StoreCondReq accesses 1579system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.027609 # mshr miss rate for demand accesses 1580system.cpu1.dcache.demand_mshr_miss_rate::total 0.027609 # mshr miss rate for demand accesses 1581system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.027609 # mshr miss rate for overall accesses 1582system.cpu1.dcache.overall_mshr_miss_rate::total 0.027609 # mshr miss rate for overall accesses 1583system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11780.177749 # average ReadReq mshr miss latency 1584system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11780.177749 # average ReadReq mshr miss latency 1585system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.873202 # average WriteReq mshr miss latency 1586system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.873202 # average WriteReq mshr miss latency 1587system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6356.491815 # average LoadLockedReq mshr miss latency 1588system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6356.491815 # average LoadLockedReq mshr miss latency 1589system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2990.091861 # average StoreCondReq mshr miss latency 1590system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2990.091861 # average StoreCondReq mshr miss latency 1591system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19769.526997 # average overall mshr miss latency 1592system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19769.526997 # average overall mshr miss latency 1593system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19769.526997 # average overall mshr miss latency 1594system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19769.526997 # average overall mshr miss latency 1595system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1596system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1597system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1598system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1599system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1600system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1601system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1602system.iocache.tags.replacements 0 # number of replacements 1603system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1604system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1605system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1606system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1607system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1608system.iocache.tags.tag_accesses 0 # Number of tag accesses 1609system.iocache.tags.data_accesses 0 # Number of data accesses 1610system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1611system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1612system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1613system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1614system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1615system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1616system.iocache.fast_writes 0 # number of fast writes performed 1617system.iocache.cache_copies 0 # number of cache copies performed 1618system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 721880739500 # number of ReadReq MSHR uncacheable cycles 1619system.iocache.ReadReq_mshr_uncacheable_latency::total 721880739500 # number of ReadReq MSHR uncacheable cycles 1620system.iocache.overall_mshr_uncacheable_latency::realview.clcd 721880739500 # number of overall MSHR uncacheable cycles 1621system.iocache.overall_mshr_uncacheable_latency::total 721880739500 # number of overall MSHR uncacheable cycles 1622system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1623system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1624system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1625system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1626system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1627 1628---------- End Simulation Statistics ---------- 1629