stats.txt revision 10260:384d554cea8c
1 2---------- Begin Simulation Statistics ---------- 3final_tick 1146785401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 81646 # Simulator instruction rate (inst/s) 5host_mem_usage 463904 # Number of bytes of host memory used 6host_op_rate 105090 # Simulator op (including micro ops) rate (op/s) 7host_seconds 758.04 # Real time elapsed on the host 8host_tick_rate 1512825196 # Simulator tick rate (ticks/s) 9sim_freq 1000000000000 # Frequency of simulated ticks 10sim_insts 61891142 # Number of instructions simulated 11sim_ops 79662361 # Number of ops (including micro ops) simulated 12sim_seconds 1.146785 # Number of seconds simulated 13sim_ticks 1146785401000 # Number of ticks simulated 14system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 15system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 16system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 17system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 18system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 19system.cf0.dma_write_txs 0 # Number of DMA write transactions. 20system.clk_domain.clock 1000 # Clock period in ticks 21system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 22system.cpu0.branchPred.BTBHitPct 71.700237 # BTB Hit Percentage 23system.cpu0.branchPred.BTBHits 3353058 # Number of BTB hits 24system.cpu0.branchPred.BTBLookups 4676495 # Number of BTB lookups 25system.cpu0.branchPred.RASInCorrect 70484 # Number of incorrect RAS predictions. 26system.cpu0.branchPred.condIncorrect 650965 # Number of conditional branches incorrect 27system.cpu0.branchPred.condPredicted 5175442 # Number of conditional branches predicted 28system.cpu0.branchPred.lookups 6862341 # Number of BP lookups 29system.cpu0.branchPred.usedRAS 848882 # Number of times the RAS was used to get a target. 30system.cpu0.committedInsts 29915640 # Number of instructions committed 31system.cpu0.committedOps 39339363 # Number of ops (including micro ops) committed 32system.cpu0.cpi 14.502071 # CPI: cycles per instruction 33system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161256 # number of LoadLockedReq accesses(hits+misses) 34system.cpu0.dcache.LoadLockedReq_accesses::total 161256 # number of LoadLockedReq accesses(hits+misses) 35system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10306.777196 # average LoadLockedReq miss latency 36system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10306.777196 # average LoadLockedReq miss latency 37system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8288.517611 # average LoadLockedReq mshr miss latency 38system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.517611 # average LoadLockedReq mshr miss latency 39system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152661 # number of LoadLockedReq hits 40system.cpu0.dcache.LoadLockedReq_hits::total 152661 # number of LoadLockedReq hits 41system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 88586750 # number of LoadLockedReq miss cycles 42system.cpu0.dcache.LoadLockedReq_miss_latency::total 88586750 # number of LoadLockedReq miss cycles 43system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053300 # miss rate for LoadLockedReq accesses 44system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053300 # miss rate for LoadLockedReq accesses 45system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8595 # number of LoadLockedReq misses 46system.cpu0.dcache.LoadLockedReq_misses::total 8595 # number of LoadLockedReq misses 47system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 21 # number of LoadLockedReq MSHR hits 48system.cpu0.dcache.LoadLockedReq_mshr_hits::total 21 # number of LoadLockedReq MSHR hits 49system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71065750 # number of LoadLockedReq MSHR miss cycles 50system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71065750 # number of LoadLockedReq MSHR miss cycles 51system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.053170 # mshr miss rate for LoadLockedReq accesses 52system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053170 # mshr miss rate for LoadLockedReq accesses 53system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8574 # number of LoadLockedReq MSHR misses 54system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8574 # number of LoadLockedReq MSHR misses 55system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6911519 # number of ReadReq accesses(hits+misses) 56system.cpu0.dcache.ReadReq_accesses::total 6911519 # number of ReadReq accesses(hits+misses) 57system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14955.771110 # average ReadReq miss latency 58system.cpu0.dcache.ReadReq_avg_miss_latency::total 14955.771110 # average ReadReq miss latency 59system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12252.616817 # average ReadReq mshr miss latency 60system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12252.616817 # average ReadReq mshr miss latency 61system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 62system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 63system.cpu0.dcache.ReadReq_hits::cpu0.inst 6653819 # number of ReadReq hits 64system.cpu0.dcache.ReadReq_hits::total 6653819 # number of ReadReq hits 65system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3854102215 # number of ReadReq miss cycles 66system.cpu0.dcache.ReadReq_miss_latency::total 3854102215 # number of ReadReq miss cycles 67system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.037286 # miss rate for ReadReq accesses 68system.cpu0.dcache.ReadReq_miss_rate::total 0.037286 # miss rate for ReadReq accesses 69system.cpu0.dcache.ReadReq_misses::cpu0.inst 257700 # number of ReadReq misses 70system.cpu0.dcache.ReadReq_misses::total 257700 # number of ReadReq misses 71system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 51318 # number of ReadReq MSHR hits 72system.cpu0.dcache.ReadReq_mshr_hits::total 51318 # number of ReadReq MSHR hits 73system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2528719564 # number of ReadReq MSHR miss cycles 74system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2528719564 # number of ReadReq MSHR miss cycles 75system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.029861 # mshr miss rate for ReadReq accesses 76system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029861 # mshr miss rate for ReadReq accesses 77system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 206382 # number of ReadReq MSHR misses 78system.cpu0.dcache.ReadReq_mshr_misses::total 206382 # number of ReadReq MSHR misses 79system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170751064250 # number of ReadReq MSHR uncacheable cycles 80system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170751064250 # number of ReadReq MSHR uncacheable cycles 81system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161153 # number of StoreCondReq accesses(hits+misses) 82system.cpu0.dcache.StoreCondReq_accesses::total 161153 # number of StoreCondReq accesses(hits+misses) 83system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6297.509524 # average StoreCondReq miss latency 84system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6297.509524 # average StoreCondReq miss latency 85system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4297.199471 # average StoreCondReq mshr miss latency 86system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4297.199471 # average StoreCondReq mshr miss latency 87system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153593 # number of StoreCondReq hits 88system.cpu0.dcache.StoreCondReq_hits::total 153593 # number of StoreCondReq hits 89system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47609172 # number of StoreCondReq miss cycles 90system.cpu0.dcache.StoreCondReq_miss_latency::total 47609172 # number of StoreCondReq miss cycles 91system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046912 # miss rate for StoreCondReq accesses 92system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046912 # miss rate for StoreCondReq accesses 93system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7560 # number of StoreCondReq misses 94system.cpu0.dcache.StoreCondReq_misses::total 7560 # number of StoreCondReq misses 95system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32486828 # number of StoreCondReq MSHR miss cycles 96system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32486828 # number of StoreCondReq MSHR miss cycles 97system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046912 # mshr miss rate for StoreCondReq accesses 98system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046912 # mshr miss rate for StoreCondReq accesses 99system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7560 # number of StoreCondReq MSHR misses 100system.cpu0.dcache.StoreCondReq_mshr_misses::total 7560 # number of StoreCondReq MSHR misses 101system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5819437 # number of WriteReq accesses(hits+misses) 102system.cpu0.dcache.WriteReq_accesses::total 5819437 # number of WriteReq accesses(hits+misses) 103system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49213.556324 # average WriteReq miss latency 104system.cpu0.dcache.WriteReq_avg_miss_latency::total 49213.556324 # average WriteReq miss latency 105system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42966.373247 # average WriteReq mshr miss latency 106system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42966.373247 # average WriteReq mshr miss latency 107system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 108system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 109system.cpu0.dcache.WriteReq_hits::cpu0.inst 5512001 # number of WriteReq hits 110system.cpu0.dcache.WriteReq_hits::total 5512001 # number of WriteReq hits 111system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15130018902 # number of WriteReq miss cycles 112system.cpu0.dcache.WriteReq_miss_latency::total 15130018902 # number of WriteReq miss cycles 113system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.052829 # miss rate for WriteReq accesses 114system.cpu0.dcache.WriteReq_miss_rate::total 0.052829 # miss rate for WriteReq accesses 115system.cpu0.dcache.WriteReq_misses::cpu0.inst 307436 # number of WriteReq misses 116system.cpu0.dcache.WriteReq_misses::total 307436 # number of WriteReq misses 117system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 139625 # number of WriteReq MSHR hits 118system.cpu0.dcache.WriteReq_mshr_hits::total 139625 # number of WriteReq MSHR hits 119system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7210230061 # number of WriteReq MSHR miss cycles 120system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7210230061 # number of WriteReq MSHR miss cycles 121system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028836 # mshr miss rate for WriteReq accesses 122system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028836 # mshr miss rate for WriteReq accesses 123system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167811 # number of WriteReq MSHR misses 124system.cpu0.dcache.WriteReq_mshr_misses::total 167811 # number of WriteReq MSHR misses 125system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513184500 # number of WriteReq MSHR uncacheable cycles 126system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513184500 # number of WriteReq MSHR uncacheable cycles 127system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 128system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 129system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 130system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 131system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 132system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 133system.cpu0.dcache.cache_copies 0 # number of cache copies performed 134system.cpu0.dcache.demand_accesses::cpu0.inst 12730956 # number of demand (read+write) accesses 135system.cpu0.dcache.demand_accesses::total 12730956 # number of demand (read+write) accesses 136system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33592.128474 # average overall miss latency 137system.cpu0.dcache.demand_avg_miss_latency::total 33592.128474 # average overall miss latency 138system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26026.541451 # average overall mshr miss latency 139system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.541451 # average overall mshr miss latency 140system.cpu0.dcache.demand_hits::cpu0.inst 12165820 # number of demand (read+write) hits 141system.cpu0.dcache.demand_hits::total 12165820 # number of demand (read+write) hits 142system.cpu0.dcache.demand_miss_latency::cpu0.inst 18984121117 # number of demand (read+write) miss cycles 143system.cpu0.dcache.demand_miss_latency::total 18984121117 # number of demand (read+write) miss cycles 144system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.044391 # miss rate for demand accesses 145system.cpu0.dcache.demand_miss_rate::total 0.044391 # miss rate for demand accesses 146system.cpu0.dcache.demand_misses::cpu0.inst 565136 # number of demand (read+write) misses 147system.cpu0.dcache.demand_misses::total 565136 # number of demand (read+write) misses 148system.cpu0.dcache.demand_mshr_hits::cpu0.inst 190943 # number of demand (read+write) MSHR hits 149system.cpu0.dcache.demand_mshr_hits::total 190943 # number of demand (read+write) MSHR hits 150system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9738949625 # number of demand (read+write) MSHR miss cycles 151system.cpu0.dcache.demand_mshr_miss_latency::total 9738949625 # number of demand (read+write) MSHR miss cycles 152system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.029392 # mshr miss rate for demand accesses 153system.cpu0.dcache.demand_mshr_miss_rate::total 0.029392 # mshr miss rate for demand accesses 154system.cpu0.dcache.demand_mshr_misses::cpu0.inst 374193 # number of demand (read+write) MSHR misses 155system.cpu0.dcache.demand_mshr_misses::total 374193 # number of demand (read+write) MSHR misses 156system.cpu0.dcache.fast_writes 0 # number of fast writes performed 157system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 158system.cpu0.dcache.overall_accesses::cpu0.inst 12730956 # number of overall (read+write) accesses 159system.cpu0.dcache.overall_accesses::total 12730956 # number of overall (read+write) accesses 160system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33592.128474 # average overall miss latency 161system.cpu0.dcache.overall_avg_miss_latency::total 33592.128474 # average overall miss latency 162system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26026.541451 # average overall mshr miss latency 163system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.541451 # average overall mshr miss latency 164system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 165system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 166system.cpu0.dcache.overall_hits::cpu0.inst 12165820 # number of overall hits 167system.cpu0.dcache.overall_hits::total 12165820 # number of overall hits 168system.cpu0.dcache.overall_miss_latency::cpu0.inst 18984121117 # number of overall miss cycles 169system.cpu0.dcache.overall_miss_latency::total 18984121117 # number of overall miss cycles 170system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.044391 # miss rate for overall accesses 171system.cpu0.dcache.overall_miss_rate::total 0.044391 # miss rate for overall accesses 172system.cpu0.dcache.overall_misses::cpu0.inst 565136 # number of overall misses 173system.cpu0.dcache.overall_misses::total 565136 # number of overall misses 174system.cpu0.dcache.overall_mshr_hits::cpu0.inst 190943 # number of overall MSHR hits 175system.cpu0.dcache.overall_mshr_hits::total 190943 # number of overall MSHR hits 176system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9738949625 # number of overall MSHR miss cycles 177system.cpu0.dcache.overall_mshr_miss_latency::total 9738949625 # number of overall MSHR miss cycles 178system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.029392 # mshr miss rate for overall accesses 179system.cpu0.dcache.overall_mshr_miss_rate::total 0.029392 # mshr miss rate for overall accesses 180system.cpu0.dcache.overall_mshr_misses::cpu0.inst 374193 # number of overall MSHR misses 181system.cpu0.dcache.overall_mshr_misses::total 374193 # number of overall MSHR misses 182system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172264248750 # number of overall MSHR uncacheable cycles 183system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172264248750 # number of overall MSHR uncacheable cycles 184system.cpu0.dcache.tags.age_task_id_blocks_1024::2 364 # Occupied blocks per task id 185system.cpu0.dcache.tags.avg_refs 37.525252 # Average number of references to valid blocks. 186system.cpu0.dcache.tags.data_accesses 52581616 # Number of data accesses 187system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.504489 # Average occupied blocks per requestor 188system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967782 # Average percentage of cache occupancy 189system.cpu0.dcache.tags.occ_percent::total 0.967782 # Average percentage of cache occupancy 190system.cpu0.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 191system.cpu0.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id 192system.cpu0.dcache.tags.replacements 332602 # number of replacements 193system.cpu0.dcache.tags.sampled_refs 332966 # Sample count of references to valid blocks. 194system.cpu0.dcache.tags.tag_accesses 52581616 # Number of tag accesses 195system.cpu0.dcache.tags.tagsinuse 495.504489 # Cycle average of tags in use 196system.cpu0.dcache.tags.total_refs 12494633 # Total number of references to valid blocks. 197system.cpu0.dcache.tags.warmup_cycle 236260250 # Cycle when the warmup percentage was hit. 198system.cpu0.dcache.writebacks::writebacks 306168 # number of writebacks 199system.cpu0.dcache.writebacks::total 306168 # number of writebacks 200system.cpu0.discardedOps 1920081 # Number of ops (including micro ops) which were discarded before commit 201system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 202system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 203system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 204system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 205system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 206system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 207system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 208system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 209system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 210system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 211system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 212system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 213system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 214system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 215system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 216system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 217system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 218system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 219system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 220system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 221system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 222system.cpu0.dtb.accesses 14321266 # DTB accesses 223system.cpu0.dtb.align_faults 1416 # Number of TLB faults due to alignment restrictions 224system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 225system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB 226system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 227system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 228system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 229system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 230system.cpu0.dtb.hits 14297430 # DTB hits 231system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 232system.cpu0.dtb.inst_hits 0 # ITB inst hits 233system.cpu0.dtb.inst_misses 0 # ITB inst misses 234system.cpu0.dtb.misses 23836 # DTB misses 235system.cpu0.dtb.perms_faults 284 # Number of TLB faults due to permissions restrictions 236system.cpu0.dtb.prefetch_faults 167 # Number of TLB faults due to prefetch 237system.cpu0.dtb.read_accesses 8272964 # DTB read accesses 238system.cpu0.dtb.read_hits 8250552 # DTB read hits 239system.cpu0.dtb.read_misses 22412 # DTB read misses 240system.cpu0.dtb.write_accesses 6048302 # DTB write accesses 241system.cpu0.dtb.write_hits 6046878 # DTB write hits 242system.cpu0.dtb.write_misses 1424 # DTB write misses 243system.cpu0.icache.ReadReq_accesses::cpu0.inst 12525310 # number of ReadReq accesses(hits+misses) 244system.cpu0.icache.ReadReq_accesses::total 12525310 # number of ReadReq accesses(hits+misses) 245system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13777.726344 # average ReadReq miss latency 246system.cpu0.icache.ReadReq_avg_miss_latency::total 13777.726344 # average ReadReq miss latency 247system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11772.390367 # average ReadReq mshr miss latency 248system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.390367 # average ReadReq mshr miss latency 249system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 250system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 251system.cpu0.icache.ReadReq_hits::cpu0.inst 11740482 # number of ReadReq hits 252system.cpu0.icache.ReadReq_hits::total 11740482 # number of ReadReq hits 253system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10813145411 # number of ReadReq miss cycles 254system.cpu0.icache.ReadReq_miss_latency::total 10813145411 # number of ReadReq miss cycles 255system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.062659 # miss rate for ReadReq accesses 256system.cpu0.icache.ReadReq_miss_rate::total 0.062659 # miss rate for ReadReq accesses 257system.cpu0.icache.ReadReq_misses::cpu0.inst 784828 # number of ReadReq misses 258system.cpu0.icache.ReadReq_misses::total 784828 # number of ReadReq misses 259system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9239301587 # number of ReadReq MSHR miss cycles 260system.cpu0.icache.ReadReq_mshr_miss_latency::total 9239301587 # number of ReadReq MSHR miss cycles 261system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.062659 # mshr miss rate for ReadReq accesses 262system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.062659 # mshr miss rate for ReadReq accesses 263system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 784828 # number of ReadReq MSHR misses 264system.cpu0.icache.ReadReq_mshr_misses::total 784828 # number of ReadReq MSHR misses 265system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171826250 # number of ReadReq MSHR uncacheable cycles 266system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171826250 # number of ReadReq MSHR uncacheable cycles 267system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 268system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 269system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 270system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 271system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 272system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 273system.cpu0.icache.cache_copies 0 # number of cache copies performed 274system.cpu0.icache.demand_accesses::cpu0.inst 12525310 # number of demand (read+write) accesses 275system.cpu0.icache.demand_accesses::total 12525310 # number of demand (read+write) accesses 276system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13777.726344 # average overall miss latency 277system.cpu0.icache.demand_avg_miss_latency::total 13777.726344 # average overall miss latency 278system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11772.390367 # average overall mshr miss latency 279system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.390367 # average overall mshr miss latency 280system.cpu0.icache.demand_hits::cpu0.inst 11740482 # number of demand (read+write) hits 281system.cpu0.icache.demand_hits::total 11740482 # number of demand (read+write) hits 282system.cpu0.icache.demand_miss_latency::cpu0.inst 10813145411 # number of demand (read+write) miss cycles 283system.cpu0.icache.demand_miss_latency::total 10813145411 # number of demand (read+write) miss cycles 284system.cpu0.icache.demand_miss_rate::cpu0.inst 0.062659 # miss rate for demand accesses 285system.cpu0.icache.demand_miss_rate::total 0.062659 # miss rate for demand accesses 286system.cpu0.icache.demand_misses::cpu0.inst 784828 # number of demand (read+write) misses 287system.cpu0.icache.demand_misses::total 784828 # number of demand (read+write) misses 288system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9239301587 # number of demand (read+write) MSHR miss cycles 289system.cpu0.icache.demand_mshr_miss_latency::total 9239301587 # number of demand (read+write) MSHR miss cycles 290system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.062659 # mshr miss rate for demand accesses 291system.cpu0.icache.demand_mshr_miss_rate::total 0.062659 # mshr miss rate for demand accesses 292system.cpu0.icache.demand_mshr_misses::cpu0.inst 784828 # number of demand (read+write) MSHR misses 293system.cpu0.icache.demand_mshr_misses::total 784828 # number of demand (read+write) MSHR misses 294system.cpu0.icache.fast_writes 0 # number of fast writes performed 295system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 296system.cpu0.icache.overall_accesses::cpu0.inst 12525310 # number of overall (read+write) accesses 297system.cpu0.icache.overall_accesses::total 12525310 # number of overall (read+write) accesses 298system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13777.726344 # average overall miss latency 299system.cpu0.icache.overall_avg_miss_latency::total 13777.726344 # average overall miss latency 300system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11772.390367 # average overall mshr miss latency 301system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.390367 # average overall mshr miss latency 302system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 303system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 304system.cpu0.icache.overall_hits::cpu0.inst 11740482 # number of overall hits 305system.cpu0.icache.overall_hits::total 11740482 # number of overall hits 306system.cpu0.icache.overall_miss_latency::cpu0.inst 10813145411 # number of overall miss cycles 307system.cpu0.icache.overall_miss_latency::total 10813145411 # number of overall miss cycles 308system.cpu0.icache.overall_miss_rate::cpu0.inst 0.062659 # miss rate for overall accesses 309system.cpu0.icache.overall_miss_rate::total 0.062659 # miss rate for overall accesses 310system.cpu0.icache.overall_misses::cpu0.inst 784828 # number of overall misses 311system.cpu0.icache.overall_misses::total 784828 # number of overall misses 312system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9239301587 # number of overall MSHR miss cycles 313system.cpu0.icache.overall_mshr_miss_latency::total 9239301587 # number of overall MSHR miss cycles 314system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.062659 # mshr miss rate for overall accesses 315system.cpu0.icache.overall_mshr_miss_rate::total 0.062659 # mshr miss rate for overall accesses 316system.cpu0.icache.overall_mshr_misses::cpu0.inst 784828 # number of overall MSHR misses 317system.cpu0.icache.overall_mshr_misses::total 784828 # number of overall MSHR misses 318system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171826250 # number of overall MSHR uncacheable cycles 319system.cpu0.icache.overall_mshr_uncacheable_latency::total 171826250 # number of overall MSHR uncacheable cycles 320system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id 321system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 322system.cpu0.icache.tags.avg_refs 14.959363 # Average number of references to valid blocks. 323system.cpu0.icache.tags.data_accesses 13310138 # Number of data accesses 324system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.783510 # Average occupied blocks per requestor 325system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997624 # Average percentage of cache occupancy 326system.cpu0.icache.tags.occ_percent::total 0.997624 # Average percentage of cache occupancy 327system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 328system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 329system.cpu0.icache.tags.replacements 784313 # number of replacements 330system.cpu0.icache.tags.sampled_refs 784825 # Sample count of references to valid blocks. 331system.cpu0.icache.tags.tag_accesses 13310138 # Number of tag accesses 332system.cpu0.icache.tags.tagsinuse 510.783510 # Cycle average of tags in use 333system.cpu0.icache.tags.total_refs 11740482 # Total number of references to valid blocks. 334system.cpu0.icache.tags.warmup_cycle 10281183000 # Cycle when the warmup percentage was hit. 335system.cpu0.idleCycles 80090425 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu0.ipc 0.068956 # IPC: instructions per cycle 337system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 338system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 339system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 341system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 344system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 345system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 346system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 348system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 349system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 350system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 351system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 352system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 354system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 355system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 356system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 357system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 358system.cpu0.itb.accesses 12532416 # DTB accesses 359system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 360system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu0.itb.flush_entries 1298 # Number of entries that have been flushed from TLB 362system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 363system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 364system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 365system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 366system.cpu0.itb.hits 12527520 # DTB hits 367system.cpu0.itb.inst_accesses 12532416 # ITB inst accesses 368system.cpu0.itb.inst_hits 12527520 # ITB inst hits 369system.cpu0.itb.inst_misses 4896 # ITB inst misses 370system.cpu0.itb.misses 4896 # DTB misses 371system.cpu0.itb.perms_faults 2037 # Number of TLB faults due to permissions restrictions 372system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu0.itb.read_accesses 0 # DTB read accesses 374system.cpu0.itb.read_hits 0 # DTB read hits 375system.cpu0.itb.read_misses 0 # DTB read misses 376system.cpu0.itb.write_accesses 0 # DTB write accesses 377system.cpu0.itb.write_hits 0 # DTB write hits 378system.cpu0.itb.write_misses 0 # DTB write misses 379system.cpu0.kern.inst.arm 0 # number of arm instructions executed 380system.cpu0.kern.inst.quiesce 50383 # number of quiesce instructions executed 381system.cpu0.numCycles 433838745 # number of cpu cycles simulated 382system.cpu0.numFetchSuspends 39517 # Number of times Execute suspended instruction fetching 383system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 384system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 385system.cpu0.quiesceCycles 1859796920 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 386system.cpu0.tickCycles 353748320 # Number of cycles that the CPU actually ticked 387system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 388system.cpu1.branchPred.BTBHitPct 75.016066 # BTB Hit Percentage 389system.cpu1.branchPred.BTBHits 3095670 # Number of BTB hits 390system.cpu1.branchPred.BTBLookups 4126676 # Number of BTB lookups 391system.cpu1.branchPred.RASInCorrect 63011 # Number of incorrect RAS predictions. 392system.cpu1.branchPred.condIncorrect 435091 # Number of conditional branches incorrect 393system.cpu1.branchPred.condPredicted 4929472 # Number of conditional branches predicted 394system.cpu1.branchPred.lookups 6347852 # Number of BP lookups 395system.cpu1.branchPred.usedRAS 662563 # Number of times the RAS was used to get a target. 396system.cpu1.committedInsts 31975502 # Number of instructions committed 397system.cpu1.committedOps 40322998 # Number of ops (including micro ops) committed 398system.cpu1.cpi 4.679096 # CPI: cycles per instruction 399system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89293 # number of LoadLockedReq accesses(hits+misses) 400system.cpu1.dcache.LoadLockedReq_accesses::total 89293 # number of LoadLockedReq accesses(hits+misses) 401system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8380.702313 # average LoadLockedReq miss latency 402system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8380.702313 # average LoadLockedReq miss latency 403system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6356.969903 # average LoadLockedReq mshr miss latency 404system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6356.969903 # average LoadLockedReq mshr miss latency 405system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78530 # number of LoadLockedReq hits 406system.cpu1.dcache.LoadLockedReq_hits::total 78530 # number of LoadLockedReq hits 407system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90201499 # number of LoadLockedReq miss cycles 408system.cpu1.dcache.LoadLockedReq_miss_latency::total 90201499 # number of LoadLockedReq miss cycles 409system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120536 # miss rate for LoadLockedReq accesses 410system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120536 # miss rate for LoadLockedReq accesses 411system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10763 # number of LoadLockedReq misses 412system.cpu1.dcache.LoadLockedReq_misses::total 10763 # number of LoadLockedReq misses 413system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 31 # number of LoadLockedReq MSHR hits 414system.cpu1.dcache.LoadLockedReq_mshr_hits::total 31 # number of LoadLockedReq MSHR hits 415system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68223001 # number of LoadLockedReq MSHR miss cycles 416system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68223001 # number of LoadLockedReq MSHR miss cycles 417system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120189 # mshr miss rate for LoadLockedReq accesses 418system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120189 # mshr miss rate for LoadLockedReq accesses 419system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10732 # number of LoadLockedReq MSHR misses 420system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10732 # number of LoadLockedReq MSHR misses 421system.cpu1.dcache.ReadReq_accesses::cpu1.inst 7361037 # number of ReadReq accesses(hits+misses) 422system.cpu1.dcache.ReadReq_accesses::total 7361037 # number of ReadReq accesses(hits+misses) 423system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14987.876806 # average ReadReq miss latency 424system.cpu1.dcache.ReadReq_avg_miss_latency::total 14987.876806 # average ReadReq miss latency 425system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11879.325450 # average ReadReq mshr miss latency 426system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11879.325450 # average ReadReq mshr miss latency 427system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 428system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 429system.cpu1.dcache.ReadReq_hits::cpu1.inst 7117762 # number of ReadReq hits 430system.cpu1.dcache.ReadReq_hits::total 7117762 # number of ReadReq hits 431system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3646175730 # number of ReadReq miss cycles 432system.cpu1.dcache.ReadReq_miss_latency::total 3646175730 # number of ReadReq miss cycles 433system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.033049 # miss rate for ReadReq accesses 434system.cpu1.dcache.ReadReq_miss_rate::total 0.033049 # miss rate for ReadReq accesses 435system.cpu1.dcache.ReadReq_misses::cpu1.inst 243275 # number of ReadReq misses 436system.cpu1.dcache.ReadReq_misses::total 243275 # number of ReadReq misses 437system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 37480 # number of ReadReq MSHR hits 438system.cpu1.dcache.ReadReq_mshr_hits::total 37480 # number of ReadReq MSHR hits 439system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2444705781 # number of ReadReq MSHR miss cycles 440system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2444705781 # number of ReadReq MSHR miss cycles 441system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for ReadReq accesses 442system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027957 # mshr miss rate for ReadReq accesses 443system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 205795 # number of ReadReq MSHR misses 444system.cpu1.dcache.ReadReq_mshr_misses::total 205795 # number of ReadReq MSHR misses 445system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11991518750 # number of ReadReq MSHR uncacheable cycles 446system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11991518750 # number of ReadReq MSHR uncacheable cycles 447system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89217 # number of StoreCondReq accesses(hits+misses) 448system.cpu1.dcache.StoreCondReq_accesses::total 89217 # number of StoreCondReq accesses(hits+misses) 449system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 5027.484214 # average StoreCondReq miss latency 450system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5027.484214 # average StoreCondReq miss latency 451system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 3027.420473 # average StoreCondReq mshr miss latency 452system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3027.420473 # average StoreCondReq mshr miss latency 453system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79145 # number of StoreCondReq hits 454system.cpu1.dcache.StoreCondReq_hits::total 79145 # number of StoreCondReq hits 455system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50636821 # number of StoreCondReq miss cycles 456system.cpu1.dcache.StoreCondReq_miss_latency::total 50636821 # number of StoreCondReq miss cycles 457system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.112893 # miss rate for StoreCondReq accesses 458system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112893 # miss rate for StoreCondReq accesses 459system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10072 # number of StoreCondReq misses 460system.cpu1.dcache.StoreCondReq_misses::total 10072 # number of StoreCondReq misses 461system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30492179 # number of StoreCondReq MSHR miss cycles 462system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30492179 # number of StoreCondReq MSHR miss cycles 463system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.112893 # mshr miss rate for StoreCondReq accesses 464system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112893 # mshr miss rate for StoreCondReq accesses 465system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10072 # number of StoreCondReq MSHR misses 466system.cpu1.dcache.StoreCondReq_mshr_misses::total 10072 # number of StoreCondReq MSHR misses 467system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4649691 # number of WriteReq accesses(hits+misses) 468system.cpu1.dcache.WriteReq_accesses::total 4649691 # number of WriteReq accesses(hits+misses) 469system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38966.175425 # average WriteReq miss latency 470system.cpu1.dcache.WriteReq_avg_miss_latency::total 38966.175425 # average WriteReq miss latency 471system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.531262 # average WriteReq mshr miss latency 472system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.531262 # average WriteReq mshr miss latency 473system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 474system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 475system.cpu1.dcache.WriteReq_hits::cpu1.inst 4425658 # number of WriteReq hits 476system.cpu1.dcache.WriteReq_hits::total 4425658 # number of WriteReq hits 477system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8729709179 # number of WriteReq miss cycles 478system.cpu1.dcache.WriteReq_miss_latency::total 8729709179 # number of WriteReq miss cycles 479system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048182 # miss rate for WriteReq accesses 480system.cpu1.dcache.WriteReq_miss_rate::total 0.048182 # miss rate for WriteReq accesses 481system.cpu1.dcache.WriteReq_misses::cpu1.inst 224033 # number of WriteReq misses 482system.cpu1.dcache.WriteReq_misses::total 224033 # number of WriteReq misses 483system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98146 # number of WriteReq MSHR hits 484system.cpu1.dcache.WriteReq_mshr_hits::total 98146 # number of WriteReq MSHR hits 485system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4132055880 # number of WriteReq MSHR miss cycles 486system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4132055880 # number of WriteReq MSHR miss cycles 487system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027074 # mshr miss rate for WriteReq accesses 488system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027074 # mshr miss rate for WriteReq accesses 489system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125887 # number of WriteReq MSHR misses 490system.cpu1.dcache.WriteReq_mshr_misses::total 125887 # number of WriteReq MSHR misses 491system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672578609 # number of WriteReq MSHR uncacheable cycles 492system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672578609 # number of WriteReq MSHR uncacheable cycles 493system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 494system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 495system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 496system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 498system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 499system.cpu1.dcache.cache_copies 0 # number of cache copies performed 500system.cpu1.dcache.demand_accesses::cpu1.inst 12010728 # number of demand (read+write) accesses 501system.cpu1.dcache.demand_accesses::total 12010728 # number of demand (read+write) accesses 502system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26483.357676 # average overall miss latency 503system.cpu1.dcache.demand_avg_miss_latency::total 26483.357676 # average overall miss latency 504system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19828.515449 # average overall mshr miss latency 505system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19828.515449 # average overall mshr miss latency 506system.cpu1.dcache.demand_hits::cpu1.inst 11543420 # number of demand (read+write) hits 507system.cpu1.dcache.demand_hits::total 11543420 # number of demand (read+write) hits 508system.cpu1.dcache.demand_miss_latency::cpu1.inst 12375884909 # number of demand (read+write) miss cycles 509system.cpu1.dcache.demand_miss_latency::total 12375884909 # number of demand (read+write) miss cycles 510system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038908 # miss rate for demand accesses 511system.cpu1.dcache.demand_miss_rate::total 0.038908 # miss rate for demand accesses 512system.cpu1.dcache.demand_misses::cpu1.inst 467308 # number of demand (read+write) misses 513system.cpu1.dcache.demand_misses::total 467308 # number of demand (read+write) misses 514system.cpu1.dcache.demand_mshr_hits::cpu1.inst 135626 # number of demand (read+write) MSHR hits 515system.cpu1.dcache.demand_mshr_hits::total 135626 # number of demand (read+write) MSHR hits 516system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6576761661 # number of demand (read+write) MSHR miss cycles 517system.cpu1.dcache.demand_mshr_miss_latency::total 6576761661 # number of demand (read+write) MSHR miss cycles 518system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.027615 # mshr miss rate for demand accesses 519system.cpu1.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses 520system.cpu1.dcache.demand_mshr_misses::cpu1.inst 331682 # number of demand (read+write) MSHR misses 521system.cpu1.dcache.demand_mshr_misses::total 331682 # number of demand (read+write) MSHR misses 522system.cpu1.dcache.fast_writes 0 # number of fast writes performed 523system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 524system.cpu1.dcache.overall_accesses::cpu1.inst 12010728 # number of overall (read+write) accesses 525system.cpu1.dcache.overall_accesses::total 12010728 # number of overall (read+write) accesses 526system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26483.357676 # average overall miss latency 527system.cpu1.dcache.overall_avg_miss_latency::total 26483.357676 # average overall miss latency 528system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19828.515449 # average overall mshr miss latency 529system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19828.515449 # average overall mshr miss latency 530system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 531system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 532system.cpu1.dcache.overall_hits::cpu1.inst 11543420 # number of overall hits 533system.cpu1.dcache.overall_hits::total 11543420 # number of overall hits 534system.cpu1.dcache.overall_miss_latency::cpu1.inst 12375884909 # number of overall miss cycles 535system.cpu1.dcache.overall_miss_latency::total 12375884909 # number of overall miss cycles 536system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038908 # miss rate for overall accesses 537system.cpu1.dcache.overall_miss_rate::total 0.038908 # miss rate for overall accesses 538system.cpu1.dcache.overall_misses::cpu1.inst 467308 # number of overall misses 539system.cpu1.dcache.overall_misses::total 467308 # number of overall misses 540system.cpu1.dcache.overall_mshr_hits::cpu1.inst 135626 # number of overall MSHR hits 541system.cpu1.dcache.overall_mshr_hits::total 135626 # number of overall MSHR hits 542system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6576761661 # number of overall MSHR miss cycles 543system.cpu1.dcache.overall_mshr_miss_latency::total 6576761661 # number of overall MSHR miss cycles 544system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.027615 # mshr miss rate for overall accesses 545system.cpu1.dcache.overall_mshr_miss_rate::total 0.027615 # mshr miss rate for overall accesses 546system.cpu1.dcache.overall_mshr_misses::cpu1.inst 331682 # number of overall MSHR misses 547system.cpu1.dcache.overall_mshr_misses::total 331682 # number of overall MSHR misses 548system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36664097359 # number of overall MSHR uncacheable cycles 549system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36664097359 # number of overall MSHR uncacheable cycles 550system.cpu1.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 551system.cpu1.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 552system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 553system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 554system.cpu1.dcache.tags.avg_refs 38.928946 # Average number of references to valid blocks. 555system.cpu1.dcache.tags.data_accesses 49080911 # Number of data accesses 556system.cpu1.dcache.tags.occ_blocks::cpu1.inst 448.678844 # Average occupied blocks per requestor 557system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.876326 # Average percentage of cache occupancy 558system.cpu1.dcache.tags.occ_percent::total 0.876326 # Average percentage of cache occupancy 559system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 560system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 561system.cpu1.dcache.tags.replacements 300905 # number of replacements 562system.cpu1.dcache.tags.sampled_refs 301417 # Sample count of references to valid blocks. 563system.cpu1.dcache.tags.tag_accesses 49080911 # Number of tag accesses 564system.cpu1.dcache.tags.tagsinuse 448.678844 # Cycle average of tags in use 565system.cpu1.dcache.tags.total_refs 11733846 # Total number of references to valid blocks. 566system.cpu1.dcache.tags.warmup_cycle 76695286250 # Cycle when the warmup percentage was hit. 567system.cpu1.dcache.writebacks::writebacks 270884 # number of writebacks 568system.cpu1.dcache.writebacks::total 270884 # number of writebacks 569system.cpu1.discardedOps 1803588 # Number of ops (including micro ops) which were discarded before commit 570system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 571system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 572system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 573system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 574system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 575system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 576system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 577system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 578system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 579system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 580system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 581system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 582system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 583system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 584system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 585system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 586system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 587system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 588system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 589system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 590system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 591system.cpu1.dtb.accesses 13158810 # DTB accesses 592system.cpu1.dtb.align_faults 2430 # Number of TLB faults due to alignment restrictions 593system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 594system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB 595system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 596system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 597system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 598system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 599system.cpu1.dtb.hits 13135953 # DTB hits 600system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 601system.cpu1.dtb.inst_hits 0 # ITB inst hits 602system.cpu1.dtb.inst_misses 0 # ITB inst misses 603system.cpu1.dtb.misses 22857 # DTB misses 604system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions 605system.cpu1.dtb.prefetch_faults 234 # Number of TLB faults due to prefetch 606system.cpu1.dtb.read_accesses 7605254 # DTB read accesses 607system.cpu1.dtb.read_hits 7584952 # DTB read hits 608system.cpu1.dtb.read_misses 20302 # DTB read misses 609system.cpu1.dtb.write_accesses 5553556 # DTB write accesses 610system.cpu1.dtb.write_hits 5551001 # DTB write hits 611system.cpu1.dtb.write_misses 2555 # DTB write misses 612system.cpu1.icache.ReadReq_accesses::cpu1.inst 11366597 # number of ReadReq accesses(hits+misses) 613system.cpu1.icache.ReadReq_accesses::total 11366597 # number of ReadReq accesses(hits+misses) 614system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.195767 # average ReadReq miss latency 615system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.195767 # average ReadReq miss latency 616system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.787952 # average ReadReq mshr miss latency 617system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11384.787952 # average ReadReq mshr miss latency 618system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 619system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 620system.cpu1.icache.ReadReq_hits::cpu1.inst 10566141 # number of ReadReq hits 621system.cpu1.icache.ReadReq_hits::total 10566141 # number of ReadReq hits 622system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10715861175 # number of ReadReq miss cycles 623system.cpu1.icache.ReadReq_miss_latency::total 10715861175 # number of ReadReq miss cycles 624system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070422 # miss rate for ReadReq accesses 625system.cpu1.icache.ReadReq_miss_rate::total 0.070422 # miss rate for ReadReq accesses 626system.cpu1.icache.ReadReq_misses::cpu1.inst 800456 # number of ReadReq misses 627system.cpu1.icache.ReadReq_misses::total 800456 # number of ReadReq misses 628system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9113021825 # number of ReadReq MSHR miss cycles 629system.cpu1.icache.ReadReq_mshr_miss_latency::total 9113021825 # number of ReadReq MSHR miss cycles 630system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070422 # mshr miss rate for ReadReq accesses 631system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070422 # mshr miss rate for ReadReq accesses 632system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 800456 # number of ReadReq MSHR misses 633system.cpu1.icache.ReadReq_mshr_misses::total 800456 # number of ReadReq MSHR misses 634system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5643750 # number of ReadReq MSHR uncacheable cycles 635system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5643750 # number of ReadReq MSHR uncacheable cycles 636system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 637system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 638system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu1.icache.cache_copies 0 # number of cache copies performed 643system.cpu1.icache.demand_accesses::cpu1.inst 11366597 # number of demand (read+write) accesses 644system.cpu1.icache.demand_accesses::total 11366597 # number of demand (read+write) accesses 645system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.195767 # average overall miss latency 646system.cpu1.icache.demand_avg_miss_latency::total 13387.195767 # average overall miss latency 647system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.787952 # average overall mshr miss latency 648system.cpu1.icache.demand_avg_mshr_miss_latency::total 11384.787952 # average overall mshr miss latency 649system.cpu1.icache.demand_hits::cpu1.inst 10566141 # number of demand (read+write) hits 650system.cpu1.icache.demand_hits::total 10566141 # number of demand (read+write) hits 651system.cpu1.icache.demand_miss_latency::cpu1.inst 10715861175 # number of demand (read+write) miss cycles 652system.cpu1.icache.demand_miss_latency::total 10715861175 # number of demand (read+write) miss cycles 653system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070422 # miss rate for demand accesses 654system.cpu1.icache.demand_miss_rate::total 0.070422 # miss rate for demand accesses 655system.cpu1.icache.demand_misses::cpu1.inst 800456 # number of demand (read+write) misses 656system.cpu1.icache.demand_misses::total 800456 # number of demand (read+write) misses 657system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9113021825 # number of demand (read+write) MSHR miss cycles 658system.cpu1.icache.demand_mshr_miss_latency::total 9113021825 # number of demand (read+write) MSHR miss cycles 659system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070422 # mshr miss rate for demand accesses 660system.cpu1.icache.demand_mshr_miss_rate::total 0.070422 # mshr miss rate for demand accesses 661system.cpu1.icache.demand_mshr_misses::cpu1.inst 800456 # number of demand (read+write) MSHR misses 662system.cpu1.icache.demand_mshr_misses::total 800456 # number of demand (read+write) MSHR misses 663system.cpu1.icache.fast_writes 0 # number of fast writes performed 664system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu1.icache.overall_accesses::cpu1.inst 11366597 # number of overall (read+write) accesses 666system.cpu1.icache.overall_accesses::total 11366597 # number of overall (read+write) accesses 667system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.195767 # average overall miss latency 668system.cpu1.icache.overall_avg_miss_latency::total 13387.195767 # average overall miss latency 669system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.787952 # average overall mshr miss latency 670system.cpu1.icache.overall_avg_mshr_miss_latency::total 11384.787952 # average overall mshr miss latency 671system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 672system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 673system.cpu1.icache.overall_hits::cpu1.inst 10566141 # number of overall hits 674system.cpu1.icache.overall_hits::total 10566141 # number of overall hits 675system.cpu1.icache.overall_miss_latency::cpu1.inst 10715861175 # number of overall miss cycles 676system.cpu1.icache.overall_miss_latency::total 10715861175 # number of overall miss cycles 677system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070422 # miss rate for overall accesses 678system.cpu1.icache.overall_miss_rate::total 0.070422 # miss rate for overall accesses 679system.cpu1.icache.overall_misses::cpu1.inst 800456 # number of overall misses 680system.cpu1.icache.overall_misses::total 800456 # number of overall misses 681system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9113021825 # number of overall MSHR miss cycles 682system.cpu1.icache.overall_mshr_miss_latency::total 9113021825 # number of overall MSHR miss cycles 683system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070422 # mshr miss rate for overall accesses 684system.cpu1.icache.overall_mshr_miss_rate::total 0.070422 # mshr miss rate for overall accesses 685system.cpu1.icache.overall_mshr_misses::cpu1.inst 800456 # number of overall MSHR misses 686system.cpu1.icache.overall_mshr_misses::total 800456 # number of overall MSHR misses 687system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5643750 # number of overall MSHR uncacheable cycles 688system.cpu1.icache.overall_mshr_uncacheable_latency::total 5643750 # number of overall MSHR uncacheable cycles 689system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 690system.cpu1.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 691system.cpu1.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id 692system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 693system.cpu1.icache.tags.avg_refs 13.200169 # Average number of references to valid blocks. 694system.cpu1.icache.tags.data_accesses 12167052 # Number of data accesses 695system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.617049 # Average occupied blocks per requestor 696system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938705 # Average percentage of cache occupancy 697system.cpu1.icache.tags.occ_percent::total 0.938705 # Average percentage of cache occupancy 698system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 699system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 700system.cpu1.icache.tags.replacements 799943 # number of replacements 701system.cpu1.icache.tags.sampled_refs 800455 # Sample count of references to valid blocks. 702system.cpu1.icache.tags.tag_accesses 12167052 # Number of tag accesses 703system.cpu1.icache.tags.tagsinuse 480.617049 # Cycle average of tags in use 704system.cpu1.icache.tags.total_refs 10566141 # Total number of references to valid blocks. 705system.cpu1.icache.tags.warmup_cycle 82057257250 # Cycle when the warmup percentage was hit. 706system.cpu1.idleCycles 29483115 # Total number of cycles that the CPU has spent unscheduled due to idling 707system.cpu1.ipc 0.213717 # IPC: instructions per cycle 708system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 709system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 710system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 711system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 712system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 713system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 714system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 715system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 716system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 717system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 718system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 719system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 720system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 721system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 722system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 723system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 724system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 725system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 726system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 727system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 728system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 729system.cpu1.itb.accesses 11372965 # DTB accesses 730system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 731system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 732system.cpu1.itb.flush_entries 1189 # Number of entries that have been flushed from TLB 733system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 734system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 735system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 736system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 737system.cpu1.itb.hits 11368674 # DTB hits 738system.cpu1.itb.inst_accesses 11372965 # ITB inst accesses 739system.cpu1.itb.inst_hits 11368674 # ITB inst hits 740system.cpu1.itb.inst_misses 4291 # ITB inst misses 741system.cpu1.itb.misses 4291 # DTB misses 742system.cpu1.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions 743system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 744system.cpu1.itb.read_accesses 0 # DTB read accesses 745system.cpu1.itb.read_hits 0 # DTB read hits 746system.cpu1.itb.read_misses 0 # DTB read misses 747system.cpu1.itb.write_accesses 0 # DTB write accesses 748system.cpu1.itb.write_hits 0 # DTB write hits 749system.cpu1.itb.write_misses 0 # DTB write misses 750system.cpu1.kern.inst.arm 0 # number of arm instructions executed 751system.cpu1.kern.inst.quiesce 40529 # number of quiesce instructions executed 752system.cpu1.numCycles 149616439 # number of cpu cycles simulated 753system.cpu1.numFetchSuspends 40001 # Number of times Execute suspended instruction fetching 754system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 755system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 756system.cpu1.quiesceCycles 2144894120 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 757system.cpu1.tickCycles 120133324 # Number of cycles that the CPU actually ticked 758system.cpu_clk_domain.clock 500 # Clock period in ticks 759system.iobus.data_through_bus 52721660 # Total data (bytes) 760system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) 761system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8050 # Packet count per connected master and slave (bytes) 762system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 763system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) 764system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 765system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 766system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes) 767system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 768system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 769system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 770system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 771system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 772system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 773system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 774system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 775system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 776system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 777system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 778system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 779system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 780system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 781system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 782system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 783system.iobus.pkt_count_system.bridge.master::total 2382664 # Packet count per connected master and slave (bytes) 784system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) 785system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) 786system.iobus.pkt_count::total 14965576 # Packet count per connected master and slave (bytes) 787system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) 788system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 789system.iobus.reqLayer1.occupancy 4031000 # Layer occupancy (ticks) 790system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 791system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 792system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 793system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 794system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 795system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 796system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 797system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 798system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 799system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 800system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 801system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 802system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 803system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 804system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 805system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 806system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 807system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 808system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 809system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 810system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 811system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 812system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 813system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 814system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 815system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 816system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 817system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 818system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 819system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 820system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 821system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) 822system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 823system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks) 824system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 825system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 826system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 827system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 828system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 829system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks) 830system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 831system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 832system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 833system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 834system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 835system.iobus.respLayer0.occupancy 2374698000 # Layer occupancy (ticks) 836system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) 837system.iobus.respLayer1.occupancy 15868889251 # Layer occupancy (ticks) 838system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) 839system.iobus.throughput 45973431 # Throughput (bytes/s) 840system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) 841system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16100 # Cumulative packet size per connected master and slave (bytes) 842system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 843system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) 844system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 845system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 846system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes) 847system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 848system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 849system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 850system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 851system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 852system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 853system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 854system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 855system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 856system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 857system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 858system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 859system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 860system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 861system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 862system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 863system.iobus.tot_pkt_size_system.bridge.master::total 2390012 # Cumulative packet size per connected master and slave (bytes) 864system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) 865system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) 866system.iobus.tot_pkt_size::total 52721660 # Cumulative packet size per connected master and slave (bytes) 867system.iobus.trans_dist::ReadReq 7474822 # Transaction distribution 868system.iobus.trans_dist::ReadResp 7474822 # Transaction distribution 869system.iobus.trans_dist::WriteReq 7966 # Transaction distribution 870system.iobus.trans_dist::WriteResp 7966 # Transaction distribution 871system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 872system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 873system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722546651251 # number of ReadReq MSHR uncacheable cycles 874system.iocache.ReadReq_mshr_uncacheable_latency::total 722546651251 # number of ReadReq MSHR uncacheable cycles 875system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 878system.iocache.blocked::no_targets 0 # number of cycles access was blocked 879system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.iocache.cache_copies 0 # number of cache copies performed 882system.iocache.fast_writes 0 # number of fast writes performed 883system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 884system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 885system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 886system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722546651251 # number of overall MSHR uncacheable cycles 887system.iocache.overall_mshr_uncacheable_latency::total 722546651251 # number of overall MSHR uncacheable cycles 888system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 889system.iocache.tags.data_accesses 0 # Number of data accesses 890system.iocache.tags.replacements 0 # number of replacements 891system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 892system.iocache.tags.tag_accesses 0 # Number of tag accesses 893system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 894system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 895system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 896system.l2c.ReadExReq_accesses::cpu0.inst 151088 # number of ReadExReq accesses(hits+misses) 897system.l2c.ReadExReq_accesses::cpu1.inst 98363 # number of ReadExReq accesses(hits+misses) 898system.l2c.ReadExReq_accesses::total 249451 # number of ReadExReq accesses(hits+misses) 899system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68340.802831 # average ReadExReq miss latency 900system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70836.135654 # average ReadExReq miss latency 901system.l2c.ReadExReq_avg_miss_latency::total 69186.818320 # average ReadExReq miss latency 902system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55784.041664 # average ReadExReq mshr miss latency 903system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58278.521386 # average ReadExReq mshr miss latency 904system.l2c.ReadExReq_avg_mshr_miss_latency::total 56629.767918 # average ReadExReq mshr miss latency 905system.l2c.ReadExReq_hits::cpu0.inst 58609 # number of ReadExReq hits 906system.l2c.ReadExReq_hits::cpu1.inst 50926 # number of ReadExReq hits 907system.l2c.ReadExReq_hits::total 109535 # number of ReadExReq hits 908system.l2c.ReadExReq_miss_latency::cpu0.inst 6320089105 # number of ReadExReq miss cycles 909system.l2c.ReadExReq_miss_latency::cpu1.inst 3360253767 # number of ReadExReq miss cycles 910system.l2c.ReadExReq_miss_latency::total 9680342872 # number of ReadExReq miss cycles 911system.l2c.ReadExReq_miss_rate::cpu0.inst 0.612087 # miss rate for ReadExReq accesses 912system.l2c.ReadExReq_miss_rate::cpu1.inst 0.482265 # miss rate for ReadExReq accesses 913system.l2c.ReadExReq_miss_rate::total 0.560896 # miss rate for ReadExReq accesses 914system.l2c.ReadExReq_misses::cpu0.inst 92479 # number of ReadExReq misses 915system.l2c.ReadExReq_misses::cpu1.inst 47437 # number of ReadExReq misses 916system.l2c.ReadExReq_misses::total 139916 # number of ReadExReq misses 917system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5158852389 # number of ReadExReq MSHR miss cycles 918system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2764558219 # number of ReadExReq MSHR miss cycles 919system.l2c.ReadExReq_mshr_miss_latency::total 7923410608 # number of ReadExReq MSHR miss cycles 920system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.612087 # mshr miss rate for ReadExReq accesses 921system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.482265 # mshr miss rate for ReadExReq accesses 922system.l2c.ReadExReq_mshr_miss_rate::total 0.560896 # mshr miss rate for ReadExReq accesses 923system.l2c.ReadExReq_mshr_misses::cpu0.inst 92479 # number of ReadExReq MSHR misses 924system.l2c.ReadExReq_mshr_misses::cpu1.inst 47437 # number of ReadExReq MSHR misses 925system.l2c.ReadExReq_mshr_misses::total 139916 # number of ReadExReq MSHR misses 926system.l2c.ReadReq_accesses::cpu0.dtb.walker 28623 # number of ReadReq accesses(hits+misses) 927system.l2c.ReadReq_accesses::cpu0.itb.walker 6686 # number of ReadReq accesses(hits+misses) 928system.l2c.ReadReq_accesses::cpu0.inst 972984 # number of ReadReq accesses(hits+misses) 929system.l2c.ReadReq_accesses::cpu1.dtb.walker 26977 # number of ReadReq accesses(hits+misses) 930system.l2c.ReadReq_accesses::cpu1.itb.walker 5385 # number of ReadReq accesses(hits+misses) 931system.l2c.ReadReq_accesses::cpu1.inst 980230 # number of ReadReq accesses(hits+misses) 932system.l2c.ReadReq_accesses::total 2020885 # number of ReadReq accesses(hits+misses) 933system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75197.368421 # average ReadReq miss latency 934system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 935system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70701.604050 # average ReadReq miss latency 936system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88575 # average ReadReq miss latency 937system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75547.349058 # average ReadReq miss latency 938system.l2c.ReadReq_avg_miss_latency::total 72536.539775 # average ReadReq miss latency 939system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579 # average ReadReq mshr miss latency 940system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 941system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58187.997185 # average ReadReq mshr miss latency 942system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76175 # average ReadReq mshr miss latency 943system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63048.000202 # average ReadReq mshr miss latency 944system.l2c.ReadReq_avg_mshr_miss_latency::total 60029.934536 # average ReadReq mshr miss latency 945system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 946system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 947system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 948system.l2c.ReadReq_hits::cpu0.dtb.walker 28604 # number of ReadReq hits 949system.l2c.ReadReq_hits::cpu0.itb.walker 6684 # number of ReadReq hits 950system.l2c.ReadReq_hits::cpu0.inst 956588 # number of ReadReq hits 951system.l2c.ReadReq_hits::cpu1.dtb.walker 26967 # number of ReadReq hits 952system.l2c.ReadReq_hits::cpu1.itb.walker 5385 # number of ReadReq hits 953system.l2c.ReadReq_hits::cpu1.inst 970309 # number of ReadReq hits 954system.l2c.ReadReq_hits::total 1994537 # number of ReadReq hits 955system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1428750 # number of ReadReq miss cycles 956system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 957system.l2c.ReadReq_miss_latency::cpu0.inst 1159223500 # number of ReadReq miss cycles 958system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 885750 # number of ReadReq miss cycles 959system.l2c.ReadReq_miss_latency::cpu1.inst 749505250 # number of ReadReq miss cycles 960system.l2c.ReadReq_miss_latency::total 1911192750 # number of ReadReq miss cycles 961system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000664 # miss rate for ReadReq accesses 962system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000299 # miss rate for ReadReq accesses 963system.l2c.ReadReq_miss_rate::cpu0.inst 0.016851 # miss rate for ReadReq accesses 964system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000371 # miss rate for ReadReq accesses 965system.l2c.ReadReq_miss_rate::cpu1.inst 0.010121 # miss rate for ReadReq accesses 966system.l2c.ReadReq_miss_rate::total 0.013038 # miss rate for ReadReq accesses 967system.l2c.ReadReq_misses::cpu0.dtb.walker 19 # number of ReadReq misses 968system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 969system.l2c.ReadReq_misses::cpu0.inst 16396 # number of ReadReq misses 970system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses 971system.l2c.ReadReq_misses::cpu1.inst 9921 # number of ReadReq misses 972system.l2c.ReadReq_misses::total 26348 # number of ReadReq misses 973system.l2c.ReadReq_mshr_hits::cpu0.inst 54 # number of ReadReq MSHR hits 974system.l2c.ReadReq_mshr_hits::cpu1.inst 20 # number of ReadReq MSHR hits 975system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 976system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1193250 # number of ReadReq MSHR miss cycles 977system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 978system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 950908250 # number of ReadReq MSHR miss cycles 979system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 761750 # number of ReadReq MSHR miss cycles 980system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 624238250 # number of ReadReq MSHR miss cycles 981system.l2c.ReadReq_mshr_miss_latency::total 1577226500 # number of ReadReq MSHR miss cycles 982system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000664 # mshr miss rate for ReadReq accesses 983system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for ReadReq accesses 984system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016796 # mshr miss rate for ReadReq accesses 985system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000371 # mshr miss rate for ReadReq accesses 986system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010101 # mshr miss rate for ReadReq accesses 987system.l2c.ReadReq_mshr_miss_rate::total 0.013001 # mshr miss rate for ReadReq accesses 988system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 19 # number of ReadReq MSHR misses 989system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 990system.l2c.ReadReq_mshr_misses::cpu0.inst 16342 # number of ReadReq MSHR misses 991system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses 992system.l2c.ReadReq_mshr_misses::cpu1.inst 9901 # number of ReadReq MSHR misses 993system.l2c.ReadReq_mshr_misses::total 26274 # number of ReadReq MSHR misses 994system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156403460492 # number of ReadReq MSHR uncacheable cycles 995system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10977229000 # number of ReadReq MSHR uncacheable cycles 996system.l2c.ReadReq_mshr_uncacheable_latency::total 167380689492 # number of ReadReq MSHR uncacheable cycles 997system.l2c.SCUpgradeReq_accesses::cpu0.inst 889 # number of SCUpgradeReq accesses(hits+misses) 998system.l2c.SCUpgradeReq_accesses::cpu1.inst 428 # number of SCUpgradeReq accesses(hits+misses) 999system.l2c.SCUpgradeReq_accesses::total 1317 # number of SCUpgradeReq accesses(hits+misses) 1000system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 821.973412 # average SCUpgradeReq miss latency 1001system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 6364.211838 # average SCUpgradeReq miss latency 1002system.l2c.SCUpgradeReq_avg_miss_latency::total 2604.597194 # average SCUpgradeReq miss latency 1003system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10035.706056 # average SCUpgradeReq mshr miss latency 1004system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.557632 # average SCUpgradeReq mshr miss latency 1005system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.044088 # average SCUpgradeReq mshr miss latency 1006system.l2c.SCUpgradeReq_hits::cpu0.inst 212 # number of SCUpgradeReq hits 1007system.l2c.SCUpgradeReq_hits::cpu1.inst 107 # number of SCUpgradeReq hits 1008system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits 1009system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 556476 # number of SCUpgradeReq miss cycles 1010system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2042912 # number of SCUpgradeReq miss cycles 1011system.l2c.SCUpgradeReq_miss_latency::total 2599388 # number of SCUpgradeReq miss cycles 1012system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.761530 # miss rate for SCUpgradeReq accesses 1013system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.750000 # miss rate for SCUpgradeReq accesses 1014system.l2c.SCUpgradeReq_miss_rate::total 0.757783 # miss rate for SCUpgradeReq accesses 1015system.l2c.SCUpgradeReq_misses::cpu0.inst 677 # number of SCUpgradeReq misses 1016system.l2c.SCUpgradeReq_misses::cpu1.inst 321 # number of SCUpgradeReq misses 1017system.l2c.SCUpgradeReq_misses::total 998 # number of SCUpgradeReq misses 1018system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6794173 # number of SCUpgradeReq MSHR miss cycles 1019system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3210821 # number of SCUpgradeReq MSHR miss cycles 1020system.l2c.SCUpgradeReq_mshr_miss_latency::total 10004994 # number of SCUpgradeReq MSHR miss cycles 1021system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.761530 # mshr miss rate for SCUpgradeReq accesses 1022system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.750000 # mshr miss rate for SCUpgradeReq accesses 1023system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.757783 # mshr miss rate for SCUpgradeReq accesses 1024system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 677 # number of SCUpgradeReq MSHR misses 1025system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 321 # number of SCUpgradeReq MSHR misses 1026system.l2c.SCUpgradeReq_mshr_misses::total 998 # number of SCUpgradeReq MSHR misses 1027system.l2c.UpgradeReq_accesses::cpu0.inst 5825 # number of UpgradeReq accesses(hits+misses) 1028system.l2c.UpgradeReq_accesses::cpu1.inst 5183 # number of UpgradeReq accesses(hits+misses) 1029system.l2c.UpgradeReq_accesses::total 11008 # number of UpgradeReq accesses(hits+misses) 1030system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1631.426752 # average UpgradeReq miss latency 1031system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3342.816847 # average UpgradeReq miss latency 1032system.l2c.UpgradeReq_avg_miss_latency::total 2419.591886 # average UpgradeReq miss latency 1033system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10026.163345 # average UpgradeReq mshr miss latency 1034system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10005.691697 # average UpgradeReq mshr miss latency 1035system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.735314 # average UpgradeReq mshr miss latency 1036system.l2c.UpgradeReq_hits::cpu0.inst 958 # number of UpgradeReq hits 1037system.l2c.UpgradeReq_hits::cpu1.inst 1028 # number of UpgradeReq hits 1038system.l2c.UpgradeReq_hits::total 1986 # number of UpgradeReq hits 1039system.l2c.UpgradeReq_miss_latency::cpu0.inst 7940154 # number of UpgradeReq miss cycles 1040system.l2c.UpgradeReq_miss_latency::cpu1.inst 13889404 # number of UpgradeReq miss cycles 1041system.l2c.UpgradeReq_miss_latency::total 21829558 # number of UpgradeReq miss cycles 1042system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.835536 # miss rate for UpgradeReq accesses 1043system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.801659 # miss rate for UpgradeReq accesses 1044system.l2c.UpgradeReq_miss_rate::total 0.819586 # miss rate for UpgradeReq accesses 1045system.l2c.UpgradeReq_misses::cpu0.inst 4867 # number of UpgradeReq misses 1046system.l2c.UpgradeReq_misses::cpu1.inst 4155 # number of UpgradeReq misses 1047system.l2c.UpgradeReq_misses::total 9022 # number of UpgradeReq misses 1048system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48797337 # number of UpgradeReq MSHR miss cycles 1049system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 41573649 # number of UpgradeReq MSHR miss cycles 1050system.l2c.UpgradeReq_mshr_miss_latency::total 90370986 # number of UpgradeReq MSHR miss cycles 1051system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.835536 # mshr miss rate for UpgradeReq accesses 1052system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.801659 # mshr miss rate for UpgradeReq accesses 1053system.l2c.UpgradeReq_mshr_miss_rate::total 0.819586 # mshr miss rate for UpgradeReq accesses 1054system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4867 # number of UpgradeReq MSHR misses 1055system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4155 # number of UpgradeReq MSHR misses 1056system.l2c.UpgradeReq_mshr_misses::total 9022 # number of UpgradeReq MSHR misses 1057system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1058system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1059system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1060system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364457493 # number of WriteReq MSHR uncacheable cycles 1061system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414956890 # number of WriteReq MSHR uncacheable cycles 1062system.l2c.WriteReq_mshr_uncacheable_latency::total 16779414383 # number of WriteReq MSHR uncacheable cycles 1063system.l2c.Writeback_accesses::writebacks 577052 # number of Writeback accesses(hits+misses) 1064system.l2c.Writeback_accesses::total 577052 # number of Writeback accesses(hits+misses) 1065system.l2c.Writeback_hits::writebacks 577052 # number of Writeback hits 1066system.l2c.Writeback_hits::total 577052 # number of Writeback hits 1067system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1068system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1069system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1071system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1072system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1073system.l2c.cache_copies 0 # number of cache copies performed 1074system.l2c.demand_accesses::cpu0.dtb.walker 28623 # number of demand (read+write) accesses 1075system.l2c.demand_accesses::cpu0.itb.walker 6686 # number of demand (read+write) accesses 1076system.l2c.demand_accesses::cpu0.inst 1124072 # number of demand (read+write) accesses 1077system.l2c.demand_accesses::cpu1.dtb.walker 26977 # number of demand (read+write) accesses 1078system.l2c.demand_accesses::cpu1.itb.walker 5385 # number of demand (read+write) accesses 1079system.l2c.demand_accesses::cpu1.inst 1078593 # number of demand (read+write) accesses 1080system.l2c.demand_accesses::total 2270336 # number of demand (read+write) accesses 1081system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75197.368421 # average overall miss latency 1082system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 1083system.l2c.demand_avg_miss_latency::cpu0.inst 68696.327026 # average overall miss latency 1084system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88575 # average overall miss latency 1085system.l2c.demand_avg_miss_latency::cpu1.inst 71651.016720 # average overall miss latency 1086system.l2c.demand_avg_miss_latency::total 69717.651578 # average overall miss latency 1087system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579 # average overall mshr miss latency 1088system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1089system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56145.051406 # average overall mshr miss latency 1090system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76175 # average overall mshr miss latency 1091system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59102.104521 # average overall mshr miss latency 1092system.l2c.demand_avg_mshr_miss_latency::total 57167.321187 # average overall mshr miss latency 1093system.l2c.demand_hits::cpu0.dtb.walker 28604 # number of demand (read+write) hits 1094system.l2c.demand_hits::cpu0.itb.walker 6684 # number of demand (read+write) hits 1095system.l2c.demand_hits::cpu0.inst 1015197 # number of demand (read+write) hits 1096system.l2c.demand_hits::cpu1.dtb.walker 26967 # number of demand (read+write) hits 1097system.l2c.demand_hits::cpu1.itb.walker 5385 # number of demand (read+write) hits 1098system.l2c.demand_hits::cpu1.inst 1021235 # number of demand (read+write) hits 1099system.l2c.demand_hits::total 2104072 # number of demand (read+write) hits 1100system.l2c.demand_miss_latency::cpu0.dtb.walker 1428750 # number of demand (read+write) miss cycles 1101system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 1102system.l2c.demand_miss_latency::cpu0.inst 7479312605 # number of demand (read+write) miss cycles 1103system.l2c.demand_miss_latency::cpu1.dtb.walker 885750 # number of demand (read+write) miss cycles 1104system.l2c.demand_miss_latency::cpu1.inst 4109759017 # number of demand (read+write) miss cycles 1105system.l2c.demand_miss_latency::total 11591535622 # number of demand (read+write) miss cycles 1106system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000664 # miss rate for demand accesses 1107system.l2c.demand_miss_rate::cpu0.itb.walker 0.000299 # miss rate for demand accesses 1108system.l2c.demand_miss_rate::cpu0.inst 0.096858 # miss rate for demand accesses 1109system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000371 # miss rate for demand accesses 1110system.l2c.demand_miss_rate::cpu1.inst 0.053179 # miss rate for demand accesses 1111system.l2c.demand_miss_rate::total 0.073233 # miss rate for demand accesses 1112system.l2c.demand_misses::cpu0.dtb.walker 19 # number of demand (read+write) misses 1113system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1114system.l2c.demand_misses::cpu0.inst 108875 # number of demand (read+write) misses 1115system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses 1116system.l2c.demand_misses::cpu1.inst 57358 # number of demand (read+write) misses 1117system.l2c.demand_misses::total 166264 # number of demand (read+write) misses 1118system.l2c.demand_mshr_hits::cpu0.inst 54 # number of demand (read+write) MSHR hits 1119system.l2c.demand_mshr_hits::cpu1.inst 20 # number of demand (read+write) MSHR hits 1120system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 1121system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1193250 # number of demand (read+write) MSHR miss cycles 1122system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 1123system.l2c.demand_mshr_miss_latency::cpu0.inst 6109760639 # number of demand (read+write) MSHR miss cycles 1124system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 761750 # number of demand (read+write) MSHR miss cycles 1125system.l2c.demand_mshr_miss_latency::cpu1.inst 3388796469 # number of demand (read+write) MSHR miss cycles 1126system.l2c.demand_mshr_miss_latency::total 9500637108 # number of demand (read+write) MSHR miss cycles 1127system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000664 # mshr miss rate for demand accesses 1128system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for demand accesses 1129system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096810 # mshr miss rate for demand accesses 1130system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000371 # mshr miss rate for demand accesses 1131system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053160 # mshr miss rate for demand accesses 1132system.l2c.demand_mshr_miss_rate::total 0.073201 # mshr miss rate for demand accesses 1133system.l2c.demand_mshr_misses::cpu0.dtb.walker 19 # number of demand (read+write) MSHR misses 1134system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 1135system.l2c.demand_mshr_misses::cpu0.inst 108821 # number of demand (read+write) MSHR misses 1136system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses 1137system.l2c.demand_mshr_misses::cpu1.inst 57338 # number of demand (read+write) MSHR misses 1138system.l2c.demand_mshr_misses::total 166190 # number of demand (read+write) MSHR misses 1139system.l2c.fast_writes 0 # number of fast writes performed 1140system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.l2c.overall_accesses::cpu0.dtb.walker 28623 # number of overall (read+write) accesses 1142system.l2c.overall_accesses::cpu0.itb.walker 6686 # number of overall (read+write) accesses 1143system.l2c.overall_accesses::cpu0.inst 1124072 # number of overall (read+write) accesses 1144system.l2c.overall_accesses::cpu1.dtb.walker 26977 # number of overall (read+write) accesses 1145system.l2c.overall_accesses::cpu1.itb.walker 5385 # number of overall (read+write) accesses 1146system.l2c.overall_accesses::cpu1.inst 1078593 # number of overall (read+write) accesses 1147system.l2c.overall_accesses::total 2270336 # number of overall (read+write) accesses 1148system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75197.368421 # average overall miss latency 1149system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 1150system.l2c.overall_avg_miss_latency::cpu0.inst 68696.327026 # average overall miss latency 1151system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88575 # average overall miss latency 1152system.l2c.overall_avg_miss_latency::cpu1.inst 71651.016720 # average overall miss latency 1153system.l2c.overall_avg_miss_latency::total 69717.651578 # average overall miss latency 1154system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579 # average overall mshr miss latency 1155system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1156system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56145.051406 # average overall mshr miss latency 1157system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76175 # average overall mshr miss latency 1158system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59102.104521 # average overall mshr miss latency 1159system.l2c.overall_avg_mshr_miss_latency::total 57167.321187 # average overall mshr miss latency 1160system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1161system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1162system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1163system.l2c.overall_hits::cpu0.dtb.walker 28604 # number of overall hits 1164system.l2c.overall_hits::cpu0.itb.walker 6684 # number of overall hits 1165system.l2c.overall_hits::cpu0.inst 1015197 # number of overall hits 1166system.l2c.overall_hits::cpu1.dtb.walker 26967 # number of overall hits 1167system.l2c.overall_hits::cpu1.itb.walker 5385 # number of overall hits 1168system.l2c.overall_hits::cpu1.inst 1021235 # number of overall hits 1169system.l2c.overall_hits::total 2104072 # number of overall hits 1170system.l2c.overall_miss_latency::cpu0.dtb.walker 1428750 # number of overall miss cycles 1171system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 1172system.l2c.overall_miss_latency::cpu0.inst 7479312605 # number of overall miss cycles 1173system.l2c.overall_miss_latency::cpu1.dtb.walker 885750 # number of overall miss cycles 1174system.l2c.overall_miss_latency::cpu1.inst 4109759017 # number of overall miss cycles 1175system.l2c.overall_miss_latency::total 11591535622 # number of overall miss cycles 1176system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000664 # miss rate for overall accesses 1177system.l2c.overall_miss_rate::cpu0.itb.walker 0.000299 # miss rate for overall accesses 1178system.l2c.overall_miss_rate::cpu0.inst 0.096858 # miss rate for overall accesses 1179system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000371 # miss rate for overall accesses 1180system.l2c.overall_miss_rate::cpu1.inst 0.053179 # miss rate for overall accesses 1181system.l2c.overall_miss_rate::total 0.073233 # miss rate for overall accesses 1182system.l2c.overall_misses::cpu0.dtb.walker 19 # number of overall misses 1183system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1184system.l2c.overall_misses::cpu0.inst 108875 # number of overall misses 1185system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses 1186system.l2c.overall_misses::cpu1.inst 57358 # number of overall misses 1187system.l2c.overall_misses::total 166264 # number of overall misses 1188system.l2c.overall_mshr_hits::cpu0.inst 54 # number of overall MSHR hits 1189system.l2c.overall_mshr_hits::cpu1.inst 20 # number of overall MSHR hits 1190system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits 1191system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1193250 # number of overall MSHR miss cycles 1192system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 1193system.l2c.overall_mshr_miss_latency::cpu0.inst 6109760639 # number of overall MSHR miss cycles 1194system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 761750 # number of overall MSHR miss cycles 1195system.l2c.overall_mshr_miss_latency::cpu1.inst 3388796469 # number of overall MSHR miss cycles 1196system.l2c.overall_mshr_miss_latency::total 9500637108 # number of overall MSHR miss cycles 1197system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000664 # mshr miss rate for overall accesses 1198system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for overall accesses 1199system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096810 # mshr miss rate for overall accesses 1200system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000371 # mshr miss rate for overall accesses 1201system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053160 # mshr miss rate for overall accesses 1202system.l2c.overall_mshr_miss_rate::total 0.073201 # mshr miss rate for overall accesses 1203system.l2c.overall_mshr_misses::cpu0.dtb.walker 19 # number of overall MSHR misses 1204system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 1205system.l2c.overall_mshr_misses::cpu0.inst 108821 # number of overall MSHR misses 1206system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses 1207system.l2c.overall_mshr_misses::cpu1.inst 57338 # number of overall MSHR misses 1208system.l2c.overall_mshr_misses::total 166190 # number of overall MSHR misses 1209system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157767917985 # number of overall MSHR uncacheable cycles 1210system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26392185890 # number of overall MSHR uncacheable cycles 1211system.l2c.overall_mshr_uncacheable_latency::total 184160103875 # number of overall MSHR uncacheable cycles 1212system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 1213system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 1214system.l2c.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id 1215system.l2c.tags.age_task_id_blocks_1024::2 2318 # Occupied blocks per task id 1216system.l2c.tags.age_task_id_blocks_1024::3 8665 # Occupied blocks per task id 1217system.l2c.tags.age_task_id_blocks_1024::4 54076 # Occupied blocks per task id 1218system.l2c.tags.avg_refs 17.496486 # Average number of references to valid blocks. 1219system.l2c.tags.data_accesses 23293968 # Number of data accesses 1220system.l2c.tags.occ_blocks::writebacks 38836.595678 # Average occupied blocks per requestor 1221system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.172943 # Average occupied blocks per requestor 1222system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001299 # Average occupied blocks per requestor 1223system.l2c.tags.occ_blocks::cpu0.inst 8927.165185 # Average occupied blocks per requestor 1224system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.671671 # Average occupied blocks per requestor 1225system.l2c.tags.occ_blocks::cpu1.inst 6116.054658 # Average occupied blocks per requestor 1226system.l2c.tags.occ_percent::writebacks 0.592599 # Average percentage of cache occupancy 1227system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000186 # Average percentage of cache occupancy 1228system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1229system.l2c.tags.occ_percent::cpu0.inst 0.136218 # Average percentage of cache occupancy 1230system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000132 # Average percentage of cache occupancy 1231system.l2c.tags.occ_percent::cpu1.inst 0.093324 # Average percentage of cache occupancy 1232system.l2c.tags.occ_percent::total 0.822459 # Average percentage of cache occupancy 1233system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 1234system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 1235system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 1236system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 1237system.l2c.tags.replacements 73691 # number of replacements 1238system.l2c.tags.sampled_refs 138862 # Sample count of references to valid blocks. 1239system.l2c.tags.tag_accesses 23293968 # Number of tag accesses 1240system.l2c.tags.tagsinuse 53900.661434 # Cycle average of tags in use 1241system.l2c.tags.total_refs 2429597 # Total number of references to valid blocks. 1242system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1243system.l2c.writebacks::writebacks 67203 # number of writebacks 1244system.l2c.writebacks::total 67203 # number of writebacks 1245system.membus.data_through_bus 70713692 # Total data (bytes) 1246system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382664 # Packet count per connected master and slave (bytes) 1247system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 1248system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11296 # Packet count per connected master and slave (bytes) 1249system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 1250system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) 1251system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1977013 # Packet count per connected master and slave (bytes) 1252system.membus.pkt_count_system.l2c.mem_side::total 4371873 # Packet count per connected master and slave (bytes) 1253system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) 1254system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) 1255system.membus.pkt_count::total 16954785 # Packet count per connected master and slave (bytes) 1256system.membus.reqLayer0.occupancy 1725804499 # Layer occupancy (ticks) 1257system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1258system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) 1259system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1260system.membus.reqLayer2.occupancy 10159500 # Layer occupancy (ticks) 1261system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1262system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 1263system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 1264system.membus.reqLayer5.occupancy 707500 # Layer occupancy (ticks) 1265system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1266system.membus.reqLayer6.occupancy 8809576499 # Layer occupancy (ticks) 1267system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) 1268system.membus.respLayer1.occupancy 4910157489 # Layer occupancy (ticks) 1269system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1270system.membus.respLayer2.occupancy 15563933749 # Layer occupancy (ticks) 1271system.membus.respLayer2.utilization 1.4 # Layer utilization (%) 1272system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 1273system.membus.throughput 61662532 # Throughput (bytes/s) 1274system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390012 # Cumulative packet size per connected master and slave (bytes) 1275system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) 1276system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22592 # Cumulative packet size per connected master and slave (bytes) 1277system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 1278system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) 1279system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17966980 # Cumulative packet size per connected master and slave (bytes) 1280system.membus.tot_pkt_size_system.l2c.mem_side::total 20382044 # Cumulative packet size per connected master and slave (bytes) 1281system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) 1282system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) 1283system.membus.tot_pkt_size::total 70713692 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.trans_dist::ReadReq 7506677 # Transaction distribution 1285system.membus.trans_dist::ReadResp 7506677 # Transaction distribution 1286system.membus.trans_dist::WriteReq 767829 # Transaction distribution 1287system.membus.trans_dist::WriteResp 767829 # Transaction distribution 1288system.membus.trans_dist::Writeback 67203 # Transaction distribution 1289system.membus.trans_dist::UpgradeReq 33449 # Transaction distribution 1290system.membus.trans_dist::SCUpgradeReq 17313 # Transaction distribution 1291system.membus.trans_dist::UpgradeResp 12389 # Transaction distribution 1292system.membus.trans_dist::ReadExReq 137872 # Transaction distribution 1293system.membus.trans_dist::ReadExResp 137547 # Transaction distribution 1294system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 1295system.physmem.avgGap 157485.55 # Average gap between requests 1296system.physmem.avgMemAccLat 44404.73 # Average memory access latency per DRAM burst 1297system.physmem.avgQLat 25654.73 # Average queueing delay per DRAM burst 1298system.physmem.avgRdBW 360.38 # Average DRAM read bandwidth in MiByte/s 1299system.physmem.avgRdBWSys 53.17 # Average system read bandwidth in MiByte/s 1300system.physmem.avgRdQLen 4.16 # Average read queue length when enqueuing 1301system.physmem.avgWrBW 6.40 # Average achieved write bandwidth in MiByte/s 1302system.physmem.avgWrBWSys 6.39 # Average system write bandwidth in MiByte/s 1303system.physmem.avgWrQLen 23.53 # Average write queue length when enqueuing 1304system.physmem.busUtil 2.87 # Data bus utilization in percentage 1305system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads 1306system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 1307system.physmem.bw_inst_read::cpu0.inst 666071 # Instruction read bandwidth from this memory (bytes/s) 1308system.physmem.bw_inst_read::cpu1.inst 241370 # Instruction read bandwidth from this memory (bytes/s) 1309system.physmem.bw_inst_read::total 907441 # Instruction read bandwidth from this memory (bytes/s) 1310system.physmem.bw_read::realview.clcd 43889334 # Total read bandwidth from this memory (bytes/s) 1311system.physmem.bw_read::cpu0.dtb.walker 1060 # Total read bandwidth from this memory (bytes/s) 1312system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) 1313system.physmem.bw_read::cpu0.inst 6125781 # Total read bandwidth from this memory (bytes/s) 1314system.physmem.bw_read::cpu1.dtb.walker 558 # Total read bandwidth from this memory (bytes/s) 1315system.physmem.bw_read::cpu1.inst 3149416 # Total read bandwidth from this memory (bytes/s) 1316system.physmem.bw_read::total 53166261 # Total read bandwidth from this memory (bytes/s) 1317system.physmem.bw_total::writebacks 3750477 # Total bandwidth to/from this memory (bytes/s) 1318system.physmem.bw_total::realview.clcd 43889334 # Total bandwidth to/from this memory (bytes/s) 1319system.physmem.bw_total::cpu0.dtb.walker 1060 # Total bandwidth to/from this memory (bytes/s) 1320system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) 1321system.physmem.bw_total::cpu0.inst 6140605 # Total bandwidth to/from this memory (bytes/s) 1322system.physmem.bw_total::cpu1.dtb.walker 558 # Total bandwidth to/from this memory (bytes/s) 1323system.physmem.bw_total::cpu1.inst 5774444 # Total bandwidth to/from this memory (bytes/s) 1324system.physmem.bw_total::total 59556590 # Total bandwidth to/from this memory (bytes/s) 1325system.physmem.bw_write::writebacks 3750477 # Write bandwidth from this memory (bytes/s) 1326system.physmem.bw_write::cpu0.inst 14824 # Write bandwidth from this memory (bytes/s) 1327system.physmem.bw_write::cpu1.inst 2625028 # Write bandwidth from this memory (bytes/s) 1328system.physmem.bw_write::total 6390329 # Write bandwidth from this memory (bytes/s) 1329system.physmem.bytesPerActivate::samples 461405 # Bytes accessed per row activation 1330system.physmem.bytesPerActivate::mean 911.601183 # Bytes accessed per row activation 1331system.physmem.bytesPerActivate::gmean 779.379075 # Bytes accessed per row activation 1332system.physmem.bytesPerActivate::stdev 292.108282 # Bytes accessed per row activation 1333system.physmem.bytesPerActivate::0-127 24920 5.40% 5.40% # Bytes accessed per row activation 1334system.physmem.bytesPerActivate::128-255 21689 4.70% 10.10% # Bytes accessed per row activation 1335system.physmem.bytesPerActivate::256-383 5921 1.28% 11.38% # Bytes accessed per row activation 1336system.physmem.bytesPerActivate::384-511 2595 0.56% 11.95% # Bytes accessed per row activation 1337system.physmem.bytesPerActivate::512-639 2392 0.52% 12.47% # Bytes accessed per row activation 1338system.physmem.bytesPerActivate::640-767 1620 0.35% 12.82% # Bytes accessed per row activation 1339system.physmem.bytesPerActivate::768-895 3961 0.86% 13.68% # Bytes accessed per row activation 1340system.physmem.bytesPerActivate::896-1023 945 0.20% 13.88% # Bytes accessed per row activation 1341system.physmem.bytesPerActivate::1024-1151 397362 86.12% 100.00% # Bytes accessed per row activation 1342system.physmem.bytesPerActivate::total 461405 # Bytes accessed per row activation 1343system.physmem.bytesReadDRAM 413277056 # Total number of bytes read from DRAM 1344system.physmem.bytesReadSys 60970292 # Total read bytes from the system interface side 1345system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue 1346system.physmem.bytesWritten 7340288 # Total number of bytes written to DRAM 1347system.physmem.bytesWrittenSys 7328336 # Total written bytes from the system interface side 1348system.physmem.bytes_inst_read::cpu0.inst 763840 # Number of instructions bytes read from this memory 1349system.physmem.bytes_inst_read::cpu1.inst 276800 # Number of instructions bytes read from this memory 1350system.physmem.bytes_inst_read::total 1040640 # Number of instructions bytes read from this memory 1351system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory 1352system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory 1353system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1354system.physmem.bytes_read::cpu0.inst 7024956 # Number of bytes read from this memory 1355system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory 1356system.physmem.bytes_read::cpu1.inst 3611704 # Number of bytes read from this memory 1357system.physmem.bytes_read::total 60970292 # Number of bytes read from this memory 1358system.physmem.bytes_written::writebacks 4300992 # Number of bytes written to this memory 1359system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory 1360system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory 1361system.physmem.bytes_written::total 7328336 # Number of bytes written to this memory 1362system.physmem.memoryStateTime::IDLE 907580229250 # Time in different power states 1363system.physmem.memoryStateTime::REF 38293580000 # Time in different power states 1364system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 1365system.physmem.memoryStateTime::ACT 200908709500 # Time in different power states 1366system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 1367system.physmem.mergedWrBursts 709322 # Number of DRAM write bursts merged with an existing one 1368system.physmem.neitherReadNorWriteReqs 12389 # Number of requests that are neither read nor write 1369system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 1370system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 1371system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory 1372system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory 1373system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 1374system.physmem.num_reads::cpu0.inst 109839 # Number of read requests responded to by this memory 1375system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory 1376system.physmem.num_reads::cpu1.inst 56461 # Number of read requests responded to by this memory 1377system.physmem.num_reads::total 6457787 # Number of read requests responded to by this memory 1378system.physmem.num_writes::writebacks 67203 # Number of write requests responded to by this memory 1379system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory 1380system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory 1381system.physmem.num_writes::total 824039 # Number of write requests responded to by this memory 1382system.physmem.pageHitRate 92.98 # Row buffer hit rate, read and write combined 1383system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 1384system.physmem.perBankRdBursts::0 403322 # Per bank write bursts 1385system.physmem.perBankRdBursts::1 403674 # Per bank write bursts 1386system.physmem.perBankRdBursts::2 403179 # Per bank write bursts 1387system.physmem.perBankRdBursts::3 403456 # Per bank write bursts 1388system.physmem.perBankRdBursts::4 406212 # Per bank write bursts 1389system.physmem.perBankRdBursts::5 403697 # Per bank write bursts 1390system.physmem.perBankRdBursts::6 403585 # Per bank write bursts 1391system.physmem.perBankRdBursts::7 403309 # Per bank write bursts 1392system.physmem.perBankRdBursts::8 403688 # Per bank write bursts 1393system.physmem.perBankRdBursts::9 404195 # Per bank write bursts 1394system.physmem.perBankRdBursts::10 403096 # Per bank write bursts 1395system.physmem.perBankRdBursts::11 402549 # Per bank write bursts 1396system.physmem.perBankRdBursts::12 403605 # Per bank write bursts 1397system.physmem.perBankRdBursts::13 403586 # Per bank write bursts 1398system.physmem.perBankRdBursts::14 403320 # Per bank write bursts 1399system.physmem.perBankRdBursts::15 402981 # Per bank write bursts 1400system.physmem.perBankWrBursts::0 7004 # Per bank write bursts 1401system.physmem.perBankWrBursts::1 7414 # Per bank write bursts 1402system.physmem.perBankWrBursts::2 6962 # Per bank write bursts 1403system.physmem.perBankWrBursts::3 7076 # Per bank write bursts 1404system.physmem.perBankWrBursts::4 7614 # Per bank write bursts 1405system.physmem.perBankWrBursts::5 7289 # Per bank write bursts 1406system.physmem.perBankWrBursts::6 7332 # Per bank write bursts 1407system.physmem.perBankWrBursts::7 7122 # Per bank write bursts 1408system.physmem.perBankWrBursts::8 7331 # Per bank write bursts 1409system.physmem.perBankWrBursts::9 7785 # Per bank write bursts 1410system.physmem.perBankWrBursts::10 6895 # Per bank write bursts 1411system.physmem.perBankWrBursts::11 6483 # Per bank write bursts 1412system.physmem.perBankWrBursts::12 7357 # Per bank write bursts 1413system.physmem.perBankWrBursts::13 7159 # Per bank write bursts 1414system.physmem.perBankWrBursts::14 7082 # Per bank write bursts 1415system.physmem.perBankWrBursts::15 6787 # Per bank write bursts 1416system.physmem.rdPerTurnAround::samples 6667 # Reads before turning the bus around for writes 1417system.physmem.rdPerTurnAround::mean 968.567572 # Reads before turning the bus around for writes 1418system.physmem.rdPerTurnAround::stdev 25247.895153 # Reads before turning the bus around for writes 1419system.physmem.rdPerTurnAround::0-65535 6659 99.88% 99.88% # Reads before turning the bus around for writes 1420system.physmem.rdPerTurnAround::196608-262143 4 0.06% 99.94% # Reads before turning the bus around for writes 1421system.physmem.rdPerTurnAround::589824-655359 1 0.01% 99.96% # Reads before turning the bus around for writes 1422system.physmem.rdPerTurnAround::786432-851967 2 0.03% 99.99% # Reads before turning the bus around for writes 1423system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.01% 100.00% # Reads before turning the bus around for writes 1424system.physmem.rdPerTurnAround::total 6667 # Reads before turning the bus around for writes 1425system.physmem.rdQLenPdf::0 559033 # What read queue length does an incoming req see 1426system.physmem.rdQLenPdf::1 398819 # What read queue length does an incoming req see 1427system.physmem.rdQLenPdf::2 399992 # What read queue length does an incoming req see 1428system.physmem.rdQLenPdf::3 446086 # What read queue length does an incoming req see 1429system.physmem.rdQLenPdf::4 404802 # What read queue length does an incoming req see 1430system.physmem.rdQLenPdf::5 432883 # What read queue length does an incoming req see 1431system.physmem.rdQLenPdf::6 1116979 # What read queue length does an incoming req see 1432system.physmem.rdQLenPdf::7 1080646 # What read queue length does an incoming req see 1433system.physmem.rdQLenPdf::8 1404200 # What read queue length does an incoming req see 1434system.physmem.rdQLenPdf::9 57088 # What read queue length does an incoming req see 1435system.physmem.rdQLenPdf::10 46892 # What read queue length does an incoming req see 1436system.physmem.rdQLenPdf::11 43646 # What read queue length does an incoming req see 1437system.physmem.rdQLenPdf::12 42022 # What read queue length does an incoming req see 1438system.physmem.rdQLenPdf::13 8400 # What read queue length does an incoming req see 1439system.physmem.rdQLenPdf::14 7955 # What read queue length does an incoming req see 1440system.physmem.rdQLenPdf::15 7847 # What read queue length does an incoming req see 1441system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see 1442system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see 1443system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1444system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1445system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1446system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1447system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1448system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1449system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1450system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1451system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1452system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1453system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1454system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1455system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1456system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1457system.physmem.readBursts 6457787 # Number of DRAM read bursts, including those serviced by the write queue 1458system.physmem.readPktSize::0 0 # Read request sizes (log2) 1459system.physmem.readPktSize::1 0 # Read request sizes (log2) 1460system.physmem.readPktSize::2 109 # Read request sizes (log2) 1461system.physmem.readPktSize::3 6291456 # Read request sizes (log2) 1462system.physmem.readPktSize::4 0 # Read request sizes (log2) 1463system.physmem.readPktSize::5 0 # Read request sizes (log2) 1464system.physmem.readPktSize::6 166222 # Read request sizes (log2) 1465system.physmem.readReqs 6457787 # Number of read requests accepted 1466system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads 1467system.physmem.readRowHits 6016258 # Number of row buffer hits during reads 1468system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue 1469system.physmem.totBusLat 32287270000 # Total ticks spent in databus transfers 1470system.physmem.totGap 1146782404500 # Total gap between requests 1471system.physmem.totMemAccLat 286741508250 # Total ticks spent from burst creation until serviced by the DRAM 1472system.physmem.totQLat 165664245750 # Total ticks spent queuing 1473system.physmem.wrPerTurnAround::samples 6667 # Writes before turning the bus around for reads 1474system.physmem.wrPerTurnAround::mean 17.202940 # Writes before turning the bus around for reads 1475system.physmem.wrPerTurnAround::gmean 17.174263 # Writes before turning the bus around for reads 1476system.physmem.wrPerTurnAround::stdev 0.985830 # Writes before turning the bus around for reads 1477system.physmem.wrPerTurnAround::16 2664 39.96% 39.96% # Writes before turning the bus around for reads 1478system.physmem.wrPerTurnAround::17 13 0.19% 40.15% # Writes before turning the bus around for reads 1479system.physmem.wrPerTurnAround::18 3969 59.53% 99.69% # Writes before turning the bus around for reads 1480system.physmem.wrPerTurnAround::19 17 0.25% 99.94% # Writes before turning the bus around for reads 1481system.physmem.wrPerTurnAround::20 3 0.04% 99.99% # Writes before turning the bus around for reads 1482system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads 1483system.physmem.wrPerTurnAround::total 6667 # Writes before turning the bus around for reads 1484system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 1485system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 1486system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 1487system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 1488system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 1489system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 1490system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 1491system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 1492system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 1493system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 1494system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 1495system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 1496system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 1497system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 1498system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 1499system.physmem.wrQLenPdf::15 3989 # What write queue length does an incoming req see 1500system.physmem.wrQLenPdf::16 4002 # What write queue length does an incoming req see 1501system.physmem.wrQLenPdf::17 6598 # What write queue length does an incoming req see 1502system.physmem.wrQLenPdf::18 6668 # What write queue length does an incoming req see 1503system.physmem.wrQLenPdf::19 6674 # What write queue length does an incoming req see 1504system.physmem.wrQLenPdf::20 6672 # What write queue length does an incoming req see 1505system.physmem.wrQLenPdf::21 6675 # What write queue length does an incoming req see 1506system.physmem.wrQLenPdf::22 6670 # What write queue length does an incoming req see 1507system.physmem.wrQLenPdf::23 6675 # What write queue length does an incoming req see 1508system.physmem.wrQLenPdf::24 6675 # What write queue length does an incoming req see 1509system.physmem.wrQLenPdf::25 6676 # What write queue length does an incoming req see 1510system.physmem.wrQLenPdf::26 6679 # What write queue length does an incoming req see 1511system.physmem.wrQLenPdf::27 6681 # What write queue length does an incoming req see 1512system.physmem.wrQLenPdf::28 6680 # What write queue length does an incoming req see 1513system.physmem.wrQLenPdf::29 6671 # What write queue length does an incoming req see 1514system.physmem.wrQLenPdf::30 6676 # What write queue length does an incoming req see 1515system.physmem.wrQLenPdf::31 6673 # What write queue length does an incoming req see 1516system.physmem.wrQLenPdf::32 6667 # What write queue length does an incoming req see 1517system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see 1518system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 1519system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 1520system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 1521system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 1522system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 1523system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 1524system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 1525system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 1526system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 1527system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 1528system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 1529system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 1530system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 1531system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 1532system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 1533system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 1534system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 1535system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 1536system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 1537system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 1538system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 1539system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 1540system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 1541system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 1542system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 1543system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 1544system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 1545system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 1546system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 1547system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 1548system.physmem.writeBursts 824039 # Number of DRAM write bursts, including those merged in the write queue 1549system.physmem.writePktSize::0 0 # Write request sizes (log2) 1550system.physmem.writePktSize::1 0 # Write request sizes (log2) 1551system.physmem.writePktSize::2 756836 # Write request sizes (log2) 1552system.physmem.writePktSize::3 0 # Write request sizes (log2) 1553system.physmem.writePktSize::4 0 # Write request sizes (log2) 1554system.physmem.writePktSize::5 0 # Write request sizes (log2) 1555system.physmem.writePktSize::6 67203 # Write request sizes (log2) 1556system.physmem.writeReqs 824039 # Number of write requests accepted 1557system.physmem.writeRowHitRate 82.36 # Row buffer hit rate for writes 1558system.physmem.writeRowHits 94483 # Number of row buffer hits during writes 1559system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) 1560system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) 1561system.realview.nvmem.bw_inst_read::total 614 # Instruction read bandwidth from this memory (bytes/s) 1562system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) 1563system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) 1564system.realview.nvmem.bw_read::total 614 # Total read bandwidth from this memory (bytes/s) 1565system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) 1566system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) 1567system.realview.nvmem.bw_total::total 614 # Total bandwidth to/from this memory (bytes/s) 1568system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory 1569system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 1570system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 1571system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory 1572system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 1573system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory 1574system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory 1575system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 1576system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 1577system.toL2Bus.data_through_bus 183769016 # Total data (bytes) 1578system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1573579 # Packet count per connected master and slave (bytes) 1579system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3284792 # Packet count per connected master and slave (bytes) 1580system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16388 # Packet count per connected master and slave (bytes) 1581system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 66250 # Packet count per connected master and slave (bytes) 1582system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1600218 # Packet count per connected master and slave (bytes) 1583system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2575101 # Packet count per connected master and slave (bytes) 1584system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13938 # Packet count per connected master and slave (bytes) 1585system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 63483 # Packet count per connected master and slave (bytes) 1586system.toL2Bus.pkt_count::total 9193749 # Packet count per connected master and slave (bytes) 1587system.toL2Bus.reqLayer0.occupancy 5169689504 # Layer occupancy (ticks) 1588system.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 1589system.toL2Bus.respLayer0.occupancy 3544874662 # Layer occupancy (ticks) 1590system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) 1591system.toL2Bus.respLayer1.occupancy 2799461047 # Layer occupancy (ticks) 1592system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 1593system.toL2Bus.respLayer2.occupancy 9704495 # Layer occupancy (ticks) 1594system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1595system.toL2Bus.respLayer3.occupancy 37627749 # Layer occupancy (ticks) 1596system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1597system.toL2Bus.respLayer6.occupancy 3603369425 # Layer occupancy (ticks) 1598system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) 1599system.toL2Bus.respLayer7.occupancy 1938898298 # Layer occupancy (ticks) 1600system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1601system.toL2Bus.respLayer8.occupancy 8556493 # Layer occupancy (ticks) 1602system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 1603system.toL2Bus.respLayer9.occupancy 36509744 # Layer occupancy (ticks) 1604system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 1605system.toL2Bus.snoop_data_through_bus 4881844 # Total snoop data (bytes) 1606system.toL2Bus.throughput 164504065 # Throughput (bytes/s) 1607system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 50330560 # Cumulative packet size per connected master and slave (bytes) 1608system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43616868 # Cumulative packet size per connected master and slave (bytes) 1609system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26744 # Cumulative packet size per connected master and slave (bytes) 1610system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 114492 # Cumulative packet size per connected master and slave (bytes) 1611system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 51179904 # Cumulative packet size per connected master and slave (bytes) 1612system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38371000 # Cumulative packet size per connected master and slave (bytes) 1613system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 21540 # Cumulative packet size per connected master and slave (bytes) 1614system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 107908 # Cumulative packet size per connected master and slave (bytes) 1615system.toL2Bus.tot_pkt_size::total 183769016 # Cumulative packet size per connected master and slave (bytes) 1616system.toL2Bus.trans_dist::ReadReq 3298101 # Transaction distribution 1617system.toL2Bus.trans_dist::ReadResp 3298100 # Transaction distribution 1618system.toL2Bus.trans_dist::WriteReq 767829 # Transaction distribution 1619system.toL2Bus.trans_dist::WriteResp 767829 # Transaction distribution 1620system.toL2Bus.trans_dist::Writeback 577052 # Transaction distribution 1621system.toL2Bus.trans_dist::UpgradeReq 33066 # Transaction distribution 1622system.toL2Bus.trans_dist::SCUpgradeReq 17632 # Transaction distribution 1623system.toL2Bus.trans_dist::UpgradeResp 50698 # Transaction distribution 1624system.toL2Bus.trans_dist::ReadExReq 260633 # Transaction distribution 1625system.toL2Bus.trans_dist::ReadExResp 260633 # Transaction distribution 1626system.voltage_domain.voltage 1 # Voltage in Volts 1627 1628---------- End Simulation Statistics ---------- 1629