simout revision 11374:c1525cc9ec7f
12810Srdreslin@umich.eduRedirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout 212500Snikos.nikoleris@arm.comRedirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr 311051Sandreas.hansson@arm.comgem5 Simulator System. http://gem5.org 411051Sandreas.hansson@arm.comgem5 is copyrighted software; use the --copyright option for details. 511051Sandreas.hansson@arm.com 611051Sandreas.hansson@arm.comgem5 compiled Mar 15 2016 21:26:42 711051Sandreas.hansson@arm.comgem5 started Mar 15 2016 21:34:30 811051Sandreas.hansson@arm.comgem5 executing on phenom, pid 15961 911051Sandreas.hansson@arm.comcommand line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual 1011051Sandreas.hansson@arm.com 1111051Sandreas.hansson@arm.comGlobal frequency set at 1000000000000 ticks per second 1211051Sandreas.hansson@arm.cominfo: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 1311051Sandreas.hansson@arm.cominfo: Using bootloader at address 0x10 1411051Sandreas.hansson@arm.cominfo: Using kernel entry physical address at 0x80008000 1511051Sandreas.hansson@arm.cominfo: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 162810Srdreslin@umich.eduinfo: Entering event queue @ 0. Starting simulation... 172810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 182810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 192810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 202810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 212810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 222810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 232810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 242810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 252810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 262810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 272810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 282810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 292810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 302810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 312810Srdreslin@umich.eduinfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 322810Srdreslin@umich.eduExiting @ tick 2649116242500 because m5_exit instruction encountered 332810Srdreslin@umich.edu