stats.txt revision 9199:2a5516167688
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.864443 # Number of seconds simulated 4sim_ticks 1864443445500 # Number of ticks simulated 5final_tick 1864443445500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 198323 # Simulator instruction rate (inst/s) 8host_op_rate 198323 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6987525181 # Simulator tick rate (ticks/s) 10host_mem_usage 299164 # Number of bytes of host memory used 11host_seconds 266.82 # Real time elapsed on the host 12sim_insts 52917560 # Number of instructions simulated 13sim_ops 52917560 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 968960 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28501248 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 968960 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 968960 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7519232 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7519232 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15140 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445332 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117488 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117488 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 519705 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13344465 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1422563 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15286732 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 519705 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 519705 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4032963 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4032963 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4032963 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 519705 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13344465 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1422563 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19319696 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 338394 # number of replacements 42system.l2c.tagsinuse 65347.941058 # Cycle average of tags in use 43system.l2c.total_refs 2558628 # Total number of references to valid blocks. 44system.l2c.sampled_refs 403561 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.340127 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 4870004000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 53835.098828 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 5353.738970 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 6159.103260 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.821458 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.081692 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.093980 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.997130 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 1006554 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 827784 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1834338 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 840935 # number of Writeback hits 58system.l2c.Writeback_hits::total 840935 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits 61system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 62system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 63system.l2c.ReadExReq_hits::cpu.data 185458 # number of ReadExReq hits 64system.l2c.ReadExReq_hits::total 185458 # number of ReadExReq hits 65system.l2c.demand_hits::cpu.inst 1006554 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 1013242 # number of demand (read+write) hits 67system.l2c.demand_hits::total 2019796 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.inst 1006554 # number of overall hits 69system.l2c.overall_hits::cpu.data 1013242 # number of overall hits 70system.l2c.overall_hits::total 2019796 # number of overall hits 71system.l2c.ReadReq_misses::cpu.inst 15142 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.data 273892 # number of ReadReq misses 73system.l2c.ReadReq_misses::total 289034 # number of ReadReq misses 74system.l2c.UpgradeReq_misses::cpu.data 50 # number of UpgradeReq misses 75system.l2c.UpgradeReq_misses::total 50 # number of UpgradeReq misses 76system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 77system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 78system.l2c.ReadExReq_misses::cpu.data 115356 # number of ReadExReq misses 79system.l2c.ReadExReq_misses::total 115356 # number of ReadExReq misses 80system.l2c.demand_misses::cpu.inst 15142 # number of demand (read+write) misses 81system.l2c.demand_misses::cpu.data 389248 # number of demand (read+write) misses 82system.l2c.demand_misses::total 404390 # number of demand (read+write) misses 83system.l2c.overall_misses::cpu.inst 15142 # number of overall misses 84system.l2c.overall_misses::cpu.data 389248 # number of overall misses 85system.l2c.overall_misses::total 404390 # number of overall misses 86system.l2c.ReadReq_miss_latency::cpu.inst 806626498 # number of ReadReq miss cycles 87system.l2c.ReadReq_miss_latency::cpu.data 14262568500 # number of ReadReq miss cycles 88system.l2c.ReadReq_miss_latency::total 15069194998 # number of ReadReq miss cycles 89system.l2c.UpgradeReq_miss_latency::cpu.data 506000 # number of UpgradeReq miss cycles 90system.l2c.UpgradeReq_miss_latency::total 506000 # number of UpgradeReq miss cycles 91system.l2c.ReadExReq_miss_latency::cpu.data 6193261496 # number of ReadExReq miss cycles 92system.l2c.ReadExReq_miss_latency::total 6193261496 # number of ReadExReq miss cycles 93system.l2c.demand_miss_latency::cpu.inst 806626498 # number of demand (read+write) miss cycles 94system.l2c.demand_miss_latency::cpu.data 20455829996 # number of demand (read+write) miss cycles 95system.l2c.demand_miss_latency::total 21262456494 # number of demand (read+write) miss cycles 96system.l2c.overall_miss_latency::cpu.inst 806626498 # number of overall miss cycles 97system.l2c.overall_miss_latency::cpu.data 20455829996 # number of overall miss cycles 98system.l2c.overall_miss_latency::total 21262456494 # number of overall miss cycles 99system.l2c.ReadReq_accesses::cpu.inst 1021696 # number of ReadReq accesses(hits+misses) 100system.l2c.ReadReq_accesses::cpu.data 1101676 # number of ReadReq accesses(hits+misses) 101system.l2c.ReadReq_accesses::total 2123372 # number of ReadReq accesses(hits+misses) 102system.l2c.Writeback_accesses::writebacks 840935 # number of Writeback accesses(hits+misses) 103system.l2c.Writeback_accesses::total 840935 # number of Writeback accesses(hits+misses) 104system.l2c.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses) 105system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) 106system.l2c.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 107system.l2c.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 108system.l2c.ReadExReq_accesses::cpu.data 300814 # number of ReadExReq accesses(hits+misses) 109system.l2c.ReadExReq_accesses::total 300814 # number of ReadExReq accesses(hits+misses) 110system.l2c.demand_accesses::cpu.inst 1021696 # number of demand (read+write) accesses 111system.l2c.demand_accesses::cpu.data 1402490 # number of demand (read+write) accesses 112system.l2c.demand_accesses::total 2424186 # number of demand (read+write) accesses 113system.l2c.overall_accesses::cpu.inst 1021696 # number of overall (read+write) accesses 114system.l2c.overall_accesses::cpu.data 1402490 # number of overall (read+write) accesses 115system.l2c.overall_accesses::total 2424186 # number of overall (read+write) accesses 116system.l2c.ReadReq_miss_rate::cpu.inst 0.014820 # miss rate for ReadReq accesses 117system.l2c.ReadReq_miss_rate::cpu.data 0.248614 # miss rate for ReadReq accesses 118system.l2c.ReadReq_miss_rate::total 0.136120 # miss rate for ReadReq accesses 119system.l2c.UpgradeReq_miss_rate::cpu.data 0.617284 # miss rate for UpgradeReq accesses 120system.l2c.UpgradeReq_miss_rate::total 0.617284 # miss rate for UpgradeReq accesses 121system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 122system.l2c.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 123system.l2c.ReadExReq_miss_rate::cpu.data 0.383479 # miss rate for ReadExReq accesses 124system.l2c.ReadExReq_miss_rate::total 0.383479 # miss rate for ReadExReq accesses 125system.l2c.demand_miss_rate::cpu.inst 0.014820 # miss rate for demand accesses 126system.l2c.demand_miss_rate::cpu.data 0.277541 # miss rate for demand accesses 127system.l2c.demand_miss_rate::total 0.166815 # miss rate for demand accesses 128system.l2c.overall_miss_rate::cpu.inst 0.014820 # miss rate for overall accesses 129system.l2c.overall_miss_rate::cpu.data 0.277541 # miss rate for overall accesses 130system.l2c.overall_miss_rate::total 0.166815 # miss rate for overall accesses 131system.l2c.ReadReq_avg_miss_latency::cpu.inst 53270.802932 # average ReadReq miss latency 132system.l2c.ReadReq_avg_miss_latency::cpu.data 52073.695106 # average ReadReq miss latency 133system.l2c.ReadReq_avg_miss_latency::total 52136.409550 # average ReadReq miss latency 134system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10120 # average UpgradeReq miss latency 135system.l2c.UpgradeReq_avg_miss_latency::total 10120 # average UpgradeReq miss latency 136system.l2c.ReadExReq_avg_miss_latency::cpu.data 53688.247651 # average ReadExReq miss latency 137system.l2c.ReadExReq_avg_miss_latency::total 53688.247651 # average ReadExReq miss latency 138system.l2c.demand_avg_miss_latency::cpu.inst 53270.802932 # average overall miss latency 139system.l2c.demand_avg_miss_latency::cpu.data 52552.177522 # average overall miss latency 140system.l2c.demand_avg_miss_latency::total 52579.085769 # average overall miss latency 141system.l2c.overall_avg_miss_latency::cpu.inst 53270.802932 # average overall miss latency 142system.l2c.overall_avg_miss_latency::cpu.data 52552.177522 # average overall miss latency 143system.l2c.overall_avg_miss_latency::total 52579.085769 # average overall miss latency 144system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 146system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked::no_targets 0 # number of cycles access was blocked 148system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 149system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 150system.l2c.fast_writes 0 # number of fast writes performed 151system.l2c.cache_copies 0 # number of cache copies performed 152system.l2c.writebacks::writebacks 75976 # number of writebacks 153system.l2c.writebacks::total 75976 # number of writebacks 154system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 155system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 156system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 157system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 158system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 159system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 160system.l2c.ReadReq_mshr_misses::cpu.inst 15141 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.data 273892 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::total 289033 # number of ReadReq MSHR misses 163system.l2c.UpgradeReq_mshr_misses::cpu.data 50 # number of UpgradeReq MSHR misses 164system.l2c.UpgradeReq_mshr_misses::total 50 # number of UpgradeReq MSHR misses 165system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 166system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 167system.l2c.ReadExReq_mshr_misses::cpu.data 115356 # number of ReadExReq MSHR misses 168system.l2c.ReadExReq_mshr_misses::total 115356 # number of ReadExReq MSHR misses 169system.l2c.demand_mshr_misses::cpu.inst 15141 # number of demand (read+write) MSHR misses 170system.l2c.demand_mshr_misses::cpu.data 389248 # number of demand (read+write) MSHR misses 171system.l2c.demand_mshr_misses::total 404389 # number of demand (read+write) MSHR misses 172system.l2c.overall_mshr_misses::cpu.inst 15141 # number of overall MSHR misses 173system.l2c.overall_mshr_misses::cpu.data 389248 # number of overall MSHR misses 174system.l2c.overall_mshr_misses::total 404389 # number of overall MSHR misses 175system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621548498 # number of ReadReq MSHR miss cycles 176system.l2c.ReadReq_mshr_miss_latency::cpu.data 10984970000 # number of ReadReq MSHR miss cycles 177system.l2c.ReadReq_mshr_miss_latency::total 11606518498 # number of ReadReq MSHR miss cycles 178system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2110000 # number of UpgradeReq MSHR miss cycles 179system.l2c.UpgradeReq_mshr_miss_latency::total 2110000 # number of UpgradeReq MSHR miss cycles 180system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles 181system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles 182system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4799591496 # number of ReadExReq MSHR miss cycles 183system.l2c.ReadExReq_mshr_miss_latency::total 4799591496 # number of ReadExReq MSHR miss cycles 184system.l2c.demand_mshr_miss_latency::cpu.inst 621548498 # number of demand (read+write) MSHR miss cycles 185system.l2c.demand_mshr_miss_latency::cpu.data 15784561496 # number of demand (read+write) MSHR miss cycles 186system.l2c.demand_mshr_miss_latency::total 16406109994 # number of demand (read+write) MSHR miss cycles 187system.l2c.overall_mshr_miss_latency::cpu.inst 621548498 # number of overall MSHR miss cycles 188system.l2c.overall_mshr_miss_latency::cpu.data 15784561496 # number of overall MSHR miss cycles 189system.l2c.overall_mshr_miss_latency::total 16406109994 # number of overall MSHR miss cycles 190system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1332350000 # number of ReadReq MSHR uncacheable cycles 191system.l2c.ReadReq_mshr_uncacheable_latency::total 1332350000 # number of ReadReq MSHR uncacheable cycles 192system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1882980500 # number of WriteReq MSHR uncacheable cycles 193system.l2c.WriteReq_mshr_uncacheable_latency::total 1882980500 # number of WriteReq MSHR uncacheable cycles 194system.l2c.overall_mshr_uncacheable_latency::cpu.data 3215330500 # number of overall MSHR uncacheable cycles 195system.l2c.overall_mshr_uncacheable_latency::total 3215330500 # number of overall MSHR uncacheable cycles 196system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for ReadReq accesses 197system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248614 # mshr miss rate for ReadReq accesses 198system.l2c.ReadReq_mshr_miss_rate::total 0.136120 # mshr miss rate for ReadReq accesses 199system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.617284 # mshr miss rate for UpgradeReq accesses 200system.l2c.UpgradeReq_mshr_miss_rate::total 0.617284 # mshr miss rate for UpgradeReq accesses 201system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 202system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 203system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383479 # mshr miss rate for ReadExReq accesses 204system.l2c.ReadExReq_mshr_miss_rate::total 0.383479 # mshr miss rate for ReadExReq accesses 205system.l2c.demand_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for demand accesses 206system.l2c.demand_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for demand accesses 207system.l2c.demand_mshr_miss_rate::total 0.166814 # mshr miss rate for demand accesses 208system.l2c.overall_mshr_miss_rate::cpu.inst 0.014819 # mshr miss rate for overall accesses 209system.l2c.overall_mshr_miss_rate::cpu.data 0.277541 # mshr miss rate for overall accesses 210system.l2c.overall_mshr_miss_rate::total 0.166814 # mshr miss rate for overall accesses 211system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41050.690047 # average ReadReq mshr miss latency 212system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.939962 # average ReadReq mshr miss latency 213system.l2c.ReadReq_avg_mshr_miss_latency::total 40156.378331 # average ReadReq mshr miss latency 214system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42200 # average UpgradeReq mshr miss latency 215system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42200 # average UpgradeReq mshr miss latency 216system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 217system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 218system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41606.778113 # average ReadExReq mshr miss latency 219system.l2c.ReadExReq_avg_mshr_miss_latency::total 41606.778113 # average ReadExReq mshr miss latency 220system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency 221system.l2c.demand_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency 222system.l2c.demand_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency 223system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41050.690047 # average overall mshr miss latency 224system.l2c.overall_avg_mshr_miss_latency::cpu.data 40551.426073 # average overall mshr miss latency 225system.l2c.overall_avg_mshr_miss_latency::total 40570.119350 # average overall mshr miss latency 226system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 227system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 228system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 229system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 230system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 231system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 232system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 233system.iocache.replacements 41685 # number of replacements 234system.iocache.tagsinuse 1.286638 # Cycle average of tags in use 235system.iocache.total_refs 0 # Total number of references to valid blocks. 236system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 237system.iocache.avg_refs 0 # Average number of references to valid blocks. 238system.iocache.warmup_cycle 1711308746000 # Cycle when the warmup percentage was hit. 239system.iocache.occ_blocks::tsunami.ide 1.286638 # Average occupied blocks per requestor 240system.iocache.occ_percent::tsunami.ide 0.080415 # Average percentage of cache occupancy 241system.iocache.occ_percent::total 0.080415 # Average percentage of cache occupancy 242system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 243system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 244system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 245system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 246system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 247system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 248system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 249system.iocache.overall_misses::total 41725 # number of overall misses 250system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 251system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 252system.iocache.WriteReq_miss_latency::tsunami.ide 7639193806 # number of WriteReq miss cycles 253system.iocache.WriteReq_miss_latency::total 7639193806 # number of WriteReq miss cycles 254system.iocache.demand_miss_latency::tsunami.ide 7659866804 # number of demand (read+write) miss cycles 255system.iocache.demand_miss_latency::total 7659866804 # number of demand (read+write) miss cycles 256system.iocache.overall_miss_latency::tsunami.ide 7659866804 # number of overall miss cycles 257system.iocache.overall_miss_latency::total 7659866804 # number of overall miss cycles 258system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 259system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 260system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 261system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 262system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 263system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 264system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 265system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 266system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 267system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 268system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 269system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 270system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 271system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 272system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 273system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 274system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 275system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 276system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183846.597179 # average WriteReq miss latency 277system.iocache.WriteReq_avg_miss_latency::total 183846.597179 # average WriteReq miss latency 278system.iocache.demand_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency 279system.iocache.demand_avg_miss_latency::total 183579.791588 # average overall miss latency 280system.iocache.overall_avg_miss_latency::tsunami.ide 183579.791588 # average overall miss latency 281system.iocache.overall_avg_miss_latency::total 183579.791588 # average overall miss latency 282system.iocache.blocked_cycles::no_mshrs 7379000 # number of cycles access was blocked 283system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 284system.iocache.blocked::no_mshrs 7110 # number of cycles access was blocked 285system.iocache.blocked::no_targets 0 # number of cycles access was blocked 286system.iocache.avg_blocked_cycles::no_mshrs 1037.834037 # average number of cycles each access was blocked 287system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 288system.iocache.fast_writes 0 # number of fast writes performed 289system.iocache.cache_copies 0 # number of cache copies performed 290system.iocache.writebacks::writebacks 41512 # number of writebacks 291system.iocache.writebacks::total 41512 # number of writebacks 292system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 293system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 294system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 295system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 296system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 297system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 298system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 299system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 300system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 301system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles 302system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478339000 # number of WriteReq MSHR miss cycles 303system.iocache.WriteReq_mshr_miss_latency::total 5478339000 # number of WriteReq MSHR miss cycles 304system.iocache.demand_mshr_miss_latency::tsunami.ide 5490015000 # number of demand (read+write) MSHR miss cycles 305system.iocache.demand_mshr_miss_latency::total 5490015000 # number of demand (read+write) MSHR miss cycles 306system.iocache.overall_mshr_miss_latency::tsunami.ide 5490015000 # number of overall MSHR miss cycles 307system.iocache.overall_mshr_miss_latency::total 5490015000 # number of overall MSHR miss cycles 308system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 309system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 310system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 311system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 312system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 313system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 314system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 315system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 316system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 317system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency 318system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131842.967848 # average WriteReq mshr miss latency 319system.iocache.WriteReq_avg_mshr_miss_latency::total 131842.967848 # average WriteReq mshr miss latency 320system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency 321system.iocache.demand_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency 322system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131576.153385 # average overall mshr miss latency 323system.iocache.overall_avg_mshr_miss_latency::total 131576.153385 # average overall mshr miss latency 324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 326system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 327system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 328system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 329system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 330system.disk0.dma_write_txs 395 # Number of DMA write transactions. 331system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 335system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 336system.disk2.dma_write_txs 1 # Number of DMA write transactions. 337system.cpu.dtb.fetch_hits 0 # ITB hits 338system.cpu.dtb.fetch_misses 0 # ITB misses 339system.cpu.dtb.fetch_acv 0 # ITB acv 340system.cpu.dtb.fetch_accesses 0 # ITB accesses 341system.cpu.dtb.read_hits 9936242 # DTB read hits 342system.cpu.dtb.read_misses 43490 # DTB read misses 343system.cpu.dtb.read_acv 516 # DTB read access violations 344system.cpu.dtb.read_accesses 957786 # DTB read accesses 345system.cpu.dtb.write_hits 6625146 # DTB write hits 346system.cpu.dtb.write_misses 10048 # DTB write misses 347system.cpu.dtb.write_acv 376 # DTB write access violations 348system.cpu.dtb.write_accesses 340602 # DTB write accesses 349system.cpu.dtb.data_hits 16561388 # DTB hits 350system.cpu.dtb.data_misses 53538 # DTB misses 351system.cpu.dtb.data_acv 892 # DTB access violations 352system.cpu.dtb.data_accesses 1298388 # DTB accesses 353system.cpu.itb.fetch_hits 1339050 # ITB hits 354system.cpu.itb.fetch_misses 40176 # ITB misses 355system.cpu.itb.fetch_acv 1137 # ITB acv 356system.cpu.itb.fetch_accesses 1379226 # ITB accesses 357system.cpu.itb.read_hits 0 # DTB read hits 358system.cpu.itb.read_misses 0 # DTB read misses 359system.cpu.itb.read_acv 0 # DTB read access violations 360system.cpu.itb.read_accesses 0 # DTB read accesses 361system.cpu.itb.write_hits 0 # DTB write hits 362system.cpu.itb.write_misses 0 # DTB write misses 363system.cpu.itb.write_acv 0 # DTB write access violations 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.data_hits 0 # DTB hits 366system.cpu.itb.data_misses 0 # DTB misses 367system.cpu.itb.data_acv 0 # DTB access violations 368system.cpu.itb.data_accesses 0 # DTB accesses 369system.cpu.numCycles 124718167 # number of cpu cycles simulated 370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 372system.cpu.BPredUnit.lookups 14016362 # Number of BP lookups 373system.cpu.BPredUnit.condPredicted 11699457 # Number of conditional branches predicted 374system.cpu.BPredUnit.condIncorrect 447467 # Number of conditional branches incorrect 375system.cpu.BPredUnit.BTBLookups 10098689 # Number of BTB lookups 376system.cpu.BPredUnit.BTBHits 5905629 # Number of BTB hits 377system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 378system.cpu.BPredUnit.usedRAS 935083 # Number of times the RAS was used to get a target. 379system.cpu.BPredUnit.RASInCorrect 44772 # Number of incorrect RAS predictions. 380system.cpu.fetch.icacheStallCycles 31431497 # Number of cycles fetch is stalled on an Icache miss 381system.cpu.fetch.Insts 71249565 # Number of instructions fetch has processed 382system.cpu.fetch.Branches 14016362 # Number of branches that fetch encountered 383system.cpu.fetch.predictedBranches 6840712 # Number of branches that fetch has predicted taken 384system.cpu.fetch.Cycles 13427140 # Number of cycles fetch has run and was not squashing or blocked 385system.cpu.fetch.SquashCycles 2133623 # Number of cycles fetch has spent squashing 386system.cpu.fetch.BlockedCycles 43145521 # Number of cycles fetch has spent blocked 387system.cpu.fetch.MiscStallCycles 33490 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 388system.cpu.fetch.PendingTrapStallCycles 277896 # Number of stall cycles due to pending traps 389system.cpu.fetch.PendingQuiesceStallCycles 300852 # Number of stall cycles due to pending quiesce instructions 390system.cpu.fetch.IcacheWaitRetryStallCycles 229 # Number of stall cycles due to full MSHR 391system.cpu.fetch.CacheLines 8810652 # Number of cache lines fetched 392system.cpu.fetch.IcacheSquashes 301668 # Number of outstanding Icache misses that were squashed 393system.cpu.fetch.rateDist::samples 90022350 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::mean 0.791465 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::stdev 2.121682 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::0 76595210 85.08% 85.08% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::1 880275 0.98% 86.06% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::2 1754034 1.95% 88.01% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::3 853758 0.95% 88.96% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::4 2767447 3.07% 92.03% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::5 598798 0.67% 92.70% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::6 668363 0.74% 93.44% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::7 1009728 1.12% 94.56% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::8 4894737 5.44% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::total 90022350 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.112384 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.571285 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 32462663 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 42944944 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 12200929 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 1050932 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 1362881 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 612569 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 43257 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 69997551 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 131864 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 1362881 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 33604793 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 17288612 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 21444377 # count of cycles rename stalled for serializing inst 425system.cpu.rename.RunCycles 11497846 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 4823839 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 66302391 # Number of instructions processed by rename 428system.cpu.rename.ROBFullEvents 7264 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 752324 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LSQFullEvents 1793006 # Number of times rename has blocked due to LSQ full 431system.cpu.rename.RenamedOperands 44298032 # Number of destination operands rename has renamed 432system.cpu.rename.RenameLookups 80385832 # Number of register rename lookups that rename has made 433system.cpu.rename.int_rename_lookups 79896368 # Number of integer rename lookups 434system.cpu.rename.fp_rename_lookups 489464 # Number of floating rename lookups 435system.cpu.rename.CommittedMaps 38124388 # Number of HB maps that are committed 436system.cpu.rename.UndoneMaps 6173636 # Number of HB maps that are undone due to squashing 437system.cpu.rename.serializingInsts 1698063 # count of serializing insts renamed 438system.cpu.rename.tempSerializingInsts 251025 # count of temporary serializing insts renamed 439system.cpu.rename.skidInsts 12720780 # count of insts added to the skid buffer 440system.cpu.memDep0.insertedLoads 10525150 # Number of loads inserted to the mem dependence unit. 441system.cpu.memDep0.insertedStores 6958577 # Number of stores inserted to the mem dependence unit. 442system.cpu.memDep0.conflictingLoads 1307223 # Number of conflicting loads. 443system.cpu.memDep0.conflictingStores 920725 # Number of conflicting stores. 444system.cpu.iq.iqInstsAdded 58755274 # Number of instructions added to the IQ (excludes non-spec) 445system.cpu.iq.iqNonSpecInstsAdded 2090184 # Number of non-speculative instructions added to the IQ 446system.cpu.iq.iqInstsIssued 57106230 # Number of instructions issued 447system.cpu.iq.iqSquashedInstsIssued 126003 # Number of squashed instructions issued 448system.cpu.iq.iqSquashedInstsExamined 7528195 # Number of squashed instructions iterated over during squash; mainly for profiling 449system.cpu.iq.iqSquashedOperandsExamined 3871424 # Number of squashed operands that are examined and possibly removed from graph 450system.cpu.iq.iqSquashedNonSpecRemoved 1424917 # Number of squashed non-spec instructions that were removed 451system.cpu.iq.issued_per_cycle::samples 90022350 # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::mean 0.634356 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::stdev 1.284426 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::0 64211383 71.33% 71.33% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::1 11984837 13.31% 84.64% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::2 5359973 5.95% 90.60% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::3 3439210 3.82% 94.42% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::4 2607784 2.90% 97.31% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::5 1324300 1.47% 98.78% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::6 687470 0.76% 99.55% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::7 352783 0.39% 99.94% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::8 54610 0.06% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::total 90022350 # Number of insts issued each cycle 468system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 469system.cpu.iq.fu_full::IntAlu 75162 9.94% 9.94% # attempts to use FU when none available 470system.cpu.iq.fu_full::IntMult 0 0.00% 9.94% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntDiv 0 0.00% 9.94% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.94% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.94% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.94% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatMult 0 0.00% 9.94% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.94% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.94% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.94% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.94% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.94% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.94% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.94% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.94% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMult 0 0.00% 9.94% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.94% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdShift 0 0.00% 9.94% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.94% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.94% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.94% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.94% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.94% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.94% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.94% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.94% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.94% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.94% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.94% # attempts to use FU when none available 498system.cpu.iq.fu_full::MemRead 361865 47.84% 57.78% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemWrite 319378 42.22% 100.00% # attempts to use FU when none available 500system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 502system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued 503system.cpu.iq.FU_type_0::IntAlu 38979239 68.26% 68.27% # Type of FU issued 504system.cpu.iq.FU_type_0::IntMult 61855 0.11% 68.38% # Type of FU issued 505system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued 506system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued 532system.cpu.iq.FU_type_0::MemRead 10375615 18.17% 86.60% # Type of FU issued 533system.cpu.iq.FU_type_0::MemWrite 6703515 11.74% 98.34% # Type of FU issued 534system.cpu.iq.FU_type_0::IprAccess 949472 1.66% 100.00% # Type of FU issued 535system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::total 57106230 # Type of FU issued 537system.cpu.iq.rate 0.457882 # Inst issue rate 538system.cpu.iq.fu_busy_cnt 756405 # FU busy when requested 539system.cpu.iq.fu_busy_rate 0.013246 # FU busy rate (busy events/executed inst) 540system.cpu.iq.int_inst_queue_reads 204420366 # Number of integer instruction queue reads 541system.cpu.iq.int_inst_queue_writes 68047675 # Number of integer instruction queue writes 542system.cpu.iq.int_inst_queue_wakeup_accesses 55829438 # Number of integer instruction queue wakeup accesses 543system.cpu.iq.fp_inst_queue_reads 696851 # Number of floating instruction queue reads 544system.cpu.iq.fp_inst_queue_writes 339603 # Number of floating instruction queue writes 545system.cpu.iq.fp_inst_queue_wakeup_accesses 327742 # Number of floating instruction queue wakeup accesses 546system.cpu.iq.int_alu_accesses 57490896 # Number of integer alu accesses 547system.cpu.iq.fp_alu_accesses 364448 # Number of floating point alu accesses 548system.cpu.iew.lsq.thread0.forwLoads 598206 # Number of loads that had data forwarded from stores 549system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 550system.cpu.iew.lsq.thread0.squashedLoads 1442254 # Number of loads squashed 551system.cpu.iew.lsq.thread0.ignoredResponses 2799 # Number of memory responses ignored because the instruction is squashed 552system.cpu.iew.lsq.thread0.memOrderViolation 13958 # Number of memory ordering violations 553system.cpu.iew.lsq.thread0.squashedStores 583775 # Number of stores squashed 554system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 555system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 556system.cpu.iew.lsq.thread0.rescheduledLoads 17984 # Number of loads that were rescheduled 557system.cpu.iew.lsq.thread0.cacheBlocked 104066 # Number of times an access to memory failed due to the cache being blocked 558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 559system.cpu.iew.iewSquashCycles 1362881 # Number of cycles IEW is squashing 560system.cpu.iew.iewBlockCycles 12351222 # Number of cycles IEW is blocking 561system.cpu.iew.iewUnblockCycles 868923 # Number of cycles IEW is unblocking 562system.cpu.iew.iewDispatchedInsts 64407898 # Number of instructions dispatched to IQ 563system.cpu.iew.iewDispSquashedInsts 684720 # Number of squashed instructions skipped by dispatch 564system.cpu.iew.iewDispLoadInsts 10525150 # Number of dispatched load instructions 565system.cpu.iew.iewDispStoreInsts 6958577 # Number of dispatched store instructions 566system.cpu.iew.iewDispNonSpecInsts 1840963 # Number of dispatched non-speculative instructions 567system.cpu.iew.iewIQFullEvents 621108 # Number of times the IQ has become full, causing a stall 568system.cpu.iew.iewLSQFullEvents 12330 # Number of times the LSQ has become full, causing a stall 569system.cpu.iew.memOrderViolationEvents 13958 # Number of memory order violations 570system.cpu.iew.predictedTakenIncorrect 238471 # Number of branches that were predicted taken incorrectly 571system.cpu.iew.predictedNotTakenIncorrect 421447 # Number of branches that were predicted not taken incorrectly 572system.cpu.iew.branchMispredicts 659918 # Number of branch mispredicts detected at execute 573system.cpu.iew.iewExecutedInsts 56579740 # Number of executed instructions 574system.cpu.iew.iewExecLoadInsts 10008035 # Number of load instructions executed 575system.cpu.iew.iewExecSquashedInsts 526489 # Number of squashed instructions skipped in execute 576system.cpu.iew.exec_swp 0 # number of swp insts executed 577system.cpu.iew.exec_nop 3562440 # number of nop insts executed 578system.cpu.iew.exec_refs 16658473 # number of memory reference insts executed 579system.cpu.iew.exec_branches 8978804 # Number of branches executed 580system.cpu.iew.exec_stores 6650438 # Number of stores executed 581system.cpu.iew.exec_rate 0.453661 # Inst execution rate 582system.cpu.iew.wb_sent 56268334 # cumulative count of insts sent to commit 583system.cpu.iew.wb_count 56157180 # cumulative count of insts written-back 584system.cpu.iew.wb_producers 27683314 # num instructions producing a value 585system.cpu.iew.wb_consumers 37519561 # num instructions consuming a value 586system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 587system.cpu.iew.wb_rate 0.450273 # insts written-back per cycle 588system.cpu.iew.wb_fanout 0.737837 # average fanout of values written-back 589system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 590system.cpu.commit.commitCommittedInsts 56104643 # The number of committed instructions 591system.cpu.commit.commitCommittedOps 56104643 # The number of committed instructions 592system.cpu.commit.commitSquashedInsts 8193317 # The number of squashed insts skipped by commit 593system.cpu.commit.commitNonSpecStalls 665267 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 615735 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 88659469 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.632811 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.547834 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::0 67465140 76.09% 76.09% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 8924230 10.07% 86.16% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 4814714 5.43% 91.59% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 2600553 2.93% 94.52% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 1445109 1.63% 96.15% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 596766 0.67% 96.83% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 516883 0.58% 97.41% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 484830 0.55% 97.96% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 1811244 2.04% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::total 88659469 # Number of insts commited each cycle 612system.cpu.commit.committedInsts 56104643 # Number of instructions committed 613system.cpu.commit.committedOps 56104643 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 15457698 # Number of memory references committed 616system.cpu.commit.loads 9082896 # Number of loads committed 617system.cpu.commit.membars 226441 # Number of memory barriers committed 618system.cpu.commit.branches 8439531 # Number of branches committed 619system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 620system.cpu.commit.int_insts 51953528 # Number of committed integer instructions. 621system.cpu.commit.function_calls 739583 # Number of function calls committed. 622system.cpu.commit.bw_lim_events 1811244 # number cycles where commit BW limit reached 623system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 624system.cpu.rob.rob_reads 150896568 # The number of ROB reads 625system.cpu.rob.rob_writes 129959625 # The number of ROB writes 626system.cpu.timesIdled 1384663 # Number of times that the entire CPU went into an idle state and unscheduled itself 627system.cpu.idleCycles 34695817 # Total number of cycles that the CPU has spent unscheduled due to idling 628system.cpu.quiesceCycles 3604162300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 629system.cpu.committedInsts 52917560 # Number of Instructions Simulated 630system.cpu.committedOps 52917560 # Number of Ops (including micro ops) Simulated 631system.cpu.committedInsts_total 52917560 # Number of Instructions Simulated 632system.cpu.cpi 2.356839 # CPI: Cycles Per Instruction 633system.cpu.cpi_total 2.356839 # CPI: Total CPI of All Threads 634system.cpu.ipc 0.424297 # IPC: Instructions Per Cycle 635system.cpu.ipc_total 0.424297 # IPC: Total IPC of All Threads 636system.cpu.int_regfile_reads 74164887 # number of integer regfile reads 637system.cpu.int_regfile_writes 40500361 # number of integer regfile writes 638system.cpu.fp_regfile_reads 166351 # number of floating regfile reads 639system.cpu.fp_regfile_writes 166958 # number of floating regfile writes 640system.cpu.misc_regfile_reads 1995249 # number of misc regfile reads 641system.cpu.misc_regfile_writes 947406 # number of misc regfile writes 642system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 643system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 644system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 645system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 646system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 647system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 648system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 649system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 650system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 651system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 652system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 653system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 654system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 655system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 656system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 657system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 658system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 659system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 660system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 661system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 662system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 663system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 664system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 665system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 666system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 667system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 668system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 669system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 670system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 671system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 672system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 673system.cpu.icache.replacements 1021086 # number of replacements 674system.cpu.icache.tagsinuse 509.954176 # Cycle average of tags in use 675system.cpu.icache.total_refs 7728678 # Total number of references to valid blocks. 676system.cpu.icache.sampled_refs 1021597 # Sample count of references to valid blocks. 677system.cpu.icache.avg_refs 7.565290 # Average number of references to valid blocks. 678system.cpu.icache.warmup_cycle 23896761000 # Cycle when the warmup percentage was hit. 679system.cpu.icache.occ_blocks::cpu.inst 509.954176 # Average occupied blocks per requestor 680system.cpu.icache.occ_percent::cpu.inst 0.996004 # Average percentage of cache occupancy 681system.cpu.icache.occ_percent::total 0.996004 # Average percentage of cache occupancy 682system.cpu.icache.ReadReq_hits::cpu.inst 7728679 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 7728679 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 7728679 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 7728679 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 7728679 # number of overall hits 687system.cpu.icache.overall_hits::total 7728679 # number of overall hits 688system.cpu.icache.ReadReq_misses::cpu.inst 1081971 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 1081971 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 1081971 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 1081971 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 1081971 # number of overall misses 693system.cpu.icache.overall_misses::total 1081971 # number of overall misses 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 17450602485 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 17450602485 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 17450602485 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 17450602485 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 17450602485 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 17450602485 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 8810650 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 8810650 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 8810650 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 8810650 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 8810650 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 8810650 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122803 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.122803 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.122803 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.122803 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.122803 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.122803 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16128.530695 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 16128.530695 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 16128.530695 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 16128.530695 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 16128.530695 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 16128.530695 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 1774492 # number of cycles access was blocked 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 205 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.avg_blocked_cycles::no_mshrs 8656.058537 # average number of cycles each access was blocked 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed 726system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60133 # number of ReadReq MSHR hits 727system.cpu.icache.ReadReq_mshr_hits::total 60133 # number of ReadReq MSHR hits 728system.cpu.icache.demand_mshr_hits::cpu.inst 60133 # number of demand (read+write) MSHR hits 729system.cpu.icache.demand_mshr_hits::total 60133 # number of demand (read+write) MSHR hits 730system.cpu.icache.overall_mshr_hits::cpu.inst 60133 # number of overall MSHR hits 731system.cpu.icache.overall_mshr_hits::total 60133 # number of overall MSHR hits 732system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021838 # number of ReadReq MSHR misses 733system.cpu.icache.ReadReq_mshr_misses::total 1021838 # number of ReadReq MSHR misses 734system.cpu.icache.demand_mshr_misses::cpu.inst 1021838 # number of demand (read+write) MSHR misses 735system.cpu.icache.demand_mshr_misses::total 1021838 # number of demand (read+write) MSHR misses 736system.cpu.icache.overall_mshr_misses::cpu.inst 1021838 # number of overall MSHR misses 737system.cpu.icache.overall_mshr_misses::total 1021838 # number of overall MSHR misses 738system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13459032492 # number of ReadReq MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_miss_latency::total 13459032492 # number of ReadReq MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13459032492 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.demand_mshr_miss_latency::total 13459032492 # number of demand (read+write) MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13459032492 # number of overall MSHR miss cycles 743system.cpu.icache.overall_mshr_miss_latency::total 13459032492 # number of overall MSHR miss cycles 744system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115978 # mshr miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115978 # mshr miss rate for ReadReq accesses 746system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115978 # mshr miss rate for demand accesses 747system.cpu.icache.demand_mshr_miss_rate::total 0.115978 # mshr miss rate for demand accesses 748system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115978 # mshr miss rate for overall accesses 749system.cpu.icache.overall_mshr_miss_rate::total 0.115978 # mshr miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13171.395556 # average ReadReq mshr miss latency 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13171.395556 # average ReadReq mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13171.395556 # average overall mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::total 13171.395556 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13171.395556 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::total 13171.395556 # average overall mshr miss latency 756system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 757system.cpu.dcache.replacements 1401888 # number of replacements 758system.cpu.dcache.tagsinuse 511.994858 # Cycle average of tags in use 759system.cpu.dcache.total_refs 11830963 # Total number of references to valid blocks. 760system.cpu.dcache.sampled_refs 1402400 # Sample count of references to valid blocks. 761system.cpu.dcache.avg_refs 8.436226 # Average number of references to valid blocks. 762system.cpu.dcache.warmup_cycle 23765000 # Cycle when the warmup percentage was hit. 763system.cpu.dcache.occ_blocks::cpu.data 511.994858 # Average occupied blocks per requestor 764system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 765system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy 766system.cpu.dcache.ReadReq_hits::cpu.data 7247947 # number of ReadReq hits 767system.cpu.dcache.ReadReq_hits::total 7247947 # number of ReadReq hits 768system.cpu.dcache.WriteReq_hits::cpu.data 4173007 # number of WriteReq hits 769system.cpu.dcache.WriteReq_hits::total 4173007 # number of WriteReq hits 770system.cpu.dcache.LoadLockedReq_hits::cpu.data 190139 # number of LoadLockedReq hits 771system.cpu.dcache.LoadLockedReq_hits::total 190139 # number of LoadLockedReq hits 772system.cpu.dcache.StoreCondReq_hits::cpu.data 219622 # number of StoreCondReq hits 773system.cpu.dcache.StoreCondReq_hits::total 219622 # number of StoreCondReq hits 774system.cpu.dcache.demand_hits::cpu.data 11420954 # number of demand (read+write) hits 775system.cpu.dcache.demand_hits::total 11420954 # number of demand (read+write) hits 776system.cpu.dcache.overall_hits::cpu.data 11420954 # number of overall hits 777system.cpu.dcache.overall_hits::total 11420954 # number of overall hits 778system.cpu.dcache.ReadReq_misses::cpu.data 1826719 # number of ReadReq misses 779system.cpu.dcache.ReadReq_misses::total 1826719 # number of ReadReq misses 780system.cpu.dcache.WriteReq_misses::cpu.data 1967450 # number of WriteReq misses 781system.cpu.dcache.WriteReq_misses::total 1967450 # number of WriteReq misses 782system.cpu.dcache.LoadLockedReq_misses::cpu.data 23276 # number of LoadLockedReq misses 783system.cpu.dcache.LoadLockedReq_misses::total 23276 # number of LoadLockedReq misses 784system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 785system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 786system.cpu.dcache.demand_misses::cpu.data 3794169 # number of demand (read+write) misses 787system.cpu.dcache.demand_misses::total 3794169 # number of demand (read+write) misses 788system.cpu.dcache.overall_misses::cpu.data 3794169 # number of overall misses 789system.cpu.dcache.overall_misses::total 3794169 # number of overall misses 790system.cpu.dcache.ReadReq_miss_latency::cpu.data 48828356500 # number of ReadReq miss cycles 791system.cpu.dcache.ReadReq_miss_latency::total 48828356500 # number of ReadReq miss cycles 792system.cpu.dcache.WriteReq_miss_latency::cpu.data 75021141961 # number of WriteReq miss cycles 793system.cpu.dcache.WriteReq_miss_latency::total 75021141961 # number of WriteReq miss cycles 794system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 428009500 # number of LoadLockedReq miss cycles 795system.cpu.dcache.LoadLockedReq_miss_latency::total 428009500 # number of LoadLockedReq miss cycles 796system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 154000 # number of StoreCondReq miss cycles 797system.cpu.dcache.StoreCondReq_miss_latency::total 154000 # number of StoreCondReq miss cycles 798system.cpu.dcache.demand_miss_latency::cpu.data 123849498461 # number of demand (read+write) miss cycles 799system.cpu.dcache.demand_miss_latency::total 123849498461 # number of demand (read+write) miss cycles 800system.cpu.dcache.overall_miss_latency::cpu.data 123849498461 # number of overall miss cycles 801system.cpu.dcache.overall_miss_latency::total 123849498461 # number of overall miss cycles 802system.cpu.dcache.ReadReq_accesses::cpu.data 9074666 # number of ReadReq accesses(hits+misses) 803system.cpu.dcache.ReadReq_accesses::total 9074666 # number of ReadReq accesses(hits+misses) 804system.cpu.dcache.WriteReq_accesses::cpu.data 6140457 # number of WriteReq accesses(hits+misses) 805system.cpu.dcache.WriteReq_accesses::total 6140457 # number of WriteReq accesses(hits+misses) 806system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213415 # number of LoadLockedReq accesses(hits+misses) 807system.cpu.dcache.LoadLockedReq_accesses::total 213415 # number of LoadLockedReq accesses(hits+misses) 808system.cpu.dcache.StoreCondReq_accesses::cpu.data 219627 # number of StoreCondReq accesses(hits+misses) 809system.cpu.dcache.StoreCondReq_accesses::total 219627 # number of StoreCondReq accesses(hits+misses) 810system.cpu.dcache.demand_accesses::cpu.data 15215123 # number of demand (read+write) accesses 811system.cpu.dcache.demand_accesses::total 15215123 # number of demand (read+write) accesses 812system.cpu.dcache.overall_accesses::cpu.data 15215123 # number of overall (read+write) accesses 813system.cpu.dcache.overall_accesses::total 15215123 # number of overall (read+write) accesses 814system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.201299 # miss rate for ReadReq accesses 815system.cpu.dcache.ReadReq_miss_rate::total 0.201299 # miss rate for ReadReq accesses 816system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320408 # miss rate for WriteReq accesses 817system.cpu.dcache.WriteReq_miss_rate::total 0.320408 # miss rate for WriteReq accesses 818system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109064 # miss rate for LoadLockedReq accesses 819system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109064 # miss rate for LoadLockedReq accesses 820system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses 821system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses 822system.cpu.dcache.demand_miss_rate::cpu.data 0.249368 # miss rate for demand accesses 823system.cpu.dcache.demand_miss_rate::total 0.249368 # miss rate for demand accesses 824system.cpu.dcache.overall_miss_rate::cpu.data 0.249368 # miss rate for overall accesses 825system.cpu.dcache.overall_miss_rate::total 0.249368 # miss rate for overall accesses 826system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26730.086291 # average ReadReq miss latency 827system.cpu.dcache.ReadReq_avg_miss_latency::total 26730.086291 # average ReadReq miss latency 828system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38131.155537 # average WriteReq miss latency 829system.cpu.dcache.WriteReq_avg_miss_latency::total 38131.155537 # average WriteReq miss latency 830system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18388.447328 # average LoadLockedReq miss latency 831system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18388.447328 # average LoadLockedReq miss latency 832system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30800 # average StoreCondReq miss latency 833system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30800 # average StoreCondReq miss latency 834system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency 835system.cpu.dcache.demand_avg_miss_latency::total 32642.061664 # average overall miss latency 836system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.061664 # average overall miss latency 837system.cpu.dcache.overall_avg_miss_latency::total 32642.061664 # average overall miss latency 838system.cpu.dcache.blocked_cycles::no_mshrs 733938028 # number of cycles access was blocked 839system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked 840system.cpu.dcache.blocked::no_mshrs 72096 # number of cycles access was blocked 841system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 842system.cpu.dcache.avg_blocked_cycles::no_mshrs 10180.010375 # average number of cycles each access was blocked 843system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked 844system.cpu.dcache.fast_writes 0 # number of fast writes performed 845system.cpu.dcache.cache_copies 0 # number of cache copies performed 846system.cpu.dcache.writebacks::writebacks 840935 # number of writebacks 847system.cpu.dcache.writebacks::total 840935 # number of writebacks 848system.cpu.dcache.ReadReq_mshr_hits::cpu.data 742319 # number of ReadReq MSHR hits 849system.cpu.dcache.ReadReq_mshr_hits::total 742319 # number of ReadReq MSHR hits 850system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667295 # number of WriteReq MSHR hits 851system.cpu.dcache.WriteReq_mshr_hits::total 1667295 # number of WriteReq MSHR hits 852system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits 853system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits 854system.cpu.dcache.demand_mshr_hits::cpu.data 2409614 # number of demand (read+write) MSHR hits 855system.cpu.dcache.demand_mshr_hits::total 2409614 # number of demand (read+write) MSHR hits 856system.cpu.dcache.overall_mshr_hits::cpu.data 2409614 # number of overall MSHR hits 857system.cpu.dcache.overall_mshr_hits::total 2409614 # number of overall MSHR hits 858system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084400 # number of ReadReq MSHR misses 859system.cpu.dcache.ReadReq_mshr_misses::total 1084400 # number of ReadReq MSHR misses 860system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300155 # number of WriteReq MSHR misses 861system.cpu.dcache.WriteReq_mshr_misses::total 300155 # number of WriteReq MSHR misses 862system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18015 # number of LoadLockedReq MSHR misses 863system.cpu.dcache.LoadLockedReq_mshr_misses::total 18015 # number of LoadLockedReq MSHR misses 864system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 865system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 866system.cpu.dcache.demand_mshr_misses::cpu.data 1384555 # number of demand (read+write) MSHR misses 867system.cpu.dcache.demand_mshr_misses::total 1384555 # number of demand (read+write) MSHR misses 868system.cpu.dcache.overall_mshr_misses::cpu.data 1384555 # number of overall MSHR misses 869system.cpu.dcache.overall_mshr_misses::total 1384555 # number of overall MSHR misses 870system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231864000 # number of ReadReq MSHR miss cycles 871system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231864000 # number of ReadReq MSHR miss cycles 872system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9653593940 # number of WriteReq MSHR miss cycles 873system.cpu.dcache.WriteReq_mshr_miss_latency::total 9653593940 # number of WriteReq MSHR miss cycles 874system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269637000 # number of LoadLockedReq MSHR miss cycles 875system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269637000 # number of LoadLockedReq MSHR miss cycles 876system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 138000 # number of StoreCondReq MSHR miss cycles 877system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 138000 # number of StoreCondReq MSHR miss cycles 878system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37885457940 # number of demand (read+write) MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::total 37885457940 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37885457940 # number of overall MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::total 37885457940 # number of overall MSHR miss cycles 882system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423534500 # number of ReadReq MSHR uncacheable cycles 883system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423534500 # number of ReadReq MSHR uncacheable cycles 884system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2001030998 # number of WriteReq MSHR uncacheable cycles 885system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2001030998 # number of WriteReq MSHR uncacheable cycles 886system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3424565498 # number of overall MSHR uncacheable cycles 887system.cpu.dcache.overall_mshr_uncacheable_latency::total 3424565498 # number of overall MSHR uncacheable cycles 888system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119498 # mshr miss rate for ReadReq accesses 889system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119498 # mshr miss rate for ReadReq accesses 890system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048882 # mshr miss rate for WriteReq accesses 891system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048882 # mshr miss rate for WriteReq accesses 892system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084413 # mshr miss rate for LoadLockedReq accesses 893system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084413 # mshr miss rate for LoadLockedReq accesses 894system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses 895system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses 896system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for demand accesses 897system.cpu.dcache.demand_mshr_miss_rate::total 0.090999 # mshr miss rate for demand accesses 898system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090999 # mshr miss rate for overall accesses 899system.cpu.dcache.overall_mshr_miss_rate::total 0.090999 # mshr miss rate for overall accesses 900system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26034.548137 # average ReadReq mshr miss latency 901system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26034.548137 # average ReadReq mshr miss latency 902system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32162.029418 # average WriteReq mshr miss latency 903system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32162.029418 # average WriteReq mshr miss latency 904system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14967.360533 # average LoadLockedReq mshr miss latency 905system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14967.360533 # average LoadLockedReq mshr miss latency 906system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27600 # average StoreCondReq mshr miss latency 907system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27600 # average StoreCondReq mshr miss latency 908system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency 909system.cpu.dcache.demand_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency 910system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27362.912950 # average overall mshr miss latency 911system.cpu.dcache.overall_avg_mshr_miss_latency::total 27362.912950 # average overall mshr miss latency 912system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 913system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 914system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 915system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 916system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 917system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 918system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 919system.cpu.kern.inst.arm 0 # number of arm instructions executed 920system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed 921system.cpu.kern.inst.hwrei 211112 # number of hwrei instructions executed 922system.cpu.kern.ipl_count::0 74681 40.96% 40.96% # number of times we switched to this ipl 923system.cpu.kern.ipl_count::21 133 0.07% 41.03% # number of times we switched to this ipl 924system.cpu.kern.ipl_count::22 1886 1.03% 42.07% # number of times we switched to this ipl 925system.cpu.kern.ipl_count::31 105636 57.93% 100.00% # number of times we switched to this ipl 926system.cpu.kern.ipl_count::total 182336 # number of times we switched to this ipl 927system.cpu.kern.ipl_good::0 73314 49.32% 49.32% # number of times we switched to this ipl from a different ipl 928system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl 929system.cpu.kern.ipl_good::22 1886 1.27% 50.68% # number of times we switched to this ipl from a different ipl 930system.cpu.kern.ipl_good::31 73315 49.32% 100.00% # number of times we switched to this ipl from a different ipl 931system.cpu.kern.ipl_good::total 148648 # number of times we switched to this ipl from a different ipl 932system.cpu.kern.ipl_ticks::0 1823792488500 97.82% 97.82% # number of cycles we spent at this ipl 933system.cpu.kern.ipl_ticks::21 71545000 0.00% 97.82% # number of cycles we spent at this ipl 934system.cpu.kern.ipl_ticks::22 571672500 0.03% 97.85% # number of cycles we spent at this ipl 935system.cpu.kern.ipl_ticks::31 40006830500 2.15% 100.00% # number of cycles we spent at this ipl 936system.cpu.kern.ipl_ticks::total 1864442536500 # number of cycles we spent at this ipl 937system.cpu.kern.ipl_used::0 0.981695 # fraction of swpipl calls that actually changed the ipl 938system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 939system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 940system.cpu.kern.ipl_used::31 0.694034 # fraction of swpipl calls that actually changed the ipl 941system.cpu.kern.ipl_used::total 0.815242 # fraction of swpipl calls that actually changed the ipl 942system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 943system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 944system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 945system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 946system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 947system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 948system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 949system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 950system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 951system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 952system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 953system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 954system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 955system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 956system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 957system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 958system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 959system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 960system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 961system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 962system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 963system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 964system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 965system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 966system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 967system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 968system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 969system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 970system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 971system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 972system.cpu.kern.syscall::total 326 # number of syscalls executed 973system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 974system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 975system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 976system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 977system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed 978system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 979system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 980system.cpu.kern.callpal::swpipl 175205 91.22% 93.43% # number of callpals executed 981system.cpu.kern.callpal::rdps 6791 3.54% 96.97% # number of callpals executed 982system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 983system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 984system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 985system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 986system.cpu.kern.callpal::rti 5112 2.66% 99.64% # number of callpals executed 987system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 988system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 989system.cpu.kern.callpal::total 192064 # number of callpals executed 990system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches 991system.cpu.kern.mode_switch::user 1735 # number of protection mode switches 992system.cpu.kern.mode_switch::idle 2104 # number of protection mode switches 993system.cpu.kern.mode_good::kernel 1905 994system.cpu.kern.mode_good::user 1735 995system.cpu.kern.mode_good::idle 170 996system.cpu.kern.mode_switch_good::kernel 0.325641 # fraction of useful protection mode switches 997system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 998system.cpu.kern.mode_switch_good::idle 0.080798 # fraction of useful protection mode switches 999system.cpu.kern.mode_switch_good::total 0.393229 # fraction of useful protection mode switches 1000system.cpu.kern.mode_ticks::kernel 29922134000 1.60% 1.60% # number of ticks spent at the given mode 1001system.cpu.kern.mode_ticks::user 2785239500 0.15% 1.75% # number of ticks spent at the given mode 1002system.cpu.kern.mode_ticks::idle 1831735155000 98.25% 100.00% # number of ticks spent at the given mode 1003system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1004 1005---------- End Simulation Statistics ---------- 1006