stats.txt revision 8721
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.858874 # Number of seconds simulated 4sim_ticks 1858873594500 # Number of ticks simulated 5final_tick 1858873594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 134152 # Simulator instruction rate (inst/s) 8host_tick_rate 4696460042 # Simulator tick rate (ticks/s) 9host_mem_usage 295432 # Number of bytes of host memory used 10host_seconds 395.80 # Real time elapsed on the host 11sim_insts 53097697 # Number of instructions simulated 12system.physmem.bytes_read 29819840 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 1062784 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 10193408 # Number of bytes written to this memory 15system.physmem.num_reads 465935 # Number of read requests responded to by this memory 16system.physmem.num_writes 159272 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 16041887 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 571735 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 5483648 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 21525535 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 391354 # number of replacements 23system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use 24system.l2c.total_refs 2410581 # Total number of references to valid blocks. 25system.l2c.sampled_refs 424231 # Sample count of references to valid blocks. 26system.l2c.avg_refs 5.682237 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 12293.296692 # Average occupied blocks per context 29system.l2c.occ_blocks::1 22604.789448 # Average occupied blocks per context 30system.l2c.occ_percent::0 0.187581 # Average percentage of cache occupancy 31system.l2c.occ_percent::1 0.344922 # Average percentage of cache occupancy 32system.l2c.ReadReq_hits::0 1801188 # number of ReadReq hits 33system.l2c.ReadReq_hits::total 1801188 # number of ReadReq hits 34system.l2c.Writeback_hits::0 835090 # number of Writeback hits 35system.l2c.Writeback_hits::total 835090 # number of Writeback hits 36system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits 37system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits 38system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits 39system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 40system.l2c.ReadExReq_hits::0 183163 # number of ReadExReq hits 41system.l2c.ReadExReq_hits::total 183163 # number of ReadExReq hits 42system.l2c.demand_hits::0 1984351 # number of demand (read+write) hits 43system.l2c.demand_hits::1 0 # number of demand (read+write) hits 44system.l2c.demand_hits::total 1984351 # number of demand (read+write) hits 45system.l2c.overall_hits::0 1984351 # number of overall hits 46system.l2c.overall_hits::1 0 # number of overall hits 47system.l2c.overall_hits::total 1984351 # number of overall hits 48system.l2c.ReadReq_misses::0 308072 # number of ReadReq misses 49system.l2c.ReadReq_misses::total 308072 # number of ReadReq misses 50system.l2c.UpgradeReq_misses::0 33 # number of UpgradeReq misses 51system.l2c.UpgradeReq_misses::total 33 # number of UpgradeReq misses 52system.l2c.ReadExReq_misses::0 116926 # number of ReadExReq misses 53system.l2c.ReadExReq_misses::total 116926 # number of ReadExReq misses 54system.l2c.demand_misses::0 424998 # number of demand (read+write) misses 55system.l2c.demand_misses::1 0 # number of demand (read+write) misses 56system.l2c.demand_misses::total 424998 # number of demand (read+write) misses 57system.l2c.overall_misses::0 424998 # number of overall misses 58system.l2c.overall_misses::1 0 # number of overall misses 59system.l2c.overall_misses::total 424998 # number of overall misses 60system.l2c.ReadReq_miss_latency 16035098000 # number of ReadReq miss cycles 61system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles 62system.l2c.ReadExReq_miss_latency 6133668000 # number of ReadExReq miss cycles 63system.l2c.demand_miss_latency 22168766000 # number of demand (read+write) miss cycles 64system.l2c.overall_miss_latency 22168766000 # number of overall miss cycles 65system.l2c.ReadReq_accesses::0 2109260 # number of ReadReq accesses(hits+misses) 66system.l2c.ReadReq_accesses::total 2109260 # number of ReadReq accesses(hits+misses) 67system.l2c.Writeback_accesses::0 835090 # number of Writeback accesses(hits+misses) 68system.l2c.Writeback_accesses::total 835090 # number of Writeback accesses(hits+misses) 69system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) 70system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) 71system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) 72system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 73system.l2c.ReadExReq_accesses::0 300089 # number of ReadExReq accesses(hits+misses) 74system.l2c.ReadExReq_accesses::total 300089 # number of ReadExReq accesses(hits+misses) 75system.l2c.demand_accesses::0 2409349 # number of demand (read+write) accesses 76system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 77system.l2c.demand_accesses::total 2409349 # number of demand (read+write) accesses 78system.l2c.overall_accesses::0 2409349 # number of overall (read+write) accesses 79system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 80system.l2c.overall_accesses::total 2409349 # number of overall (read+write) accesses 81system.l2c.ReadReq_miss_rate::0 0.146057 # miss rate for ReadReq accesses 82system.l2c.UpgradeReq_miss_rate::0 0.673469 # miss rate for UpgradeReq accesses 83system.l2c.ReadExReq_miss_rate::0 0.389638 # miss rate for ReadExReq accesses 84system.l2c.demand_miss_rate::0 0.176395 # miss rate for demand accesses 85system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 86system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 87system.l2c.overall_miss_rate::0 0.176395 # miss rate for overall accesses 88system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 89system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 90system.l2c.ReadReq_avg_miss_latency::0 52049.838999 # average ReadReq miss latency 91system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 92system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 93system.l2c.UpgradeReq_avg_miss_latency::0 12878.787879 # average UpgradeReq miss latency 94system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 95system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 96system.l2c.ReadExReq_avg_miss_latency::0 52457.691189 # average ReadExReq miss latency 97system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 98system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 99system.l2c.demand_avg_miss_latency::0 52162.047821 # average overall miss latency 100system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency 101system.l2c.demand_avg_miss_latency::total inf # average overall miss latency 102system.l2c.overall_avg_miss_latency::0 52162.047821 # average overall miss latency 103system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency 104system.l2c.overall_avg_miss_latency::total inf # average overall miss latency 105system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 107system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 108system.l2c.blocked::no_targets 0 # number of cycles access was blocked 109system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 110system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 111system.l2c.fast_writes 0 # number of fast writes performed 112system.l2c.cache_copies 0 # number of cache copies performed 113system.l2c.writebacks 117760 # number of writebacks 114system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 115system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 116system.l2c.ReadReq_mshr_misses 308072 # number of ReadReq MSHR misses 117system.l2c.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses 118system.l2c.ReadExReq_mshr_misses 116926 # number of ReadExReq MSHR misses 119system.l2c.demand_mshr_misses 424998 # number of demand (read+write) MSHR misses 120system.l2c.overall_mshr_misses 424998 # number of overall MSHR misses 121system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 122system.l2c.ReadReq_mshr_miss_latency 12331827500 # number of ReadReq MSHR miss cycles 123system.l2c.UpgradeReq_mshr_miss_latency 1380000 # number of UpgradeReq MSHR miss cycles 124system.l2c.ReadExReq_mshr_miss_latency 4711722000 # number of ReadExReq MSHR miss cycles 125system.l2c.demand_mshr_miss_latency 17043549500 # number of demand (read+write) MSHR miss cycles 126system.l2c.overall_mshr_miss_latency 17043549500 # number of overall MSHR miss cycles 127system.l2c.ReadReq_mshr_uncacheable_latency 810479000 # number of ReadReq MSHR uncacheable cycles 128system.l2c.WriteReq_mshr_uncacheable_latency 1115452498 # number of WriteReq MSHR uncacheable cycles 129system.l2c.overall_mshr_uncacheable_latency 1925931498 # number of overall MSHR uncacheable cycles 130system.l2c.ReadReq_mshr_miss_rate::0 0.146057 # mshr miss rate for ReadReq accesses 131system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 132system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 133system.l2c.UpgradeReq_mshr_miss_rate::0 0.673469 # mshr miss rate for UpgradeReq accesses 134system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 135system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 136system.l2c.ReadExReq_mshr_miss_rate::0 0.389638 # mshr miss rate for ReadExReq accesses 137system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 138system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 139system.l2c.demand_mshr_miss_rate::0 0.176395 # mshr miss rate for demand accesses 140system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 141system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 142system.l2c.overall_mshr_miss_rate::0 0.176395 # mshr miss rate for overall accesses 143system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 144system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 145system.l2c.ReadReq_avg_mshr_miss_latency 40029.043535 # average ReadReq mshr miss latency 146system.l2c.UpgradeReq_avg_mshr_miss_latency 41818.181818 # average UpgradeReq mshr miss latency 147system.l2c.ReadExReq_avg_mshr_miss_latency 40296.614953 # average ReadExReq mshr miss latency 148system.l2c.demand_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency 149system.l2c.overall_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency 150system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 151system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 152system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 153system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 154system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 155system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 156system.iocache.replacements 41685 # number of replacements 157system.iocache.tagsinuse 1.268274 # Cycle average of tags in use 158system.iocache.total_refs 0 # Total number of references to valid blocks. 159system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 160system.iocache.avg_refs 0 # Average number of references to valid blocks. 161system.iocache.warmup_cycle 1708338694000 # Cycle when the warmup percentage was hit. 162system.iocache.occ_blocks::1 1.268274 # Average occupied blocks per context 163system.iocache.occ_percent::1 0.079267 # Average percentage of cache occupancy 164system.iocache.demand_hits::0 0 # number of demand (read+write) hits 165system.iocache.demand_hits::1 0 # number of demand (read+write) hits 166system.iocache.demand_hits::total 0 # number of demand (read+write) hits 167system.iocache.overall_hits::0 0 # number of overall hits 168system.iocache.overall_hits::1 0 # number of overall hits 169system.iocache.overall_hits::total 0 # number of overall hits 170system.iocache.ReadReq_misses::1 173 # number of ReadReq misses 171system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 172system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 173system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 174system.iocache.demand_misses::0 0 # number of demand (read+write) misses 175system.iocache.demand_misses::1 41725 # number of demand (read+write) misses 176system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 177system.iocache.overall_misses::0 0 # number of overall misses 178system.iocache.overall_misses::1 41725 # number of overall misses 179system.iocache.overall_misses::total 41725 # number of overall misses 180system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles 181system.iocache.WriteReq_miss_latency 5722643806 # number of WriteReq miss cycles 182system.iocache.demand_miss_latency 5742583804 # number of demand (read+write) miss cycles 183system.iocache.overall_miss_latency 5742583804 # number of overall miss cycles 184system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) 185system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 186system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 187system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 188system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 189system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses 190system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 191system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 192system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses 193system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 194system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 195system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 196system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 197system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 198system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 199system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 200system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 201system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 202system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 203system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency 204system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 205system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 206system.iocache.WriteReq_avg_miss_latency::1 137722.463564 # average WriteReq miss latency 207system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 208system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 209system.iocache.demand_avg_miss_latency::1 137629.330234 # average overall miss latency 210system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 211system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 212system.iocache.overall_avg_miss_latency::1 137629.330234 # average overall miss latency 213system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 214system.iocache.blocked_cycles::no_mshrs 64634068 # number of cycles access was blocked 215system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 216system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked 217system.iocache.blocked::no_targets 0 # number of cycles access was blocked 218system.iocache.avg_blocked_cycles::no_mshrs 6174.442874 # average number of cycles each access was blocked 219system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 220system.iocache.fast_writes 0 # number of fast writes performed 221system.iocache.cache_copies 0 # number of cache copies performed 222system.iocache.writebacks 41512 # number of writebacks 223system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 224system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 225system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 226system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 227system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 228system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 229system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 230system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles 231system.iocache.WriteReq_mshr_miss_latency 3561790996 # number of WriteReq MSHR miss cycles 232system.iocache.demand_mshr_miss_latency 3572734994 # number of demand (read+write) MSHR miss cycles 233system.iocache.overall_mshr_miss_latency 3572734994 # number of overall MSHR miss cycles 234system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 235system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 236system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 237system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 238system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 239system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 240system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 241system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 242system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 243system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 244system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 245system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 246system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 247system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency 248system.iocache.WriteReq_avg_mshr_miss_latency 85718.882268 # average WriteReq mshr miss latency 249system.iocache.demand_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency 250system.iocache.overall_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency 251system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 252system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 253system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 254system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 255system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 256system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 257system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 258system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 259system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 260system.disk0.dma_write_txs 395 # Number of DMA write transactions. 261system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 262system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 263system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 264system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 265system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 266system.disk2.dma_write_txs 1 # Number of DMA write transactions. 267system.cpu.dtb.fetch_hits 0 # ITB hits 268system.cpu.dtb.fetch_misses 0 # ITB misses 269system.cpu.dtb.fetch_acv 0 # ITB acv 270system.cpu.dtb.fetch_accesses 0 # ITB accesses 271system.cpu.dtb.read_hits 10138302 # DTB read hits 272system.cpu.dtb.read_misses 46569 # DTB read misses 273system.cpu.dtb.read_acv 588 # DTB read access violations 274system.cpu.dtb.read_accesses 971478 # DTB read accesses 275system.cpu.dtb.write_hits 6627002 # DTB write hits 276system.cpu.dtb.write_misses 12216 # DTB write misses 277system.cpu.dtb.write_acv 416 # DTB write access violations 278system.cpu.dtb.write_accesses 347261 # DTB write accesses 279system.cpu.dtb.data_hits 16765304 # DTB hits 280system.cpu.dtb.data_misses 58785 # DTB misses 281system.cpu.dtb.data_acv 1004 # DTB access violations 282system.cpu.dtb.data_accesses 1318739 # DTB accesses 283system.cpu.itb.fetch_hits 1327158 # ITB hits 284system.cpu.itb.fetch_misses 39816 # ITB misses 285system.cpu.itb.fetch_acv 1096 # ITB acv 286system.cpu.itb.fetch_accesses 1366974 # ITB accesses 287system.cpu.itb.read_hits 0 # DTB read hits 288system.cpu.itb.read_misses 0 # DTB read misses 289system.cpu.itb.read_acv 0 # DTB read access violations 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_acv 0 # DTB write access violations 294system.cpu.itb.write_accesses 0 # DTB write accesses 295system.cpu.itb.data_hits 0 # DTB hits 296system.cpu.itb.data_misses 0 # DTB misses 297system.cpu.itb.data_acv 0 # DTB access violations 298system.cpu.itb.data_accesses 0 # DTB accesses 299system.cpu.numCycles 116293341 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.BPredUnit.lookups 14403200 # Number of BP lookups 303system.cpu.BPredUnit.condPredicted 12045652 # Number of conditional branches predicted 304system.cpu.BPredUnit.condIncorrect 530716 # Number of conditional branches incorrect 305system.cpu.BPredUnit.BTBLookups 12993662 # Number of BTB lookups 306system.cpu.BPredUnit.BTBHits 6702662 # Number of BTB hits 307system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 308system.cpu.BPredUnit.usedRAS 972407 # Number of times the RAS was used to get a target. 309system.cpu.BPredUnit.RASInCorrect 45058 # Number of incorrect RAS predictions. 310system.cpu.fetch.icacheStallCycles 29094387 # Number of cycles fetch is stalled on an Icache miss 311system.cpu.fetch.Insts 73505774 # Number of instructions fetch has processed 312system.cpu.fetch.Branches 14403200 # Number of branches that fetch encountered 313system.cpu.fetch.predictedBranches 7675069 # Number of branches that fetch has predicted taken 314system.cpu.fetch.Cycles 14268794 # Number of cycles fetch has run and was not squashing or blocked 315system.cpu.fetch.SquashCycles 2359863 # Number of cycles fetch has spent squashing 316system.cpu.fetch.BlockedCycles 36645005 # Number of cycles fetch has spent blocked 317system.cpu.fetch.MiscStallCycles 31889 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 318system.cpu.fetch.PendingTrapStallCycles 259043 # Number of stall cycles due to pending traps 319system.cpu.fetch.PendingQuiesceStallCycles 335706 # Number of stall cycles due to pending quiesce instructions 320system.cpu.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR 321system.cpu.fetch.CacheLines 9051868 # Number of cache lines fetched 322system.cpu.fetch.IcacheSquashes 321893 # Number of outstanding Icache misses that were squashed 323system.cpu.fetch.rateDist::samples 82174946 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::mean 0.894503 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::stdev 2.211429 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::0 67906152 82.64% 82.64% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::1 1023009 1.24% 83.88% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::2 2022244 2.46% 86.34% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::3 965640 1.18% 87.52% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::4 2953506 3.59% 91.11% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::5 686113 0.83% 91.95% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::6 790817 0.96% 92.91% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::7 1067854 1.30% 94.21% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::8 4759611 5.79% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::total 82174946 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.branchRate 0.123852 # Number of branch fetches per cycle 341system.cpu.fetch.rate 0.632072 # Number of inst fetches per cycle 342system.cpu.decode.IdleCycles 30353273 # Number of cycles decode is idle 343system.cpu.decode.BlockedCycles 36299982 # Number of cycles decode is blocked 344system.cpu.decode.RunCycles 13051372 # Number of cycles decode is running 345system.cpu.decode.UnblockCycles 972104 # Number of cycles decode is unblocking 346system.cpu.decode.SquashCycles 1498214 # Number of cycles decode is squashing 347system.cpu.decode.BranchResolved 610003 # Number of times decode resolved a branch 348system.cpu.decode.BranchMispred 42096 # Number of times decode detected a branch misprediction 349system.cpu.decode.DecodedInsts 71896046 # Number of instructions handled by decode 350system.cpu.decode.SquashedInsts 128197 # Number of squashed instructions handled by decode 351system.cpu.rename.SquashCycles 1498214 # Number of cycles rename is squashing 352system.cpu.rename.IdleCycles 31555942 # Number of cycles rename is idle 353system.cpu.rename.BlockCycles 12820674 # Number of cycles rename is blocking 354system.cpu.rename.serializeStallCycles 19773044 # count of cycles rename stalled for serializing inst 355system.cpu.rename.RunCycles 12199083 # Number of cycles rename is running 356system.cpu.rename.UnblockCycles 4327987 # Number of cycles rename is unblocking 357system.cpu.rename.RenamedInsts 67967172 # Number of instructions processed by rename 358system.cpu.rename.ROBFullEvents 7022 # Number of times rename has blocked due to ROB full 359system.cpu.rename.IQFullEvents 504365 # Number of times rename has blocked due to IQ full 360system.cpu.rename.LSQFullEvents 1538985 # Number of times rename has blocked due to LSQ full 361system.cpu.rename.RenamedOperands 45476353 # Number of destination operands rename has renamed 362system.cpu.rename.RenameLookups 82567749 # Number of register rename lookups that rename has made 363system.cpu.rename.int_rename_lookups 82088652 # Number of integer rename lookups 364system.cpu.rename.fp_rename_lookups 479097 # Number of floating rename lookups 365system.cpu.rename.CommittedMaps 38265070 # Number of HB maps that are committed 366system.cpu.rename.UndoneMaps 7211275 # Number of HB maps that are undone due to squashing 367system.cpu.rename.serializingInsts 1700634 # count of serializing insts renamed 368system.cpu.rename.tempSerializingInsts 251496 # count of temporary serializing insts renamed 369system.cpu.rename.skidInsts 12093975 # count of insts added to the skid buffer 370system.cpu.memDep0.insertedLoads 10722948 # Number of loads inserted to the mem dependence unit. 371system.cpu.memDep0.insertedStores 6992313 # Number of stores inserted to the mem dependence unit. 372system.cpu.memDep0.conflictingLoads 1255970 # Number of conflicting loads. 373system.cpu.memDep0.conflictingStores 835280 # Number of conflicting stores. 374system.cpu.iq.iqInstsAdded 59689379 # Number of instructions added to the IQ (excludes non-spec) 375system.cpu.iq.iqNonSpecInstsAdded 2116105 # Number of non-speculative instructions added to the IQ 376system.cpu.iq.iqInstsIssued 57965210 # Number of instructions issued 377system.cpu.iq.iqSquashedInstsIssued 118570 # Number of squashed instructions issued 378system.cpu.iq.iqSquashedInstsExamined 8314088 # Number of squashed instructions iterated over during squash; mainly for profiling 379system.cpu.iq.iqSquashedOperandsExamined 4277616 # Number of squashed operands that are examined and possibly removed from graph 380system.cpu.iq.iqSquashedNonSpecRemoved 1448303 # Number of squashed non-spec instructions that were removed 381system.cpu.iq.issued_per_cycle::samples 82174946 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::mean 0.705388 # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::stdev 1.352124 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::0 56717955 69.02% 69.02% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::1 11192734 13.62% 82.64% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::2 5489796 6.68% 89.32% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::3 3501881 4.26% 93.58% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::4 2637968 3.21% 96.79% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::5 1562716 1.90% 98.70% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::6 689256 0.84% 99.53% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::7 274867 0.33% 99.87% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::8 107773 0.13% 100.00% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::total 82174946 # Number of insts issued each cycle 398system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntAlu 67060 8.71% 8.71% # attempts to use FU when none available 400system.cpu.iq.fu_full::IntMult 0 0.00% 8.71% # attempts to use FU when none available 401system.cpu.iq.fu_full::IntDiv 0 0.00% 8.71% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.71% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.71% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.71% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatMult 0 0.00% 8.71% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.71% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.71% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.71% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.71% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.71% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.71% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.71% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.71% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdMult 0 0.00% 8.71% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.71% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdShift 0 0.00% 8.71% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.71% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.71% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.71% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.71% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.71% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.71% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.71% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.71% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.71% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.71% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.71% # attempts to use FU when none available 428system.cpu.iq.fu_full::MemRead 379426 49.28% 57.99% # attempts to use FU when none available 429system.cpu.iq.fu_full::MemWrite 323507 42.01% 100.00% # attempts to use FU when none available 430system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 431system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 432system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued 433system.cpu.iq.FU_type_0::IntAlu 39583689 68.29% 68.30% # Type of FU issued 434system.cpu.iq.FU_type_0::IntMult 62189 0.11% 68.41% # Type of FU issued 435system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.45% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued 462system.cpu.iq.FU_type_0::MemRead 10615864 18.31% 86.77% # Type of FU issued 463system.cpu.iq.FU_type_0::MemWrite 6714571 11.58% 98.36% # Type of FU issued 464system.cpu.iq.FU_type_0::IprAccess 952373 1.64% 100.00% # Type of FU issued 465system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 466system.cpu.iq.FU_type_0::total 57965210 # Type of FU issued 467system.cpu.iq.rate 0.498440 # Inst issue rate 468system.cpu.iq.fu_busy_cnt 769993 # FU busy when requested 469system.cpu.iq.fu_busy_rate 0.013284 # FU busy rate (busy events/executed inst) 470system.cpu.iq.int_inst_queue_reads 198301844 # Number of integer instruction queue reads 471system.cpu.iq.int_inst_queue_writes 69800593 # Number of integer instruction queue writes 472system.cpu.iq.int_inst_queue_wakeup_accesses 56410393 # Number of integer instruction queue wakeup accesses 473system.cpu.iq.fp_inst_queue_reads 692084 # Number of floating instruction queue reads 474system.cpu.iq.fp_inst_queue_writes 332994 # Number of floating instruction queue writes 475system.cpu.iq.fp_inst_queue_wakeup_accesses 328299 # Number of floating instruction queue wakeup accesses 476system.cpu.iq.int_alu_accesses 58364794 # Number of integer alu accesses 477system.cpu.iq.fp_alu_accesses 363128 # Number of floating point alu accesses 478system.cpu.iew.lsq.thread0.forwLoads 575597 # Number of loads that had data forwarded from stores 479system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 480system.cpu.iew.lsq.thread0.squashedLoads 1608607 # Number of loads squashed 481system.cpu.iew.lsq.thread0.ignoredResponses 13533 # Number of memory responses ignored because the instruction is squashed 482system.cpu.iew.lsq.thread0.memOrderViolation 14401 # Number of memory ordering violations 483system.cpu.iew.lsq.thread0.squashedStores 599018 # Number of stores squashed 484system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 485system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 486system.cpu.iew.lsq.thread0.rescheduledLoads 18904 # Number of loads that were rescheduled 487system.cpu.iew.lsq.thread0.cacheBlocked 170936 # Number of times an access to memory failed due to the cache being blocked 488system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 489system.cpu.iew.iewSquashCycles 1498214 # Number of cycles IEW is squashing 490system.cpu.iew.iewBlockCycles 8974617 # Number of cycles IEW is blocking 491system.cpu.iew.iewUnblockCycles 617389 # Number of cycles IEW is unblocking 492system.cpu.iew.iewDispatchedInsts 65429620 # Number of instructions dispatched to IQ 493system.cpu.iew.iewDispSquashedInsts 865390 # Number of squashed instructions skipped by dispatch 494system.cpu.iew.iewDispLoadInsts 10722948 # Number of dispatched load instructions 495system.cpu.iew.iewDispStoreInsts 6992313 # Number of dispatched store instructions 496system.cpu.iew.iewDispNonSpecInsts 1869565 # Number of dispatched non-speculative instructions 497system.cpu.iew.iewIQFullEvents 485054 # Number of times the IQ has become full, causing a stall 498system.cpu.iew.iewLSQFullEvents 15735 # Number of times the LSQ has become full, causing a stall 499system.cpu.iew.memOrderViolationEvents 14401 # Number of memory order violations 500system.cpu.iew.predictedTakenIncorrect 385242 # Number of branches that were predicted taken incorrectly 501system.cpu.iew.predictedNotTakenIncorrect 382803 # Number of branches that were predicted not taken incorrectly 502system.cpu.iew.branchMispredicts 768045 # Number of branch mispredicts detected at execute 503system.cpu.iew.iewExecutedInsts 57270091 # Number of executed instructions 504system.cpu.iew.iewExecLoadInsts 10215279 # Number of load instructions executed 505system.cpu.iew.iewExecSquashedInsts 695118 # Number of squashed instructions skipped in execute 506system.cpu.iew.exec_swp 0 # number of swp insts executed 507system.cpu.iew.exec_nop 3624136 # number of nop insts executed 508system.cpu.iew.exec_refs 16869985 # number of memory reference insts executed 509system.cpu.iew.exec_branches 9097351 # Number of branches executed 510system.cpu.iew.exec_stores 6654706 # Number of stores executed 511system.cpu.iew.exec_rate 0.492462 # Inst execution rate 512system.cpu.iew.wb_sent 56872608 # cumulative count of insts sent to commit 513system.cpu.iew.wb_count 56738692 # cumulative count of insts written-back 514system.cpu.iew.wb_producers 28028831 # num instructions producing a value 515system.cpu.iew.wb_consumers 37767423 # num instructions consuming a value 516system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 517system.cpu.iew.wb_rate 0.487893 # insts written-back per cycle 518system.cpu.iew.wb_fanout 0.742143 # average fanout of values written-back 519system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 520system.cpu.commit.commitCommittedInsts 56292492 # The number of committed instructions 521system.cpu.commit.commitSquashedInsts 9013620 # The number of squashed insts skipped by commit 522system.cpu.commit.commitNonSpecStalls 667802 # The number of times commit has been forced to stall to communicate backwards 523system.cpu.commit.branchMispredicts 700532 # The number of times a branch was mispredicted 524system.cpu.commit.committed_per_cycle::samples 80676732 # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::mean 0.697754 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::stdev 1.611305 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::0 59494729 73.74% 73.74% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::1 8894659 11.03% 84.77% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::2 4715834 5.85% 90.62% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::3 2613071 3.24% 93.85% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::4 1534221 1.90% 95.76% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::5 644957 0.80% 96.56% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::6 475888 0.59% 97.14% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::7 517029 0.64% 97.79% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::8 1786344 2.21% 100.00% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::total 80676732 # Number of insts commited each cycle 541system.cpu.commit.count 56292492 # Number of instructions committed 542system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 543system.cpu.commit.refs 15507636 # Number of memory references committed 544system.cpu.commit.loads 9114341 # Number of loads committed 545system.cpu.commit.membars 227905 # Number of memory barriers committed 546system.cpu.commit.branches 8463183 # Number of branches committed 547system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 548system.cpu.commit.int_insts 52130666 # Number of committed integer instructions. 549system.cpu.commit.function_calls 744656 # Number of function calls committed. 550system.cpu.commit.bw_lim_events 1786344 # number cycles where commit BW limit reached 551system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 552system.cpu.rob.rob_reads 143945413 # The number of ROB reads 553system.cpu.rob.rob_writes 132113260 # The number of ROB writes 554system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself 555system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling 556system.cpu.quiesceCycles 3601447413 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 557system.cpu.committedInsts 53097697 # Number of Instructions Simulated 558system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated 559system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction 560system.cpu.cpi_total 2.190177 # CPI: Total CPI of All Threads 561system.cpu.ipc 0.456584 # IPC: Instructions Per Cycle 562system.cpu.ipc_total 0.456584 # IPC: Total IPC of All Threads 563system.cpu.int_regfile_reads 75078413 # number of integer regfile reads 564system.cpu.int_regfile_writes 40965985 # number of integer regfile writes 565system.cpu.fp_regfile_reads 166494 # number of floating regfile reads 566system.cpu.fp_regfile_writes 167403 # number of floating regfile writes 567system.cpu.misc_regfile_reads 1996876 # number of misc regfile reads 568system.cpu.misc_regfile_writes 949968 # number of misc regfile writes 569system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 570system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 571system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 572system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 573system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 574system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 575system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 576system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 577system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 578system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 579system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 580system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 581system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 582system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 583system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 584system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 585system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 586system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 587system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 588system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 589system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 590system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 591system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 592system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 593system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 594system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 595system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 596system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 597system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 598system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 599system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 600system.cpu.icache.replacements 1004954 # number of replacements 601system.cpu.icache.tagsinuse 509.962774 # Cycle average of tags in use 602system.cpu.icache.total_refs 7985922 # Total number of references to valid blocks. 603system.cpu.icache.sampled_refs 1005463 # Sample count of references to valid blocks. 604system.cpu.icache.avg_refs 7.942532 # Average number of references to valid blocks. 605system.cpu.icache.warmup_cycle 23358245000 # Cycle when the warmup percentage was hit. 606system.cpu.icache.occ_blocks::0 509.962774 # Average occupied blocks per context 607system.cpu.icache.occ_percent::0 0.996021 # Average percentage of cache occupancy 608system.cpu.icache.ReadReq_hits::0 7985923 # number of ReadReq hits 609system.cpu.icache.ReadReq_hits::total 7985923 # number of ReadReq hits 610system.cpu.icache.demand_hits::0 7985923 # number of demand (read+write) hits 611system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 612system.cpu.icache.demand_hits::total 7985923 # number of demand (read+write) hits 613system.cpu.icache.overall_hits::0 7985923 # number of overall hits 614system.cpu.icache.overall_hits::1 0 # number of overall hits 615system.cpu.icache.overall_hits::total 7985923 # number of overall hits 616system.cpu.icache.ReadReq_misses::0 1065945 # number of ReadReq misses 617system.cpu.icache.ReadReq_misses::total 1065945 # number of ReadReq misses 618system.cpu.icache.demand_misses::0 1065945 # number of demand (read+write) misses 619system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 620system.cpu.icache.demand_misses::total 1065945 # number of demand (read+write) misses 621system.cpu.icache.overall_misses::0 1065945 # number of overall misses 622system.cpu.icache.overall_misses::1 0 # number of overall misses 623system.cpu.icache.overall_misses::total 1065945 # number of overall misses 624system.cpu.icache.ReadReq_miss_latency 15930410995 # number of ReadReq miss cycles 625system.cpu.icache.demand_miss_latency 15930410995 # number of demand (read+write) miss cycles 626system.cpu.icache.overall_miss_latency 15930410995 # number of overall miss cycles 627system.cpu.icache.ReadReq_accesses::0 9051868 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.ReadReq_accesses::total 9051868 # number of ReadReq accesses(hits+misses) 629system.cpu.icache.demand_accesses::0 9051868 # number of demand (read+write) accesses 630system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 631system.cpu.icache.demand_accesses::total 9051868 # number of demand (read+write) accesses 632system.cpu.icache.overall_accesses::0 9051868 # number of overall (read+write) accesses 633system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 634system.cpu.icache.overall_accesses::total 9051868 # number of overall (read+write) accesses 635system.cpu.icache.ReadReq_miss_rate::0 0.117760 # miss rate for ReadReq accesses 636system.cpu.icache.demand_miss_rate::0 0.117760 # miss rate for demand accesses 637system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 638system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 639system.cpu.icache.overall_miss_rate::0 0.117760 # miss rate for overall accesses 640system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 641system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 642system.cpu.icache.ReadReq_avg_miss_latency::0 14944.871447 # average ReadReq miss latency 643system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 644system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 645system.cpu.icache.demand_avg_miss_latency::0 14944.871447 # average overall miss latency 646system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 647system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 648system.cpu.icache.overall_avg_miss_latency::0 14944.871447 # average overall miss latency 649system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 650system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 651system.cpu.icache.blocked_cycles::no_mshrs 1290996 # number of cycles access was blocked 652system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 653system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked 654system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.avg_blocked_cycles::no_mshrs 10581.934426 # average number of cycles each access was blocked 656system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 657system.cpu.icache.fast_writes 0 # number of fast writes performed 658system.cpu.icache.cache_copies 0 # number of cache copies performed 659system.cpu.icache.writebacks 235 # number of writebacks 660system.cpu.icache.ReadReq_mshr_hits 60269 # number of ReadReq MSHR hits 661system.cpu.icache.demand_mshr_hits 60269 # number of demand (read+write) MSHR hits 662system.cpu.icache.overall_mshr_hits 60269 # number of overall MSHR hits 663system.cpu.icache.ReadReq_mshr_misses 1005676 # number of ReadReq MSHR misses 664system.cpu.icache.demand_mshr_misses 1005676 # number of demand (read+write) MSHR misses 665system.cpu.icache.overall_mshr_misses 1005676 # number of overall MSHR misses 666system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 667system.cpu.icache.ReadReq_mshr_miss_latency 12050431496 # number of ReadReq MSHR miss cycles 668system.cpu.icache.demand_mshr_miss_latency 12050431496 # number of demand (read+write) MSHR miss cycles 669system.cpu.icache.overall_mshr_miss_latency 12050431496 # number of overall MSHR miss cycles 670system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 671system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111101 # mshr miss rate for ReadReq accesses 672system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 673system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 674system.cpu.icache.demand_mshr_miss_rate::0 0.111101 # mshr miss rate for demand accesses 675system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 676system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 677system.cpu.icache.overall_mshr_miss_rate::0 0.111101 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 679system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 680system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.419284 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency 682system.cpu.icache.overall_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 684system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 685system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 686system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 687system.cpu.dcache.replacements 1403374 # number of replacements 688system.cpu.dcache.tagsinuse 511.996006 # Cycle average of tags in use 689system.cpu.dcache.total_refs 12090411 # Total number of references to valid blocks. 690system.cpu.dcache.sampled_refs 1403886 # Sample count of references to valid blocks. 691system.cpu.dcache.avg_refs 8.612103 # Average number of references to valid blocks. 692system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. 693system.cpu.dcache.occ_blocks::0 511.996006 # Average occupied blocks per context 694system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy 695system.cpu.dcache.ReadReq_hits::0 7456106 # number of ReadReq hits 696system.cpu.dcache.ReadReq_hits::total 7456106 # number of ReadReq hits 697system.cpu.dcache.WriteReq_hits::0 4221921 # number of WriteReq hits 698system.cpu.dcache.WriteReq_hits::total 4221921 # number of WriteReq hits 699system.cpu.dcache.LoadLockedReq_hits::0 192075 # number of LoadLockedReq hits 700system.cpu.dcache.LoadLockedReq_hits::total 192075 # number of LoadLockedReq hits 701system.cpu.dcache.StoreCondReq_hits::0 220104 # number of StoreCondReq hits 702system.cpu.dcache.StoreCondReq_hits::total 220104 # number of StoreCondReq hits 703system.cpu.dcache.demand_hits::0 11678027 # number of demand (read+write) hits 704system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 705system.cpu.dcache.demand_hits::total 11678027 # number of demand (read+write) hits 706system.cpu.dcache.overall_hits::0 11678027 # number of overall hits 707system.cpu.dcache.overall_hits::1 0 # number of overall hits 708system.cpu.dcache.overall_hits::total 11678027 # number of overall hits 709system.cpu.dcache.ReadReq_misses::0 1809770 # number of ReadReq misses 710system.cpu.dcache.ReadReq_misses::total 1809770 # number of ReadReq misses 711system.cpu.dcache.WriteReq_misses::0 1936125 # number of WriteReq misses 712system.cpu.dcache.WriteReq_misses::total 1936125 # number of WriteReq misses 713system.cpu.dcache.LoadLockedReq_misses::0 22580 # number of LoadLockedReq misses 714system.cpu.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses 715system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses 716system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 717system.cpu.dcache.demand_misses::0 3745895 # number of demand (read+write) misses 718system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 719system.cpu.dcache.demand_misses::total 3745895 # number of demand (read+write) misses 720system.cpu.dcache.overall_misses::0 3745895 # number of overall misses 721system.cpu.dcache.overall_misses::1 0 # number of overall misses 722system.cpu.dcache.overall_misses::total 3745895 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency 38933932500 # number of ReadReq miss cycles 724system.cpu.dcache.WriteReq_miss_latency 57800126852 # number of WriteReq miss cycles 725system.cpu.dcache.LoadLockedReq_miss_latency 338100500 # number of LoadLockedReq miss cycles 726system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles 727system.cpu.dcache.demand_miss_latency 96734059352 # number of demand (read+write) miss cycles 728system.cpu.dcache.overall_miss_latency 96734059352 # number of overall miss cycles 729system.cpu.dcache.ReadReq_accesses::0 9265876 # number of ReadReq accesses(hits+misses) 730system.cpu.dcache.ReadReq_accesses::total 9265876 # number of ReadReq accesses(hits+misses) 731system.cpu.dcache.WriteReq_accesses::0 6158046 # number of WriteReq accesses(hits+misses) 732system.cpu.dcache.WriteReq_accesses::total 6158046 # number of WriteReq accesses(hits+misses) 733system.cpu.dcache.LoadLockedReq_accesses::0 214655 # number of LoadLockedReq accesses(hits+misses) 734system.cpu.dcache.LoadLockedReq_accesses::total 214655 # number of LoadLockedReq accesses(hits+misses) 735system.cpu.dcache.StoreCondReq_accesses::0 220106 # number of StoreCondReq accesses(hits+misses) 736system.cpu.dcache.StoreCondReq_accesses::total 220106 # number of StoreCondReq accesses(hits+misses) 737system.cpu.dcache.demand_accesses::0 15423922 # number of demand (read+write) accesses 738system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 739system.cpu.dcache.demand_accesses::total 15423922 # number of demand (read+write) accesses 740system.cpu.dcache.overall_accesses::0 15423922 # number of overall (read+write) accesses 741system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 742system.cpu.dcache.overall_accesses::total 15423922 # number of overall (read+write) accesses 743system.cpu.dcache.ReadReq_miss_rate::0 0.195316 # miss rate for ReadReq accesses 744system.cpu.dcache.WriteReq_miss_rate::0 0.314406 # miss rate for WriteReq accesses 745system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105192 # miss rate for LoadLockedReq accesses 746system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses 747system.cpu.dcache.demand_miss_rate::0 0.242863 # miss rate for demand accesses 748system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 749system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 750system.cpu.dcache.overall_miss_rate::0 0.242863 # miss rate for overall accesses 751system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 752system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 753system.cpu.dcache.ReadReq_avg_miss_latency::0 21513.193665 # average ReadReq miss latency 754system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 755system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 756system.cpu.dcache.WriteReq_avg_miss_latency::0 29853.509898 # average WriteReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 759system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14973.449956 # average LoadLockedReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 761system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 762system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency 763system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 764system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 765system.cpu.dcache.demand_avg_miss_latency::0 25824.017852 # average overall miss latency 766system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 767system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 768system.cpu.dcache.overall_avg_miss_latency::0 25824.017852 # average overall miss latency 769system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 770system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 771system.cpu.dcache.blocked_cycles::no_mshrs 917367309 # number of cycles access was blocked 772system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked 773system.cpu.dcache.blocked::no_mshrs 103073 # number of cycles access was blocked 774system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked 775system.cpu.dcache.avg_blocked_cycles::no_mshrs 8900.170840 # average number of cycles each access was blocked 776system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked 777system.cpu.dcache.fast_writes 0 # number of fast writes performed 778system.cpu.dcache.cache_copies 0 # number of cache copies performed 779system.cpu.dcache.writebacks 834855 # number of writebacks 780system.cpu.dcache.ReadReq_mshr_hits 722036 # number of ReadReq MSHR hits 781system.cpu.dcache.WriteReq_mshr_hits 1637277 # number of WriteReq MSHR hits 782system.cpu.dcache.LoadLockedReq_mshr_hits 5104 # number of LoadLockedReq MSHR hits 783system.cpu.dcache.demand_mshr_hits 2359313 # number of demand (read+write) MSHR hits 784system.cpu.dcache.overall_mshr_hits 2359313 # number of overall MSHR hits 785system.cpu.dcache.ReadReq_mshr_misses 1087734 # number of ReadReq MSHR misses 786system.cpu.dcache.WriteReq_mshr_misses 298848 # number of WriteReq MSHR misses 787system.cpu.dcache.LoadLockedReq_mshr_misses 17476 # number of LoadLockedReq MSHR misses 788system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses 789system.cpu.dcache.demand_mshr_misses 1386582 # number of demand (read+write) MSHR misses 790system.cpu.dcache.overall_mshr_misses 1386582 # number of overall MSHR misses 791system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 792system.cpu.dcache.ReadReq_mshr_miss_latency 24802725500 # number of ReadReq MSHR miss cycles 793system.cpu.dcache.WriteReq_mshr_miss_latency 8508331309 # number of WriteReq MSHR miss cycles 794system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206132500 # number of LoadLockedReq MSHR miss cycles 795system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles 796system.cpu.dcache.demand_mshr_miss_latency 33311056809 # number of demand (read+write) MSHR miss cycles 797system.cpu.dcache.overall_mshr_miss_latency 33311056809 # number of overall MSHR miss cycles 798system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905005000 # number of ReadReq MSHR uncacheable cycles 799system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234795498 # number of WriteReq MSHR uncacheable cycles 800system.cpu.dcache.overall_mshr_uncacheable_latency 2139800498 # number of overall MSHR uncacheable cycles 801system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117391 # mshr miss rate for ReadReq accesses 802system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 803system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 804system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048530 # mshr miss rate for WriteReq accesses 805system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 806system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 807system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081414 # mshr miss rate for LoadLockedReq accesses 808system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 809system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 810system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses 811system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 812system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 813system.cpu.dcache.demand_mshr_miss_rate::0 0.089898 # mshr miss rate for demand accesses 814system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 815system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 816system.cpu.dcache.overall_mshr_miss_rate::0 0.089898 # mshr miss rate for overall accesses 817system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 818system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 819system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22802.197504 # average ReadReq mshr miss latency 820system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28470.430818 # average WriteReq mshr miss latency 821system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11795.176242 # average LoadLockedReq mshr miss latency 822system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency 825system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 826system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 827system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 828system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 829system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 830system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 831system.cpu.kern.inst.arm 0 # number of arm instructions executed 832system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed 833system.cpu.kern.inst.hwrei 211595 # number of hwrei instructions executed 834system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl 835system.cpu.kern.ipl_count::21 245 0.13% 41.09% # number of times we switched to this ipl 836system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl 837system.cpu.kern.ipl_count::31 105819 57.88% 100.00% # number of times we switched to this ipl 838system.cpu.kern.ipl_count::total 182823 # number of times we switched to this ipl 839system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl 840system.cpu.kern.ipl_good::21 245 0.16% 49.45% # number of times we switched to this ipl from a different ipl 841system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl 842system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl 843system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl 844system.cpu.kern.ipl_ticks::0 1820223133000 97.92% 97.92% # number of cycles we spent at this ipl 845system.cpu.kern.ipl_ticks::21 94250000 0.01% 97.93% # number of cycles we spent at this ipl 846system.cpu.kern.ipl_ticks::22 384615500 0.02% 97.95% # number of cycles we spent at this ipl 847system.cpu.kern.ipl_ticks::31 38170735500 2.05% 100.00% # number of cycles we spent at this ipl 848system.cpu.kern.ipl_ticks::total 1858872734000 # number of cycles we spent at this ipl 849system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl 850system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 851system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 852system.cpu.kern.ipl_used::31 0.694715 # fraction of swpipl calls that actually changed the ipl 853system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 854system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 855system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 856system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 857system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 858system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 859system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 860system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 861system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 862system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 863system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 864system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 865system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 866system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 867system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 868system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 869system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 870system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 871system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 872system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 873system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 874system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 875system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 876system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 877system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 878system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 879system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 880system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 881system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 882system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 883system.cpu.kern.syscall::total 326 # number of syscalls executed 884system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 885system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 886system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 887system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 888system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 889system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 890system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 891system.cpu.kern.callpal::swpipl 175482 91.19% 93.39% # number of callpals executed 892system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed 893system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 894system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 895system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 896system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 897system.cpu.kern.callpal::rti 5217 2.71% 99.64% # number of callpals executed 898system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 899system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 900system.cpu.kern.callpal::total 192442 # number of callpals executed 901system.cpu.kern.mode_switch::kernel 5953 # number of protection mode switches 902system.cpu.kern.mode_switch::user 1737 # number of protection mode switches 903system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches 904system.cpu.kern.mode_good::kernel 1907 905system.cpu.kern.mode_good::user 1737 906system.cpu.kern.mode_good::idle 170 907system.cpu.kern.mode_switch_good::kernel 0.320343 # fraction of useful protection mode switches 908system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 909system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches 910system.cpu.kern.mode_switch_good::total 1.401064 # fraction of useful protection mode switches 911system.cpu.kern.mode_ticks::kernel 29154617000 1.57% 1.57% # number of ticks spent at the given mode 912system.cpu.kern.mode_ticks::user 2680769000 0.14% 1.71% # number of ticks spent at the given mode 913system.cpu.kern.mode_ticks::idle 1827037340000 98.29% 100.00% # number of ticks spent at the given mode 914system.cpu.kern.swap_context 4177 # number of times the context was actually changed 915 916---------- End Simulation Statistics ---------- 917