xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.854316                       # Number of seconds simulated
sim_ticks                                1854315933000                       # Number of ticks simulated
final_tick                               1854315933000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  49330                       # Simulator instruction rate (inst/s)
host_op_rate                                    49330                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1727408560                       # Simulator tick rate (ticks/s)
host_mem_usage                                 351576                       # Number of bytes of host memory used
host_seconds                                  1073.47                       # Real time elapsed on the host
sim_insts                                    52953842                       # Number of instructions simulated
sim_ops                                      52953842                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            964736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24879104                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28496192                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       964736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7502848                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7502848                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15074                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388736                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445253                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117232                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117232                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               520265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13416864                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1430367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15367496                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          520265                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             520265                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4046154                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4046154                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4046154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              520265                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13416864                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1430367                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19413650                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445253                       # Total number of read requests seen
system.physmem.writeReqs                       117232                       # Total number of write requests seen
system.physmem.cpureqs                         562681                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28496192                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7502848                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28496192                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7502848                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       65                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                180                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28014                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 27757                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 27571                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 27335                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 27900                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 27985                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 27992                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27793                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28084                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27816                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                27970                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27741                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27761                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                27965                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27782                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27722                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7549                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7292                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7139                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  6981                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7370                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7386                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7449                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7331                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7642                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7358                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7506                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7213                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7258                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7375                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7186                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7197                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                          16                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1854310455000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  445253                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 117232                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    323581                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64321                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     19541                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7565                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2703                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2648                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1542                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1361                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1385                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      921                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      765                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5076                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5079                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      376                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       18                       # What write queue length does an incoming req see
system.physmem.totQLat                     7494847250                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               15211767250                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2225940000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5490980000                       # Total cycles spent in bank access
system.physmem.avgQLat                       16835.24                       # Average queueing delay per request
system.physmem.avgBankLat                    12334.07                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  34169.31                       # Average memory access latency
system.physmem.avgRdBW                          15.37                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.05                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.37                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.05                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        12.10                       # Average write queue length over time
system.physmem.readRowHits                     417708                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     91270                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.85                       # Row buffer hit rate for writes
system.physmem.avgGap                      3296639.83                       # Average gap between requests
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.265086                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1704475467000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.265086                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.079068                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.079068                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20927998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20927998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10643328423                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10643328423                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10664256421                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10664256421                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10664256421                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10664256421                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256144.792621                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256144.792621                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255584.336034                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255584.336034                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255584.336034                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255584.336034                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        284060                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27214                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.438010                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11931249                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11931249                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8481334185                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8481334185                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8493265434                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8493265434                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8493265434                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8493265434                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204113.741456                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204113.741456                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203553.395662                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203553.395662                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203553.395662                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203553.395662                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13854129                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11621858                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            400402                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9160821                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5815827                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             63.485871                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  906747                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              38946                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9920210                       # DTB read hits
system.cpu.dtb.read_misses                      41076                       # DTB read misses
system.cpu.dtb.read_acv                           544                       # DTB read access violations
system.cpu.dtb.read_accesses                   941527                       # DTB read accesses
system.cpu.dtb.write_hits                     6593814                       # DTB write hits
system.cpu.dtb.write_misses                     10775                       # DTB write misses
system.cpu.dtb.write_acv                          404                       # DTB write access violations
system.cpu.dtb.write_accesses                  338229                       # DTB write accesses
system.cpu.dtb.data_hits                     16514024                       # DTB hits
system.cpu.dtb.data_misses                      51851                       # DTB misses
system.cpu.dtb.data_acv                           948                       # DTB access violations
system.cpu.dtb.data_accesses                  1279756                       # DTB accesses
system.cpu.itb.fetch_hits                     1305070                       # ITB hits
system.cpu.itb.fetch_misses                     36981                       # ITB misses
system.cpu.itb.fetch_acv                         1089                       # ITB acv
system.cpu.itb.fetch_accesses                 1342051                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        108723981                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28071835                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70691782                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13854129                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6722574                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13248795                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1991444                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               37396273                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32851                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        253900                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       295773                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          814                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8551942                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                266251                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           80590196                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.877176                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.220882                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 67341401     83.56%     83.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   854251      1.06%     84.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1698632      2.11%     86.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   828031      1.03%     87.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2750245      3.41%     91.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   562298      0.70%     91.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   643304      0.80%     92.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1012392      1.26%     93.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4899642      6.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             80590196                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.127425                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.650195                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29205934                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37061149                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12112258                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                963051                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1247803                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               585584                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42566                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69386312                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                128816                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1247803                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30327018                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                13624252                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       19779589                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11347768                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4263764                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65637148                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  6817                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 509709                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1485643                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43822331                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79670452                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79191261                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            479191                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38158982                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5663341                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1681975                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         239504                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12131366                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10436836                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6902083                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1326454                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           859310                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58185317                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2050283                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56802944                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            107134                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6922426                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3549333                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1389358                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      80590196                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.704837                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.365985                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            55946315     69.42%     69.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10805415     13.41%     82.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5162410      6.41%     89.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3384715      4.20%     93.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2645600      3.28%     96.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1461420      1.81%     98.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              757318      0.94%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              330868      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               96135      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        80590196                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   91816     11.60%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 373288     47.16%     58.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                326368     41.24%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38732288     68.19%     68.20% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61693      0.11%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10350848     18.22%     86.58% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6672590     11.75%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             948996      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56802944                       # Type of FU issued
system.cpu.iq.rate                           0.522451                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      791472                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013934                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          194402098                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66835363                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55566146                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              692591                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             336490                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327919                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57225685                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  361445                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           601434                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1348949                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         4999                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14153                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       526604                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17963                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        174400                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1247803                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 9948703                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                684680                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63760053                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            677795                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10436836                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6902083                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1805728                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 512612                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 18477                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14153                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         203761                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       412011                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               615772                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56335729                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts               9989502                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            467214                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3524453                       # number of nop insts executed
system.cpu.iew.exec_refs                     16609334                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8926219                       # Number of branches executed
system.cpu.iew.exec_stores                    6619832                       # Number of stores executed
system.cpu.iew.exec_rate                     0.518154                       # Inst execution rate
system.cpu.iew.wb_sent                       56008573                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55894065                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27763400                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37619407                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.514091                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.738007                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7499464                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660925                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            569249                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     79342393                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.707610                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.636795                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     58576225     73.83%     73.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8604152     10.84%     84.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4604262      5.80%     90.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2532350      3.19%     93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1516866      1.91%     95.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       607587      0.77%     96.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       525202      0.66%     97.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       528895      0.67%     97.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1846854      2.33%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     79342393                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56143434                       # Number of instructions committed
system.cpu.commit.committedOps               56143434                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15463366                       # Number of memory references committed
system.cpu.commit.loads                       9087887                       # Number of loads committed
system.cpu.commit.membars                      226338                       # Number of memory barriers committed
system.cpu.commit.branches                    8437404                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  51994306                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740223                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1846854                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    140888897                       # The number of ROB reads
system.cpu.rob.rob_writes                   128535372                       # The number of ROB writes
system.cpu.timesIdled                         1178030                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        28133785                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3599901445                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52953842                       # Number of Instructions Simulated
system.cpu.committedOps                      52953842                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52953842                       # Number of Instructions Simulated
system.cpu.cpi                               2.053184                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.053184                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.487048                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.487048                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73863718                       # number of integer regfile reads
system.cpu.int_regfile_writes                40309148                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166055                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167445                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1987577                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938916                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                1008056                       # number of replacements
system.cpu.icache.tagsinuse                510.288662                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7486559                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1008564                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.422989                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            20267924000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.288662                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996658                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996658                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7486560                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7486560                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7486560                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7486560                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7486560                       # number of overall hits
system.cpu.icache.overall_hits::total         7486560                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1065380                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1065380                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1065380                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1065380                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1065380                       # number of overall misses
system.cpu.icache.overall_misses::total       1065380                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14692786493                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14692786493                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14692786493                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14692786493                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14692786493                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14692786493                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8551940                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8551940                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8551940                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8551940                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8551940                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8551940                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124578                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124578                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124578                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124578                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124578                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124578                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13791.122879                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13791.122879                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13791.122879                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13791.122879                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13791.122879                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13791.122879                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4755                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets         1956                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               145                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    32.793103                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          489                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56595                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        56595                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        56595                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        56595                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        56595                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        56595                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1008785                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1008785                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1008785                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1008785                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1008785                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1008785                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12038039995                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12038039995                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12038039995                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12038039995                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12038039995                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12038039995                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.117960                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.117960                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.117960                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.117960                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.117960                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.117960                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11933.206773                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11933.206773                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11933.206773                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11933.206773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11933.206773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11933.206773                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                338326                       # number of replacements
system.cpu.l2cache.tagsinuse             65364.753625                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 2543033                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                403496                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.302499                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle            4078120751                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 54051.179621                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   5324.310561                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   5989.263443                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.824756                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.081243                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.091389                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997387                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       993589                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       826269                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1819858                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840029                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840029                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           27                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           27                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185368                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185368                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       993589                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1011637                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2005226                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       993589                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1011637                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2005226                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15076                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273797                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288873                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           40                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           40                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115432                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115432                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15076                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389229                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404305                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15076                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389229                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404305                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1050370500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11953523500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  13003894000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       302500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       302500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7672961500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7672961500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1050370500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  19626485000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  20676855500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1050370500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  19626485000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  20676855500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1008665                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100066                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2108731                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840029                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840029                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           67                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           67                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       300800                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       300800                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1008665                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1400866                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2409531                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1008665                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1400866                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2409531                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014946                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248891                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136989                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.597015                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.597015                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383750                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383750                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014946                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277849                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167794                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014946                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277849                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167794                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69671.696737                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43658.343590                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 45015.955108                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7562.500000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7562.500000                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66471.701954                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66471.701954                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69671.696737                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50424.004892                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51141.725925                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69671.696737                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50424.004892                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51141.725925                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75720                       # number of writebacks
system.cpu.l2cache.writebacks::total            75720                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15075                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273797                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288872                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           40                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           40                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115432                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115432                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15075                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389229                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404304                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15075                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389229                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404304                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    862398247                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8602310526                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9464708773                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       569536                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       569536                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6262852352                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6262852352                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    862398247                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14865162878                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  15727561125                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    862398247                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14865162878                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  15727561125                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333774000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333774000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882495000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882495000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216269000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216269000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014945                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248891                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136989                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.597015                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.597015                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383750                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383750                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014945                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277849                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167794                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014945                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277849                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167794                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57207.180564                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.571153                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32764.368900                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14238.400000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14238.400000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54255.772680                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54255.772680                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57207.180564                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38191.303521                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.335206                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57207.180564                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38191.303521                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.335206                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1400274                       # number of replacements
system.cpu.dcache.tagsinuse                511.995157                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 11811900                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1400786                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   8.432337                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21808000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.995157                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7207099                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7207099                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4203008                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4203008                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186038                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186038                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215505                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215505                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11410107                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11410107                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11410107                       # number of overall hits
system.cpu.dcache.overall_hits::total        11410107                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1800868                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1800868                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1942264                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1942264                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22743                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22743                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3743132                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3743132                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3743132                       # number of overall misses
system.cpu.dcache.overall_misses::total       3743132                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33858803000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33858803000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  65085084522                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  65085084522                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    304812500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    304812500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        37500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        37500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  98943887522                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  98943887522                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  98943887522                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  98943887522                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9007967                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9007967                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6145272                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6145272                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208781                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       208781                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215507                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215507                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15153239                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15153239                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15153239                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15153239                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199919                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.199919                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316058                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316058                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108932                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108932                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247019                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247019                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247019                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247019                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18801.379668                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18801.379668                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33509.906234                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33509.906234                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13402.475487                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13402.475487                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        18750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        18750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26433.448653                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26433.448653                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26433.448653                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26433.448653                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      2202746                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          567                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             95919                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.964647                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           81                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840029                       # number of writebacks
system.cpu.dcache.writebacks::total            840029                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       717621                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       717621                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1642056                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1642056                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5266                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5266                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2359677                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2359677                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2359677                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2359677                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083247                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1083247                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300208                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300208                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17477                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17477                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1383455                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1383455                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1383455                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1383455                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21329073000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  21329073000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9889442761                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9889442761                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    199091500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    199091500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        33500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        33500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31218515761                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  31218515761                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31218515761                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31218515761                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423851000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423851000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997662998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997662998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421513998                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421513998                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120254                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120254                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048852                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048852                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083710                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083710                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091298                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091298                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091298                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091298                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19689.944214                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19689.944214                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32941.969438                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32941.969438                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11391.628998                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11391.628998                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        16750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        16750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22565.617068                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22565.617068                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22565.617068                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22565.617068                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6441                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     210999                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74661     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105559     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182230                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73294     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1818345164500     98.06%     98.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                63914000      0.00%     98.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               557987500      0.03%     98.09% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             35348021500      1.91%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1854315087500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694342                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815442                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175115     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191959                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5849                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326552                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29469027500      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2713167500      0.15%      1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1822132884500     98.26%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------