xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.854310                       # Number of seconds simulated
sim_ticks                                1854310449000                       # Number of ticks simulated
final_tick                               1854310449000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  95500                       # Simulator instruction rate (inst/s)
host_op_rate                                    95500                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3343297346                       # Simulator tick rate (ticks/s)
host_mem_usage                                 333588                       # Number of bytes of host memory used
host_seconds                                   554.64                       # Real time elapsed on the host
sim_insts                                    52967561                       # Number of instructions simulated
sim_ops                                      52967561                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            964416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24875392                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28492160                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       964416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964416                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7502272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7502272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15069                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388678                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445190                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117223                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117223                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               520094                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13414901                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1430371                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15365367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          520094                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             520094                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4045855                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4045855                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4045855                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              520094                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13414901                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1430371                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19411222                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445190                       # Total number of read requests seen
system.physmem.writeReqs                       117223                       # Total number of write requests seen
system.physmem.cpureqs                         562598                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28492160                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7502272                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28492160                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7502272                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       59                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                174                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28015                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 27749                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 27564                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 27303                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 27868                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 27959                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 27979                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27788                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28082                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27814                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                27969                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27768                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27789                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                27980                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27796                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27708                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7542                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7286                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7135                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  6966                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7347                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7367                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7431                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7327                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7648                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7363                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7509                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7240                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7287                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7384                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7205                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7186                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                          11                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1854305000000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  445190                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 117223                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    323496                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64344                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     19569                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7556                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3202                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2964                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2691                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2660                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2613                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1522                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1467                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1417                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1353                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1391                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1613                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1504                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      920                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5070                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5081                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5084                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       13                       # What write queue length does an incoming req see
system.physmem.totQLat                     7465727500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               15177783750                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2225655000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5486401250                       # Total cycles spent in bank access
system.physmem.avgQLat                       16771.98                       # Average queueing delay per request
system.physmem.avgBankLat                    12325.36                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  34097.34                       # Average memory access latency
system.physmem.avgRdBW                          15.37                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.05                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.37                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.05                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        14.50                       # Average write queue length over time
system.physmem.readRowHits                     417731                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     91366                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.84                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.94                       # Row buffer hit rate for writes
system.physmem.avgGap                      3297052.17                       # Average gap between requests
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.265060                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1704474218000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.265060                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.079066                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.079066                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20927998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20927998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10634243420                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10634243420                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10655171418                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10655171418                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10655171418                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10655171418                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.150847                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 255926.150847                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 255366.600791                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 255366.600791                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 255366.600791                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 255366.600791                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        283342                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27068                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.467785                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11931249                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11931249                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8472243194                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8472243194                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8484174443                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8484174443                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8484174443                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8484174443                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203894.955574                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 203894.955574                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.516908                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 203335.516908                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.516908                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 203335.516908                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13849744                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11622401                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            399564                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9420297                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5813323                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             61.710613                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  901783                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              38632                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9912266                       # DTB read hits
system.cpu.dtb.read_misses                      41544                       # DTB read misses
system.cpu.dtb.read_acv                           542                       # DTB read access violations
system.cpu.dtb.read_accesses                   940163                       # DTB read accesses
system.cpu.dtb.write_hits                     6601788                       # DTB write hits
system.cpu.dtb.write_misses                     10570                       # DTB write misses
system.cpu.dtb.write_acv                          410                       # DTB write access violations
system.cpu.dtb.write_accesses                  337668                       # DTB write accesses
system.cpu.dtb.data_hits                     16514054                       # DTB hits
system.cpu.dtb.data_misses                      52114                       # DTB misses
system.cpu.dtb.data_acv                           952                       # DTB access violations
system.cpu.dtb.data_accesses                  1277831                       # DTB accesses
system.cpu.itb.fetch_hits                     1306011                       # ITB hits
system.cpu.itb.fetch_misses                     36868                       # ITB misses
system.cpu.itb.fetch_acv                         1103                       # ITB acv
system.cpu.itb.fetch_accesses                 1342879                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        108629038                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28026689                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70680176                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13849744                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6715106                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13246427                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1984359                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               37388108                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32353                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        254081                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       294447                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          699                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8549154                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                266665                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           80527554                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.877714                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.221537                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 67281127     83.55%     83.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   855303      1.06%     84.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1700571      2.11%     86.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   822573      1.02%     87.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2750497      3.42%     91.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   561265      0.70%     91.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   645561      0.80%     92.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1010923      1.26%     93.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4899734      6.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             80527554                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.127496                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.650656                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29153725                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37057832                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12110647                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                962931                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1242418                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               586230                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42729                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69379302                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129899                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1242418                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30276016                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                13626490                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       19778343                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11345486                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4258799                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65628358                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  6970                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 508418                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1479478                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43831634                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79654682                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79176161                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            478521                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38170118                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5661508                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1682525                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         240085                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12113982                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10427074                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6890989                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1312659                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           851378                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58169067                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2051551                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56810875                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             88738                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6892578                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3503311                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1390624                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      80527554                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.705484                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.366898                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            55885936     69.40%     69.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10804988     13.42%     82.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5163321      6.41%     89.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3374568      4.19%     93.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2652291      3.29%     96.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1461239      1.81%     98.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              754842      0.94%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              331822      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               98547      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        80527554                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   91181     11.49%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 373750     47.11%     58.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                328508     41.40%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38738406     68.19%     68.20% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61707      0.11%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10344574     18.21%     86.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6680654     11.76%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949005      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56810875                       # Type of FU issued
system.cpu.iq.rate                           0.522981                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      793439                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013966                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          194338715                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66791274                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55577661                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              692765                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             335658                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327829                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57234972                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  362056                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           601138                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1337046                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         4207                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14068                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       514312                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17961                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        173725                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1242418                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 9954083                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                684701                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63749782                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            676077                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10427074                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6890989                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1807007                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 512952                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 18311                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14068                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         203273                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       412234                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               615507                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56340822                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts               9981988                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            470052                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3529164                       # number of nop insts executed
system.cpu.iew.exec_refs                     16609586                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8925674                       # Number of branches executed
system.cpu.iew.exec_stores                    6627598                       # Number of stores executed
system.cpu.iew.exec_rate                     0.518653                       # Inst execution rate
system.cpu.iew.wb_sent                       56019458                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55905490                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27772636                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37602554                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.514646                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.738584                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7474791                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660927                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            568232                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     79285136                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.708301                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.637990                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     58523209     73.81%     73.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8600768     10.85%     84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4599944      5.80%     90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2533685      3.20%     93.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1517149      1.91%     95.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       606925      0.77%     96.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       524667      0.66%     97.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       525488      0.66%     97.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1853301      2.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     79285136                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56157758                       # Number of instructions committed
system.cpu.commit.committedOps               56157758                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15466705                       # Number of memory references committed
system.cpu.commit.loads                       9090028                       # Number of loads committed
system.cpu.commit.membars                      226335                       # Number of memory barriers committed
system.cpu.commit.branches                    8438960                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52008025                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740393                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1853301                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    140814788                       # The number of ROB reads
system.cpu.rob.rob_writes                   128509305                       # The number of ROB writes
system.cpu.timesIdled                         1177982                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        28101484                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3599985419                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52967561                       # Number of Instructions Simulated
system.cpu.committedOps                      52967561                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52967561                       # Number of Instructions Simulated
system.cpu.cpi                               2.050860                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.050860                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.487600                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.487600                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73882509                       # number of integer regfile reads
system.cpu.int_regfile_writes                40314112                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    165977                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167436                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1987247                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938923                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                1008504                       # number of replacements
system.cpu.icache.tagsinuse                510.288693                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7484267                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1009012                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.417421                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            20267575000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.288693                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996658                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996658                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7484268                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7484268                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7484268                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7484268                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7484268                       # number of overall hits
system.cpu.icache.overall_hits::total         7484268                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1064885                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1064885                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1064885                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1064885                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1064885                       # number of overall misses
system.cpu.icache.overall_misses::total       1064885                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14670837493                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14670837493                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14670837493                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14670837493                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14670837493                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14670837493                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8549153                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8549153                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8549153                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8549153                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8549153                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8549153                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124560                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124560                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124560                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124560                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124560                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124560                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.921915                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13776.921915                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.921915                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13776.921915                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.921915                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13776.921915                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         5769                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets         1606                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               170                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    33.935294                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          803                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        55656                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        55656                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        55656                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        55656                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        55656                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        55656                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1009229                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1009229                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1009229                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1009229                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1009229                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1009229                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12029446495                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12029446495                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12029446495                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12029446495                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12029446495                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12029446495                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118050                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118050                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118050                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.118050                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118050                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.118050                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11919.441965                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11919.441965                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11919.441965                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11919.441965                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11919.441965                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11919.441965                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                338273                       # number of replacements
system.cpu.l2cache.tagsinuse             65365.869534                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 2544201                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                403437                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.306315                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle            4078120751                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 53972.455267                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   5323.078272                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6070.335995                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.823554                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.081224                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.092626                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997404                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       994045                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       826710                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1820755                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840363                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840363                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           24                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           24                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185332                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185332                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       994045                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1012042                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2006087                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       994045                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1012042                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2006087                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15071                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273774                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288845                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           37                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           37                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115394                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115394                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15071                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389168                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404239                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15071                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389168                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404239                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1036442500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11953176500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  12989619000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       267000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       267000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7638606500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7638606500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1036442500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  19591783000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  20628225500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1036442500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  19591783000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  20628225500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1009116                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100484                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2109600                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840363                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840363                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           61                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           61                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            4                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       300726                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       300726                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1009116                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1401210                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2410326                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1009116                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1401210                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2410326                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014935                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248776                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136919                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.606557                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.606557                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383718                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383718                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014935                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277737                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167711                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014935                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277737                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167711                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.652246                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43660.743898                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 44970.897886                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7216.216216                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7216.216216                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66195.872402                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66195.872402                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68770.652246                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50342.738869                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51029.775702                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68770.652246                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50342.738869                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51029.775702                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75711                       # number of writebacks
system.cpu.l2cache.writebacks::total            75711                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15070                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273774                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288844                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           37                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           37                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115394                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115394                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15070                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389168                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404238                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15070                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389168                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404238                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    848510264                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8602226741                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9450737005                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       527532                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       527532                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6229012981                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6229012981                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    848510264                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14831239722                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  15679749986                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    848510264                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14831239722                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  15679749986                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333826500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333826500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882595500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882595500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216422000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216422000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014934                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248776                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136919                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.606557                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.606557                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383718                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383718                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014934                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277737                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167711                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014934                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277737                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167711                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.596151                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.904618                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.173689                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14257.621622                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14257.621622                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53980.388764                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53980.388764                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56304.596151                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38110.121392                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38788.411743                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56304.596151                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38110.121392                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38788.411743                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1400618                       # number of replacements
system.cpu.dcache.tagsinuse                511.995158                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 11803573                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1401130                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   8.424324                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21807000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.995158                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7198104                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7198104                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4203343                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4203343                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186395                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186395                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215505                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215505                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11401447                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11401447                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11401447                       # number of overall hits
system.cpu.dcache.overall_hits::total        11401447                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1802656                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1802656                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1943125                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1943125                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22671                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22671                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3745781                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3745781                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3745781                       # number of overall misses
system.cpu.dcache.overall_misses::total       3745781                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33855022500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33855022500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  64910918483                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  64910918483                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    306639500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    306639500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        64000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        64000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  98765940983                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  98765940983                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  98765940983                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  98765940983                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9000760                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9000760                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6146468                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6146468                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209066                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       209066                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215509                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215509                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15147228                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15147228                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15147228                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15147228                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200278                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.200278                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316137                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316137                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108439                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108439                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000019                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000019                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247292                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247292                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247292                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247292                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18780.633965                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18780.633965                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33405.426045                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33405.426045                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13525.627454                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13525.627454                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        16000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        16000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26367.249175                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26367.249175                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26367.249175                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26367.249175                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      2192171                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          774                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             95789                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               6                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.885415                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          129                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840363                       # number of writebacks
system.cpu.dcache.writebacks::total            840363                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       719064                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       719064                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1642999                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1642999                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5119                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5119                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2362063                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2362063                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2362063                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2362063                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083592                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1083592                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300126                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300126                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17552                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17552                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1383718                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1383718                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1383718                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1383718                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21332679000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  21332679000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9855100772                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9855100772                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200264000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200264000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        56000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        56000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31187779772                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  31187779772                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31187779772                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31187779772                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423903500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423903500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997763498                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997763498                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421666998                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421666998                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120389                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120389                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048829                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048829                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083954                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083954                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091351                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091351                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091351                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091351                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19687.003042                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19687.003042                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32836.544558                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32836.544558                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11409.753874                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11409.753874                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        14000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        14000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22539.115464                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22539.115464                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22539.115464                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22539.115464                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6442                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211000                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74661     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105560     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182231                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73294     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1818337876500     98.06%     98.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                63843000      0.00%     98.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               549015500      0.03%     98.09% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             35358867000      1.91%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1854309602000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694335                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815438                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175116     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191960                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5849                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1911                      
system.cpu.kern.mode_good::user                  1741                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326723                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394549                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29457658500      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2706866000      0.15%      1.73% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1822145069500     98.27%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------