stats.txt revision 9568
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39568Sandreas.hansson@arm.comsim_seconds 1.854307 # Number of seconds simulated 49568Sandreas.hansson@arm.comsim_ticks 1854307399500 # Number of ticks simulated 59568Sandreas.hansson@arm.comfinal_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79568Sandreas.hansson@arm.comhost_inst_rate 106006 # Simulator instruction rate (inst/s) 89568Sandreas.hansson@arm.comhost_op_rate 106006 # Simulator op (including micro ops) rate (op/s) 99568Sandreas.hansson@arm.comhost_tick_rate 3711029376 # Simulator tick rate (ticks/s) 109568Sandreas.hansson@arm.comhost_mem_usage 333480 # Number of bytes of host memory used 119568Sandreas.hansson@arm.comhost_seconds 499.67 # Real time elapsed on the host 129568Sandreas.hansson@arm.comsim_insts 52968721 # Number of instructions simulated 139568Sandreas.hansson@arm.comsim_ops 52968721 # Number of ops (including micro ops) simulated 149568Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory 159568Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory 169568Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 179568Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28491392 # Number of bytes read from this memory 189568Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory 199568Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory 209568Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory 219568Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7501184 # Number of bytes written to this memory 229568Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory 239568Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory 249568Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 259568Sandreas.hansson@arm.comsystem.physmem.num_reads::total 445178 # Number of read requests responded to by this memory 269568Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory 279568Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117206 # Number of write requests responded to by this memory 289568Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s) 299568Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s) 309568Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s) 319568Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s) 329568Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s) 339568Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s) 349568Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s) 359568Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s) 369568Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s) 379568Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s) 389568Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s) 399568Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s) 409568Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s) 419568Sandreas.hansson@arm.comsystem.physmem.readReqs 445178 # Total number of read requests seen 429568Sandreas.hansson@arm.comsystem.physmem.writeReqs 117206 # Total number of write requests seen 439568Sandreas.hansson@arm.comsystem.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady 449568Sandreas.hansson@arm.comsystem.physmem.bytesRead 28491392 # Total number of bytes read from memory 459568Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7501184 # Total number of bytes written to memory 469568Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize() 479568Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize() 489568Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q 499568Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 176 # Reqs where no action is needed 509568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis 519568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis 529568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis 539568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis 549568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis 559568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis 569568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis 579568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis 589568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis 599568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis 609568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis 619568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis 629568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis 639568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis 649568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis 659568Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis 669568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis 679568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis 689568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis 699568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis 709568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis 719568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis 729568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis 739568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis 749568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis 759568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis 769568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis 779568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis 789568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis 799568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis 809568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis 819568Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 839568Sandreas.hansson@arm.comsystem.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry 849568Sandreas.hansson@arm.comsystem.physmem.totGap 1854301986000 # Total gap between requests 859312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 919568Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 445178 # Categorize read packet sizes 929568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 939568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 949568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 959568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 969568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 979568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 989568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117206 # Categorize write packet sizes 999568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see 1009568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see 1019568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see 1029568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see 1039568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see 1049568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see 1059568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see 1069568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see 1079568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see 1089568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see 1099568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see 1109568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see 1119568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see 1129568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see 1139568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see 1149568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see 1159568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see 1169568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see 1179568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see 1189568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see 1199568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see 1209568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see 1219568Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1319568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see 1329568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see 1339568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see 1349568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see 1359568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see 1369568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see 1379568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see 1389568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see 1399568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see 1409568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see 1419568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see 1429568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see 1439568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see 1449568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see 1459568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see 1469568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see 1479568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see 1489568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see 1499568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see 1509568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see 1519568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see 1529568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see 1539568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see 1549568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see 1559568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see 1569536SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see 1579568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see 1589568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see 1599568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see 1609568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see 1619568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see 1629568Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see 1639568Sandreas.hansson@arm.comsystem.physmem.totQLat 7499469250 # Total cycles spent in queuing delays 1649568Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests 1659568Sandreas.hansson@arm.comsystem.physmem.totBusLat 2225595000 # Total cycles spent in databus access 1669568Sandreas.hansson@arm.comsystem.physmem.totBankLat 5484971250 # Total cycles spent in bank access 1679568Sandreas.hansson@arm.comsystem.physmem.avgQLat 16848.23 # Average queueing delay per request 1689568Sandreas.hansson@arm.comsystem.physmem.avgBankLat 12322.48 # Average bank access latency per request 1699490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 1709568Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 34170.72 # Average memory access latency 1719568Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s 1729312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 1739568Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s 1749312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 1759490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1769490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 1779312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.01 # Average read queue length over time 1789568Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 14.44 # Average write queue length over time 1799568Sandreas.hansson@arm.comsystem.physmem.readRowHits 417746 # Number of row buffer hits during reads 1809568Sandreas.hansson@arm.comsystem.physmem.writeRowHits 91351 # Number of row buffer hits during writes 1819568Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads 1829568Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes 1839568Sandreas.hansson@arm.comsystem.physmem.avgGap 3297216.82 # Average gap between requests 1848464SN/Asystem.iocache.replacements 41685 # number of replacements 1859568Sandreas.hansson@arm.comsystem.iocache.tagsinuse 1.265036 # Cycle average of tags in use 1868464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 1878464SN/Asystem.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 1888464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 1899568Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. 1909568Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor 1919568Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy 1929568Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy 1938835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1948464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1958835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 1968464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 1978835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1988464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1998835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 2008464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 2019348SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles 2029348SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles 2039568Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles 2049568Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles 2059568Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles 2069568Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles 2079568Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles 2089568Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles 2098835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 2108464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 2118835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 2128464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 2138835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 2148464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 2158835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 2168464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 2178835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2189055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2198835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 2209055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2218835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2229055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2238835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2249055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2259348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency 2269348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency 2279568Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency 2289568Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency 2299568Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency 2309568Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency 2319568Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency 2329568Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency 2339568Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked 2348464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2359568Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked 2368464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2379568Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked 2388983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2398464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2408464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2418835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 2428835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 2438835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 2448835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 2458835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 2468835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 2478835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 2488835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 2498835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 2508835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 2519568Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles 2529568Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles 2539568Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles 2549568Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles 2559568Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles 2569568Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles 2579568Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles 2589568Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles 2598835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 2609055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2618835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 2629055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2638835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 2649055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2658835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 2669055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2679568Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency 2689568Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency 2699568Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency 2709568Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency 2719568Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency 2729568Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency 2739568Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency 2749568Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency 2758464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2768464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2778464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2788464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2798464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2808464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2818464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2828464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2838464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2848464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2858464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2868464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2878464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2889568Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 13852347 # Number of BP lookups 2899568Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted 2909568Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect 2919568Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups 2929568Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5813293 # Number of BTB hits 2939481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2949568Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage 2959568Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target. 2969568Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions. 2978464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2988464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2998464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3008464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 3019568Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9912757 # DTB read hits 3029568Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41466 # DTB read misses 3039568Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 543 # DTB read access violations 3049568Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 941271 # DTB read accesses 3059568Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6601987 # DTB write hits 3069568Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 10361 # DTB write misses 3079568Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 401 # DTB write access violations 3089568Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 337783 # DTB write accesses 3099568Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16514744 # DTB hits 3109568Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 51827 # DTB misses 3119568Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 944 # DTB access violations 3129568Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1279054 # DTB accesses 3139568Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1307981 # ITB hits 3149568Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 36519 # ITB misses 3159568Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 1105 # ITB acv 3169568Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1344500 # ITB accesses 3178464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3188464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3198464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3208464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3218464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3228464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3238464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3248464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3258464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3268464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3278464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3288464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 3299568Sandreas.hansson@arm.comsystem.cpu.numCycles 108624305 # number of cpu cycles simulated 3308464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3318464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3329568Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss 3339568Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed 3349568Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered 3359568Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken 3369568Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked 3379568Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing 3389568Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked 3399568Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 3409568Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps 3419568Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions 3429568Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR 3439568Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched 3449568Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed 3459568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total) 3469568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total) 3479568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total) 3488464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3499568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total) 3509568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total) 3519568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total) 3529568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total) 3539568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total) 3549568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total) 3559568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total) 3569568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total) 3579568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total) 3588464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3598464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3608464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3619568Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total) 3629568Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle 3639568Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle 3649568Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle 3659568Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked 3669568Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 12110722 # Number of cycles decode is running 3679568Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking 3689568Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing 3699568Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch 3709568Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction 3719568Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode 3729568Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode 3739568Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing 3749568Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle 3759568Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking 3769568Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst 3779568Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11346001 # Number of cycles rename is running 3789568Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking 3799568Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename 3809568Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full 3819568Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full 3829568Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full 3839568Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed 3849568Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made 3859568Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups 3869568Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups 3879568Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed 3889568Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing 3899568Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed 3909568Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed 3919568Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer 3929568Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit. 3939568Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit. 3949568Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads. 3959568Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores. 3969568Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec) 3979568Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ 3989568Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued 3999568Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued 4009568Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling 4019568Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph 4029568Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed 4039568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle 4049568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle 4059568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle 4068464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 4079568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle 4089568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle 4099568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle 4109568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle 4119568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle 4129568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle 4139568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle 4149568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle 4159568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle 4168464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4178464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4188464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 4199568Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle 4208464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 4219568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available 4229568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available 4239568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available 4249568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available 4259568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available 4269568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available 4279568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available 4289568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available 4299568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available 4309568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available 4319568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available 4329568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available 4339568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available 4349568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available 4359568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available 4369568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available 4379568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available 4389568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available 4399568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available 4409568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available 4419568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available 4429568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available 4439568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available 4449568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available 4459568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available 4469568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available 4479568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available 4489568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available 4499568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available 4509568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available 4519568Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available 4528464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4538464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4549348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 4559568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued 4569568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued 4579568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued 4589490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued 4599490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued 4609490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued 4619490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued 4629568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued 4639568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued 4649568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued 4659568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued 4669568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued 4679568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued 4689568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued 4699568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued 4709568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued 4719568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued 4729568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued 4739568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued 4749568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued 4759568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued 4769568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued 4779568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued 4789568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued 4799568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued 4809568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued 4819568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued 4829568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued 4839568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued 4849568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued 4859568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued 4869568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued 4878464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4889568Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 56809344 # Type of FU issued 4899568Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.522989 # Inst issue rate 4909568Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 793713 # FU busy when requested 4919568Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst) 4929568Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads 4939568Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes 4949568Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses 4959568Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads 4969568Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes 4979568Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses 4989568Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses 4999568Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses 5009568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores 5018464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 5029568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed 5039568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed 5049568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations 5059568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed 5068464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5078464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5089568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled 5099568Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked 5108464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 5119568Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing 5129568Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking 5139568Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking 5149568Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ 5159568Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch 5169568Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions 5179568Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions 5189568Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions 5199568Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall 5209568Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall 5219568Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations 5229568Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly 5239568Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly 5249568Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute 5259568Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions 5269568Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed 5279568Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute 5288464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5299568Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3528457 # number of nop insts executed 5309568Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16609952 # number of memory reference insts executed 5319568Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8925181 # Number of branches executed 5329568Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6627584 # Number of stores executed 5339568Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.518660 # Inst execution rate 5349568Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit 5359568Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 55903887 # cumulative count of insts written-back 5369568Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 27773544 # num instructions producing a value 5379568Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 37603829 # num instructions consuming a value 5388464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 5399568Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.514654 # insts written-back per cycle 5409568Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back 5418464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 5429568Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit 5439568Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards 5449568Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted 5459568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle 5469568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle 5479568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle 5488241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5499568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle 5509568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle 5519568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle 5529568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle 5539568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle 5549568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle 5559568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle 5569568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle 5579568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle 5588241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5598241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5608241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5619568Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle 5629568Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56158922 # Number of instructions committed 5639568Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed 5648464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5659568Sandreas.hansson@arm.comsystem.cpu.commit.refs 15466723 # Number of memory references committed 5669568Sandreas.hansson@arm.comsystem.cpu.commit.loads 9090045 # Number of loads committed 5679568Sandreas.hansson@arm.comsystem.cpu.commit.membars 226335 # Number of memory barriers committed 5689568Sandreas.hansson@arm.comsystem.cpu.commit.branches 8439344 # Number of branches committed 5698517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 5709568Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52009184 # Number of committed integer instructions. 5719568Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740395 # Number of function calls committed. 5729568Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached 5738464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5749568Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 140815408 # The number of ROB reads 5759568Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 128505533 # The number of ROB writes 5769568Sandreas.hansson@arm.comsystem.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself 5779568Sandreas.hansson@arm.comsystem.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling 5789568Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 5799568Sandreas.hansson@arm.comsystem.cpu.committedInsts 52968721 # Number of Instructions Simulated 5809568Sandreas.hansson@arm.comsystem.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated 5819568Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 52968721 # Number of Instructions Simulated 5829568Sandreas.hansson@arm.comsystem.cpu.cpi 2.050725 # CPI: Cycles Per Instruction 5839568Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads 5849568Sandreas.hansson@arm.comsystem.cpu.ipc 0.487632 # IPC: Instructions Per Cycle 5859568Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads 5869568Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 73881531 # number of integer regfile reads 5879568Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40312822 # number of integer regfile writes 5889568Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166061 # number of floating regfile reads 5899568Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167429 # number of floating regfile writes 5909568Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1987886 # number of misc regfile reads 5919568Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 938918 # number of misc regfile writes 5928464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 5938464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 5948464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 5958464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 5968464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 5978983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 5988464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 5998464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 6008983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 6018464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 6028464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 6038983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 6048464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 6058464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 6068983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 6078464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 6088464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 6098983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 6108464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 6118464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 6128983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 6138464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 6148464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 6158983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 6168464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 6178464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 6188983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 6198464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 6208983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 6218464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 6228464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 6239568Sandreas.hansson@arm.comsystem.cpu.icache.replacements 1008795 # number of replacements 6249568Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use 6259568Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 7484836 # Total number of references to valid blocks. 6269568Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks. 6279568Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks. 6289568Sandreas.hansson@arm.comsystem.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. 6299568Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor 6309568Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy 6319568Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy 6329568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits 6339568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits 6349568Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits 6359568Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits 6369568Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits 6379568Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7484837 # number of overall hits 6389568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses 6399568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses 6409568Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses 6419568Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses 6429568Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses 6439568Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1065140 # number of overall misses 6449568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14678664495 # number of ReadReq miss cycles 6459568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles 6469568Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles 6479568Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles 6489568Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles 6499568Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles 6509568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8549977 # number of ReadReq accesses(hits+misses) 6519568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses) 6529568Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses 6539568Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses 6549568Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8549977 # number of overall (read+write) accesses 6559568Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses 6569568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses 6579568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses 6589568Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses 6599568Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses 6609568Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses 6619568Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses 6629568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency 6639568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency 6649568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency 6659568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency 6669568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency 6679568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency 6689568Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 7122 # number of cycles access was blocked 6699568Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked 6709568Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 164 # number of cycles access was blocked 6719568Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 6729568Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 43.426829 # average number of cycles each access was blocked 6739568Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked 6748464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6758464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6769568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 55619 # number of ReadReq MSHR hits 6779568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 55619 # number of ReadReq MSHR hits 6789568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 55619 # number of demand (read+write) MSHR hits 6799568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 55619 # number of demand (read+write) MSHR hits 6809568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 55619 # number of overall MSHR hits 6819568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 55619 # number of overall MSHR hits 6829568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009521 # number of ReadReq MSHR misses 6839568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1009521 # number of ReadReq MSHR misses 6849568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1009521 # number of demand (read+write) MSHR misses 6859568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1009521 # number of demand (read+write) MSHR misses 6869568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1009521 # number of overall MSHR misses 6879568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1009521 # number of overall MSHR misses 6889568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12035617996 # number of ReadReq MSHR miss cycles 6899568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12035617996 # number of ReadReq MSHR miss cycles 6909568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12035617996 # number of demand (read+write) MSHR miss cycles 6919568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12035617996 # number of demand (read+write) MSHR miss cycles 6929568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12035617996 # number of overall MSHR miss cycles 6939568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12035617996 # number of overall MSHR miss cycles 6949568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for ReadReq accesses 6959568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.118073 # mshr miss rate for ReadReq accesses 6969568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for demand accesses 6979568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.118073 # mshr miss rate for demand accesses 6989568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for overall accesses 6999568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.118073 # mshr miss rate for overall accesses 7009568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.107609 # average ReadReq mshr miss latency 7019568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.107609 # average ReadReq mshr miss latency 7029568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency 7039568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency 7049568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency 7059568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency 7068464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7079568Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements 338260 # number of replacements 7089568Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 65365.866515 # Cycle average of tags in use 7099568Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 2544525 # Total number of references to valid blocks. 7109568Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 403426 # Sample count of references to valid blocks. 7119568Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 6.307291 # Average number of references to valid blocks. 7129568Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit. 7139568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 53972.516540 # Average occupied blocks per requestor 7149568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 5322.981591 # Average occupied blocks per requestor 7159568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 6070.368385 # Average occupied blocks per requestor 7169568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.823555 # Average percentage of cache occupancy 7179568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.081222 # Average percentage of cache occupancy 7189568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.092626 # Average percentage of cache occupancy 7199568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.997404 # Average percentage of cache occupancy 7209568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 994349 # number of ReadReq hits 7219568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 826677 # number of ReadReq hits 7229568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1821026 # number of ReadReq hits 7239568Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 840320 # number of Writeback hits 7249568Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 840320 # number of Writeback hits 7259568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits 7269568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits 7279568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 7289568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 7299568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185342 # number of ReadExReq hits 7309568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185342 # number of ReadExReq hits 7319568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 994349 # number of demand (read+write) hits 7329568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1012019 # number of demand (read+write) hits 7339568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2006368 # number of demand (read+write) hits 7349568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 994349 # number of overall hits 7359568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1012019 # number of overall hits 7369568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2006368 # number of overall hits 7379568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15056 # number of ReadReq misses 7389568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273775 # number of ReadReq misses 7399568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288831 # number of ReadReq misses 7409568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses 7419568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses 7429568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 7439568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 7449568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses 7459568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses 7469568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15056 # number of demand (read+write) misses 7479568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389170 # number of demand (read+write) misses 7489568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404226 # number of demand (read+write) misses 7499568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15056 # number of overall misses 7509568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389170 # number of overall misses 7519568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404226 # number of overall misses 7529568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1039366500 # number of ReadReq miss cycles 7539568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 11945940500 # number of ReadReq miss cycles 7549568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 12985307000 # number of ReadReq miss cycles 7559568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 290000 # number of UpgradeReq miss cycles 7569568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 290000 # number of UpgradeReq miss cycles 7579568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 23000 # number of SCUpgradeReq miss cycles 7589568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 23000 # number of SCUpgradeReq miss cycles 7599568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7619154000 # number of ReadExReq miss cycles 7609568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7619154000 # number of ReadExReq miss cycles 7619568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1039366500 # number of demand (read+write) miss cycles 7629568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 19565094500 # number of demand (read+write) miss cycles 7639568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 20604461000 # number of demand (read+write) miss cycles 7649568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1039366500 # number of overall miss cycles 7659568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 19565094500 # number of overall miss cycles 7669568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 20604461000 # number of overall miss cycles 7679568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1009405 # number of ReadReq accesses(hits+misses) 7689568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1100452 # number of ReadReq accesses(hits+misses) 7699568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2109857 # number of ReadReq accesses(hits+misses) 7709568Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 840320 # number of Writeback accesses(hits+misses) 7719568Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 840320 # number of Writeback accesses(hits+misses) 7729568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) 7739568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) 7749568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 7759568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 7769568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 300737 # number of ReadExReq accesses(hits+misses) 7779568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 300737 # number of ReadExReq accesses(hits+misses) 7789568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1009405 # number of demand (read+write) accesses 7799568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1401189 # number of demand (read+write) accesses 7809568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2410594 # number of demand (read+write) accesses 7819568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1009405 # number of overall (read+write) accesses 7829568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1401189 # number of overall (read+write) accesses 7839568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2410594 # number of overall (read+write) accesses 7849568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014916 # miss rate for ReadReq accesses 7859568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248784 # miss rate for ReadReq accesses 7869568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136896 # miss rate for ReadReq accesses 7879568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses 7889568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses 7899568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 7909568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 7919568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383707 # miss rate for ReadExReq accesses 7929568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383707 # miss rate for ReadExReq accesses 7939568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014916 # miss rate for demand accesses 7949568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277743 # miss rate for demand accesses 7959568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.167687 # miss rate for demand accesses 7969568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014916 # miss rate for overall accesses 7979568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277743 # miss rate for overall accesses 7989568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.167687 # miss rate for overall accesses 7999568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69033.375399 # average ReadReq miss latency 8009568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43634.153959 # average ReadReq miss latency 8019568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 44958.148537 # average ReadReq miss latency 8029568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7435.897436 # average UpgradeReq miss latency 8039568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7435.897436 # average UpgradeReq miss latency 8049568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11500 # average SCUpgradeReq miss latency 8059568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11500 # average SCUpgradeReq miss latency 8069568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66026.725595 # average ReadExReq miss latency 8079568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 66026.725595 # average ReadExReq miss latency 8089568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69033.375399 # average overall miss latency 8099568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 50273.902151 # average overall miss latency 8109568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 50972.626699 # average overall miss latency 8119568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69033.375399 # average overall miss latency 8129568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 50273.902151 # average overall miss latency 8139568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 50972.626699 # average overall miss latency 8149285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8159285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8169285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8179285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8189285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8199285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8209285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8219285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8229568Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 75694 # number of writebacks 8239568Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 75694 # number of writebacks 8249285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 8259285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 8269285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 8279285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 8289285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 8299285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 8309568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15055 # number of ReadReq MSHR misses 8319568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273775 # number of ReadReq MSHR misses 8329568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288830 # number of ReadReq MSHR misses 8339568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses 8349568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses 8359568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 8369568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 8379568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses 8389568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses 8399568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15055 # number of demand (read+write) MSHR misses 8409568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389170 # number of demand (read+write) MSHR misses 8419568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404225 # number of demand (read+write) MSHR misses 8429568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15055 # number of overall MSHR misses 8439568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389170 # number of overall MSHR misses 8449568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404225 # number of overall MSHR misses 8459568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851622750 # number of ReadReq MSHR miss cycles 8469568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8594985001 # number of ReadReq MSHR miss cycles 8479568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 9446607751 # number of ReadReq MSHR miss cycles 8489568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 547534 # number of UpgradeReq MSHR miss cycles 8499568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 547534 # number of UpgradeReq MSHR miss cycles 8509568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 8519568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles 8529568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6209572959 # number of ReadExReq MSHR miss cycles 8539568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6209572959 # number of ReadExReq MSHR miss cycles 8549568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851622750 # number of demand (read+write) MSHR miss cycles 8559568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14804557960 # number of demand (read+write) MSHR miss cycles 8569568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles 8579568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles 8589568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles 8599568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles 8609568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles 8619568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles 8629568Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles 8639568Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles 8649568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles 8659568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles 8669568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses 8679568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses 8689568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses 8699568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses 8709568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses 8719568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 8729568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 8739568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses 8749568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses 8759568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses 8769568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses 8779568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses 8789568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses 8799568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses 8809568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses 8819568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency 8829568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency 8839568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency 8849568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency 8859568Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency 8869568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 8879568Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 8889568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency 8899568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency 8909568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency 8919568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency 8929568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency 8939568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency 8949568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency 8959568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency 8969285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 8979285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 8989285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 8999285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 9009285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 9019285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 9029285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 9039568Sandreas.hansson@arm.comsystem.cpu.dcache.replacements 1400597 # number of replacements 9049568Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use 9059568Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks. 9069568Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks. 9079568Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks. 9089490Sandreas.hansson@arm.comsystem.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. 9099568Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor 9109348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 9119348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 9129568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits 9139568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits 9149568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits 9159568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits 9169568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits 9179568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits 9189568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits 9199568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits 9209568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits 9219568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits 9229568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits 9239568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11402525 # number of overall hits 9249568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses 9259568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses 9269568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses 9279568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses 9289568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses 9299568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses 9309568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 9319568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 9329568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses 9339568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses 9349568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses 9359568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3745583 # number of overall misses 9369568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles 9379568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles 9389568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles 9399568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles 9409568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles 9419568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles 9429568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles 9439568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles 9449568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles 9459568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles 9469568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles 9479568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles 9489568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses) 9499568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses) 9509568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses) 9519568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses) 9529568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses) 9539568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses) 9549568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) 9559568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) 9569568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses 9579568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses 9589568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses 9599568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses 9609568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses 9619568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses 9629568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses 9639568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses 9649568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses 9659568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses 9669568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses 9679568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses 9689568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses 9699568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses 9709568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses 9719568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses 9729568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency 9739568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency 9749568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency 9759568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency 9769568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency 9779568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency 9789568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency 9799568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency 9809568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency 9819568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency 9829568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency 9839568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency 9849568Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked 9859568Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked 9869568Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked 9879568Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked 9889568Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked 9899568Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked 9909348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 9919348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 9929568Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 840320 # number of writebacks 9939568Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 840320 # number of writebacks 9949568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits 9959568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits 9969568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits 9979568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits 9989568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits 9999568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits 10009568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits 10019568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits 10029568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits 10039568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits 10049568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses 10059568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses 10069568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses 10079568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses 10089568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses 10099568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses 10109568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 10119568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 10129568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses 10139568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses 10149568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses 10159568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses 10169568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles 10179568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles 10189568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles 10199568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles 10209568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles 10219568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles 10229568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles 10239568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles 10249568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles 10259568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles 10269568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles 10279568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles 10289568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles 10299568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles 10309568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles 10319568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles 10329568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles 10339568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles 10349568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses 10359568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses 10369568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses 10379568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses 10389568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses 10399568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses 10409568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses 10419568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses 10429568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses 10439568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses 10449568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses 10459568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses 10469568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency 10479568Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency 10489568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency 10499568Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency 10509568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency 10519568Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency 10529568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency 10539568Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency 10549568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency 10559568Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency 10569568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency 10579568Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency 10589348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 10599348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 10609348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 10619348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 10629348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 10639348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 10649348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10655703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 10669568Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed 10679568Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed 10689568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl 10699285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 10709490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 10719568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl 10729568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl 10739568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl 10749285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 10759490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 10769568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl 10779568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl 10789568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl 10799568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl 10809568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl 10819568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl 10829568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl 10839568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 10846127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 10856127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 10869568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl 10879568Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl 10886291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 10896291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 10906291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 10916291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 10926291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 10936291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 10946291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 10956291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 10966291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 10976291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 10986291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 10996291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 11006291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 11016291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 11026291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 11036291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 11046291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 11056291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 11066291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 11076291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 11086291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 11096291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 11106291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 11116291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 11126291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 11136291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 11146291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 11156291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 11166291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 11176291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 11186127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 11198464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 11208464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 11218464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 11228464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 11239285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 11249285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 11259199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 11269568Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed 11279490Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 11289285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 11299199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 11309285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 11319285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 11329490Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 11338464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 11348464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 11359568Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191959 # number of callpals executed 11369490Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches 11379536SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch::user 1740 # number of protection mode switches 11389348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 11399536SAli.Saidi@ARM.comsystem.cpu.kern.mode_good::kernel 1910 11409536SAli.Saidi@ARM.comsystem.cpu.kern.mode_good::user 1740 11418517SN/Asystem.cpu.kern.mode_good::idle 170 11429536SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches 11438464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 11449348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 11459536SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches 11469568Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode 11479568Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode 11489568Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode 11498517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 11505703SN/A 11515703SN/A---------- End Simulation Statistics ---------- 1152