xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.854310                       # Number of seconds simulated
sim_ticks                                1854310111000                       # Number of ticks simulated
final_tick                               1854310111000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 145253                       # Simulator instruction rate (inst/s)
host_op_rate                                   145253                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5083862253                       # Simulator tick rate (ticks/s)
host_mem_usage                                 332668                       # Number of bytes of host memory used
host_seconds                                   364.74                       # Real time elapsed on the host
sim_insts                                    52980262                       # Number of instructions simulated
sim_ops                                      52980262                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            964224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24877184                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28493696                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       964224                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964224                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7514944                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7514944                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15066                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388706                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445214                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117421                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117421                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               519991                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13415870                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1430337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15366198                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          519991                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             519991                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4052690                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4052690                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4052690                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              519991                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13415870                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1430337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19418888                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445214                       # Total number of read requests seen
system.physmem.writeReqs                       117421                       # Total number of write requests seen
system.physmem.cpureqs                         564314                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28493696                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7514944                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28493696                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7514944                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       56                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                174                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28116                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 27866                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 27714                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 27520                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 27750                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 27793                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 27726                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27564                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 28224                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27918                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                27999                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27794                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27705                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                27923                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27829                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27717                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7633                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7399                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7274                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7170                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7277                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7235                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7211                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7144                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7765                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7469                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7552                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7291                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7210                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7327                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7264                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7200                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                         946                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1854304705000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  445214                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 118367                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                  174                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    323357                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64296                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     19752                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7564                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2966                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2710                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2705                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2662                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2613                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1551                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1409                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1357                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1393                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1607                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1481                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      912                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      777                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2975                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3712                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5093                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     1394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      941                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                      356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     7913395266                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               15649662766                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2225790000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5510477500                       # Total cycles spent in bank access
system.physmem.avgQLat                       17776.60                       # Average queueing delay per request
system.physmem.avgBankLat                    12378.70                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  35155.30                       # Average memory access latency
system.physmem.avgRdBW                          15.37                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.05                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.37                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.05                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        11.52                       # Average write queue length over time
system.physmem.readRowHits                     417628                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     91533                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.95                       # Row buffer hit rate for writes
system.physmem.avgGap                      3295750.72                       # Average gap between requests
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.265053                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1704474436000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.265053                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.079066                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.079066                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20927998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20927998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  10610366806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10610366806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  10631294804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10631294804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  10631294804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10631294804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 255351.530757                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 254794.363188                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 254794.363188                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        282772                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27194                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.398323                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11931250                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11931250                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   8448369274                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8448369274                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   8460300524                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8460300524                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   8460300524                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8460300524                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 202763.343895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 202763.343895                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13838840                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11607895                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            399412                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9524270                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5814876                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             61.053246                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  905729                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              39052                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9926019                       # DTB read hits
system.cpu.dtb.read_misses                      41533                       # DTB read misses
system.cpu.dtb.read_acv                           530                       # DTB read access violations
system.cpu.dtb.read_accesses                   942239                       # DTB read accesses
system.cpu.dtb.write_hits                     6593693                       # DTB write hits
system.cpu.dtb.write_misses                     10528                       # DTB write misses
system.cpu.dtb.write_acv                          400                       # DTB write access violations
system.cpu.dtb.write_accesses                  337995                       # DTB write accesses
system.cpu.dtb.data_hits                     16519712                       # DTB hits
system.cpu.dtb.data_misses                      52061                       # DTB misses
system.cpu.dtb.data_acv                           930                       # DTB access violations
system.cpu.dtb.data_accesses                  1280234                       # DTB accesses
system.cpu.itb.fetch_hits                     1304342                       # ITB hits
system.cpu.itb.fetch_misses                     39856                       # ITB misses
system.cpu.itb.fetch_acv                         1022                       # ITB acv
system.cpu.itb.fetch_accesses                 1344198                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        109629781                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28054548                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70673295                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13838840                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6720605                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13244077                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1985157                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               37404215                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32636                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        256282                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       293547                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          309                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8545648                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                265175                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           80570729                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.877158                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.220803                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 67326652     83.56%     83.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   851821      1.06%     84.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1698513      2.11%     86.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   825554      1.02%     87.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2751975      3.42%     91.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   562639      0.70%     91.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   645154      0.80%     92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1011601      1.26%     93.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4896820      6.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             80570729                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.126232                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.644654                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29191187                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37065229                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12109046                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                962419                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1242847                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               584292                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42668                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69380603                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129620                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1242847                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30314558                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                13623750                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       19784463                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11341758                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4263351                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65627824                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  6945                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 510530                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1483365                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43820100                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79668795                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79189543                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            479252                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38180356                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5639736                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1682796                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         239926                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12145356                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10440685                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6902590                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1325482                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           872752                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58180873                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2047058                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56813064                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            111741                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6883646                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3532849                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1386082                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      80570729                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.705133                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.366225                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            55925631     69.41%     69.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10804122     13.41%     82.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5164072      6.41%     89.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3379310      4.19%     93.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2651147      3.29%     96.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1461283      1.81%     98.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              759145      0.94%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              331157      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               94862      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        80570729                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   89963     11.41%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 373446     47.37%     58.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                325006     41.22%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38735893     68.18%     68.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61716      0.11%     68.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10357569     18.23%     86.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6672257     11.74%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949100      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56813064                       # Type of FU issued
system.cpu.iq.rate                           0.518227                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      788415                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013877                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          194404430                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66788743                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55573367                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              692582                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             336629                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327887                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57232794                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  361399                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           600057                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1348422                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         4157                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14125                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       524715                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17951                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        174954                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1242847                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 9951157                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                684131                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63754506                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            676985                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10440685                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6902590                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1803123                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 512112                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 18418                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14125                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         202045                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       411832                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               613877                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56345945                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts               9995759                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            467118                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3526575                       # number of nop insts executed
system.cpu.iew.exec_refs                     16615200                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8926807                       # Number of branches executed
system.cpu.iew.exec_stores                    6619441                       # Number of stores executed
system.cpu.iew.exec_rate                     0.513966                       # Inst execution rate
system.cpu.iew.wb_sent                       56016691                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55901254                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27769565                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37614191                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.509909                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.738274                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7465102                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660976                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            568169                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     79327882                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.708087                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.637784                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     58561818     73.82%     73.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8602415     10.84%     84.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4601651      5.80%     90.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2532853      3.19%     93.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1516154      1.91%     95.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       607730      0.77%     96.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       522045      0.66%     97.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       534524      0.67%     97.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1848692      2.33%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     79327882                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56171016                       # Number of instructions committed
system.cpu.commit.committedOps               56171016                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15470138                       # Number of memory references committed
system.cpu.commit.loads                       9092263                       # Number of loads committed
system.cpu.commit.membars                      226349                       # Number of memory barriers committed
system.cpu.commit.branches                    8440338                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52020652                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740552                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1848692                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    140865752                       # The number of ROB reads
system.cpu.rob.rob_writes                   128516921                       # The number of ROB writes
system.cpu.timesIdled                         1179002                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        29059052                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3598984001                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52980262                       # Number of Instructions Simulated
system.cpu.committedOps                      52980262                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52980262                       # Number of Instructions Simulated
system.cpu.cpi                               2.069257                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.069257                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.483265                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.483265                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73880365                       # number of integer regfile reads
system.cpu.int_regfile_writes                40316413                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166011                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167446                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1987331                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938994                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                1008798                       # number of replacements
system.cpu.icache.tagsinuse                510.238342                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7480626                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1009306                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.411653                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            20723156000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.238342                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996559                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996559                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7480627                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7480627                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7480627                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7480627                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7480627                       # number of overall hits
system.cpu.icache.overall_hits::total         7480627                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1065018                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1065018                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1065018                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1065018                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1065018                       # number of overall misses
system.cpu.icache.overall_misses::total       1065018                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14700112992                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14700112992                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14700112992                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14700112992                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14700112992                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14700112992                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8545645                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8545645                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8545645                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8545645                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8545645                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8545645                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124627                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124627                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124627                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124627                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124627                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124627                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13802.689712                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13802.689712                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         5838                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          237                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               203                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    28.758621                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          237                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        55491                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        55491                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        55491                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        55491                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        55491                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        55491                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1009527                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1009527                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1009527                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1009527                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1009527                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1009527                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12048771993                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12048771993                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12048771993                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12048771993                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12048771993                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12048771993                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118134                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118134                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118134                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.118134                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118134                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.118134                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                338275                       # number of replacements
system.cpu.l2cache.tagsinuse             65364.674694                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 2545615                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                403441                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.309758                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle            4180772752                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 54011.059986                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   5325.208257                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6028.406451                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.824143                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.081256                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.091986                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997386                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       994342                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       827132                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1821474                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840875                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840875                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185593                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185593                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       994342                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1012725                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2007067                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       994342                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1012725                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2007067                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15068                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273766                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288834                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           35                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           35                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115432                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115432                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15068                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389198                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404266                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15068                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389198                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404266                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1052241000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  12408474500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  13460715500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       274500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       274500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7669350500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7669350500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1052241000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  20077825000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  21130066000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1052241000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  20077825000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  21130066000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1009410                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100898                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2110308                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840875                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840875                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           61                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           61                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       301025                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       301025                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1009410                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1401923                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2411333                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1009410                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1401923                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2411333                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014928                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248675                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136868                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.573770                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.573770                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383463                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383463                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014928                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277617                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167652                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014928                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277617                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167652                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69832.824529                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45325.111592                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46603.639115                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7842.857143                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7842.857143                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66440.419468                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66440.419468                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69832.824529                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51587.688015                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52267.729663                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69832.824529                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51587.688015                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52267.729663                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75909                       # number of writebacks
system.cpu.l2cache.writebacks::total            75909                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15067                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273766                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288833                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           35                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           35                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115432                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115432                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15067                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389198                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404265                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15067                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389198                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404265                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    864374583                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   9058859411                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   9923233994                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       514531                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       514531                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6259293268                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6259293268                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    864374583                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15318152679                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  16182527262                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    864374583                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15318152679                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  16182527262                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333805500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333805500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882511000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882511000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216316500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216316500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014927                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248675                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136868                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.573770                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.573770                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383463                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383463                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014927                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277617                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167652                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014927                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277617                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167652                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1401332                       # number of replacements
system.cpu.dcache.tagsinuse                511.995159                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 11818848                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1401844                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   8.430930                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21807000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.995159                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7212145                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7212145                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4204906                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4204906                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186063                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186063                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215520                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215520                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11417051                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11417051                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11417051                       # number of overall hits
system.cpu.dcache.overall_hits::total        11417051                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1802577                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1802577                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1942748                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1942748                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22749                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22749                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3745325                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3745325                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3745325                       # number of overall misses
system.cpu.dcache.overall_misses::total       3745325                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  34332308500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  34332308500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  65131487898                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  65131487898                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    306015000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    306015000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        13000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  99463796398                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  99463796398                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  99463796398                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  99463796398                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9014722                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9014722                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6147654                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6147654                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208812                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       208812                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215521                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215521                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15162376                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15162376                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15162376                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15162376                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199959                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.199959                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316015                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316015                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108945                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108945                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000005                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247014                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247014                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247014                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247014                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26556.786500                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26556.786500                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      2193487                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          506                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             95928                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.865972                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    72.285714                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840875                       # number of writebacks
system.cpu.dcache.writebacks::total            840875                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       718560                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       718560                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1642321                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1642321                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5210                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5210                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2360881                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2360881                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2360881                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2360881                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084017                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1084017                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300427                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300427                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17539                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17539                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1384444                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1384444                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1384444                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1384444                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21793042000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  21793042000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9888893772                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9888893772                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    199306000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    199306000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31681935772                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  31681935772                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31681935772                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31681935772                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423882500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423882500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997678998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997678998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421561498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421561498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120250                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120250                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048869                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048869                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083994                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083994                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091308                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091308                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091308                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091308                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6441                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211025                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74671     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105575     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182256                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73304     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73304     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148618                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1817868211500     98.03%     98.03% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                63824000      0.00%     98.04% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               559692500      0.03%     98.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             35817544000      1.93%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1854309272000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981693                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694331                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815435                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175141     91.23%     93.44% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191985                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5849                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326552                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29467227000      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2708568500      0.15%      1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1822133468500     98.26%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------