stats.txt revision 9490
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39490Sandreas.hansson@arm.comsim_seconds 1.854310 # Number of seconds simulated 49490Sandreas.hansson@arm.comsim_ticks 1854309852000 # Number of ticks simulated 59490Sandreas.hansson@arm.comfinal_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79490Sandreas.hansson@arm.comhost_inst_rate 117975 # Simulator instruction rate (inst/s) 89490Sandreas.hansson@arm.comhost_op_rate 117975 # Simulator op (including micro ops) rate (op/s) 99490Sandreas.hansson@arm.comhost_tick_rate 4129044881 # Simulator tick rate (ticks/s) 109490Sandreas.hansson@arm.comhost_mem_usage 335500 # Number of bytes of host memory used 119490Sandreas.hansson@arm.comhost_seconds 449.09 # Real time elapsed on the host 129490Sandreas.hansson@arm.comsim_insts 52981417 # Number of instructions simulated 139490Sandreas.hansson@arm.comsim_ops 52981417 # Number of ops (including micro ops) simulated 149490Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory 159490Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179490Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28494848 # Number of bytes read from this memory 189490Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory 199490Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory 209459Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory 219459Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 7516416 # Number of bytes written to this memory 229490Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory 239490Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory 249348SAli.Saidi@ARM.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259490Sandreas.hansson@arm.comsystem.physmem.num_reads::total 445232 # Number of read requests responded to by this memory 269459Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory 279459Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 117444 # Number of write requests responded to by this memory 289490Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s) 299490Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s) 309490Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) 319490Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s) 329490Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s) 339490Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s) 349490Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s) 359490Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s) 369490Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s) 379490Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s) 389490Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s) 399490Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) 409490Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s) 419490Sandreas.hansson@arm.comsystem.physmem.readReqs 445232 # Total number of read requests seen 429459Ssaidi@eecs.umich.edusystem.physmem.writeReqs 117444 # Total number of write requests seen 439490Sandreas.hansson@arm.comsystem.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady 449490Sandreas.hansson@arm.comsystem.physmem.bytesRead 28494848 # Total number of bytes read from memory 459459Ssaidi@eecs.umich.edusystem.physmem.bytesWritten 7516416 # Total number of bytes written to memory 469490Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize() 479459Ssaidi@eecs.umich.edusystem.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize() 489490Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q 499490Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 171 # Reqs where no action is needed 509490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis 519490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis 529490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis 539490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis 549490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis 559490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis 569490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis 579490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis 589490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis 599490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis 609490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis 619490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis 629490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis 639490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis 649490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis 659490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis 669490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis 679490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis 689490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis 699490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis 709490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis 719490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis 729490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis 739490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis 749490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis 759490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis 769490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis 779490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis 789490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis 799490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis 809490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis 819490Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 839490Sandreas.hansson@arm.comsystem.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry 849490Sandreas.hansson@arm.comsystem.physmem.totGap 1854304427000 # Total gap between requests 859312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 919490Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 445232 # Categorize read packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 1009490Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 119231 # categorize write packet sizes 1019312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 1029312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 1039312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 1049312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 1059312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 1069312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 1089312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 1099490Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 171 # categorize neither packet sizes 1109312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1119312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1129490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see 1139490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see 1149490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see 1159490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see 1169490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see 1179490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see 1189490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see 1199490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see 1209490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see 1219490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see 1229490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see 1239490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see 1249490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see 1259490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see 1269490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see 1279490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see 1289490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see 1299490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see 1309490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see 1319490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see 1329490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see 1339490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see 1349490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1459490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see 1469490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see 1479490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see 1489490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see 1499490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see 1509490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see 1519490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see 1529490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see 1539490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see 1549459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see 1559459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see 1569459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see 1579459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see 1589459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see 1599459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see 1609459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see 1619459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see 1629459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see 1639459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see 1649459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see 1659459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see 1669459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see 1679459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see 1689490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see 1699490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see 1709490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see 1719490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see 1729490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see 1739490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see 1749490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see 1759490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 1769490Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see 1779312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1789490Sandreas.hansson@arm.comsystem.physmem.totQLat 7898633503 # Total cycles spent in queuing delays 1799490Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests 1809490Sandreas.hansson@arm.comsystem.physmem.totBusLat 2225860000 # Total cycles spent in databus access 1819490Sandreas.hansson@arm.comsystem.physmem.totBankLat 5511935000 # Total cycles spent in bank access 1829490Sandreas.hansson@arm.comsystem.physmem.avgQLat 17742.88 # Average queueing delay per request 1839490Sandreas.hansson@arm.comsystem.physmem.avgBankLat 12381.59 # Average bank access latency per request 1849490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 1859490Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 35124.47 # Average memory access latency 1869312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s 1879312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 1889312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s 1899312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 1909490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1919490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 1929312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.01 # Average read queue length over time 1939490Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 10.74 # Average write queue length over time 1949490Sandreas.hansson@arm.comsystem.physmem.readRowHits 417598 # Number of row buffer hits during reads 1959490Sandreas.hansson@arm.comsystem.physmem.writeRowHits 91555 # Number of row buffer hits during writes 1969490Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads 1979490Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes 1989490Sandreas.hansson@arm.comsystem.physmem.avgGap 3295510.08 # Average gap between requests 1998464SN/Asystem.iocache.replacements 41685 # number of replacements 2009490Sandreas.hansson@arm.comsystem.iocache.tagsinuse 1.265033 # Cycle average of tags in use 2018464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 2028464SN/Asystem.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 2038464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 2049490Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit. 2059490Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor 2069490Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy 2079490Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy 2088835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 2098464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 2108835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 2118464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 2128835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 2138464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 2148835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 2158464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 2169348SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles 2179348SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles 2189490Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles 2199490Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles 2209490Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles 2219490Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles 2229490Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles 2239490Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles 2248835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 2258464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 2268835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 2278464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 2288835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 2298464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 2308835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 2318464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 2328835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2339055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2348835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 2359055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2368835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2379055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2388835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2399055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2409348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency 2419348SAli.Saidi@ARM.comsystem.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency 2429490Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency 2439490Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency 2449490Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency 2459490Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency 2469490Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency 2479490Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency 2489490Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked 2498464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2509490Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked 2518464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2529490Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked 2538983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2548464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2558464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2568835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 2578835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 2588835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 2598835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 2608835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 2618835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 2628835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 2638835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 2648835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 2658835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 2669490Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles 2679490Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles 2689490Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles 2699490Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles 2709490Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles 2719490Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles 2729490Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles 2739490Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles 2748835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 2759055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2768835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 2779055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2788835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 2799055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2808835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 2819055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2829490Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency 2839490Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency 2849490Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency 2859490Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency 2869490Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency 2879490Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency 2889490Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency 2899490Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency 2908464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2918464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2928464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2938464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2948464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2958464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2968464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2978464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2988464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2998464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 3008464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 3018464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 3028464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 3039490Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 13854519 # Number of BP lookups 3049490Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted 3059490Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect 3069490Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups 3079490Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5815567 # Number of BTB hits 3089481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 3099490Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage 3109490Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target. 3119490Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions. 3128464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3138464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3148464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3158464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 3169490Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9921013 # DTB read hits 3179490Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41705 # DTB read misses 3189490Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 547 # DTB read access violations 3199490Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 941529 # DTB read accesses 3209490Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6598119 # DTB write hits 3219490Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 10489 # DTB write misses 3229490Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 411 # DTB write access violations 3239490Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 338424 # DTB write accesses 3249490Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16519132 # DTB hits 3259490Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 52194 # DTB misses 3269490Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 958 # DTB access violations 3279490Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1279953 # DTB accesses 3289490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1307587 # ITB hits 3299490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 36909 # ITB misses 3309490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 1032 # ITB acv 3319490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1344496 # ITB accesses 3328464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3338464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3348464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3358464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3368464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3378464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3388464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3398464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3408464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3418464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3428464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3438464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 3449490Sandreas.hansson@arm.comsystem.cpu.numCycles 109625107 # number of cpu cycles simulated 3458464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3468464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3479490Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss 3489490Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed 3499490Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered 3509490Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken 3519490Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked 3529490Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing 3539490Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked 3549490Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 3559490Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps 3569490Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions 3579490Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR 3589490Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched 3599490Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed 3609490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total) 3619490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total) 3629490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total) 3638464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3649490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total) 3659490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total) 3669490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total) 3679490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total) 3689490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total) 3699490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total) 3709490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total) 3719490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total) 3729490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total) 3738464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3748464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3758464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3769490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total) 3779490Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle 3789490Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle 3799490Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle 3809490Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked 3819490Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 12111886 # Number of cycles decode is running 3829490Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking 3839490Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing 3849490Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch 3859490Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction 3869490Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode 3879490Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode 3889490Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing 3899490Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle 3909490Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking 3919490Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst 3929490Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11346848 # Number of cycles rename is running 3939490Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking 3949490Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename 3959490Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full 3969490Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full 3979490Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full 3989490Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed 3999490Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made 4009490Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups 4019490Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups 4029490Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed 4039490Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing 4049490Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed 4059490Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed 4069490Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer 4079490Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit. 4089490Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit. 4099490Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads. 4109490Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores. 4119490Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec) 4129490Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ 4139490Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued 4149490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued 4159490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling 4169490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph 4179490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed 4189490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle 4199490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle 4209490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle 4218464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 4229490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle 4239490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle 4249490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle 4259490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle 4269490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle 4279490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle 4289490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle 4299490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle 4309490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle 4318464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4328464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4338464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 4349490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle 4358464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 4369490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available 4379490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available 4389490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available 4399490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available 4409490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available 4419490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available 4429490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available 4439490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available 4449490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available 4459490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available 4469490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available 4479490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available 4489490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available 4499490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available 4509490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available 4519490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available 4529490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available 4539490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available 4549490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available 4559490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available 4569490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available 4579490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available 4589490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available 4599490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available 4609490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available 4619490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available 4629490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available 4639490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available 4649490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available 4659490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available 4669490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available 4678464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4688464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4699348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 4709490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued 4719490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued 4729490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued 4739490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued 4749490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued 4759490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued 4769490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued 4779490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued 4789490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued 4799490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued 4809490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued 4819490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued 4829490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued 4839490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued 4849490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued 4859490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued 4869490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued 4879490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued 4889490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued 4899490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued 4909490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued 4919490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued 4929490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued 4939490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued 4949490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued 4959490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued 4969490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued 4979490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued 4989490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued 4999490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued 5009490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued 5019490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued 5028464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 5039490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 56823763 # Type of FU issued 5049490Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.518346 # Inst issue rate 5059490Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 789067 # FU busy when requested 5069490Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst) 5079490Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads 5089490Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes 5099490Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses 5109490Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads 5119490Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes 5129490Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses 5139490Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses 5149490Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses 5159490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores 5168464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 5179490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed 5189490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed 5199490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations 5209490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed 5218464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5228464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5239490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled 5249490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked 5258464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 5269490Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing 5279490Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking 5289490Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking 5299490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ 5309490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch 5319490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions 5329490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions 5339490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions 5349490Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall 5359490Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall 5369490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations 5379490Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly 5389490Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly 5399490Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute 5409490Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions 5419490Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed 5429490Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute 5438464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5449490Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3527845 # number of nop insts executed 5459490Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16614745 # number of memory reference insts executed 5469490Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8928138 # Number of branches executed 5479490Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6623837 # Number of stores executed 5489490Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.514074 # Inst execution rate 5499490Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit 5509490Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 55913848 # cumulative count of insts written-back 5519490Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 27775021 # num instructions producing a value 5529490Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 37616621 # num instructions consuming a value 5538464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 5549490Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.510046 # insts written-back per cycle 5559490Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back 5568464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 5579490Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit 5589490Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards 5599490Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted 5609490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle 5619490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle 5629490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle 5638241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5649490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle 5659490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle 5669490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle 5679490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle 5689490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle 5699490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle 5709490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle 5719490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle 5729490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle 5738241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5748241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5758241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5769490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle 5779490Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56172173 # Number of instructions committed 5789490Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed 5798464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5809490Sandreas.hansson@arm.comsystem.cpu.commit.refs 15470144 # Number of memory references committed 5819490Sandreas.hansson@arm.comsystem.cpu.commit.loads 9092271 # Number of loads committed 5829490Sandreas.hansson@arm.comsystem.cpu.commit.membars 226349 # Number of memory barriers committed 5839490Sandreas.hansson@arm.comsystem.cpu.commit.branches 8440686 # Number of branches committed 5848517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 5859490Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52021801 # Number of committed integer instructions. 5869490Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740555 # Number of function calls committed. 5879490Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached 5888464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5899490Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 140883934 # The number of ROB reads 5909490Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 128542305 # The number of ROB writes 5919490Sandreas.hansson@arm.comsystem.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself 5929490Sandreas.hansson@arm.comsystem.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling 5939490Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 5949490Sandreas.hansson@arm.comsystem.cpu.committedInsts 52981417 # Number of Instructions Simulated 5959490Sandreas.hansson@arm.comsystem.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated 5969490Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 52981417 # Number of Instructions Simulated 5979490Sandreas.hansson@arm.comsystem.cpu.cpi 2.069124 # CPI: Cycles Per Instruction 5989490Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads 5999490Sandreas.hansson@arm.comsystem.cpu.ipc 0.483296 # IPC: Instructions Per Cycle 6009490Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads 6019490Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 73895852 # number of integer regfile reads 6029490Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40324169 # number of integer regfile writes 6039490Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166027 # number of floating regfile reads 6049490Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167433 # number of floating regfile writes 6059490Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1987804 # number of misc regfile reads 6069490Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 938984 # number of misc regfile writes 6078464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 6088464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 6098464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 6108464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 6118464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 6128983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 6138464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 6148464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 6158983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 6168464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 6178464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 6188983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 6198464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 6208464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 6218983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 6228464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 6238464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 6248983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 6258464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 6268464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 6278983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 6288464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 6298464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 6308983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 6318464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 6328464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 6338983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 6348464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 6358983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 6368464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 6378464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 6389490Sandreas.hansson@arm.comsystem.cpu.icache.replacements 1009308 # number of replacements 6399490Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 510.238404 # Cycle average of tags in use 6409490Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 7486940 # Total number of references to valid blocks. 6419490Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 1009816 # Sample count of references to valid blocks. 6429490Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 7.414163 # Average number of references to valid blocks. 6439490Sandreas.hansson@arm.comsystem.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit. 6449490Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 510.238404 # Average occupied blocks per requestor 6459490Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy 6469490Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy 6479490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7486941 # number of ReadReq hits 6489490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7486941 # number of ReadReq hits 6499490Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7486941 # number of demand (read+write) hits 6509490Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7486941 # number of demand (read+write) hits 6519490Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7486941 # number of overall hits 6529490Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7486941 # number of overall hits 6539490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1065537 # number of ReadReq misses 6549490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1065537 # number of ReadReq misses 6559490Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1065537 # number of demand (read+write) misses 6569490Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1065537 # number of demand (read+write) misses 6579490Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1065537 # number of overall misses 6589490Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1065537 # number of overall misses 6599490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14679368493 # number of ReadReq miss cycles 6609490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 14679368493 # number of ReadReq miss cycles 6619490Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14679368493 # number of demand (read+write) miss cycles 6629490Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 14679368493 # number of demand (read+write) miss cycles 6639490Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles 6649490Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles 6659490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses) 6669490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses) 6679490Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses 6689490Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses 6699490Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses 6709490Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses 6719490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses 6729490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses 6739490Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses 6749490Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses 6759490Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses 6769490Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses 6779490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency 6789490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency 6799490Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency 6809490Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency 6819490Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency 6829490Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency 6839490Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked 6849490Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 616 # number of cycles access was blocked 6859490Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 184 # number of cycles access was blocked 6869490Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 6879490Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 37.652174 # average number of cycles each access was blocked 6889490Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 308 # average number of cycles each access was blocked 6898464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6908464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6919490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 55502 # number of ReadReq MSHR hits 6929490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 55502 # number of ReadReq MSHR hits 6939490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 55502 # number of demand (read+write) MSHR hits 6949490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 55502 # number of demand (read+write) MSHR hits 6959490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 55502 # number of overall MSHR hits 6969490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 55502 # number of overall MSHR hits 6979490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010035 # number of ReadReq MSHR misses 6989490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1010035 # number of ReadReq MSHR misses 6999490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1010035 # number of demand (read+write) MSHR misses 7009490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1010035 # number of demand (read+write) MSHR misses 7019490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1010035 # number of overall MSHR misses 7029490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1010035 # number of overall MSHR misses 7039490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042197495 # number of ReadReq MSHR miss cycles 7049490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12042197495 # number of ReadReq MSHR miss cycles 7059490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042197495 # number of demand (read+write) MSHR miss cycles 7069490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12042197495 # number of demand (read+write) MSHR miss cycles 7079490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042197495 # number of overall MSHR miss cycles 7089490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12042197495 # number of overall MSHR miss cycles 7099490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for ReadReq accesses 7109490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.118099 # mshr miss rate for ReadReq accesses 7119490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for demand accesses 7129490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.118099 # mshr miss rate for demand accesses 7139490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for overall accesses 7149490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.118099 # mshr miss rate for overall accesses 7159490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.554659 # average ReadReq mshr miss latency 7169490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.554659 # average ReadReq mshr miss latency 7179490Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency 7189490Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency 7199490Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency 7209490Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency 7218464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7229490Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements 338291 # number of replacements 7239490Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 65364.646667 # Cycle average of tags in use 7249490Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 2546198 # Total number of references to valid blocks. 7259490Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 403460 # Sample count of references to valid blocks. 7269490Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 6.310906 # Average number of references to valid blocks. 7279490Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle 4180772752 # Cycle when the warmup percentage was hit. 7289490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 54014.481347 # Average occupied blocks per requestor 7299490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 5327.723075 # Average occupied blocks per requestor 7309490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 6022.442245 # Average occupied blocks per requestor 7319490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.824196 # Average percentage of cache occupancy 7329490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.081295 # Average percentage of cache occupancy 7339490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.091895 # Average percentage of cache occupancy 7349490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.997385 # Average percentage of cache occupancy 7359490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 994848 # number of ReadReq hits 7369490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 827113 # number of ReadReq hits 7379490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1821961 # number of ReadReq hits 7389490Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 840942 # number of Writeback hits 7399490Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 840942 # number of Writeback hits 7409490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 7419490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 7429490Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 7439490Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 7449490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185617 # number of ReadExReq hits 7459490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185617 # number of ReadExReq hits 7469490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 994848 # number of demand (read+write) hits 7479490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1012730 # number of demand (read+write) hits 7489490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2007578 # number of demand (read+write) hits 7499490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 994848 # number of overall hits 7509490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1012730 # number of overall hits 7519490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2007578 # number of overall hits 7529490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15075 # number of ReadReq misses 7539490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273765 # number of ReadReq misses 7549490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288840 # number of ReadReq misses 7559490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses 7569490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses 7579490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115444 # number of ReadExReq misses 7589490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115444 # number of ReadExReq misses 7599490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15075 # number of demand (read+write) misses 7609490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389209 # number of demand (read+write) misses 7619490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404284 # number of demand (read+write) misses 7629490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15075 # number of overall misses 7639490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389209 # number of overall misses 7649490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404284 # number of overall misses 7659490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1040084000 # number of ReadReq miss cycles 7669490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 12407885000 # number of ReadReq miss cycles 7679490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 13447969000 # number of ReadReq miss cycles 7689490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 291000 # number of UpgradeReq miss cycles 7699490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles 7709490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7693925000 # number of ReadExReq miss cycles 7719490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7693925000 # number of ReadExReq miss cycles 7729490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1040084000 # number of demand (read+write) miss cycles 7739490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 20101810000 # number of demand (read+write) miss cycles 7749490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 21141894000 # number of demand (read+write) miss cycles 7759490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1040084000 # number of overall miss cycles 7769490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 20101810000 # number of overall miss cycles 7779490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 21141894000 # number of overall miss cycles 7789490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1009923 # number of ReadReq accesses(hits+misses) 7799490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1100878 # number of ReadReq accesses(hits+misses) 7809490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2110801 # number of ReadReq accesses(hits+misses) 7819490Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 840942 # number of Writeback accesses(hits+misses) 7829490Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 840942 # number of Writeback accesses(hits+misses) 7839490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses) 7849490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses) 7859490Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 7869490Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 7879490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 301061 # number of ReadExReq accesses(hits+misses) 7889490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 301061 # number of ReadExReq accesses(hits+misses) 7899490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1009923 # number of demand (read+write) accesses 7909490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1401939 # number of demand (read+write) accesses 7919490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2411862 # number of demand (read+write) accesses 7929490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1009923 # number of overall (read+write) accesses 7939490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1401939 # number of overall (read+write) accesses 7949490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2411862 # number of overall (read+write) accesses 7959490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014927 # miss rate for ReadReq accesses 7969490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248679 # miss rate for ReadReq accesses 7979490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136839 # miss rate for ReadReq accesses 7989490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.573770 # miss rate for UpgradeReq accesses 7999490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.573770 # miss rate for UpgradeReq accesses 8009490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383457 # miss rate for ReadExReq accesses 8019490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383457 # miss rate for ReadExReq accesses 8029490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014927 # miss rate for demand accesses 8039490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277622 # miss rate for demand accesses 8049490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.167623 # miss rate for demand accesses 8059490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014927 # miss rate for overall accesses 8069490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277622 # miss rate for overall accesses 8079490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.167623 # miss rate for overall accesses 8089490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68993.963516 # average ReadReq miss latency 8099490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45323.123847 # average ReadReq miss latency 8109490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 46558.541061 # average ReadReq miss latency 8119490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8314.285714 # average UpgradeReq miss latency 8129490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8314.285714 # average UpgradeReq miss latency 8139490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66646.382662 # average ReadExReq miss latency 8149490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 66646.382662 # average ReadExReq miss latency 8159490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency 8169490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency 8179490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 52294.659200 # average overall miss latency 8189490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency 8199490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency 8209490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 52294.659200 # average overall miss latency 8219285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8229285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8239285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8249285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8259285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8269285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8279285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8289285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8299459Ssaidi@eecs.umich.edusystem.cpu.l2cache.writebacks::writebacks 75932 # number of writebacks 8309459Ssaidi@eecs.umich.edusystem.cpu.l2cache.writebacks::total 75932 # number of writebacks 8319285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 8329285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 8339285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 8349285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 8359285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 8369285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 8379490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15074 # number of ReadReq MSHR misses 8389490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273765 # number of ReadReq MSHR misses 8399490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288839 # number of ReadReq MSHR misses 8409490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses 8419490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses 8429490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115444 # number of ReadExReq MSHR misses 8439490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115444 # number of ReadExReq MSHR misses 8449490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15074 # number of demand (read+write) MSHR misses 8459490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389209 # number of demand (read+write) MSHR misses 8469490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404283 # number of demand (read+write) MSHR misses 8479490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15074 # number of overall MSHR misses 8489490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389209 # number of overall MSHR misses 8499490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404283 # number of overall MSHR misses 8509490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 852119347 # number of ReadReq MSHR miss cycles 8519490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058627177 # number of ReadReq MSHR miss cycles 8529490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 9910746524 # number of ReadReq MSHR miss cycles 8539490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 507531 # number of UpgradeReq MSHR miss cycles 8549490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 507531 # number of UpgradeReq MSHR miss cycles 8559490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6283747927 # number of ReadExReq MSHR miss cycles 8569490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6283747927 # number of ReadExReq MSHR miss cycles 8579490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 852119347 # number of demand (read+write) MSHR miss cycles 8589490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15342375104 # number of demand (read+write) MSHR miss cycles 8599490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16194494451 # number of demand (read+write) MSHR miss cycles 8609490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 852119347 # number of overall MSHR miss cycles 8619490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15342375104 # number of overall MSHR miss cycles 8629490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16194494451 # number of overall MSHR miss cycles 8639490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333816000 # number of ReadReq MSHR uncacheable cycles 8649490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333816000 # number of ReadReq MSHR uncacheable cycles 8659490Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882705000 # number of WriteReq MSHR uncacheable cycles 8669490Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882705000 # number of WriteReq MSHR uncacheable cycles 8679490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216521000 # number of overall MSHR uncacheable cycles 8689490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216521000 # number of overall MSHR uncacheable cycles 8699490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for ReadReq accesses 8709490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses 8719490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136839 # mshr miss rate for ReadReq accesses 8729490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.573770 # mshr miss rate for UpgradeReq accesses 8739490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.573770 # mshr miss rate for UpgradeReq accesses 8749490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383457 # mshr miss rate for ReadExReq accesses 8759490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383457 # mshr miss rate for ReadExReq accesses 8769490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for demand accesses 8779490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses 8789490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.167623 # mshr miss rate for demand accesses 8799490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for overall accesses 8809490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses 8819490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.167623 # mshr miss rate for overall accesses 8829490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56529.079674 # average ReadReq mshr miss latency 8839490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.062433 # average ReadReq mshr miss latency 8849490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34312.355755 # average ReadReq mshr miss latency 8859490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14500.885714 # average UpgradeReq mshr miss latency 8869490Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14500.885714 # average UpgradeReq mshr miss latency 8879490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54431.134810 # average ReadExReq mshr miss latency 8889490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54431.134810 # average ReadExReq mshr miss latency 8899490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency 8909490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency 8919490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency 8929490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency 8939490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency 8949490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency 8959285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 8969285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 8979285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 8989285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 8999285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 9009285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 9019285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 9029490Sandreas.hansson@arm.comsystem.cpu.dcache.replacements 1401345 # number of replacements 9039490Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use 9049490Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 11814052 # Total number of references to valid blocks. 9059490Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 1401857 # Sample count of references to valid blocks. 9069490Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 8.427430 # Average number of references to valid blocks. 9079490Sandreas.hansson@arm.comsystem.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. 9089490Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor 9099348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 9109348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 9119490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7207582 # number of ReadReq hits 9129490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7207582 # number of ReadReq hits 9139490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4204734 # number of WriteReq hits 9149490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4204734 # number of WriteReq hits 9159490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 185999 # number of LoadLockedReq hits 9169490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 185999 # number of LoadLockedReq hits 9179490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits 9189490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits 9199490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11412316 # number of demand (read+write) hits 9209490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11412316 # number of demand (read+write) hits 9219490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11412316 # number of overall hits 9229490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11412316 # number of overall hits 9239490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1803400 # number of ReadReq misses 9249490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1803400 # number of ReadReq misses 9259490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1942918 # number of WriteReq misses 9269490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1942918 # number of WriteReq misses 9279490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses 9289490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses 9299490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 9309490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 9319490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3746318 # number of demand (read+write) misses 9329490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3746318 # number of demand (read+write) misses 9339490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3746318 # number of overall misses 9349490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3746318 # number of overall misses 9359490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 34352879000 # number of ReadReq miss cycles 9369490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 34352879000 # number of ReadReq miss cycles 9379490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 65301849857 # number of WriteReq miss cycles 9389490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 65301849857 # number of WriteReq miss cycles 9399490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 305868500 # number of LoadLockedReq miss cycles 9409490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 305868500 # number of LoadLockedReq miss cycles 9419490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 9429490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 9439490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 99654728857 # number of demand (read+write) miss cycles 9449490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 99654728857 # number of demand (read+write) miss cycles 9459490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 99654728857 # number of overall miss cycles 9469490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 99654728857 # number of overall miss cycles 9479490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9010982 # number of ReadReq accesses(hits+misses) 9489490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9010982 # number of ReadReq accesses(hits+misses) 9499490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147652 # number of WriteReq accesses(hits+misses) 9509490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147652 # number of WriteReq accesses(hits+misses) 9519490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 208748 # number of LoadLockedReq accesses(hits+misses) 9529490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 208748 # number of LoadLockedReq accesses(hits+misses) 9539490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) 9549490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) 9559490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15158634 # number of demand (read+write) accesses 9569490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15158634 # number of demand (read+write) accesses 9579490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15158634 # number of overall (read+write) accesses 9589490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15158634 # number of overall (read+write) accesses 9599490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200134 # miss rate for ReadReq accesses 9609490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.200134 # miss rate for ReadReq accesses 9619490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses 9629490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses 9639490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses 9649490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses 9659490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 9669490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 9679490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses 9689490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses 9699490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses 9709490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses 9719490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency 9729490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency 9739490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency 9749490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency 9759490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency 9769490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency 9779348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 9789348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 9799490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency 9809490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency 9819490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency 9829490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency 9839490Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked 9849490Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked 9859490Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked 9869459Ssaidi@eecs.umich.edusystem.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 9879490Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked 9889490Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked 9899348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 9909348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 9919490Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 840942 # number of writebacks 9929490Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 840942 # number of writebacks 9939490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits 9949490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits 9959490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits 9969490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits 9979490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits 9989490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits 9999490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits 10009490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits 10019490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits 10029490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits 10039490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses 10049490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses 10059490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses 10069490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses 10079490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses 10089490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses 10099490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 10109490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 10119490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses 10129490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses 10139490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses 10149490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses 10159490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles 10169490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles 10179490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles 10189490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles 10199490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles 10209490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles 10219490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 10229490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 10239490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles 10249490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles 10259490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles 10269490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles 10279490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles 10289490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles 10299490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles 10309490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles 10319490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles 10329490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles 10339490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses 10349490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses 10359490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses 10369490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses 10379490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses 10389490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses 10399490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 10409490Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 10419490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses 10429490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses 10439490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses 10449490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses 10459490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency 10469490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency 10479490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency 10489490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency 10499490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency 10509490Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency 10519348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 10529348SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 10539490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency 10549490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency 10559490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency 10569490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency 10579348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 10589348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 10599348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 10609348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 10619348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 10629348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 10639348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10645703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 10659490Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 10669490Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed 10679490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl 10689285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 10699490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 10709490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl 10719490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl 10729490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl 10739285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 10749490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 10759490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl 10769490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl 10779490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl 10789490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl 10799490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl 10809490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl 10819490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl 10829490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl 10836127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 10846127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 10859490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl 10869490Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl 10876291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 10886291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 10896291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 10906291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 10916291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 10926291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 10936291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 10946291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 10956291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 10966291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 10976291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 10986291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 10996291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 11006291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 11016291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 11026291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 11036291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 11046291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 11056291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 11066291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 11076291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 11086291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 11096291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 11106291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 11116291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 11126291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 11136291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 11146291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 11156291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 11166291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 11176127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 11188464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 11198464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 11208464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 11218464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 11229285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 11239285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 11249199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 11259490Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed 11269490Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 11279285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 11289199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 11299285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 11309285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 11319490Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 11328464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 11338464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 11349490Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191983 # number of callpals executed 11359490Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches 11369490Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1738 # number of protection mode switches 11379348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 11389490Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1908 11399490Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1738 11408517SN/Asystem.cpu.kern.mode_good::idle 170 11419490Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches 11428464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 11439348SAli.Saidi@ARM.comsystem.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 11449490Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches 11459490Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode 11469490Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode 11479490Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode 11488517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 11495703SN/A 11505703SN/A---------- End Simulation Statistics ---------- 1151