xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.854344                       # Number of seconds simulated
sim_ticks                                1854344296500                       # Number of ticks simulated
final_tick                               1854344296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 131278                       # Simulator instruction rate (inst/s)
host_op_rate                                   131278                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4595190559                       # Simulator tick rate (ticks/s)
host_mem_usage                                 336376                       # Number of bytes of host memory used
host_seconds                                   403.54                       # Real time elapsed on the host
sim_insts                                    52976017                       # Number of instructions simulated
sim_ops                                      52976017                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            964864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24879424                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28496576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       964864                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          964864                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7516416                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7516416                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15076                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388741                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445259                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117444                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117444                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               520326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13416831                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1430310                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15367468                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          520326                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             520326                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4053409                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4053409                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4053409                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              520326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13416831                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1430310                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19420877                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445259                       # Total number of read requests seen
system.physmem.writeReqs                       117444                       # Total number of write requests seen
system.physmem.cpureqs                         564803                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     28496576                       # Total number of bytes read from memory
system.physmem.bytesWritten                   7516416                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               28496576                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7516416                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       63                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                176                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 28168                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 27749                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 27864                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 27384                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 28323                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 28119                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 27841                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 27693                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 27856                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 27503                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                27630                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                27839                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                27855                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                27734                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                27743                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                27895                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7646                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7409                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7290                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  6889                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7790                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7556                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7291                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  7179                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7418                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7047                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7168                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 7402                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7478                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7343                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7210                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7328                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                        1365                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1854338900000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  445259                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 118809                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                  176                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    331910                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     65137                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     18515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6392                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2870                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2399                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1760                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2006                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1645                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1906                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1586                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1660                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1745                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1229                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1437                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      898                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      159                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3944                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4990                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     6228802493                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               13434068493                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1780784000                       # Total cycles spent in databus access
system.physmem.totBankLat                  5424482000                       # Total cycles spent in bank access
system.physmem.avgQLat                       13991.15                       # Average queueing delay per request
system.physmem.avgBankLat                    12184.48                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  30175.63                       # Average memory access latency
system.physmem.avgRdBW                          15.37                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           4.05                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  15.37                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   4.05                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
system.physmem.avgWrQLen                        11.37                       # Average write queue length over time
system.physmem.readRowHits                     425317                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     76610                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   95.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  65.23                       # Row buffer hit rate for writes
system.physmem.avgGap                      3295413.21                       # Average gap between requests
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.265367                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1704469917000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.265367                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.079085                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.079085                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20927998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20927998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   9519862806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   9519862806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   9540790804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   9540790804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   9540790804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   9540790804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229107.210387                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229107.210387                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 228658.856896                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 228658.856896                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 228658.856896                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 228658.856896                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        189620                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                22696                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.354776                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11931000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11931000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   7357096000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7357096000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   7369027000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7369027000                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   7369027000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7369027000                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177057.566423                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 177057.566423                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176609.394847                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176609.394847                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176609.394847                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176609.394847                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9948747                       # DTB read hits
system.cpu.dtb.read_misses                      41658                       # DTB read misses
system.cpu.dtb.read_acv                           544                       # DTB read access violations
system.cpu.dtb.read_accesses                   942034                       # DTB read accesses
system.cpu.dtb.write_hits                     6596243                       # DTB write hits
system.cpu.dtb.write_misses                     10259                       # DTB write misses
system.cpu.dtb.write_acv                          405                       # DTB write access violations
system.cpu.dtb.write_accesses                  337916                       # DTB write accesses
system.cpu.dtb.data_hits                     16544990                       # DTB hits
system.cpu.dtb.data_misses                      51917                       # DTB misses
system.cpu.dtb.data_acv                           949                       # DTB access violations
system.cpu.dtb.data_accesses                  1279950                       # DTB accesses
system.cpu.itb.fetch_hits                     1308175                       # ITB hits
system.cpu.itb.fetch_misses                     37074                       # ITB misses
system.cpu.itb.fetch_acv                         1064                       # ITB acv
system.cpu.itb.fetch_accesses                 1345249                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        108725026                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 13851594                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11614390                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             401305                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups               9533712                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  5819078                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                   909714                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect               39020                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           28116472                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70876145                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13851594                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6728792                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13285208                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2019522                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               37381794                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                31979                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        254614                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       318469                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          142                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8594512                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                267109                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           80688804                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.878389                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.221787                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 67403596     83.54%     83.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   853020      1.06%     84.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1704381      2.11%     86.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   825297      1.02%     87.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2770281      3.43%     91.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   565024      0.70%     91.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   647860      0.80%     92.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1009692      1.25%     93.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4909653      6.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             80688804                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.127400                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.651884                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29267449                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37052866                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12136986                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                973710                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1257792                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               584936                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42720                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69563521                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129851                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1257792                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30404358                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                13652369                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       19747652                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11366309                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4260322                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65705710                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  6891                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 503348                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1491459                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43870153                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79781182                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79301924                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            479258                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38177024                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5693121                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1683221                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         240085                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12184382                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10464940                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6914709                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1324795                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           859458                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58224316                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2050276                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56824991                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            109552                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6935340                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3625371                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1389407                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      80688804                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.704249                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.364971                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            56018871     69.43%     69.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10823549     13.41%     82.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5172467      6.41%     89.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3386571      4.20%     93.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2641337      3.27%     96.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1466438      1.82%     98.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              753039      0.93%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              331233      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               95299      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        80688804                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   89852     11.44%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 373396     47.53%     58.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                322395     41.04%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38724808     68.15%     68.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61690      0.11%     68.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10379587     18.27%     86.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6673501     11.74%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             948876      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56824991                       # Type of FU issued
system.cpu.iq.rate                           0.522649                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      785643                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013826                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          194541335                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66886966                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55559556                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              692645                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             336736                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327839                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57241937                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  361411                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           597577                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1373561                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         3601                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14111                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       537300                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17953                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        206148                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1257792                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 9964029                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                681966                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63803743                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            689880                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10464940                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6914709                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1805552                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 511141                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 18669                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14111                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         204181                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       411284                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               615465                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56359720                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              10018596                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            465270                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3529151                       # number of nop insts executed
system.cpu.iew.exec_refs                     16640307                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8921025                       # Number of branches executed
system.cpu.iew.exec_stores                    6621711                       # Number of stores executed
system.cpu.iew.exec_rate                     0.518369                       # Inst execution rate
system.cpu.iew.wb_sent                       56002392                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55887395                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27763328                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37600496                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.514025                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.738377                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7517612                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660869                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            569940                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     79431012                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.707112                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.636757                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     58662505     73.85%     73.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8598581     10.83%     84.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4616252      5.81%     90.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2527219      3.18%     93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1515396      1.91%     95.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       608578      0.77%     96.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       519366      0.65%     97.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       531746      0.67%     97.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1851369      2.33%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     79431012                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56166586                       # Number of instructions committed
system.cpu.commit.committedOps               56166586                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15468788                       # Number of memory references committed
system.cpu.commit.loads                       9091379                       # Number of loads committed
system.cpu.commit.membars                      226331                       # Number of memory barriers committed
system.cpu.commit.branches                    8439881                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52016583                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740455                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1851369                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    141014350                       # The number of ROB reads
system.cpu.rob.rob_writes                   128628080                       # The number of ROB writes
system.cpu.timesIdled                         1177475                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        28036222                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3599957129                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52976017                       # Number of Instructions Simulated
system.cpu.committedOps                      52976017                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52976017                       # Number of Instructions Simulated
system.cpu.cpi                               2.052344                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.052344                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.487248                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.487248                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73894396                       # number of integer regfile reads
system.cpu.int_regfile_writes                40308039                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    165978                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167424                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1987130                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938828                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                1010112                       # number of replacements
system.cpu.icache.tagsinuse                510.299453                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7527432                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1010620                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.448331                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            20108875000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.299453                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996679                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996679                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7527433                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7527433                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7527433                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7527433                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7527433                       # number of overall hits
system.cpu.icache.overall_hits::total         7527433                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1067079                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1067079                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1067079                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1067079                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1067079                       # number of overall misses
system.cpu.icache.overall_misses::total       1067079                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14519095993                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14519095993                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14519095993                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14519095993                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14519095993                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14519095993                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8594512                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8594512                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8594512                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8594512                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8594512                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8594512                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124158                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124158                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124158                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124158                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124158                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124158                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.392772                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13606.392772                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.392772                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13606.392772                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.392772                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13606.392772                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4279                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               166                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    25.777108                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56239                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        56239                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        56239                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        56239                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        56239                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        56239                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1010840                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1010840                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1010840                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1010840                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1010840                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1010840                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11925850497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11925850497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11925850497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11925850497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11925850497                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11925850497                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.117615                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.117615                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.117615                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.117615                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.117615                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.117615                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11797.960604                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11797.960604                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11797.960604                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11797.960604                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11797.960604                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11797.960604                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                338316                       # number of replacements
system.cpu.l2cache.tagsinuse             65366.388920                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 2545796                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                403484                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.309534                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle            4043215002                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 54012.841717                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   5326.780623                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6026.766580                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.824171                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.081280                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.091961                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997412                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       995646                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       826421                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1822067                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840422                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840422                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           24                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           24                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185485                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185485                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       995646                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1011906                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2007552                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       995646                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1011906                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2007552                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15078                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273811                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288889                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           39                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           39                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115423                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115423                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15078                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389234                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404312                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15078                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389234                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404312                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    915536500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11794969500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  12710506000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       273500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       273500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8550291000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8550291000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    915536500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  20345260500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  21260797000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    915536500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  20345260500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  21260797000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1010724                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100232                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2110956                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840422                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840422                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           63                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           63                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       300908                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       300908                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1010724                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1401140                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2411864                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1010724                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1401140                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2411864                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014918                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248867                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136852                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.619048                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.619048                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383582                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383582                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014918                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277798                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167635                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014918                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277798                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167635                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60720.022549                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43077.047672                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 43997.888462                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7012.820513                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7012.820513                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74077.878759                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74077.878759                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60720.022549                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52269.998253                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52585.124854                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60720.022549                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52269.998253                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52585.124854                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75932                       # number of writebacks
system.cpu.l2cache.writebacks::total            75932                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15077                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273811                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288888                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           39                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           39                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115423                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115423                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15077                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389234                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404311                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15077                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389234                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404311                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    725191735                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   8251461653                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   8976653388                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       555033                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       555033                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7120922957                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7120922957                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    725191735                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15372384610                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  16097576345                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    725191735                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15372384610                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  16097576345                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333795500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333795500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882091500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882091500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3215887000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3215887000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014917                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248867                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136852                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.619048                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383582                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383582                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014917                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277798                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167634                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014917                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277798                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167634                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48099.206407                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30135.610523                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31073.126568                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14231.615385                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14231.615385                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61694.142043                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61694.142043                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48099.206407                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39493.940946                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39814.836463                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48099.206407                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39493.940946                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39814.836463                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1400546                       # number of replacements
system.cpu.dcache.tagsinuse                511.995190                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 11813976                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1401058                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   8.432182                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21532000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.995190                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7207955                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7207955                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4204220                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4204220                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186078                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186078                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215492                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215492                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11412175                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11412175                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11412175                       # number of overall hits
system.cpu.dcache.overall_hits::total        11412175                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1800587                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1800587                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1942997                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1942997                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22666                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22666                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3743584                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3743584                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3743584                       # number of overall misses
system.cpu.dcache.overall_misses::total       3743584                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33818200500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33818200500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  70794455130                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  70794455130                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    303687500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    303687500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        26000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 104612655630                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 104612655630                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 104612655630                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 104612655630                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9008542                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9008542                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6147217                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6147217                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208744                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       208744                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215494                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215494                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15155759                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15155759                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15155759                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15155759                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199876                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.199876                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316078                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316078                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108583                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108583                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247007                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247007                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247007                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247007                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18781.764225                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18781.764225                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36435.699659                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36435.699659                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13398.372011                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13398.372011                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 27944.519378                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 27944.519378                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27944.519378                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27944.519378                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      2603227                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          567                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             95613                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    27.226706                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           81                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840422                       # number of writebacks
system.cpu.dcache.writebacks::total            840422                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       717194                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       717194                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1642682                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1642682                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5172                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5172                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2359876                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2359876                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2359876                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2359876                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083393                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1083393                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300315                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300315                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17494                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17494                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1383708                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1383708                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1383708                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1383708                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21171794000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  21171794000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10766258774                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10766258774                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    199318000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    199318000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31938052774                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  31938052774                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31938052774                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31938052774                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423872500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423872500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997246998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997246998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421119498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421119498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120263                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120263                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048854                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048854                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083806                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083806                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091299                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091299                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091299                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091299                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19542.118142                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19542.118142                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35849.886865                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35849.886865                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11393.506345                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11393.506345                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23081.497523                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23081.497523                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23081.497523                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23081.497523                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     210969                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74649     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1878      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105543     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182201                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73282     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1878      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73282     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148573                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1818511438500     98.07%     98.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                63990000      0.00%     98.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               557700000      0.03%     98.10% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             35210339500      1.90%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1854343468000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981688                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694333                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815435                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175088     91.22%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6783      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5103      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191930                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5848                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1911                      
system.cpu.kern.mode_good::user                  1741                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326778                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394590                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29685190500      1.60%      1.60% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2663206500      0.14%      1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1821995063000     98.26%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------