xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.864443                       # Number of seconds simulated
sim_ticks                                1864443445500                       # Number of ticks simulated
final_tick                               1864443445500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 198323                       # Simulator instruction rate (inst/s)
host_op_rate                                   198323                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6987525181                       # Simulator tick rate (ticks/s)
host_mem_usage                                 299164                       # Number of bytes of host memory used
host_seconds                                   266.82                       # Real time elapsed on the host
sim_insts                                    52917560                       # Number of instructions simulated
sim_ops                                      52917560                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            968960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24880000                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28501248                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       968960                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          968960                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7519232                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7519232                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15140                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388750                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445332                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117488                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117488                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               519705                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13344465                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1422563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15286732                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          519705                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             519705                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4032963                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4032963                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4032963                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              519705                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13344465                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1422563                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19319696                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        338394                       # number of replacements
system.l2c.tagsinuse                     65347.941058                       # Cycle average of tags in use
system.l2c.total_refs                         2558628                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        403561                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.340127                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    4870004000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53835.098828                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           5353.738970                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           6159.103260                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.821458                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.081692                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.093980                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.997130                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.inst             1006554                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              827784                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1834338                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          840935                       # number of Writeback hits
system.l2c.Writeback_hits::total               840935                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               31                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu.data              3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            185458                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               185458                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.inst              1006554                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data              1013242                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2019796                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.inst             1006554                       # number of overall hits
system.l2c.overall_hits::cpu.data             1013242                       # number of overall hits
system.l2c.overall_hits::total                2019796                       # number of overall hits
system.l2c.ReadReq_misses::cpu.inst             15142                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data            273892                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289034                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data             50                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total                50                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          115356                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             115356                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.inst              15142                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             389248                       # number of demand (read+write) misses
system.l2c.demand_misses::total                404390                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.inst             15142                       # number of overall misses
system.l2c.overall_misses::cpu.data            389248                       # number of overall misses
system.l2c.overall_misses::total               404390                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.inst    806626498                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data  14262568500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15069194998                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data       506000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       506000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   6193261496                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6193261496                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.inst    806626498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data  20455829996                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21262456494                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.inst    806626498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data  20455829996                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21262456494                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.inst         1021696                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data         1101676                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2123372                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       840935                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           840935                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data           81                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total              81                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        300814                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           300814                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.inst          1021696                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data          1402490                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2424186                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.inst         1021696                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data         1402490                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2424186                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.014820                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.248614                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.136120                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.617284                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.617284                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.383479                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.383479                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.inst        0.014820                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.277541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.166815                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.inst       0.014820                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.277541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.166815                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53270.802932                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52073.695106                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52136.409550                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data        10120                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total        10120                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 53688.247651                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53688.247651                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 53270.802932                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52552.177522                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52579.085769                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 53270.802932                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52552.177522                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52579.085769                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               75976                       # number of writebacks
system.l2c.writebacks::total                    75976                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.inst        15141                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data       273892                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289033                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data           50                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total           50                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       115356                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        115356                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         15141                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        389248                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           404389                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        15141                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       389248                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          404389                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    621548498                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data  10984970000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11606518498                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2110000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      2110000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4799591496                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4799591496                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    621548498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data  15784561496                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16406109994                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    621548498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data  15784561496                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16406109994                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data   1332350000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1332350000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1882980500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1882980500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data   3215330500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3215330500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014819                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248614                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.136120                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.617284                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.617284                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383479                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.383479                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.014819                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.277541                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.166814                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.014819                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.277541                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.166814                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41050.690047                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.939962                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40156.378331                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data        42200                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total        42200                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41606.778113                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41606.778113                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41050.690047                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40551.426073                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40570.119350                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41050.690047                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40551.426073                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40570.119350                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41685                       # number of replacements
system.iocache.tagsinuse                     1.286638                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1711308746000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       1.286638                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.080415                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.080415                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   7639193806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   7639193806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   7659866804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   7659866804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   7659866804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   7659866804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183846.597179                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 183846.597179                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 183579.791588                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183579.791588                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 183579.791588                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183579.791588                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs       7379000                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7110                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  1037.834037                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5478339000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   5478339000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   5490015000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   5490015000                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   5490015000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   5490015000                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131842.967848                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 131842.967848                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131576.153385                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131576.153385                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131576.153385                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131576.153385                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9936242                       # DTB read hits
system.cpu.dtb.read_misses                      43490                       # DTB read misses
system.cpu.dtb.read_acv                           516                       # DTB read access violations
system.cpu.dtb.read_accesses                   957786                       # DTB read accesses
system.cpu.dtb.write_hits                     6625146                       # DTB write hits
system.cpu.dtb.write_misses                     10048                       # DTB write misses
system.cpu.dtb.write_acv                          376                       # DTB write access violations
system.cpu.dtb.write_accesses                  340602                       # DTB write accesses
system.cpu.dtb.data_hits                     16561388                       # DTB hits
system.cpu.dtb.data_misses                      53538                       # DTB misses
system.cpu.dtb.data_acv                           892                       # DTB access violations
system.cpu.dtb.data_accesses                  1298388                       # DTB accesses
system.cpu.itb.fetch_hits                     1339050                       # ITB hits
system.cpu.itb.fetch_misses                     40176                       # ITB misses
system.cpu.itb.fetch_acv                         1137                       # ITB acv
system.cpu.itb.fetch_accesses                 1379226                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        124718167                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 14016362                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           11699457                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect             447467                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              10098689                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                  5905629                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                   935083                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect               44772                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           31431497                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       71249565                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14016362                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6840712                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13427140                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2133623                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               43145521                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                33490                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        277896                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       300852                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          229                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8810652                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                301668                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           90022350                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.791465                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.121682                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 76595210     85.08%     85.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   880275      0.98%     86.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1754034      1.95%     88.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   853758      0.95%     88.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2767447      3.07%     92.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   598798      0.67%     92.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   668363      0.74%     93.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1009728      1.12%     94.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4894737      5.44%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             90022350                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.112384                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.571285                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32462663                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              42944944                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12200929                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1050932                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1362881                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               612569                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 43257                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69997551                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                131864                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1362881                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33604793                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                17288612                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       21444377                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11497846                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4823839                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               66302391                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  7264                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 752324                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1793006                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            44298032                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              80385832                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79896368                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            489464                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38124388                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  6173636                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1698063                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         251025                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12720780                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10525150                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6958577                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1307223                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           920725                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58755274                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2090184                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  57106230                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            126003                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7528195                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3871424                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1424917                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      90022350                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.634356                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.284426                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            64211383     71.33%     71.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            11984837     13.31%     84.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5359973      5.95%     90.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3439210      3.82%     94.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2607784      2.90%     97.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1324300      1.47%     98.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              687470      0.76%     99.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              352783      0.39%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               54610      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        90022350                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   75162      9.94%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 361865     47.84%     57.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                319378     42.22%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7291      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38979239     68.26%     68.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61855      0.11%     68.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10375615     18.17%     86.60% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6703515     11.74%     98.34% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949472      1.66%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               57106230                       # Type of FU issued
system.cpu.iq.rate                           0.457882                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      756405                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013246                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          204420366                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          68047675                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55829438                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              696851                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             339603                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327742                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57490896                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  364448                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           598206                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1442254                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2799                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13958                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       583775                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17984                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        104066                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1362881                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                12351222                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                868923                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            64407898                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            684720                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10525150                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6958577                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1840963                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 621108                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12330                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13958                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         238471                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       421447                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               659918                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56579740                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              10008035                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            526489                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3562440                       # number of nop insts executed
system.cpu.iew.exec_refs                     16658473                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8978804                       # Number of branches executed
system.cpu.iew.exec_stores                    6650438                       # Number of stores executed
system.cpu.iew.exec_rate                     0.453661                       # Inst execution rate
system.cpu.iew.wb_sent                       56268334                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      56157180                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27683314                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37519561                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.450273                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.737837                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts       56104643                       # The number of committed instructions
system.cpu.commit.commitCommittedOps         56104643                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts         8193317                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          665267                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            615735                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     88659469                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.632811                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.547834                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     67465140     76.09%     76.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8924230     10.07%     86.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4814714      5.43%     91.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2600553      2.93%     94.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1445109      1.63%     96.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       596766      0.67%     96.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       516883      0.58%     97.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       484830      0.55%     97.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1811244      2.04%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     88659469                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56104643                       # Number of instructions committed
system.cpu.commit.committedOps               56104643                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15457698                       # Number of memory references committed
system.cpu.commit.loads                       9082896                       # Number of loads committed
system.cpu.commit.membars                      226441                       # Number of memory barriers committed
system.cpu.commit.branches                    8439531                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  51953528                       # Number of committed integer instructions.
system.cpu.commit.function_calls               739583                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1811244                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    150896568                       # The number of ROB reads
system.cpu.rob.rob_writes                   129959625                       # The number of ROB writes
system.cpu.timesIdled                         1384663                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        34695817                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3604162300                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52917560                       # Number of Instructions Simulated
system.cpu.committedOps                      52917560                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52917560                       # Number of Instructions Simulated
system.cpu.cpi                               2.356839                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.356839                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.424297                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.424297                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 74164887                       # number of integer regfile reads
system.cpu.int_regfile_writes                40500361                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166351                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   166958                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 1995249                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 947406                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.icache.replacements                1021086                       # number of replacements
system.cpu.icache.tagsinuse                509.954176                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7728678                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1021597                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.565290                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            23896761000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     509.954176                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996004                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996004                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7728679                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7728679                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7728679                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7728679                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7728679                       # number of overall hits
system.cpu.icache.overall_hits::total         7728679                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1081971                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1081971                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1081971                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1081971                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1081971                       # number of overall misses
system.cpu.icache.overall_misses::total       1081971                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  17450602485                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  17450602485                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  17450602485                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  17450602485                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  17450602485                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  17450602485                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8810650                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8810650                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8810650                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8810650                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8810650                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8810650                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122803                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.122803                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.122803                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.122803                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.122803                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.122803                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16128.530695                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16128.530695                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16128.530695                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16128.530695                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16128.530695                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16128.530695                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      1774492                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               205                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  8656.058537                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60133                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        60133                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        60133                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        60133                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        60133                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        60133                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1021838                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1021838                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1021838                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1021838                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1021838                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1021838                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13459032492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13459032492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13459032492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13459032492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13459032492                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13459032492                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115978                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115978                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115978                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.115978                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115978                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.115978                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13171.395556                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13171.395556                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13171.395556                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13171.395556                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13171.395556                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13171.395556                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1401888                       # number of replacements
system.cpu.dcache.tagsinuse                511.994858                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 11830963                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1402400                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   8.436226                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               23765000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.994858                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data      7247947                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7247947                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4173007                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4173007                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       190139                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       190139                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       219622                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       219622                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11420954                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11420954                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11420954                       # number of overall hits
system.cpu.dcache.overall_hits::total        11420954                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1826719                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1826719                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1967450                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1967450                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        23276                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        23276                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3794169                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3794169                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3794169                       # number of overall misses
system.cpu.dcache.overall_misses::total       3794169                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  48828356500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  48828356500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  75021141961                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  75021141961                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    428009500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    428009500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       154000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       154000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 123849498461                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 123849498461                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 123849498461                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 123849498461                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9074666                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9074666                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6140457                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6140457                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       213415                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       213415                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       219627                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       219627                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15215123                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15215123                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15215123                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15215123                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.201299                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.201299                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.320408                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.320408                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109064                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109064                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000023                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000023                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.249368                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.249368                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.249368                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.249368                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26730.086291                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26730.086291                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38131.155537                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38131.155537                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18388.447328                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18388.447328                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        30800                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        30800                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.061664                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32642.061664                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.061664                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32642.061664                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs    733938028                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             72096                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10180.010375                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840935                       # number of writebacks
system.cpu.dcache.writebacks::total            840935                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       742319                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       742319                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667295                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1667295                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5261                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5261                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2409614                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2409614                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2409614                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2409614                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084400                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1084400                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300155                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300155                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18015                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        18015                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1384555                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1384555                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1384555                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1384555                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28231864000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  28231864000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9653593940                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9653593940                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    269637000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    269637000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       138000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       138000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37885457940                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  37885457940                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37885457940                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  37885457940                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423534500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423534500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2001030998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2001030998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3424565498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3424565498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119498                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119498                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048882                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048882                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084413                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084413                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090999                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.090999                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090999                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.090999                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26034.548137                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26034.548137                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32162.029418                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32162.029418                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14967.360533                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14967.360533                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        27600                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        27600                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27362.912950                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27362.912950                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27362.912950                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27362.912950                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6425                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211112                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74681     40.96%     40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     133      0.07%     41.03% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1886      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105636     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182336                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73314     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1886      1.27%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73315     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148648                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1823792488500     97.82%     97.82% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                71545000      0.00%     97.82% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               571672500      0.03%     97.85% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             40006830500      2.15%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1864442536500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981695                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694034                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815242                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.17%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175205     91.22%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6791      3.54%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5112      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 192064                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5850                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1735                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2104                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1905                      
system.cpu.kern.mode_good::user                  1735                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.325641                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.080798                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.393229                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29922134000      1.60%      1.60% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2785239500      0.15%      1.75% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1831735155000     98.25%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------