stats.txt revision 8825
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 38825Snilay@cs.wisc.edusim_seconds 1.859851 # Number of seconds simulated 48825Snilay@cs.wisc.edusim_ticks 1859850554500 # Number of ticks simulated 58825Snilay@cs.wisc.edufinal_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 78825Snilay@cs.wisc.eduhost_inst_rate 100457 # Simulator instruction rate (inst/s) 88825Snilay@cs.wisc.eduhost_tick_rate 3519496587 # Simulator tick rate (ticks/s) 98825Snilay@cs.wisc.eduhost_mem_usage 323652 # Number of bytes of host memory used 108825Snilay@cs.wisc.eduhost_seconds 528.44 # Real time elapsed on the host 118825Snilay@cs.wisc.edusim_insts 53085804 # Number of instructions simulated 128825Snilay@cs.wisc.edusystem.physmem.bytes_read 29820864 # Number of bytes read from this memory 138825Snilay@cs.wisc.edusystem.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory 148825Snilay@cs.wisc.edusystem.physmem.bytes_written 10193536 # Number of bytes written to this memory 158825Snilay@cs.wisc.edusystem.physmem.num_reads 465951 # Number of read requests responded to by this memory 168825Snilay@cs.wisc.edusystem.physmem.num_writes 159274 # Number of write requests responded to by this memory 178721SN/Asystem.physmem.num_other 0 # Number of other requests responded to by this memory 188825Snilay@cs.wisc.edusystem.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s) 198825Snilay@cs.wisc.edusystem.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s) 208825Snilay@cs.wisc.edusystem.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s) 218825Snilay@cs.wisc.edusystem.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s) 228825Snilay@cs.wisc.edusystem.l2c.replacements 391353 # number of replacements 238825Snilay@cs.wisc.edusystem.l2c.tagsinuse 34925.820021 # Cycle average of tags in use 248825Snilay@cs.wisc.edusystem.l2c.total_refs 2406767 # Total number of references to valid blocks. 258825Snilay@cs.wisc.edusystem.l2c.sampled_refs 424249 # Sample count of references to valid blocks. 268825Snilay@cs.wisc.edusystem.l2c.avg_refs 5.673006 # Average number of references to valid blocks. 278546SN/Asystem.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. 288825Snilay@cs.wisc.edusystem.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context 298825Snilay@cs.wisc.edusystem.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context 308825Snilay@cs.wisc.edusystem.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy 318825Snilay@cs.wisc.edusystem.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy 328825Snilay@cs.wisc.edusystem.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits 338825Snilay@cs.wisc.edusystem.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits 348825Snilay@cs.wisc.edusystem.l2c.Writeback_hits::0 835189 # number of Writeback hits 358825Snilay@cs.wisc.edusystem.l2c.Writeback_hits::total 835189 # number of Writeback hits 368521SN/Asystem.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits 378521SN/Asystem.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits 388464SN/Asystem.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits 398464SN/Asystem.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 408825Snilay@cs.wisc.edusystem.l2c.ReadExReq_hits::0 183241 # number of ReadExReq hits 418825Snilay@cs.wisc.edusystem.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits 428825Snilay@cs.wisc.edusystem.l2c.demand_hits::0 1984005 # number of demand (read+write) hits 438464SN/Asystem.l2c.demand_hits::1 0 # number of demand (read+write) hits 448825Snilay@cs.wisc.edusystem.l2c.demand_hits::total 1984005 # number of demand (read+write) hits 458825Snilay@cs.wisc.edusystem.l2c.overall_hits::0 1984005 # number of overall hits 468464SN/Asystem.l2c.overall_hits::1 0 # number of overall hits 478825Snilay@cs.wisc.edusystem.l2c.overall_hits::total 1984005 # number of overall hits 488825Snilay@cs.wisc.edusystem.l2c.ReadReq_misses::0 308137 # number of ReadReq misses 498825Snilay@cs.wisc.edusystem.l2c.ReadReq_misses::total 308137 # number of ReadReq misses 508825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_misses::0 35 # number of UpgradeReq misses 518825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses 528825Snilay@cs.wisc.edusystem.l2c.ReadExReq_misses::0 116889 # number of ReadExReq misses 538825Snilay@cs.wisc.edusystem.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses 548825Snilay@cs.wisc.edusystem.l2c.demand_misses::0 425026 # number of demand (read+write) misses 558464SN/Asystem.l2c.demand_misses::1 0 # number of demand (read+write) misses 568825Snilay@cs.wisc.edusystem.l2c.demand_misses::total 425026 # number of demand (read+write) misses 578825Snilay@cs.wisc.edusystem.l2c.overall_misses::0 425026 # number of overall misses 588464SN/Asystem.l2c.overall_misses::1 0 # number of overall misses 598825Snilay@cs.wisc.edusystem.l2c.overall_misses::total 425026 # number of overall misses 608825Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_latency 16037812500 # number of ReadReq miss cycles 618825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_miss_latency 424500 # number of UpgradeReq miss cycles 628825Snilay@cs.wisc.edusystem.l2c.ReadExReq_miss_latency 6132457500 # number of ReadExReq miss cycles 638825Snilay@cs.wisc.edusystem.l2c.demand_miss_latency 22170270000 # number of demand (read+write) miss cycles 648825Snilay@cs.wisc.edusystem.l2c.overall_miss_latency 22170270000 # number of overall miss cycles 658825Snilay@cs.wisc.edusystem.l2c.ReadReq_accesses::0 2108901 # number of ReadReq accesses(hits+misses) 668825Snilay@cs.wisc.edusystem.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) 678825Snilay@cs.wisc.edusystem.l2c.Writeback_accesses::0 835189 # number of Writeback accesses(hits+misses) 688825Snilay@cs.wisc.edusystem.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) 698825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_accesses::0 51 # number of UpgradeReq accesses(hits+misses) 708825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) 718464SN/Asystem.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) 728464SN/Asystem.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 738825Snilay@cs.wisc.edusystem.l2c.ReadExReq_accesses::0 300130 # number of ReadExReq accesses(hits+misses) 748825Snilay@cs.wisc.edusystem.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) 758825Snilay@cs.wisc.edusystem.l2c.demand_accesses::0 2409031 # number of demand (read+write) accesses 768464SN/Asystem.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 778825Snilay@cs.wisc.edusystem.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses 788825Snilay@cs.wisc.edusystem.l2c.overall_accesses::0 2409031 # number of overall (read+write) accesses 798464SN/Asystem.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 808825Snilay@cs.wisc.edusystem.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses 818825Snilay@cs.wisc.edusystem.l2c.ReadReq_miss_rate::0 0.146113 # miss rate for ReadReq accesses 828825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_miss_rate::0 0.686275 # miss rate for UpgradeReq accesses 838825Snilay@cs.wisc.edusystem.l2c.ReadExReq_miss_rate::0 0.389461 # miss rate for ReadExReq accesses 848825Snilay@cs.wisc.edusystem.l2c.demand_miss_rate::0 0.176430 # miss rate for demand accesses 858464SN/Asystem.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 868464SN/Asystem.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 878825Snilay@cs.wisc.edusystem.l2c.overall_miss_rate::0 0.176430 # miss rate for overall accesses 888464SN/Asystem.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 898464SN/Asystem.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 908825Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_miss_latency::0 52047.668732 # average ReadReq miss latency 918464SN/Asystem.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 928464SN/Asystem.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 938825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_avg_miss_latency::0 12128.571429 # average UpgradeReq miss latency 948464SN/Asystem.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 958464SN/Asystem.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 968825Snilay@cs.wisc.edusystem.l2c.ReadExReq_avg_miss_latency::0 52463.940148 # average ReadExReq miss latency 978464SN/Asystem.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 988464SN/Asystem.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 998825Snilay@cs.wisc.edusystem.l2c.demand_avg_miss_latency::0 52162.150080 # average overall miss latency 1008464SN/Asystem.l2c.demand_avg_miss_latency::1 inf # average overall miss latency 1018464SN/Asystem.l2c.demand_avg_miss_latency::total inf # average overall miss latency 1028825Snilay@cs.wisc.edusystem.l2c.overall_avg_miss_latency::0 52162.150080 # average overall miss latency 1038464SN/Asystem.l2c.overall_avg_miss_latency::1 inf # average overall miss latency 1048464SN/Asystem.l2c.overall_avg_miss_latency::total inf # average overall miss latency 1058464SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068464SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1078464SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1088464SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 1098464SN/Asystem.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1108464SN/Asystem.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1118464SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 1128464SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 1138825Snilay@cs.wisc.edusystem.l2c.writebacks 117762 # number of writebacks 1148464SN/Asystem.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1158464SN/Asystem.l2c.overall_mshr_hits 0 # number of overall MSHR hits 1168825Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_misses 308137 # number of ReadReq MSHR misses 1178825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses 1188825Snilay@cs.wisc.edusystem.l2c.ReadExReq_mshr_misses 116889 # number of ReadExReq MSHR misses 1198825Snilay@cs.wisc.edusystem.l2c.demand_mshr_misses 425026 # number of demand (read+write) MSHR misses 1208825Snilay@cs.wisc.edusystem.l2c.overall_mshr_misses 425026 # number of overall MSHR misses 1218464SN/Asystem.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1228825Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_miss_latency 12334071500 # number of ReadReq MSHR miss cycles 1238825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_mshr_miss_latency 1460000 # number of UpgradeReq MSHR miss cycles 1248825Snilay@cs.wisc.edusystem.l2c.ReadExReq_mshr_miss_latency 4711233500 # number of ReadExReq MSHR miss cycles 1258825Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_latency 17045305000 # number of demand (read+write) MSHR miss cycles 1268825Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_latency 17045305000 # number of overall MSHR miss cycles 1278825Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_uncacheable_latency 809589500 # number of ReadReq MSHR uncacheable cycles 1288825Snilay@cs.wisc.edusystem.l2c.WriteReq_mshr_uncacheable_latency 1114928998 # number of WriteReq MSHR uncacheable cycles 1298825Snilay@cs.wisc.edusystem.l2c.overall_mshr_uncacheable_latency 1924518498 # number of overall MSHR uncacheable cycles 1308825Snilay@cs.wisc.edusystem.l2c.ReadReq_mshr_miss_rate::0 0.146113 # mshr miss rate for ReadReq accesses 1318464SN/Asystem.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 1328464SN/Asystem.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 1338825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_mshr_miss_rate::0 0.686275 # mshr miss rate for UpgradeReq accesses 1348464SN/Asystem.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 1358464SN/Asystem.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 1368825Snilay@cs.wisc.edusystem.l2c.ReadExReq_mshr_miss_rate::0 0.389461 # mshr miss rate for ReadExReq accesses 1378464SN/Asystem.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 1388464SN/Asystem.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 1398825Snilay@cs.wisc.edusystem.l2c.demand_mshr_miss_rate::0 0.176430 # mshr miss rate for demand accesses 1408464SN/Asystem.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 1418464SN/Asystem.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 1428825Snilay@cs.wisc.edusystem.l2c.overall_mshr_miss_rate::0 0.176430 # mshr miss rate for overall accesses 1438464SN/Asystem.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 1448464SN/Asystem.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 1458825Snilay@cs.wisc.edusystem.l2c.ReadReq_avg_mshr_miss_latency 40027.882078 # average ReadReq mshr miss latency 1468825Snilay@cs.wisc.edusystem.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714 # average UpgradeReq mshr miss latency 1478825Snilay@cs.wisc.edusystem.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250 # average ReadExReq mshr miss latency 1488825Snilay@cs.wisc.edusystem.l2c.demand_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency 1498825Snilay@cs.wisc.edusystem.l2c.overall_avg_mshr_miss_latency 40104.146570 # average overall mshr miss latency 1508464SN/Asystem.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 1518464SN/Asystem.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 1528464SN/Asystem.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 1538464SN/Asystem.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 1548464SN/Asystem.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1558464SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1568464SN/Asystem.iocache.replacements 41685 # number of replacements 1578825Snilay@cs.wisc.edusystem.iocache.tagsinuse 1.276011 # Cycle average of tags in use 1588464SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 1598464SN/Asystem.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 1608464SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 1618825Snilay@cs.wisc.edusystem.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. 1628825Snilay@cs.wisc.edusystem.iocache.occ_blocks::1 1.276011 # Average occupied blocks per context 1638825Snilay@cs.wisc.edusystem.iocache.occ_percent::1 0.079751 # Average percentage of cache occupancy 1648464SN/Asystem.iocache.demand_hits::0 0 # number of demand (read+write) hits 1658464SN/Asystem.iocache.demand_hits::1 0 # number of demand (read+write) hits 1668464SN/Asystem.iocache.demand_hits::total 0 # number of demand (read+write) hits 1678464SN/Asystem.iocache.overall_hits::0 0 # number of overall hits 1688464SN/Asystem.iocache.overall_hits::1 0 # number of overall hits 1698464SN/Asystem.iocache.overall_hits::total 0 # number of overall hits 1708464SN/Asystem.iocache.ReadReq_misses::1 173 # number of ReadReq misses 1718464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1728464SN/Asystem.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 1738464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 1748464SN/Asystem.iocache.demand_misses::0 0 # number of demand (read+write) misses 1758464SN/Asystem.iocache.demand_misses::1 41725 # number of demand (read+write) misses 1768464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1778464SN/Asystem.iocache.overall_misses::0 0 # number of overall misses 1788464SN/Asystem.iocache.overall_misses::1 41725 # number of overall misses 1798464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 1808825Snilay@cs.wisc.edusystem.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles 1818825Snilay@cs.wisc.edusystem.iocache.WriteReq_miss_latency 5721891806 # number of WriteReq miss cycles 1828825Snilay@cs.wisc.edusystem.iocache.demand_miss_latency 5741829804 # number of demand (read+write) miss cycles 1838825Snilay@cs.wisc.edusystem.iocache.overall_miss_latency 5741829804 # number of overall miss cycles 1848464SN/Asystem.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) 1858464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1868464SN/Asystem.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 1878464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 1888464SN/Asystem.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 1898464SN/Asystem.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses 1908464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1918464SN/Asystem.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 1928464SN/Asystem.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses 1938464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1948464SN/Asystem.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 1958464SN/Asystem.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 1968464SN/Asystem.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 1978464SN/Asystem.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 1988464SN/Asystem.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 1998464SN/Asystem.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 2008464SN/Asystem.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 2018464SN/Asystem.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 2028464SN/Asystem.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 2038825Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency 2048464SN/Asystem.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 2058464SN/Asystem.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 2068825Snilay@cs.wisc.edusystem.iocache.WriteReq_avg_miss_latency::1 137704.365759 # average WriteReq miss latency 2078464SN/Asystem.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 2088464SN/Asystem.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 2098825Snilay@cs.wisc.edusystem.iocache.demand_avg_miss_latency::1 137611.259533 # average overall miss latency 2108464SN/Asystem.iocache.demand_avg_miss_latency::total inf # average overall miss latency 2118464SN/Asystem.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 2128825Snilay@cs.wisc.edusystem.iocache.overall_avg_miss_latency::1 137611.259533 # average overall miss latency 2138464SN/Asystem.iocache.overall_avg_miss_latency::total inf # average overall miss latency 2148825Snilay@cs.wisc.edusystem.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked 2158464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2168825Snilay@cs.wisc.edusystem.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked 2178464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2188825Snilay@cs.wisc.edusystem.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked 2198464SN/Asystem.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 2208464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2218464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2228464SN/Asystem.iocache.writebacks 41512 # number of writebacks 2238464SN/Asystem.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 2248464SN/Asystem.iocache.overall_mshr_hits 0 # number of overall MSHR hits 2258464SN/Asystem.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 2268464SN/Asystem.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 2278464SN/Asystem.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 2288464SN/Asystem.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 2298464SN/Asystem.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 2308825Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles 2318825Snilay@cs.wisc.edusystem.iocache.WriteReq_mshr_miss_latency 3561041984 # number of WriteReq MSHR miss cycles 2328825Snilay@cs.wisc.edusystem.iocache.demand_mshr_miss_latency 3571983982 # number of demand (read+write) MSHR miss cycles 2338825Snilay@cs.wisc.edusystem.iocache.overall_mshr_miss_latency 3571983982 # number of overall MSHR miss cycles 2348464SN/Asystem.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 2358464SN/Asystem.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 2368464SN/Asystem.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 2378464SN/Asystem.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 2388464SN/Asystem.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 2398464SN/Asystem.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 2408464SN/Asystem.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 2418464SN/Asystem.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 2428464SN/Asystem.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 2438464SN/Asystem.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 2448464SN/Asystem.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 2458464SN/Asystem.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 2468464SN/Asystem.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 2478825Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency 2488825Snilay@cs.wisc.edusystem.iocache.WriteReq_avg_mshr_miss_latency 85700.856373 # average WriteReq mshr miss latency 2498825Snilay@cs.wisc.edusystem.iocache.demand_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency 2508825Snilay@cs.wisc.edusystem.iocache.overall_avg_mshr_miss_latency 85607.764697 # average overall mshr miss latency 2518464SN/Asystem.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 2528464SN/Asystem.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 2538464SN/Asystem.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 2548464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2558464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2568464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2578464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2588464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2598464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2608464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2618464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2628464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2638464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2648464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2658464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2668464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2678464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2688464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2698464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2708464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 2718825Snilay@cs.wisc.edusystem.cpu.dtb.read_hits 10136178 # DTB read hits 2728825Snilay@cs.wisc.edusystem.cpu.dtb.read_misses 46729 # DTB read misses 2738825Snilay@cs.wisc.edusystem.cpu.dtb.read_acv 584 # DTB read access violations 2748825Snilay@cs.wisc.edusystem.cpu.dtb.read_accesses 970980 # DTB read accesses 2758825Snilay@cs.wisc.edusystem.cpu.dtb.write_hits 6626287 # DTB write hits 2768825Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 12218 # DTB write misses 2778825Snilay@cs.wisc.edusystem.cpu.dtb.write_acv 419 # DTB write access violations 2788825Snilay@cs.wisc.edusystem.cpu.dtb.write_accesses 347267 # DTB write accesses 2798825Snilay@cs.wisc.edusystem.cpu.dtb.data_hits 16762465 # DTB hits 2808825Snilay@cs.wisc.edusystem.cpu.dtb.data_misses 58947 # DTB misses 2818825Snilay@cs.wisc.edusystem.cpu.dtb.data_acv 1003 # DTB access violations 2828825Snilay@cs.wisc.edusystem.cpu.dtb.data_accesses 1318247 # DTB accesses 2838825Snilay@cs.wisc.edusystem.cpu.itb.fetch_hits 1326719 # ITB hits 2848825Snilay@cs.wisc.edusystem.cpu.itb.fetch_misses 39613 # ITB misses 2858825Snilay@cs.wisc.edusystem.cpu.itb.fetch_acv 1063 # ITB acv 2868825Snilay@cs.wisc.edusystem.cpu.itb.fetch_accesses 1366332 # ITB accesses 2878464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2888464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2898464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2908464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2918464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2928464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2938464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2948464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2958464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2968464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2978464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2988464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2998825Snilay@cs.wisc.edusystem.cpu.numCycles 116271514 # number of cpu cycles simulated 3008464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3018464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3028825Snilay@cs.wisc.edusystem.cpu.BPredUnit.lookups 14404381 # Number of BP lookups 3038825Snilay@cs.wisc.edusystem.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted 3048825Snilay@cs.wisc.edusystem.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect 3058825Snilay@cs.wisc.edusystem.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups 3068825Snilay@cs.wisc.edusystem.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits 3076006SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 3088825Snilay@cs.wisc.edusystem.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target. 3098825Snilay@cs.wisc.edusystem.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions. 3108825Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss 3118825Snilay@cs.wisc.edusystem.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed 3128825Snilay@cs.wisc.edusystem.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered 3138825Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken 3148825Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked 3158825Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing 3168825Snilay@cs.wisc.edusystem.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked 3178825Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 3188825Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps 3198825Snilay@cs.wisc.edusystem.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions 3208825Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR 3218825Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched 3228825Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed 3238825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total) 3248825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total) 3258825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total) 3268464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3278825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total) 3288825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total) 3298825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total) 3308825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total) 3318825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total) 3328825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total) 3338825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total) 3348825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total) 3358825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total) 3368464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3378464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3388464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3398825Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total) 3408825Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle 3418825Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle 3428825Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle 3438825Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked 3448825Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 13055396 # Number of cycles decode is running 3458825Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking 3468825Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing 3478825Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch 3488825Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction 3498825Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode 3508825Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode 3518825Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing 3528825Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle 3538825Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking 3548825Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst 3558825Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 12205401 # Number of cycles rename is running 3568825Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking 3578825Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename 3588825Snilay@cs.wisc.edusystem.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full 3598825Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full 3608825Snilay@cs.wisc.edusystem.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full 3618825Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed 3628825Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made 3638825Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups 3648825Snilay@cs.wisc.edusystem.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups 3658825Snilay@cs.wisc.edusystem.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed 3668825Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing 3678825Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed 3688825Snilay@cs.wisc.edusystem.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed 3698825Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer 3708825Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit. 3718825Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit. 3728825Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads. 3738825Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores. 3748825Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec) 3758825Snilay@cs.wisc.edusystem.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ 3768825Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued 3778825Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued 3788825Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling 3798825Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph 3808825Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed 3818825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle 3828825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle 3838825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle 3848464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3858825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle 3868825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle 3878825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle 3888825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle 3898825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle 3908825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle 3918825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle 3928825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle 3938825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle 3948464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3958464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3968464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3978825Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle 3988464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3998825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available 4008825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available 4018825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available 4028825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available 4038825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available 4048825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available 4058825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available 4068825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available 4078825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available 4088825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available 4098825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available 4108825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available 4118825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available 4128825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available 4138825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available 4148825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available 4158825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available 4168825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available 4178825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available 4188825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available 4198825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available 4208825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available 4218825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available 4228825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available 4238825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available 4248825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available 4258825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available 4268825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available 4278825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available 4288825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available 4298825Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available 4308464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4318464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4328464SN/Asystem.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued 4338825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued 4348825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued 4358825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued 4368825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued 4378825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued 4388825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued 4398825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued 4408825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued 4418825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued 4428825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued 4438825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued 4448825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued 4458825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued 4468825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued 4478825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued 4488825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued 4498825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued 4508825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued 4518825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued 4528825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued 4538825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued 4548825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued 4558825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued 4568825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued 4578825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued 4588825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued 4598825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued 4608825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued 4618825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued 4628825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued 4638825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued 4648825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued 4658464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4668825Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 57966423 # Type of FU issued 4678825Snilay@cs.wisc.edusystem.cpu.iq.rate 0.498544 # Inst issue rate 4688825Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 769465 # FU busy when requested 4698825Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst) 4708825Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads 4718825Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes 4728825Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses 4738825Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads 4748825Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes 4758825Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses 4768825Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses 4778825Snilay@cs.wisc.edusystem.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses 4788825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores 4798464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4808825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed 4818825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed 4828825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations 4838825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed 4848464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4858464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4868825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled 4878825Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked 4888464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4898825Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing 4908825Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking 4918825Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking 4928825Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ 4938825Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch 4948825Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions 4958825Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions 4968825Snilay@cs.wisc.edusystem.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions 4978825Snilay@cs.wisc.edusystem.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall 4988825Snilay@cs.wisc.edusystem.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall 4998825Snilay@cs.wisc.edusystem.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations 5008825Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly 5018825Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly 5028825Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute 5038825Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions 5048825Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed 5058825Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute 5068464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5078825Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 3625473 # number of nop insts executed 5088825Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 16867223 # number of memory reference insts executed 5098825Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 9097936 # Number of branches executed 5108825Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 6653902 # Number of stores executed 5118825Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.492563 # Inst execution rate 5128825Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit 5138825Snilay@cs.wisc.edusystem.cpu.iew.wb_count 56738020 # cumulative count of insts written-back 5148825Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 28030988 # num instructions producing a value 5158825Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 37770905 # num instructions consuming a value 5168464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 5178825Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.487979 # insts written-back per cycle 5188825Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back 5198464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 5208825Snilay@cs.wisc.edusystem.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions 5218825Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit 5228825Snilay@cs.wisc.edusystem.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards 5238825Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted 5248825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle 5258825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle 5268825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle 5278241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5288825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle 5298825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle 5308825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle 5318825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle 5328825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle 5338825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle 5348825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle 5358825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle 5368825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle 5378241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5388241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5398241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5408825Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle 5418825Snilay@cs.wisc.edusystem.cpu.commit.count 56280196 # Number of instructions committed 5428464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5438825Snilay@cs.wisc.edusystem.cpu.commit.refs 15504446 # Number of memory references committed 5448825Snilay@cs.wisc.edusystem.cpu.commit.loads 9112319 # Number of loads committed 5458825Snilay@cs.wisc.edusystem.cpu.commit.membars 227818 # Number of memory barriers committed 5468825Snilay@cs.wisc.edusystem.cpu.commit.branches 8461284 # Number of branches committed 5478517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 5488825Snilay@cs.wisc.edusystem.cpu.commit.int_insts 52119152 # Number of committed integer instructions. 5498825Snilay@cs.wisc.edusystem.cpu.commit.function_calls 744404 # Number of function calls committed. 5508825Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached 5518464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5528825Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 143937484 # The number of ROB reads 5538825Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 132136289 # The number of ROB writes 5548825Snilay@cs.wisc.edusystem.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself 5558825Snilay@cs.wisc.edusystem.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling 5568825Snilay@cs.wisc.edusystem.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 5578825Snilay@cs.wisc.edusystem.cpu.committedInsts 53085804 # Number of Instructions Simulated 5588825Snilay@cs.wisc.edusystem.cpu.committedInsts_total 53085804 # Number of Instructions Simulated 5598825Snilay@cs.wisc.edusystem.cpu.cpi 2.190256 # CPI: Cycles Per Instruction 5608825Snilay@cs.wisc.edusystem.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads 5618825Snilay@cs.wisc.edusystem.cpu.ipc 0.456568 # IPC: Instructions Per Cycle 5628825Snilay@cs.wisc.edusystem.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads 5638825Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 75080091 # number of integer regfile reads 5648825Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 40965330 # number of integer regfile writes 5658825Snilay@cs.wisc.edusystem.cpu.fp_regfile_reads 166532 # number of floating regfile reads 5668546SN/Asystem.cpu.fp_regfile_writes 167403 # number of floating regfile writes 5678825Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 1996306 # number of misc regfile reads 5688825Snilay@cs.wisc.edusystem.cpu.misc_regfile_writes 949674 # number of misc regfile writes 5698464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 5708464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 5718464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 5728464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 5738464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 5748464SN/Asystem.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 5758464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 5768464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 5778464SN/Asystem.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 5788464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 5798464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 5808464SN/Asystem.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 5818464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 5828464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 5838464SN/Asystem.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 5848464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 5858464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 5868464SN/Asystem.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 5878464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 5888464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 5898464SN/Asystem.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 5908464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 5918464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 5928464SN/Asystem.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 5938464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 5948464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 5958464SN/Asystem.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 5968464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 5978464SN/Asystem.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 5988464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 5998464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 6008825Snilay@cs.wisc.edusystem.cpu.icache.replacements 1004588 # number of replacements 6018825Snilay@cs.wisc.edusystem.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use 6028825Snilay@cs.wisc.edusystem.cpu.icache.total_refs 7985769 # Total number of references to valid blocks. 6038825Snilay@cs.wisc.edusystem.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. 6048825Snilay@cs.wisc.edusystem.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. 6058825Snilay@cs.wisc.edusystem.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. 6068825Snilay@cs.wisc.edusystem.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context 6078825Snilay@cs.wisc.edusystem.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy 6088825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::0 7985770 # number of ReadReq hits 6098825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits 6108825Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::0 7985770 # number of demand (read+write) hits 6118464SN/Asystem.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 6128825Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits 6138825Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::0 7985770 # number of overall hits 6148464SN/Asystem.cpu.icache.overall_hits::1 0 # number of overall hits 6158825Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 7985770 # number of overall hits 6168825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::0 1065446 # number of ReadReq misses 6178825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses 6188825Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::0 1065446 # number of demand (read+write) misses 6198464SN/Asystem.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 6208825Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses 6218825Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::0 1065446 # number of overall misses 6228464SN/Asystem.cpu.icache.overall_misses::1 0 # number of overall misses 6238825Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 1065446 # number of overall misses 6248825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency 15927822494 # number of ReadReq miss cycles 6258825Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency 15927822494 # number of demand (read+write) miss cycles 6268825Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency 15927822494 # number of overall miss cycles 6278825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::0 9051216 # number of ReadReq accesses(hits+misses) 6288825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) 6298825Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::0 9051216 # number of demand (read+write) accesses 6308464SN/Asystem.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 6318825Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses 6328825Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::0 9051216 # number of overall (read+write) accesses 6338464SN/Asystem.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 6348825Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses 6358825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::0 0.117713 # miss rate for ReadReq accesses 6368825Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::0 0.117713 # miss rate for demand accesses 6378464SN/Asystem.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 6388464SN/Asystem.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 6398825Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::0 0.117713 # miss rate for overall accesses 6408464SN/Asystem.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 6418464SN/Asystem.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 6428825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355 # average ReadReq miss latency 6438464SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 6448464SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 6458825Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::0 14949.441355 # average overall miss latency 6468464SN/Asystem.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 6478464SN/Asystem.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 6488825Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::0 14949.441355 # average overall miss latency 6498464SN/Asystem.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 6508464SN/Asystem.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 6518825Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked 6528464SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6538825Snilay@cs.wisc.edusystem.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked 6548464SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 6558825Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked 6568464SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 6578464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6588464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 6598825Snilay@cs.wisc.edusystem.cpu.icache.writebacks 234 # number of writebacks 6608825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits 60134 # number of ReadReq MSHR hits 6618825Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits 60134 # number of demand (read+write) MSHR hits 6628825Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits 60134 # number of overall MSHR hits 6638825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses 1005312 # number of ReadReq MSHR misses 6648825Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses 1005312 # number of demand (read+write) MSHR misses 6658825Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses 1005312 # number of overall MSHR misses 6668464SN/Asystem.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 6678825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles 6688825Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency 12047333996 # number of demand (read+write) MSHR miss cycles 6698825Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles 6708464SN/Asystem.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 6718825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses 6728464SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 6738464SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 6748825Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::0 0.111069 # mshr miss rate for demand accesses 6758464SN/Asystem.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 6768464SN/Asystem.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 6778825Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::0 0.111069 # mshr miss rate for overall accesses 6788464SN/Asystem.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 6798464SN/Asystem.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 6808825Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency 6818825Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency 6828825Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency 6838464SN/Asystem.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 6848464SN/Asystem.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 6858464SN/Asystem.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 6868464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6878825Snilay@cs.wisc.edusystem.cpu.dcache.replacements 1403406 # number of replacements 6888825Snilay@cs.wisc.edusystem.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use 6898825Snilay@cs.wisc.edusystem.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks. 6908825Snilay@cs.wisc.edusystem.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. 6918825Snilay@cs.wisc.edusystem.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. 6928546SN/Asystem.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. 6938825Snilay@cs.wisc.edusystem.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context 6948464SN/Asystem.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy 6958825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits 6968825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits 6978825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits 6988825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits 6998825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits 7008825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits 7018825Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits 7028825Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits 7038825Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits 7048464SN/Asystem.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 7058825Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits 7068825Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::0 11674234 # number of overall hits 7078464SN/Asystem.cpu.dcache.overall_hits::1 0 # number of overall hits 7088825Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 11674234 # number of overall hits 7098825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses 7108825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses 7118825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses 7128825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses 7138825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses 7148825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses 7158464SN/Asystem.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses 7168464SN/Asystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 7178825Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses 7188464SN/Asystem.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 7198825Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses 7208825Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::0 3745657 # number of overall misses 7218464SN/Asystem.cpu.dcache.overall_misses::1 0 # number of overall misses 7228825Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 3745657 # number of overall misses 7238825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles 7248825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles 7258825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles 7268464SN/Asystem.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles 7278825Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles 7288825Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles 7298825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses) 7308825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) 7318825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses) 7328825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) 7338825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses) 7348825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) 7358825Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses) 7368825Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) 7378825Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses 7388464SN/Asystem.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 7398825Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses 7408825Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses 7418464SN/Asystem.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 7428825Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses 7438825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses 7448825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses 7458825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses 7468464SN/Asystem.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses 7478825Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses 7488464SN/Asystem.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 7498464SN/Asystem.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 7508825Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses 7518464SN/Asystem.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 7528464SN/Asystem.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 7538825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency 7548464SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 7558464SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 7568825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency 7578464SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 7588464SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 7598825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency 7606980SN/Asystem.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 7616980SN/Asystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 7628464SN/Asystem.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency 7638464SN/Asystem.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 7648464SN/Asystem.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 7658825Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency 7668464SN/Asystem.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 7678464SN/Asystem.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 7688825Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency 7698464SN/Asystem.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 7708464SN/Asystem.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 7718825Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked 7728825Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked 7738825Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked 7748825Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 7758825Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked 7768825Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked 7778464SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 7788464SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 7798825Snilay@cs.wisc.edusystem.cpu.dcache.writebacks 834955 # number of writebacks 7808825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits 7818825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits 7828825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits 7838825Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits 7848825Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits 7858825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses 7868825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses 7878825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses 7888464SN/Asystem.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses 7898825Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses 7908825Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses 7918464SN/Asystem.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 7928825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles 7938825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles 7948825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles 7958464SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles 7968825Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles 7978825Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles 7988825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles 7998825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles 8008825Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles 8018825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses 8028464SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 8038464SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 8048825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses 8058464SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 8068464SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 8078825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses 8086980SN/Asystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 8096980SN/Asystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 8108464SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses 8116980SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 8126980SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 8138825Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses 8146980SN/Asystem.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 8156980SN/Asystem.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 8168825Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses 8176980SN/Asystem.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 8186980SN/Asystem.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 8198825Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency 8208825Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency 8218825Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency 8228464SN/Asystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency 8238825Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency 8248825Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency 8258464SN/Asystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 8268464SN/Asystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 8278464SN/Asystem.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 8288464SN/Asystem.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 8295703SN/Asystem.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 8308464SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8315703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 8328825Snilay@cs.wisc.edusystem.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed 8338825Snilay@cs.wisc.edusystem.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed 8348825Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl 8358825Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl 8368825Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl 8378825Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl 8388825Snilay@cs.wisc.edusystem.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl 8398825Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl 8408825Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl 8418825Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl 8428825Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl 8438825Snilay@cs.wisc.edusystem.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl 8448825Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl 8458825Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl 8468825Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl 8478825Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl 8488825Snilay@cs.wisc.edusystem.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl 8498825Snilay@cs.wisc.edusystem.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl 8506127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 8516127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 8528825Snilay@cs.wisc.edusystem.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl 8536291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 8546291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 8556291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 8566291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 8576291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 8586291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 8596291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 8606291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 8616291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 8626291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 8636291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 8646291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 8656291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 8666291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 8676291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 8686291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 8696291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 8706291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 8716291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 8726291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 8736291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 8746291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 8756291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 8766291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 8776291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 8786291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 8796291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 8806291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 8816291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 8826291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 8836127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 8848464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 8858464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 8868464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 8878464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 8888517SN/Asystem.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 8898464SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 8908464SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 8918825Snilay@cs.wisc.edusystem.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed 8928825Snilay@cs.wisc.edusystem.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed 8938464SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 8948464SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 8958464SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 8968464SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 8978825Snilay@cs.wisc.edusystem.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed 8988464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 8998464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 9008825Snilay@cs.wisc.edusystem.cpu.kern.callpal::total 192344 # number of callpals executed 9018825Snilay@cs.wisc.edusystem.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches 9028825Snilay@cs.wisc.edusystem.cpu.kern.mode_switch::user 1739 # number of protection mode switches 9038825Snilay@cs.wisc.edusystem.cpu.kern.mode_switch::idle 2105 # number of protection mode switches 9048825Snilay@cs.wisc.edusystem.cpu.kern.mode_good::kernel 1909 9058825Snilay@cs.wisc.edusystem.cpu.kern.mode_good::user 1739 9068517SN/Asystem.cpu.kern.mode_good::idle 170 9078825Snilay@cs.wisc.edusystem.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches 9088464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 9098825Snilay@cs.wisc.edusystem.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches 9108825Snilay@cs.wisc.edusystem.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches 9118825Snilay@cs.wisc.edusystem.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode 9128825Snilay@cs.wisc.edusystem.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode 9138825Snilay@cs.wisc.edusystem.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode 9148517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 9155703SN/A 9165703SN/A---------- End Simulation Statistics ---------- 917