stats.txt revision 8517
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.858709 # Number of seconds simulated 4sim_ticks 1858708914500 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 124964 # Simulator instruction rate (inst/s) 7host_tick_rate 4374927606 # Simulator tick rate (ticks/s) 8host_mem_usage 340632 # Number of bytes of host memory used 9host_seconds 424.85 # Real time elapsed on the host 10sim_insts 53091761 # Number of instructions simulated 11system.l2c.replacements 391302 # number of replacements 12system.l2c.tagsinuse 34944.632545 # Cycle average of tags in use 13system.l2c.total_refs 2405534 # Total number of references to valid blocks. 14system.l2c.sampled_refs 424233 # Sample count of references to valid blocks. 15system.l2c.avg_refs 5.670313 # Average number of references to valid blocks. 16system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. 17system.l2c.occ_blocks::0 12322.596332 # Average occupied blocks per context 18system.l2c.occ_blocks::1 22622.036213 # Average occupied blocks per context 19system.l2c.occ_percent::0 0.188028 # Average percentage of cache occupancy 20system.l2c.occ_percent::1 0.345185 # Average percentage of cache occupancy 21system.l2c.ReadReq_hits::0 1801216 # number of ReadReq hits 22system.l2c.ReadReq_hits::total 1801216 # number of ReadReq hits 23system.l2c.Writeback_hits::0 835065 # number of Writeback hits 24system.l2c.Writeback_hits::total 835065 # number of Writeback hits 25system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits 26system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits 27system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits 28system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 29system.l2c.ReadExReq_hits::0 183191 # number of ReadExReq hits 30system.l2c.ReadExReq_hits::total 183191 # number of ReadExReq hits 31system.l2c.demand_hits::0 1984407 # number of demand (read+write) hits 32system.l2c.demand_hits::1 0 # number of demand (read+write) hits 33system.l2c.demand_hits::total 1984407 # number of demand (read+write) hits 34system.l2c.overall_hits::0 1984407 # number of overall hits 35system.l2c.overall_hits::1 0 # number of overall hits 36system.l2c.overall_hits::total 1984407 # number of overall hits 37system.l2c.ReadReq_misses::0 308126 # number of ReadReq misses 38system.l2c.ReadReq_misses::total 308126 # number of ReadReq misses 39system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses 40system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses 41system.l2c.ReadExReq_misses::0 116919 # number of ReadExReq misses 42system.l2c.ReadExReq_misses::total 116919 # number of ReadExReq misses 43system.l2c.demand_misses::0 425045 # number of demand (read+write) misses 44system.l2c.demand_misses::1 0 # number of demand (read+write) misses 45system.l2c.demand_misses::total 425045 # number of demand (read+write) misses 46system.l2c.overall_misses::0 425045 # number of overall misses 47system.l2c.overall_misses::1 0 # number of overall misses 48system.l2c.overall_misses::total 425045 # number of overall misses 49system.l2c.ReadReq_miss_latency 16035962500 # number of ReadReq miss cycles 50system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles 51system.l2c.ReadExReq_miss_latency 6137530000 # number of ReadExReq miss cycles 52system.l2c.demand_miss_latency 22173492500 # number of demand (read+write) miss cycles 53system.l2c.overall_miss_latency 22173492500 # number of overall miss cycles 54system.l2c.ReadReq_accesses::0 2109342 # number of ReadReq accesses(hits+misses) 55system.l2c.ReadReq_accesses::total 2109342 # number of ReadReq accesses(hits+misses) 56system.l2c.Writeback_accesses::0 835065 # number of Writeback accesses(hits+misses) 57system.l2c.Writeback_accesses::total 835065 # number of Writeback accesses(hits+misses) 58system.l2c.UpgradeReq_accesses::0 44 # number of UpgradeReq accesses(hits+misses) 59system.l2c.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) 60system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) 61system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 62system.l2c.ReadExReq_accesses::0 300110 # number of ReadExReq accesses(hits+misses) 63system.l2c.ReadExReq_accesses::total 300110 # number of ReadExReq accesses(hits+misses) 64system.l2c.demand_accesses::0 2409452 # number of demand (read+write) accesses 65system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 66system.l2c.demand_accesses::total 2409452 # number of demand (read+write) accesses 67system.l2c.overall_accesses::0 2409452 # number of overall (read+write) accesses 68system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 69system.l2c.overall_accesses::total 2409452 # number of overall (read+write) accesses 70system.l2c.ReadReq_miss_rate::0 0.146077 # miss rate for ReadReq accesses 71system.l2c.UpgradeReq_miss_rate::0 0.704545 # miss rate for UpgradeReq accesses 72system.l2c.ReadExReq_miss_rate::0 0.389587 # miss rate for ReadExReq accesses 73system.l2c.demand_miss_rate::0 0.176407 # miss rate for demand accesses 74system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 75system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 76system.l2c.overall_miss_rate::0 0.176407 # miss rate for overall accesses 77system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 78system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 79system.l2c.ReadReq_avg_miss_latency::0 52043.522780 # average ReadReq miss latency 80system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 81system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 82system.l2c.UpgradeReq_avg_miss_latency::0 13709.677419 # average UpgradeReq miss latency 83system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 84system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 85system.l2c.ReadExReq_avg_miss_latency::0 52493.863273 # average ReadExReq miss latency 86system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 87system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 88system.l2c.demand_avg_miss_latency::0 52167.399922 # average overall miss latency 89system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency 90system.l2c.demand_avg_miss_latency::total inf # average overall miss latency 91system.l2c.overall_avg_miss_latency::0 52167.399922 # average overall miss latency 92system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency 93system.l2c.overall_avg_miss_latency::total inf # average overall miss latency 94system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 95system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 96system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 97system.l2c.blocked::no_targets 0 # number of cycles access was blocked 98system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 99system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 100system.l2c.fast_writes 0 # number of fast writes performed 101system.l2c.cache_copies 0 # number of cache copies performed 102system.l2c.writebacks 117722 # number of writebacks 103system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 104system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 105system.l2c.ReadReq_mshr_misses 308126 # number of ReadReq MSHR misses 106system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses 107system.l2c.ReadExReq_mshr_misses 116919 # number of ReadExReq MSHR misses 108system.l2c.demand_mshr_misses 425045 # number of demand (read+write) MSHR misses 109system.l2c.overall_mshr_misses 425045 # number of overall MSHR misses 110system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 111system.l2c.ReadReq_mshr_miss_latency 12333217500 # number of ReadReq MSHR miss cycles 112system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles 113system.l2c.ReadExReq_mshr_miss_latency 4715307000 # number of ReadExReq MSHR miss cycles 114system.l2c.demand_mshr_miss_latency 17048524500 # number of demand (read+write) MSHR miss cycles 115system.l2c.overall_mshr_miss_latency 17048524500 # number of overall MSHR miss cycles 116system.l2c.ReadReq_mshr_uncacheable_latency 809593500 # number of ReadReq MSHR uncacheable cycles 117system.l2c.WriteReq_mshr_uncacheable_latency 1114721998 # number of WriteReq MSHR uncacheable cycles 118system.l2c.overall_mshr_uncacheable_latency 1924315498 # number of overall MSHR uncacheable cycles 119system.l2c.ReadReq_mshr_miss_rate::0 0.146077 # mshr miss rate for ReadReq accesses 120system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 121system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 122system.l2c.UpgradeReq_mshr_miss_rate::0 0.704545 # mshr miss rate for UpgradeReq accesses 123system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 124system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 125system.l2c.ReadExReq_mshr_miss_rate::0 0.389587 # mshr miss rate for ReadExReq accesses 126system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 127system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 128system.l2c.demand_mshr_miss_rate::0 0.176407 # mshr miss rate for demand accesses 129system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 130system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 131system.l2c.overall_mshr_miss_rate::0 0.176407 # mshr miss rate for overall accesses 132system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 133system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 134system.l2c.ReadReq_avg_mshr_miss_latency 40026.539468 # average ReadReq mshr miss latency 135system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency 136system.l2c.ReadExReq_avg_mshr_miss_latency 40329.689785 # average ReadExReq mshr miss latency 137system.l2c.demand_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency 138system.l2c.overall_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency 139system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 140system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 141system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 142system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 143system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 144system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 145system.iocache.replacements 41685 # number of replacements 146system.iocache.tagsinuse 1.266801 # Cycle average of tags in use 147system.iocache.total_refs 0 # Total number of references to valid blocks. 148system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 149system.iocache.avg_refs 0 # Average number of references to valid blocks. 150system.iocache.warmup_cycle 1708338851000 # Cycle when the warmup percentage was hit. 151system.iocache.occ_blocks::1 1.266801 # Average occupied blocks per context 152system.iocache.occ_percent::1 0.079175 # Average percentage of cache occupancy 153system.iocache.demand_hits::0 0 # number of demand (read+write) hits 154system.iocache.demand_hits::1 0 # number of demand (read+write) hits 155system.iocache.demand_hits::total 0 # number of demand (read+write) hits 156system.iocache.overall_hits::0 0 # number of overall hits 157system.iocache.overall_hits::1 0 # number of overall hits 158system.iocache.overall_hits::total 0 # number of overall hits 159system.iocache.ReadReq_misses::1 173 # number of ReadReq misses 160system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 161system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 162system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 163system.iocache.demand_misses::0 0 # number of demand (read+write) misses 164system.iocache.demand_misses::1 41725 # number of demand (read+write) misses 165system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 166system.iocache.overall_misses::0 0 # number of overall misses 167system.iocache.overall_misses::1 41725 # number of overall misses 168system.iocache.overall_misses::total 41725 # number of overall misses 169system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles 170system.iocache.WriteReq_miss_latency 5722275806 # number of WriteReq miss cycles 171system.iocache.demand_miss_latency 5742213804 # number of demand (read+write) miss cycles 172system.iocache.overall_miss_latency 5742213804 # number of overall miss cycles 173system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) 174system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 175system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 176system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 177system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 178system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses 179system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 180system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 181system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses 182system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 183system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 184system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 185system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 186system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 187system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 188system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 189system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 190system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 191system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 192system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency 193system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 194system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 195system.iocache.WriteReq_avg_miss_latency::1 137713.607191 # average WriteReq miss latency 196system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 197system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 198system.iocache.demand_avg_miss_latency::1 137620.462648 # average overall miss latency 199system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 200system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 201system.iocache.overall_avg_miss_latency::1 137620.462648 # average overall miss latency 202system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 203system.iocache.blocked_cycles::no_mshrs 64594068 # number of cycles access was blocked 204system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 205system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked 206system.iocache.blocked::no_targets 0 # number of cycles access was blocked 207system.iocache.avg_blocked_cycles::no_mshrs 6170.621704 # average number of cycles each access was blocked 208system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 209system.iocache.fast_writes 0 # number of fast writes performed 210system.iocache.cache_copies 0 # number of cache copies performed 211system.iocache.writebacks 41512 # number of writebacks 212system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 213system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 214system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 215system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 216system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 217system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 218system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 219system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles 220system.iocache.WriteReq_mshr_miss_latency 3561421998 # number of WriteReq MSHR miss cycles 221system.iocache.demand_mshr_miss_latency 3572363996 # number of demand (read+write) MSHR miss cycles 222system.iocache.overall_mshr_miss_latency 3572363996 # number of overall MSHR miss cycles 223system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 224system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 225system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 226system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 227system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 228system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 229system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 230system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 231system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 232system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 233system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 234system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 235system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 236system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency 237system.iocache.WriteReq_avg_mshr_miss_latency 85710.001877 # average WriteReq mshr miss latency 238system.iocache.demand_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency 239system.iocache.overall_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency 240system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 241system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 242system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 243system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 244system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 245system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 246system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 247system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 248system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 249system.disk0.dma_write_txs 395 # Number of DMA write transactions. 250system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 251system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 252system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 253system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 254system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 255system.disk2.dma_write_txs 1 # Number of DMA write transactions. 256system.cpu.dtb.fetch_hits 0 # ITB hits 257system.cpu.dtb.fetch_misses 0 # ITB misses 258system.cpu.dtb.fetch_acv 0 # ITB acv 259system.cpu.dtb.fetch_accesses 0 # ITB accesses 260system.cpu.dtb.read_hits 10154080 # DTB read hits 261system.cpu.dtb.read_misses 43144 # DTB read misses 262system.cpu.dtb.read_acv 557 # DTB read access violations 263system.cpu.dtb.read_accesses 952445 # DTB read accesses 264system.cpu.dtb.write_hits 6614848 # DTB write hits 265system.cpu.dtb.write_misses 9467 # DTB write misses 266system.cpu.dtb.write_acv 320 # DTB write access violations 267system.cpu.dtb.write_accesses 334339 # DTB write accesses 268system.cpu.dtb.data_hits 16768928 # DTB hits 269system.cpu.dtb.data_misses 52611 # DTB misses 270system.cpu.dtb.data_acv 877 # DTB access violations 271system.cpu.dtb.data_accesses 1286784 # DTB accesses 272system.cpu.itb.fetch_hits 1336327 # ITB hits 273system.cpu.itb.fetch_misses 39787 # ITB misses 274system.cpu.itb.fetch_acv 1065 # ITB acv 275system.cpu.itb.fetch_accesses 1376114 # ITB accesses 276system.cpu.itb.read_hits 0 # DTB read hits 277system.cpu.itb.read_misses 0 # DTB read misses 278system.cpu.itb.read_acv 0 # DTB read access violations 279system.cpu.itb.read_accesses 0 # DTB read accesses 280system.cpu.itb.write_hits 0 # DTB write hits 281system.cpu.itb.write_misses 0 # DTB write misses 282system.cpu.itb.write_acv 0 # DTB write access violations 283system.cpu.itb.write_accesses 0 # DTB write accesses 284system.cpu.itb.data_hits 0 # DTB hits 285system.cpu.itb.data_misses 0 # DTB misses 286system.cpu.itb.data_acv 0 # DTB access violations 287system.cpu.itb.data_accesses 0 # DTB accesses 288system.cpu.numCycles 117237485 # number of cpu cycles simulated 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu.BPredUnit.lookups 14455551 # Number of BP lookups 292system.cpu.BPredUnit.condPredicted 12084424 # Number of conditional branches predicted 293system.cpu.BPredUnit.condIncorrect 532367 # Number of conditional branches incorrect 294system.cpu.BPredUnit.BTBLookups 13050115 # Number of BTB lookups 295system.cpu.BPredUnit.BTBHits 6745735 # Number of BTB hits 296system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 297system.cpu.BPredUnit.usedRAS 978348 # Number of times the RAS was used to get a target. 298system.cpu.BPredUnit.RASInCorrect 45278 # Number of incorrect RAS predictions. 299system.cpu.fetch.icacheStallCycles 29236023 # Number of cycles fetch is stalled on an Icache miss 300system.cpu.fetch.Insts 74164805 # Number of instructions fetch has processed 301system.cpu.fetch.Branches 14455551 # Number of branches that fetch encountered 302system.cpu.fetch.predictedBranches 7724083 # Number of branches that fetch has predicted taken 303system.cpu.fetch.Cycles 14385478 # Number of cycles fetch has run and was not squashing or blocked 304system.cpu.fetch.SquashCycles 2439202 # Number of cycles fetch has spent squashing 305system.cpu.fetch.BlockedCycles 37224537 # Number of cycles fetch has spent blocked 306system.cpu.fetch.MiscStallCycles 33011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 307system.cpu.fetch.PendingTrapStallCycles 262840 # Number of stall cycles due to pending traps 308system.cpu.fetch.PendingQuiesceStallCycles 335923 # Number of stall cycles due to pending quiesce instructions 309system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR 310system.cpu.fetch.CacheLines 9135306 # Number of cache lines fetched 311system.cpu.fetch.IcacheSquashes 330174 # Number of outstanding Icache misses that were squashed 312system.cpu.fetch.rateDist::samples 83080083 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::mean 0.892691 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::stdev 2.209867 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::0 68694605 82.68% 82.68% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::1 1023953 1.23% 83.92% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::2 2033478 2.45% 86.36% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::3 975932 1.17% 87.54% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::4 2976777 3.58% 91.12% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::5 700548 0.84% 91.97% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::6 794915 0.96% 92.92% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::7 1072238 1.29% 94.21% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::8 4807637 5.79% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::total 83080083 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.branchRate 0.123301 # Number of branch fetches per cycle 330system.cpu.fetch.rate 0.632603 # Number of inst fetches per cycle 331system.cpu.decode.IdleCycles 30551542 # Number of cycles decode is idle 332system.cpu.decode.BlockedCycles 36838313 # Number of cycles decode is blocked 333system.cpu.decode.RunCycles 13095678 # Number of cycles decode is running 334system.cpu.decode.UnblockCycles 1034253 # Number of cycles decode is unblocking 335system.cpu.decode.SquashCycles 1560296 # Number of cycles decode is squashing 336system.cpu.decode.BranchResolved 613869 # Number of times decode resolved a branch 337system.cpu.decode.BranchMispred 42144 # Number of times decode detected a branch misprediction 338system.cpu.decode.DecodedInsts 72480994 # Number of instructions handled by decode 339system.cpu.decode.SquashedInsts 127271 # Number of squashed instructions handled by decode 340system.cpu.rename.SquashCycles 1560296 # Number of cycles rename is squashing 341system.cpu.rename.IdleCycles 31800995 # Number of cycles rename is idle 342system.cpu.rename.BlockCycles 12812731 # Number of cycles rename is blocking 343system.cpu.rename.serializeStallCycles 19871114 # count of cycles rename stalled for serializing inst 344system.cpu.rename.RunCycles 12262779 # Number of cycles rename is running 345system.cpu.rename.UnblockCycles 4772166 # Number of cycles rename is unblocking 346system.cpu.rename.RenamedInsts 68475649 # Number of instructions processed by rename 347system.cpu.rename.ROBFullEvents 4094 # Number of times rename has blocked due to ROB full 348system.cpu.rename.IQFullEvents 996372 # Number of times rename has blocked due to IQ full 349system.cpu.rename.LSQFullEvents 1464404 # Number of times rename has blocked due to LSQ full 350system.cpu.rename.RenamedOperands 45853535 # Number of destination operands rename has renamed 351system.cpu.rename.RenameLookups 83251938 # Number of register rename lookups that rename has made 352system.cpu.rename.int_rename_lookups 82772461 # Number of integer rename lookups 353system.cpu.rename.fp_rename_lookups 479477 # Number of floating rename lookups 354system.cpu.rename.CommittedMaps 38260770 # Number of HB maps that are committed 355system.cpu.rename.UndoneMaps 7592757 # Number of HB maps that are undone due to squashing 356system.cpu.rename.serializingInsts 1700825 # count of serializing insts renamed 357system.cpu.rename.tempSerializingInsts 251533 # count of temporary serializing insts renamed 358system.cpu.rename.skidInsts 12956852 # count of insts added to the skid buffer 359system.cpu.memDep0.insertedLoads 10812074 # Number of loads inserted to the mem dependence unit. 360system.cpu.memDep0.insertedStores 7051744 # Number of stores inserted to the mem dependence unit. 361system.cpu.memDep0.conflictingLoads 2165147 # Number of conflicting loads. 362system.cpu.memDep0.conflictingStores 2346616 # Number of conflicting stores. 363system.cpu.iq.iqInstsAdded 60096918 # Number of instructions added to the IQ (excludes non-spec) 364system.cpu.iq.iqNonSpecInstsAdded 2117388 # Number of non-speculative instructions added to the IQ 365system.cpu.iq.iqInstsIssued 58031681 # Number of instructions issued 366system.cpu.iq.iqSquashedInstsIssued 82818 # Number of squashed instructions issued 367system.cpu.iq.iqSquashedInstsExamined 8738509 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedOperandsExamined 4816872 # Number of squashed operands that are examined and possibly removed from graph 369system.cpu.iq.iqSquashedNonSpecRemoved 1449642 # Number of squashed non-spec instructions that were removed 370system.cpu.iq.issued_per_cycle::samples 83080083 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::mean 0.698503 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::stdev 1.311149 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::0 56639169 68.17% 68.17% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::1 11994103 14.44% 82.61% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::2 5929931 7.14% 89.75% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::3 3560683 4.29% 94.03% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::4 2591551 3.12% 97.15% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::5 1336446 1.61% 98.76% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::6 797054 0.96% 99.72% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::7 184259 0.22% 99.94% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::8 46887 0.06% 100.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::total 83080083 # Number of insts issued each cycle 387system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 388system.cpu.iq.fu_full::IntAlu 68783 12.83% 12.83% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntMult 0 0.00% 12.83% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntDiv 0 0.00% 12.83% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.83% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.83% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.83% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatMult 0 0.00% 12.83% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.83% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.83% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.83% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.83% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.83% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.83% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.83% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.83% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdMult 0 0.00% 12.83% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.83% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdShift 0 0.00% 12.83% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.83% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.83% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.83% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.83% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.83% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.83% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.83% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.83% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.83% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.83% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.83% # attempts to use FU when none available 417system.cpu.iq.fu_full::MemRead 305726 57.04% 69.88% # attempts to use FU when none available 418system.cpu.iq.fu_full::MemWrite 161454 30.12% 100.00% # attempts to use FU when none available 419system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 421system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued 422system.cpu.iq.FU_type_0::IntAlu 39661101 68.34% 68.36% # Type of FU issued 423system.cpu.iq.FU_type_0::IntMult 62145 0.11% 68.46% # Type of FU issued 424system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatAdd 25610 0.04% 68.51% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.51% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.51% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.51% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.51% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.51% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.51% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.51% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.51% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.51% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.51% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.51% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.51% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.51% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.51% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.51% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.51% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.51% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.51% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.51% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.51% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.51% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.51% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued 451system.cpu.iq.FU_type_0::MemRead 10623971 18.31% 86.82% # Type of FU issued 452system.cpu.iq.FU_type_0::MemWrite 6695582 11.54% 98.36% # Type of FU issued 453system.cpu.iq.FU_type_0::IprAccess 952355 1.64% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::total 58031681 # Type of FU issued 456system.cpu.iq.rate 0.494993 # Inst issue rate 457system.cpu.iq.fu_busy_cnt 535963 # FU busy when requested 458system.cpu.iq.fu_busy_rate 0.009236 # FU busy rate (busy events/executed inst) 459system.cpu.iq.int_inst_queue_reads 199072460 # Number of integer instruction queue reads 460system.cpu.iq.int_inst_queue_writes 70641414 # Number of integer instruction queue writes 461system.cpu.iq.int_inst_queue_wakeup_accesses 56449878 # Number of integer instruction queue wakeup accesses 462system.cpu.iq.fp_inst_queue_reads 689765 # Number of floating instruction queue reads 463system.cpu.iq.fp_inst_queue_writes 333951 # Number of floating instruction queue writes 464system.cpu.iq.fp_inst_queue_wakeup_accesses 328040 # Number of floating instruction queue wakeup accesses 465system.cpu.iq.int_alu_accesses 58199260 # Number of integer alu accesses 466system.cpu.iq.fp_alu_accesses 361103 # Number of floating point alu accesses 467system.cpu.iew.lsq.thread0.forwLoads 552721 # Number of loads that had data forwarded from stores 468system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 469system.cpu.iew.lsq.thread0.squashedLoads 1698615 # Number of loads squashed 470system.cpu.iew.lsq.thread0.ignoredResponses 15451 # Number of memory responses ignored because the instruction is squashed 471system.cpu.iew.lsq.thread0.memOrderViolation 23451 # Number of memory ordering violations 472system.cpu.iew.lsq.thread0.squashedStores 659180 # Number of stores squashed 473system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 474system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 475system.cpu.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled 476system.cpu.iew.lsq.thread0.cacheBlocked 200829 # Number of times an access to memory failed due to the cache being blocked 477system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 478system.cpu.iew.iewSquashCycles 1560296 # Number of cycles IEW is squashing 479system.cpu.iew.iewBlockCycles 8872665 # Number of cycles IEW is blocking 480system.cpu.iew.iewUnblockCycles 625505 # Number of cycles IEW is unblocking 481system.cpu.iew.iewDispatchedInsts 65852816 # Number of instructions dispatched to IQ 482system.cpu.iew.iewDispSquashedInsts 871025 # Number of squashed instructions skipped by dispatch 483system.cpu.iew.iewDispLoadInsts 10812074 # Number of dispatched load instructions 484system.cpu.iew.iewDispStoreInsts 7051744 # Number of dispatched store instructions 485system.cpu.iew.iewDispNonSpecInsts 1870069 # Number of dispatched non-speculative instructions 486system.cpu.iew.iewIQFullEvents 491565 # Number of times the IQ has become full, causing a stall 487system.cpu.iew.iewLSQFullEvents 7470 # Number of times the LSQ has become full, causing a stall 488system.cpu.iew.memOrderViolationEvents 23451 # Number of memory order violations 489system.cpu.iew.predictedTakenIncorrect 385257 # Number of branches that were predicted taken incorrectly 490system.cpu.iew.predictedNotTakenIncorrect 383183 # Number of branches that were predicted not taken incorrectly 491system.cpu.iew.branchMispredicts 768440 # Number of branch mispredicts detected at execute 492system.cpu.iew.iewExecutedInsts 57350351 # Number of executed instructions 493system.cpu.iew.iewExecLoadInsts 10227555 # Number of load instructions executed 494system.cpu.iew.iewExecSquashedInsts 681329 # Number of squashed instructions skipped in execute 495system.cpu.iew.exec_swp 0 # number of swp insts executed 496system.cpu.iew.exec_nop 3638510 # number of nop insts executed 497system.cpu.iew.exec_refs 16867130 # number of memory reference insts executed 498system.cpu.iew.exec_branches 9102477 # Number of branches executed 499system.cpu.iew.exec_stores 6639575 # Number of stores executed 500system.cpu.iew.exec_rate 0.489181 # Inst execution rate 501system.cpu.iew.wb_sent 56909286 # cumulative count of insts sent to commit 502system.cpu.iew.wb_count 56777918 # cumulative count of insts written-back 503system.cpu.iew.wb_producers 28083144 # num instructions producing a value 504system.cpu.iew.wb_consumers 37838196 # num instructions consuming a value 505system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 506system.cpu.iew.wb_rate 0.484298 # insts written-back per cycle 507system.cpu.iew.wb_fanout 0.742190 # average fanout of values written-back 508system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 509system.cpu.commit.commitCommittedInsts 56286421 # The number of committed instructions 510system.cpu.commit.commitSquashedInsts 9443080 # The number of squashed insts skipped by commit 511system.cpu.commit.commitNonSpecStalls 667746 # The number of times commit has been forced to stall to communicate backwards 512system.cpu.commit.branchMispredicts 702134 # The number of times a branch was mispredicted 513system.cpu.commit.committed_per_cycle::samples 81519787 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::mean 0.690463 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::stdev 1.566765 # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::0 59658965 73.18% 73.18% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::1 9249179 11.35% 84.53% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::2 5213125 6.39% 90.92% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::3 2451549 3.01% 93.93% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::4 1701758 2.09% 96.02% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::5 617367 0.76% 96.78% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::6 434350 0.53% 97.31% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::7 791574 0.97% 98.28% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::8 1401920 1.72% 100.00% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::total 81519787 # Number of insts commited each cycle 530system.cpu.commit.count 56286421 # Number of instructions committed 531system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 532system.cpu.commit.refs 15506023 # Number of memory references committed 533system.cpu.commit.loads 9113459 # Number of loads committed 534system.cpu.commit.membars 227879 # Number of memory barriers committed 535system.cpu.commit.branches 8462155 # Number of branches committed 536system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 537system.cpu.commit.int_insts 52124782 # Number of committed integer instructions. 538system.cpu.commit.function_calls 744514 # Number of function calls committed. 539system.cpu.commit.bw_lim_events 1401920 # number cycles where commit BW limit reached 540system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 541system.cpu.rob.rob_reads 145596309 # The number of ROB reads 542system.cpu.rob.rob_writes 133022104 # The number of ROB writes 543system.cpu.timesIdled 1258228 # Number of times that the entire CPU went into an idle state and unscheduled itself 544system.cpu.idleCycles 34157402 # Total number of cycles that the CPU has spent unscheduled due to idling 545system.cpu.committedInsts 53091761 # Number of Instructions Simulated 546system.cpu.committedInsts_total 53091761 # Number of Instructions Simulated 547system.cpu.cpi 2.208205 # CPI: Cycles Per Instruction 548system.cpu.cpi_total 2.208205 # CPI: Total CPI of All Threads 549system.cpu.ipc 0.452857 # IPC: Instructions Per Cycle 550system.cpu.ipc_total 0.452857 # IPC: Total IPC of All Threads 551system.cpu.int_regfile_reads 75150720 # number of integer regfile reads 552system.cpu.int_regfile_writes 41017067 # number of integer regfile writes 553system.cpu.fp_regfile_reads 166113 # number of floating regfile reads 554system.cpu.fp_regfile_writes 167453 # number of floating regfile writes 555system.cpu.misc_regfile_reads 1996494 # number of misc regfile reads 556system.cpu.misc_regfile_writes 949911 # number of misc regfile writes 557system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 558system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 559system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 560system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 561system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 562system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 563system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 564system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 565system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 566system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 567system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 568system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 569system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 570system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 571system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 572system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 573system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 574system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 575system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 576system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 577system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 578system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 579system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 580system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 581system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 582system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 583system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 584system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 585system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 586system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 587system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 588system.cpu.icache.replacements 1005090 # number of replacements 589system.cpu.icache.tagsinuse 509.951538 # Cycle average of tags in use 590system.cpu.icache.total_refs 8070754 # Total number of references to valid blocks. 591system.cpu.icache.sampled_refs 1005599 # Sample count of references to valid blocks. 592system.cpu.icache.avg_refs 8.025817 # Average number of references to valid blocks. 593system.cpu.icache.warmup_cycle 23351335000 # Cycle when the warmup percentage was hit. 594system.cpu.icache.occ_blocks::0 509.951538 # Average occupied blocks per context 595system.cpu.icache.occ_percent::0 0.995999 # Average percentage of cache occupancy 596system.cpu.icache.ReadReq_hits::0 8070755 # number of ReadReq hits 597system.cpu.icache.ReadReq_hits::total 8070755 # number of ReadReq hits 598system.cpu.icache.demand_hits::0 8070755 # number of demand (read+write) hits 599system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 8070755 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::0 8070755 # number of overall hits 602system.cpu.icache.overall_hits::1 0 # number of overall hits 603system.cpu.icache.overall_hits::total 8070755 # number of overall hits 604system.cpu.icache.ReadReq_misses::0 1064551 # number of ReadReq misses 605system.cpu.icache.ReadReq_misses::total 1064551 # number of ReadReq misses 606system.cpu.icache.demand_misses::0 1064551 # number of demand (read+write) misses 607system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 608system.cpu.icache.demand_misses::total 1064551 # number of demand (read+write) misses 609system.cpu.icache.overall_misses::0 1064551 # number of overall misses 610system.cpu.icache.overall_misses::1 0 # number of overall misses 611system.cpu.icache.overall_misses::total 1064551 # number of overall misses 612system.cpu.icache.ReadReq_miss_latency 15926988994 # number of ReadReq miss cycles 613system.cpu.icache.demand_miss_latency 15926988994 # number of demand (read+write) miss cycles 614system.cpu.icache.overall_miss_latency 15926988994 # number of overall miss cycles 615system.cpu.icache.ReadReq_accesses::0 9135306 # number of ReadReq accesses(hits+misses) 616system.cpu.icache.ReadReq_accesses::total 9135306 # number of ReadReq accesses(hits+misses) 617system.cpu.icache.demand_accesses::0 9135306 # number of demand (read+write) accesses 618system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 619system.cpu.icache.demand_accesses::total 9135306 # number of demand (read+write) accesses 620system.cpu.icache.overall_accesses::0 9135306 # number of overall (read+write) accesses 621system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 622system.cpu.icache.overall_accesses::total 9135306 # number of overall (read+write) accesses 623system.cpu.icache.ReadReq_miss_rate::0 0.116532 # miss rate for ReadReq accesses 624system.cpu.icache.demand_miss_rate::0 0.116532 # miss rate for demand accesses 625system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 626system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 627system.cpu.icache.overall_miss_rate::0 0.116532 # miss rate for overall accesses 628system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 629system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 630system.cpu.icache.ReadReq_avg_miss_latency::0 14961.226840 # average ReadReq miss latency 631system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 632system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 633system.cpu.icache.demand_avg_miss_latency::0 14961.226840 # average overall miss latency 634system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 635system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::0 14961.226840 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 638system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 639system.cpu.icache.blocked_cycles::no_mshrs 1261996 # number of cycles access was blocked 640system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 641system.cpu.icache.blocked::no_mshrs 120 # number of cycles access was blocked 642system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 643system.cpu.icache.avg_blocked_cycles::no_mshrs 10516.633333 # average number of cycles each access was blocked 644system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 645system.cpu.icache.fast_writes 0 # number of fast writes performed 646system.cpu.icache.cache_copies 0 # number of cache copies performed 647system.cpu.icache.writebacks 232 # number of writebacks 648system.cpu.icache.ReadReq_mshr_hits 58739 # number of ReadReq MSHR hits 649system.cpu.icache.demand_mshr_hits 58739 # number of demand (read+write) MSHR hits 650system.cpu.icache.overall_mshr_hits 58739 # number of overall MSHR hits 651system.cpu.icache.ReadReq_mshr_misses 1005812 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses 1005812 # number of demand (read+write) MSHR misses 653system.cpu.icache.overall_mshr_misses 1005812 # number of overall MSHR misses 654system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 655system.cpu.icache.ReadReq_mshr_miss_latency 12051659996 # number of ReadReq MSHR miss cycles 656system.cpu.icache.demand_mshr_miss_latency 12051659996 # number of demand (read+write) MSHR miss cycles 657system.cpu.icache.overall_mshr_miss_latency 12051659996 # number of overall MSHR miss cycles 658system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 659system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110102 # mshr miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 661system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 662system.cpu.icache.demand_mshr_miss_rate::0 0.110102 # mshr miss rate for demand accesses 663system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 664system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 665system.cpu.icache.overall_mshr_miss_rate::0 0.110102 # mshr miss rate for overall accesses 666system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 667system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.020493 # average ReadReq mshr miss latency 669system.cpu.icache.demand_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency 670system.cpu.icache.overall_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency 671system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 672system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 673system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 674system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cpu.dcache.replacements 1403296 # number of replacements 676system.cpu.dcache.tagsinuse 511.995990 # Cycle average of tags in use 677system.cpu.dcache.total_refs 12128638 # Total number of references to valid blocks. 678system.cpu.dcache.sampled_refs 1403808 # Sample count of references to valid blocks. 679system.cpu.dcache.avg_refs 8.639813 # Average number of references to valid blocks. 680system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. 681system.cpu.dcache.occ_blocks::0 511.995990 # Average occupied blocks per context 682system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy 683system.cpu.dcache.ReadReq_hits::0 7493448 # number of ReadReq hits 684system.cpu.dcache.ReadReq_hits::total 7493448 # number of ReadReq hits 685system.cpu.dcache.WriteReq_hits::0 4222901 # number of WriteReq hits 686system.cpu.dcache.WriteReq_hits::total 4222901 # number of WriteReq hits 687system.cpu.dcache.LoadLockedReq_hits::0 192043 # number of LoadLockedReq hits 688system.cpu.dcache.LoadLockedReq_hits::total 192043 # number of LoadLockedReq hits 689system.cpu.dcache.StoreCondReq_hits::0 220080 # number of StoreCondReq hits 690system.cpu.dcache.StoreCondReq_hits::total 220080 # number of StoreCondReq hits 691system.cpu.dcache.demand_hits::0 11716349 # number of demand (read+write) hits 692system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 693system.cpu.dcache.demand_hits::total 11716349 # number of demand (read+write) hits 694system.cpu.dcache.overall_hits::0 11716349 # number of overall hits 695system.cpu.dcache.overall_hits::1 0 # number of overall hits 696system.cpu.dcache.overall_hits::total 11716349 # number of overall hits 697system.cpu.dcache.ReadReq_misses::0 1778869 # number of ReadReq misses 698system.cpu.dcache.ReadReq_misses::total 1778869 # number of ReadReq misses 699system.cpu.dcache.WriteReq_misses::0 1934444 # number of WriteReq misses 700system.cpu.dcache.WriteReq_misses::total 1934444 # number of WriteReq misses 701system.cpu.dcache.LoadLockedReq_misses::0 23262 # number of LoadLockedReq misses 702system.cpu.dcache.LoadLockedReq_misses::total 23262 # number of LoadLockedReq misses 703system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses 704system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 705system.cpu.dcache.demand_misses::0 3713313 # number of demand (read+write) misses 706system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 707system.cpu.dcache.demand_misses::total 3713313 # number of demand (read+write) misses 708system.cpu.dcache.overall_misses::0 3713313 # number of overall misses 709system.cpu.dcache.overall_misses::1 0 # number of overall misses 710system.cpu.dcache.overall_misses::total 3713313 # number of overall misses 711system.cpu.dcache.ReadReq_miss_latency 38377192500 # number of ReadReq miss cycles 712system.cpu.dcache.WriteReq_miss_latency 57331444318 # number of WriteReq miss cycles 713system.cpu.dcache.LoadLockedReq_miss_latency 363604000 # number of LoadLockedReq miss cycles 714system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles 715system.cpu.dcache.demand_miss_latency 95708636818 # number of demand (read+write) miss cycles 716system.cpu.dcache.overall_miss_latency 95708636818 # number of overall miss cycles 717system.cpu.dcache.ReadReq_accesses::0 9272317 # number of ReadReq accesses(hits+misses) 718system.cpu.dcache.ReadReq_accesses::total 9272317 # number of ReadReq accesses(hits+misses) 719system.cpu.dcache.WriteReq_accesses::0 6157345 # number of WriteReq accesses(hits+misses) 720system.cpu.dcache.WriteReq_accesses::total 6157345 # number of WriteReq accesses(hits+misses) 721system.cpu.dcache.LoadLockedReq_accesses::0 215305 # number of LoadLockedReq accesses(hits+misses) 722system.cpu.dcache.LoadLockedReq_accesses::total 215305 # number of LoadLockedReq accesses(hits+misses) 723system.cpu.dcache.StoreCondReq_accesses::0 220082 # number of StoreCondReq accesses(hits+misses) 724system.cpu.dcache.StoreCondReq_accesses::total 220082 # number of StoreCondReq accesses(hits+misses) 725system.cpu.dcache.demand_accesses::0 15429662 # number of demand (read+write) accesses 726system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 727system.cpu.dcache.demand_accesses::total 15429662 # number of demand (read+write) accesses 728system.cpu.dcache.overall_accesses::0 15429662 # number of overall (read+write) accesses 729system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 730system.cpu.dcache.overall_accesses::total 15429662 # number of overall (read+write) accesses 731system.cpu.dcache.ReadReq_miss_rate::0 0.191847 # miss rate for ReadReq accesses 732system.cpu.dcache.WriteReq_miss_rate::0 0.314169 # miss rate for WriteReq accesses 733system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108042 # miss rate for LoadLockedReq accesses 734system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses 735system.cpu.dcache.demand_miss_rate::0 0.240661 # miss rate for demand accesses 736system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 737system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 738system.cpu.dcache.overall_miss_rate::0 0.240661 # miss rate for overall accesses 739system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 740system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 741system.cpu.dcache.ReadReq_avg_miss_latency::0 21573.928434 # average ReadReq miss latency 742system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 743system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 744system.cpu.dcache.WriteReq_avg_miss_latency::0 29637.169294 # average WriteReq miss latency 745system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 746system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 747system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15630.814203 # average LoadLockedReq miss latency 748system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 749system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 750system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency 751system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 752system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 753system.cpu.dcache.demand_avg_miss_latency::0 25774.459847 # average overall miss latency 754system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 755system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 756system.cpu.dcache.overall_avg_miss_latency::0 25774.459847 # average overall miss latency 757system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 758system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 759system.cpu.dcache.blocked_cycles::no_mshrs 916364836 # number of cycles access was blocked 760system.cpu.dcache.blocked_cycles::no_targets 209000 # number of cycles access was blocked 761system.cpu.dcache.blocked::no_mshrs 100291 # number of cycles access was blocked 762system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 763system.cpu.dcache.avg_blocked_cycles::no_mshrs 9137.059517 # average number of cycles each access was blocked 764system.cpu.dcache.avg_blocked_cycles::no_targets 23222.222222 # average number of cycles each access was blocked 765system.cpu.dcache.fast_writes 0 # number of fast writes performed 766system.cpu.dcache.cache_copies 0 # number of cache copies performed 767system.cpu.dcache.writebacks 834833 # number of writebacks 768system.cpu.dcache.ReadReq_mshr_hits 691203 # number of ReadReq MSHR hits 769system.cpu.dcache.WriteReq_mshr_hits 1635634 # number of WriteReq MSHR hits 770system.cpu.dcache.LoadLockedReq_mshr_hits 5726 # number of LoadLockedReq MSHR hits 771system.cpu.dcache.demand_mshr_hits 2326837 # number of demand (read+write) MSHR hits 772system.cpu.dcache.overall_mshr_hits 2326837 # number of overall MSHR hits 773system.cpu.dcache.ReadReq_mshr_misses 1087666 # number of ReadReq MSHR misses 774system.cpu.dcache.WriteReq_mshr_misses 298810 # number of WriteReq MSHR misses 775system.cpu.dcache.LoadLockedReq_mshr_misses 17536 # number of LoadLockedReq MSHR misses 776system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses 777system.cpu.dcache.demand_mshr_misses 1386476 # number of demand (read+write) MSHR misses 778system.cpu.dcache.overall_mshr_misses 1386476 # number of overall MSHR misses 779system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 780system.cpu.dcache.ReadReq_mshr_miss_latency 24813377000 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency 8487477836 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207860000 # number of LoadLockedReq MSHR miss cycles 783system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles 784system.cpu.dcache.demand_mshr_miss_latency 33300854836 # number of demand (read+write) MSHR miss cycles 785system.cpu.dcache.overall_mshr_miss_latency 33300854836 # number of overall MSHR miss cycles 786system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904007000 # number of ReadReq MSHR uncacheable cycles 787system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234009498 # number of WriteReq MSHR uncacheable cycles 788system.cpu.dcache.overall_mshr_uncacheable_latency 2138016498 # number of overall MSHR uncacheable cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117303 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 791system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048529 # mshr miss rate for WriteReq accesses 793system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 794system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 795system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081447 # mshr miss rate for LoadLockedReq accesses 796system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 797system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 798system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses 799system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 800system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 801system.cpu.dcache.demand_mshr_miss_rate::0 0.089858 # mshr miss rate for demand accesses 802system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 803system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 804system.cpu.dcache.overall_mshr_miss_rate::0 0.089858 # mshr miss rate for overall accesses 805system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 806system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22813.416067 # average ReadReq mshr miss latency 808system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28404.263030 # average WriteReq mshr miss latency 809system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11853.330292 # average LoadLockedReq mshr miss latency 810system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency 811system.cpu.dcache.demand_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency 812system.cpu.dcache.overall_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency 813system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 814system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 816system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 817system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 818system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 819system.cpu.kern.inst.arm 0 # number of arm instructions executed 820system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed 821system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed 822system.cpu.kern.ipl_count::0 74884 40.96% 40.96% # number of times we switched to this ipl 823system.cpu.kern.ipl_count::21 241 0.13% 41.09% # number of times we switched to this ipl 824system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl 825system.cpu.kern.ipl_count::31 105815 57.88% 100.00% # number of times we switched to this ipl 826system.cpu.kern.ipl_count::total 182822 # number of times we switched to this ipl 827system.cpu.kern.ipl_good::0 73517 49.29% 49.29% # number of times we switched to this ipl from a different ipl 828system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl 829system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl 830system.cpu.kern.ipl_good::31 73519 49.29% 100.00% # number of times we switched to this ipl from a different ipl 831system.cpu.kern.ipl_good::total 149159 # number of times we switched to this ipl from a different ipl 832system.cpu.kern.ipl_ticks::0 1820013648500 97.92% 97.92% # number of cycles we spent at this ipl 833system.cpu.kern.ipl_ticks::21 93762000 0.01% 97.92% # number of cycles we spent at this ipl 834system.cpu.kern.ipl_ticks::22 384408000 0.02% 97.94% # number of cycles we spent at this ipl 835system.cpu.kern.ipl_ticks::31 38216235500 2.06% 100.00% # number of cycles we spent at this ipl 836system.cpu.kern.ipl_ticks::total 1858708054000 # number of cycles we spent at this ipl 837system.cpu.kern.ipl_used::0 0.981745 # fraction of swpipl calls that actually changed the ipl 838system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 839system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 840system.cpu.kern.ipl_used::31 0.694788 # fraction of swpipl calls that actually changed the ipl 841system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 842system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 843system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 844system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 845system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 846system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 847system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 848system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 849system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 850system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 851system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 852system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 853system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 854system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 855system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 856system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 857system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 858system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 859system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 860system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 861system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 862system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 863system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 864system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 865system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 866system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 867system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 868system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 869system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 870system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 871system.cpu.kern.syscall::total 326 # number of syscalls executed 872system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 873system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 874system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 875system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 876system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 877system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 878system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 879system.cpu.kern.callpal::swpipl 175485 91.19% 93.39% # number of callpals executed 880system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed 881system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 882system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 883system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 884system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 885system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed 886system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 887system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 888system.cpu.kern.callpal::total 192443 # number of callpals executed 889system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches 890system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 891system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches 892system.cpu.kern.mode_good::kernel 1908 893system.cpu.kern.mode_good::user 1738 894system.cpu.kern.mode_good::idle 170 895system.cpu.kern.mode_switch_good::kernel 0.320349 # fraction of useful protection mode switches 896system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 897system.cpu.kern.mode_switch_good::idle 0.080914 # fraction of useful protection mode switches 898system.cpu.kern.mode_switch_good::total 1.401263 # fraction of useful protection mode switches 899system.cpu.kern.mode_ticks::kernel 29483328500 1.59% 1.59% # number of ticks spent at the given mode 900system.cpu.kern.mode_ticks::user 2787065000 0.15% 1.74% # number of ticks spent at the given mode 901system.cpu.kern.mode_ticks::idle 1826437652500 98.26% 100.00% # number of ticks spent at the given mode 902system.cpu.kern.swap_context 4177 # number of times the context was actually changed 903 904---------- End Simulation Statistics ---------- 905