stats.txt revision 6980
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 86499 # Simulator instruction rate (inst/s) 4host_mem_usage 277924 # Number of bytes of host memory used 5host_seconds 613.76 # Real time elapsed on the host 6host_tick_rate 3042478511 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 53090223 # Number of instructions simulated 9sim_seconds 1.867363 # Number of seconds simulated 10sim_ticks 1867362977500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 8461925 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 100629475 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.559325 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.322901 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0-1 76387036 75.91% 75.91% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1-2 10760374 10.69% 86.60% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2-3 5981089 5.94% 92.55% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3-4 2990150 2.97% 95.52% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4-5 2079430 2.07% 97.58% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5-6 662647 0.66% 98.24% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6-7 398739 0.40% 98.64% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7-8 391912 0.39% 99.03% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 978098 0.97% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 100629475 # Number of insts commited each cycle 39system.cpu.commit.COM:count 56284559 # Number of instructions committed 40system.cpu.commit.COM:loads 9308572 # Number of loads committed 41system.cpu.commit.COM:membars 228000 # Number of memory barriers committed 42system.cpu.commit.COM:refs 15700770 # Number of memory references committed 43system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 44system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted 45system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions 46system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards 47system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit 48system.cpu.committedInsts 53090223 # Number of Instructions Simulated 49system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated 50system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction 51system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads 52system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses) 53system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses) 54system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency 55system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency 56system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency 57system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency 58system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits 59system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits 60system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles 61system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses 62system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses 63system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses 64system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits 65system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles 66system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses 67system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses 68system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses 69system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses 70system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses) 71system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses) 72system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency 73system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 74system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 75system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency 76system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 77system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits 78system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits 79system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles 80system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses 81system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses 82system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses 83system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits 84system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles 85system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses 86system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 87system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 88system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses 89system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles 90system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses) 91system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses) 92system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency 93system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency 94system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency 95system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency 96system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits 97system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits 98system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles 99system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses 100system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses 101system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses 102system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles 103system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses 104system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses 105system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses 106system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses 107system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses) 108system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses) 109system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency 110system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 111system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 112system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency 113system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 114system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits 115system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits 116system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles 117system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses 118system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses 119system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses 120system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits 121system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles 122system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses 123system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 124system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 125system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses 126system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles 127system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked 128system.cpu.dcache.avg_blocked_cycles::no_targets 16500 # average number of cycles each access was blocked 129system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. 130system.cpu.dcache.blocked::no_mshrs 137083 # number of cycles access was blocked 131system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 132system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked 133system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked 134system.cpu.dcache.cache_copies 0 # number of cache copies performed 135system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses 136system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 137system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses 138system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency 139system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 140system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 141system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency 142system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits 143system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 144system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits 145system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles 146system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses 147system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 148system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 149system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses 150system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 151system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses 152system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits 153system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles 154system.cpu.dcache.demand_mshr_miss_rate::0 0.095600 # mshr miss rate for demand accesses 155system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 156system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 157system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses 158system.cpu.dcache.fast_writes 0 # number of fast writes performed 159system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 160system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 161system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy 162system.cpu.dcache.occ_blocks::0 511.995450 # Average occupied blocks per context 163system.cpu.dcache.overall_accesses::0 15499631 # number of overall (read+write) accesses 164system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 165system.cpu.dcache.overall_accesses::total 15499631 # number of overall (read+write) accesses 166system.cpu.dcache.overall_avg_miss_latency::0 38794.252006 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 168system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 169system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency 170system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 171system.cpu.dcache.overall_hits::0 11736725 # number of overall hits 172system.cpu.dcache.overall_hits::1 0 # number of overall hits 173system.cpu.dcache.overall_hits::total 11736725 # number of overall hits 174system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles 175system.cpu.dcache.overall_miss_rate::0 0.242774 # miss rate for overall accesses 176system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 177system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 178system.cpu.dcache.overall_misses::0 3762906 # number of overall misses 179system.cpu.dcache.overall_misses::1 0 # number of overall misses 180system.cpu.dcache.overall_misses::total 3762906 # number of overall misses 181system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits 182system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles 183system.cpu.dcache.overall_mshr_miss_rate::0 0.095600 # mshr miss rate for overall accesses 184system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 185system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 186system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses 187system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles 188system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 189system.cpu.dcache.replacements 1402110 # number of replacements 190system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks. 191system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 192system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use 193system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks. 194system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. 195system.cpu.dcache.writebacks 430447 # number of writebacks 196system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked 197system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction 198system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch 199system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode 200system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle 201system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running 202system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing 203system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode 204system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking 205system.cpu.dtb.data_accesses 1236133 # DTB accesses 206system.cpu.dtb.data_acv 823 # DTB access violations 207system.cpu.dtb.data_hits 16770289 # DTB hits 208system.cpu.dtb.data_misses 44393 # DTB misses 209system.cpu.dtb.fetch_accesses 0 # ITB accesses 210system.cpu.dtb.fetch_acv 0 # ITB acv 211system.cpu.dtb.fetch_hits 0 # ITB hits 212system.cpu.dtb.fetch_misses 0 # ITB misses 213system.cpu.dtb.read_accesses 909859 # DTB read accesses 214system.cpu.dtb.read_acv 588 # DTB read access violations 215system.cpu.dtb.read_hits 10173052 # DTB read hits 216system.cpu.dtb.read_misses 36219 # DTB read misses 217system.cpu.dtb.write_accesses 326274 # DTB write accesses 218system.cpu.dtb.write_acv 235 # DTB write access violations 219system.cpu.dtb.write_hits 6597237 # DTB write hits 220system.cpu.dtb.write_misses 8174 # DTB write misses 221system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered 222system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched 223system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked 224system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed 225system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed 226system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 227system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing 228system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle 229system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss 230system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken 231system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle 232system.cpu.fetch.rateDist::samples 102272708 # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::mean 0.726149 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::stdev 2.019798 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::0-1 87829962 85.88% 85.88% # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::1-2 1051726 1.03% 86.91% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::2-3 2021481 1.98% 88.88% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::3-4 968950 0.95% 89.83% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::4-5 2998384 2.93% 92.76% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::5-6 688876 0.67% 93.44% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::6-7 831559 0.81% 94.25% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::7-8 1217734 1.19% 95.44% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::8 4664036 4.56% 100.00% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) 249system.cpu.icache.ReadReq_accesses::0 8997144 # number of ReadReq accesses(hits+misses) 250system.cpu.icache.ReadReq_accesses::total 8997144 # number of ReadReq accesses(hits+misses) 251system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449 # average ReadReq miss latency 252system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 253system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 254system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency 255system.cpu.icache.ReadReq_hits::0 7949609 # number of ReadReq hits 256system.cpu.icache.ReadReq_hits::total 7949609 # number of ReadReq hits 257system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles 258system.cpu.icache.ReadReq_miss_rate::0 0.116430 # miss rate for ReadReq accesses 259system.cpu.icache.ReadReq_misses::0 1047535 # number of ReadReq misses 260system.cpu.icache.ReadReq_misses::total 1047535 # number of ReadReq misses 261system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits 262system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles 263system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110664 # mshr miss rate for ReadReq accesses 264system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 266system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses 267system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked 268system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 269system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. 270system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked 271system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked 273system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.cache_copies 0 # number of cache copies performed 275system.cpu.icache.demand_accesses::0 8997144 # number of demand (read+write) accesses 276system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 277system.cpu.icache.demand_accesses::total 8997144 # number of demand (read+write) accesses 278system.cpu.icache.demand_avg_miss_latency::0 14906.743449 # average overall miss latency 279system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 280system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 281system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency 282system.cpu.icache.demand_hits::0 7949609 # number of demand (read+write) hits 283system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 284system.cpu.icache.demand_hits::total 7949609 # number of demand (read+write) hits 285system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles 286system.cpu.icache.demand_miss_rate::0 0.116430 # miss rate for demand accesses 287system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 288system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 289system.cpu.icache.demand_misses::0 1047535 # number of demand (read+write) misses 290system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 291system.cpu.icache.demand_misses::total 1047535 # number of demand (read+write) misses 292system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits 293system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles 294system.cpu.icache.demand_mshr_miss_rate::0 0.110664 # mshr miss rate for demand accesses 295system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 296system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 297system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses 298system.cpu.icache.fast_writes 0 # number of fast writes performed 299system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 300system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 301system.cpu.icache.occ_%::0 0.995649 # Average percentage of cache occupancy 302system.cpu.icache.occ_blocks::0 509.772438 # Average occupied blocks per context 303system.cpu.icache.overall_accesses::0 8997144 # number of overall (read+write) accesses 304system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 305system.cpu.icache.overall_accesses::total 8997144 # number of overall (read+write) accesses 306system.cpu.icache.overall_avg_miss_latency::0 14906.743449 # average overall miss latency 307system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 308system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 311system.cpu.icache.overall_hits::0 7949609 # number of overall hits 312system.cpu.icache.overall_hits::1 0 # number of overall hits 313system.cpu.icache.overall_hits::total 7949609 # number of overall hits 314system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles 315system.cpu.icache.overall_miss_rate::0 0.116430 # miss rate for overall accesses 316system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 317system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 318system.cpu.icache.overall_misses::0 1047535 # number of overall misses 319system.cpu.icache.overall_misses::1 0 # number of overall misses 320system.cpu.icache.overall_misses::total 1047535 # number of overall misses 321system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits 322system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles 323system.cpu.icache.overall_mshr_miss_rate::0 0.110664 # mshr miss rate for overall accesses 324system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 325system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 326system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses 327system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 328system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 329system.cpu.icache.replacements 994957 # number of replacements 330system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks. 331system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 332system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use 333system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks. 334system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. 335system.cpu.icache.writebacks 0 # number of writebacks 336system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling 337system.cpu.iew.EXEC:branches 9164165 # Number of branches executed 338system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed 339system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate 340system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed 341system.cpu.iew.EXEC:stores 6620337 # Number of stores executed 342system.cpu.iew.EXEC:swp 0 # number of swp insts executed 343system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value 344system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back 345system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back 346system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 347system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 348system.cpu.iew.WB:producers 26380221 # num instructions producing a value 349system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle 350system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit 351system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute 352system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking 353system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions 354system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions 355system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch 356system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions 357system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ 358system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed 359system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute 360system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions 361system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall 362system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 363system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall 364system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing 365system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking 366system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 367system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked 368system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores 369system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed 370system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 371system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 372system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations 373system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled 374system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed 375system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed 376system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations 377system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly 378system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly 379system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle 380system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads 381system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7284 0.01% 0.01% # Type of FU issued 382system.cpu.iq.ISSUE:FU_type_0::IntAlu 39611417 68.15% 68.16% # Type of FU issued 383system.cpu.iq.ISSUE:FU_type_0::IntMult 62110 0.11% 68.27% # Type of FU issued 384system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued 385system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued 386system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued 387system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued 388system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued 389system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued 390system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued 391system.cpu.iq.ISSUE:FU_type_0::MemRead 10788116 18.56% 86.88% # Type of FU issued 392system.cpu.iq.ISSUE:FU_type_0::MemWrite 6673339 11.48% 98.36% # Type of FU issued 393system.cpu.iq.ISSUE:FU_type_0::IprAccess 953263 1.64% 100.00% # Type of FU issued 394system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 395system.cpu.iq.ISSUE:FU_type_0::total 58124772 # Type of FU issued 396system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested 397system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) 398system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 399system.cpu.iq.ISSUE:fu_full::IntAlu 50716 11.71% 11.71% # attempts to use FU when none available 400system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available 401system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available 402system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available 403system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available 404system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available 405system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available 406system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available 407system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available 408system.cpu.iq.ISSUE:fu_full::MemRead 279321 64.50% 76.21% # attempts to use FU when none available 409system.cpu.iq.ISSUE:fu_full::MemWrite 103014 23.79% 100.00% # attempts to use FU when none available 410system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 # Number of insts issued each cycle 413system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 # Number of insts issued each cycle 414system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 # Number of insts issued each cycle 415system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 416system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% 71.52% # Number of insts issued each cycle 417system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% 85.85% # Number of insts issued each cycle 418system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% 92.12% # Number of insts issued each cycle 419system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% 95.96% # Number of insts issued each cycle 420system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% 98.43% # Number of insts issued each cycle 421system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% 99.44% # Number of insts issued each cycle 422system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% 99.87% # Number of insts issued each cycle 423system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% 99.98% # Number of insts issued each cycle 424system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% 100.00% # Number of insts issued each cycle 425system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 426system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 427system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 428system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 # Number of insts issued each cycle 429system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate 430system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) 431system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued 432system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ 433system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling 434system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued 435system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed 436system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph 437system.cpu.itb.data_accesses 0 # DTB accesses 438system.cpu.itb.data_acv 0 # DTB access violations 439system.cpu.itb.data_hits 0 # DTB hits 440system.cpu.itb.data_misses 0 # DTB misses 441system.cpu.itb.fetch_accesses 1303750 # ITB accesses 442system.cpu.itb.fetch_acv 951 # ITB acv 443system.cpu.itb.fetch_hits 1264322 # ITB hits 444system.cpu.itb.fetch_misses 39428 # ITB misses 445system.cpu.itb.read_accesses 0 # DTB read accesses 446system.cpu.itb.read_acv 0 # DTB read access violations 447system.cpu.itb.read_hits 0 # DTB read hits 448system.cpu.itb.read_misses 0 # DTB read misses 449system.cpu.itb.write_accesses 0 # DTB write accesses 450system.cpu.itb.write_acv 0 # DTB write access violations 451system.cpu.itb.write_hits 0 # DTB write hits 452system.cpu.itb.write_misses 0 # DTB write misses 453system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 454system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 455system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 456system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 457system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 458system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 459system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 460system.cpu.kern.callpal::swpipl 175681 91.19% 93.39% # number of callpals executed 461system.cpu.kern.callpal::rdps 6794 3.53% 96.92% # number of callpals executed 462system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 463system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 464system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 465system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 466system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed 467system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 468system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 469system.cpu.kern.callpal::total 192652 # number of callpals executed 470system.cpu.kern.inst.arm 0 # number of arm instructions executed 471system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed 472system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed 473system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl 474system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl 475system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl 476system.cpu.kern.ipl_count::31 105947 57.89% 100.00% # number of times we switched to this ipl 477system.cpu.kern.ipl_count::total 183030 # number of times we switched to this ipl 478system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl 479system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl 480system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl 481system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl 482system.cpu.kern.ipl_good::total 149305 # number of times we switched to this ipl from a different ipl 483system.cpu.kern.ipl_ticks::0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl 484system.cpu.kern.ipl_ticks::21 102621000 0.01% 97.72% # number of cycles we spent at this ipl 485system.cpu.kern.ipl_ticks::22 392338000 0.02% 97.75% # number of cycles we spent at this ipl 486system.cpu.kern.ipl_ticks::31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl 487system.cpu.kern.ipl_ticks::total 1867362103000 # number of cycles we spent at this ipl 488system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl 489system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 490system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 491system.cpu.kern.ipl_used::31 0.694583 # fraction of swpipl calls that actually changed the ipl 492system.cpu.kern.mode_good::kernel 1910 493system.cpu.kern.mode_good::user 1740 494system.cpu.kern.mode_good::idle 170 495system.cpu.kern.mode_switch::kernel 5972 # number of protection mode switches 496system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 497system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 498system.cpu.kern.mode_switch_good::kernel 0.319826 # fraction of useful protection mode switches 499system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 500system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 501system.cpu.kern.mode_switch_good::total 1.400971 # fraction of useful protection mode switches 502system.cpu.kern.mode_ticks::kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode 503system.cpu.kern.mode_ticks::user 3191204500 0.17% 1.85% # number of ticks spent at the given mode 504system.cpu.kern.mode_ticks::idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode 505system.cpu.kern.swap_context 4177 # number of times the context was actually changed 506system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 507system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 508system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 509system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 510system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 511system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 512system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 513system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 514system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 515system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 516system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 517system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 518system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 519system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 520system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 521system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 522system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 523system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 524system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 525system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 526system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 527system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 528system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 529system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 530system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 531system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 532system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 533system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 534system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 535system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 536system.cpu.kern.syscall::total 326 # number of syscalls executed 537system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. 538system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. 539system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. 540system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit. 541system.cpu.numCycles 136997789 # number of cpu cycles simulated 542system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking 543system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed 544system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full 545system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle 546system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full 547system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full 548system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made 549system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename 550system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed 551system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running 552system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing 553system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking 554system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing 555system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst 556system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed 557system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer 558system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed 559system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself 560system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 561system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 562system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 563system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 564system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 565system.disk0.dma_write_txs 395 # Number of DMA write transactions. 566system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 567system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 568system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 569system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 570system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 571system.disk2.dma_write_txs 1 # Number of DMA write transactions. 572system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) 573system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 574system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 575system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency 576system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 577system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency 578system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles 579system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 580system.iocache.ReadReq_misses::1 173 # number of ReadReq misses 581system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 582system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles 583system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 584system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 585system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 586system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses 587system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 588system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 589system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 590system.iocache.WriteReq_avg_miss_latency::1 137794.253129 # average WriteReq miss latency 591system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 592system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency 593system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles 594system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 595system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 596system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 597system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles 598system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 599system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 600system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 601system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses 602system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked 603system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 604system.iocache.avg_refs 0 # Average number of references to valid blocks. 605system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked 606system.iocache.blocked::no_targets 0 # number of cycles access was blocked 607system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked 608system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 609system.iocache.cache_copies 0 # number of cache copies performed 610system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 611system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses 612system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 613system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 614system.iocache.demand_avg_miss_latency::1 137700.822145 # average overall miss latency 615system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 616system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency 617system.iocache.demand_hits::0 0 # number of demand (read+write) hits 618system.iocache.demand_hits::1 0 # number of demand (read+write) hits 619system.iocache.demand_hits::total 0 # number of demand (read+write) hits 620system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles 621system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 622system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 623system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 624system.iocache.demand_misses::0 0 # number of demand (read+write) misses 625system.iocache.demand_misses::1 41725 # number of demand (read+write) misses 626system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 627system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 628system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles 629system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 630system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 631system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 632system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses 633system.iocache.fast_writes 0 # number of fast writes performed 634system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 635system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 636system.iocache.occ_%::1 0.079213 # Average percentage of cache occupancy 637system.iocache.occ_blocks::1 1.267415 # Average occupied blocks per context 638system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 639system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses 640system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 641system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 642system.iocache.overall_avg_miss_latency::1 137700.822145 # average overall miss latency 643system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 644system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency 645system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 646system.iocache.overall_hits::0 0 # number of overall hits 647system.iocache.overall_hits::1 0 # number of overall hits 648system.iocache.overall_hits::total 0 # number of overall hits 649system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles 650system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 651system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 652system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 653system.iocache.overall_misses::0 0 # number of overall misses 654system.iocache.overall_misses::1 41725 # number of overall misses 655system.iocache.overall_misses::total 41725 # number of overall misses 656system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 657system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles 658system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 659system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 660system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 661system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses 662system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 663system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 664system.iocache.replacements 41685 # number of replacements 665system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 666system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 667system.iocache.tagsinuse 1.267415 # Cycle average of tags in use 668system.iocache.total_refs 0 # Total number of references to valid blocks. 669system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. 670system.iocache.writebacks 41512 # number of writebacks 671system.l2c.ReadExReq_accesses::0 300582 # number of ReadExReq accesses(hits+misses) 672system.l2c.ReadExReq_accesses::total 300582 # number of ReadExReq accesses(hits+misses) 673system.l2c.ReadExReq_avg_miss_latency::0 52361.965557 # average ReadExReq miss latency 674system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 675system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 676system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency 677system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles 678system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses 679system.l2c.ReadExReq_misses::0 300582 # number of ReadExReq misses 680system.l2c.ReadExReq_misses::total 300582 # number of ReadExReq misses 681system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles 682system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses 683system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 684system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 685system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses 686system.l2c.ReadReq_accesses::0 2097743 # number of ReadReq accesses(hits+misses) 687system.l2c.ReadReq_accesses::total 2097743 # number of ReadReq accesses(hits+misses) 688system.l2c.ReadReq_avg_miss_latency::0 52046.745492 # average ReadReq miss latency 689system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 690system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 691system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency 692system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 693system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits 694system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits 695system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles 696system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses 697system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses 698system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses 699system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits 700system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles 701system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses 702system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 703system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 704system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses 705system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles 706system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses) 707system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses) 708system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency 709system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 710system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 711system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency 712system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles 713system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses 714system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses 715system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses 716system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles 717system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses 718system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 719system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 720system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses 721system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 722system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles 723system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses) 724system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses) 725system.l2c.Writeback_hits::0 430447 # number of Writeback hits 726system.l2c.Writeback_hits::total 430447 # number of Writeback hits 727system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 728system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 729system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. 730system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 731system.l2c.blocked::no_targets 0 # number of cycles access was blocked 732system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.l2c.cache_copies 0 # number of cache copies performed 735system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses 736system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 737system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses 738system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency 739system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency 740system.l2c.demand_avg_miss_latency::total inf # average overall miss latency 741system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency 742system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits 743system.l2c.demand_hits::1 0 # number of demand (read+write) hits 744system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits 745system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles 746system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses 747system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 748system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 749system.l2c.demand_misses::0 611735 # number of demand (read+write) misses 750system.l2c.demand_misses::1 0 # number of demand (read+write) misses 751system.l2c.demand_misses::total 611735 # number of demand (read+write) misses 752system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits 753system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles 754system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses 755system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 756system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 757system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses 758system.l2c.fast_writes 0 # number of fast writes performed 759system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 760system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 761system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy 762system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy 763system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context 764system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context 765system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses 766system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 767system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses 768system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency 769system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency 770system.l2c.overall_avg_miss_latency::total inf # average overall miss latency 771system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency 772system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 773system.l2c.overall_hits::0 1786590 # number of overall hits 774system.l2c.overall_hits::1 0 # number of overall hits 775system.l2c.overall_hits::total 1786590 # number of overall hits 776system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles 777system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses 778system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 779system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 780system.l2c.overall_misses::0 611735 # number of overall misses 781system.l2c.overall_misses::1 0 # number of overall misses 782system.l2c.overall_misses::total 611735 # number of overall misses 783system.l2c.overall_mshr_hits 1 # number of overall MSHR hits 784system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles 785system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses 786system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 787system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 788system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses 789system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles 790system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 791system.l2c.replacements 396039 # number of replacements 792system.l2c.sampled_refs 427720 # Sample count of references to valid blocks. 793system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 794system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use 795system.l2c.total_refs 1966597 # Total number of references to valid blocks. 796system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. 797system.l2c.writebacks 119094 # number of writebacks 798system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 799system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 800system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 801system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 802system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 803system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 804system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 805system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 806system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 807system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 808system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 809system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 810system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 811system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 812system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 813system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 814system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 815system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 816system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 817system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 818system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 819system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 820system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 821system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 822system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 823system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 824system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 825system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 826system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 827system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 828system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 829 830---------- End Simulation Statistics ---------- 831