xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.876794                       # Number of seconds simulated
sim_ticks                                1876794488000                       # Number of ticks simulated
final_tick                               1876794488000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 164316                       # Simulator instruction rate (inst/s)
host_op_rate                                   164316                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5820514836                       # Simulator tick rate (ticks/s)
host_mem_usage                                 335448                       # Number of bytes of host memory used
host_seconds                                   322.44                       # Real time elapsed on the host
sim_insts                                    52982943                       # Number of instructions simulated
sim_ops                                      52982943                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            961728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24880448                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             25843136                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       961728                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          961728                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7527680                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7527680                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15027                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388757                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                403799                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117620                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117620                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               512431                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13256885                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide               512                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13769827                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          512431                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             512431                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4010924                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4010924                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4010924                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              512431                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13256885                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide              512                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               17780751                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        403799                       # Number of read requests accepted
system.physmem.writeReqs                       117620                       # Number of write requests accepted
system.physmem.readBursts                      403799                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     117620                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 25835776                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7525824                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  25843136                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7527680                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               25625                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25421                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25559                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25464                       # Per bank write bursts
system.physmem.perBankRdBursts::4               25431                       # Per bank write bursts
system.physmem.perBankRdBursts::5               24732                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24935                       # Per bank write bursts
system.physmem.perBankRdBursts::7               25090                       # Per bank write bursts
system.physmem.perBankRdBursts::8               24946                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25020                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25560                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24886                       # Per bank write bursts
system.physmem.perBankRdBursts::12              24460                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25266                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25703                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25586                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7949                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7513                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7969                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7485                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7367                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6667                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6767                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6715                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7150                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6697                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7421                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6978                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7150                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7899                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8060                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7804                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    1876789160500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  403799                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117620                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    315619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     35764                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     28247                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     23961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        77                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4960                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6949                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6473                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7602                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5823                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        62139                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      536.886657                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     331.247155                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     411.697741                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          13677     22.01%     22.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10478     16.86%     38.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4968      7.99%     46.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2775      4.47%     51.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2441      3.93%     55.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1588      2.56%     57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3776      6.08%     63.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1174      1.89%     65.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        21262     34.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          62139                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5217                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        77.374545                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2903.927058                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           5214     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5217                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5217                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        22.539965                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.244136                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.635763                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4619     88.54%     88.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31              29      0.56%     89.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39              25      0.48%     89.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              38      0.73%     90.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             214      4.10%     94.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63               9      0.17%     94.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              11      0.21%     94.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              34      0.65%     95.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             184      3.53%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               5      0.10%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              5      0.10%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             4      0.08%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135             6      0.12%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             1      0.02%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             1      0.02%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             4      0.08%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             8      0.15%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             4      0.08%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             3      0.06%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             2      0.04%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             2      0.04%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             6      0.12%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             2      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5217                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4201005000                       # Total ticks spent queuing
system.physmem.totMemAccLat               11770080000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2018420000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10406.67                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29156.67                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.98                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.46                       # Average write queue length when enqueuing
system.physmem.readRowHits                     363845                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95291                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.13                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.02                       # Row buffer hit rate for writes
system.physmem.avgGap                      3599387.75                       # Average gap between requests
system.physmem.pageHitRate                      88.07                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  233399880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  127351125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1577604600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                378639360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           122582793840                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            61740410985                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1071915840750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1258556040540                       # Total energy per rank (pJ)
system.physmem_0.averagePower              670.589641                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   1783024934000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     62670140000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31095099750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  236370960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  128972250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1571130600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                383350320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           122582793840                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            61477234290                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1072146705750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1258526558010                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.573928                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   1783410314000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     62670140000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30709733500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                19569408                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16632311                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            593173                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             12870136                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5420664                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             42.118156                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1123230                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              42865                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         6372302                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             563108                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          5809194                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       264983                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     11131372                       # DTB read hits
system.cpu.dtb.read_misses                      49301                       # DTB read misses
system.cpu.dtb.read_acv                           623                       # DTB read access violations
system.cpu.dtb.read_accesses                   996761                       # DTB read accesses
system.cpu.dtb.write_hits                     6776847                       # DTB write hits
system.cpu.dtb.write_misses                     12217                       # DTB write misses
system.cpu.dtb.write_acv                          418                       # DTB write access violations
system.cpu.dtb.write_accesses                  345142                       # DTB write accesses
system.cpu.dtb.data_hits                     17908219                       # DTB hits
system.cpu.dtb.data_misses                      61518                       # DTB misses
system.cpu.dtb.data_acv                          1041                       # DTB access violations
system.cpu.dtb.data_accesses                  1341903                       # DTB accesses
system.cpu.itb.fetch_hits                     1817383                       # ITB hits
system.cpu.itb.fetch_misses                     10321                       # ITB misses
system.cpu.itb.fetch_acv                          767                       # ITB acv
system.cpu.itb.fetch_accesses                 1827704                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        155167561                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30150844                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85742172                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    19569408                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            7107002                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     116772481                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1681668                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                         87                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                29150                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        207083                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       421165                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          751                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9930605                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                406777                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          148422395                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.577690                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.864310                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                132578342     89.33%     89.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1033201      0.70%     90.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2106811      1.42%     91.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   971505      0.65%     92.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2908700      1.96%     94.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   663530      0.45%     94.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   808471      0.54%     95.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1037122      0.70%     95.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  6314713      4.25%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            148422395                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.126118                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.552578                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 24118440                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             111208587                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  10245196                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2044112                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 806059                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               738327                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 35573                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               74062953                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                114064                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 806059                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25129468                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                79314805                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       20217508                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11209636                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              11744917                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               71031430                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                202187                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2134257                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 304114                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                7385918                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands            47856784                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              85577316                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         85396639                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            168224                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38182032                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  9674744                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1729903                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         277398                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13945265                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             11667584                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             7222268                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1740236                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1128330                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   62719117                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2208284                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  60532785                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             94680                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        11944453                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      5319004                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1547012                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     148422395                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.407841                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.141989                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           123871811     83.46%     83.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10428219      7.03%     90.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             4419616      2.98%     93.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3188761      2.15%     95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             3243069      2.19%     97.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1605515      1.08%     98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1096686      0.74%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              430660      0.29%     99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              138058      0.09%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       148422395                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  206261     16.62%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.62% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 637065     51.34%     67.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                397617     32.04%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7280      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              40910867     67.58%     67.60% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                62087      0.10%     67.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               38559      0.06%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.77% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             11677582     19.29%     87.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6883616     11.37%     98.43% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949158      1.57%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               60532785                       # Type of FU issued
system.cpu.iq.rate                           0.390112                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1240943                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.020500                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          270086631                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          76534291                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     58304379                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              736956                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             359180                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       336827                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               61370896                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  395552                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           686477                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2574541                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         4210                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        22293                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       843973                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        18024                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        466103                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 806059                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                75493298                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1202730                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            68906340                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            204916                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              11667584                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              7222268                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1958885                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  46577                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                953145                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          22293                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         228745                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       630471                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               859216                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              59676170                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              11213777                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            856614                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3978939                       # number of nop insts executed
system.cpu.iew.exec_refs                     18023142                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  9384066                       # Number of branches executed
system.cpu.iew.exec_stores                    6809365                       # Number of stores executed
system.cpu.iew.exec_rate                     0.384592                       # Inst execution rate
system.cpu.iew.wb_sent                       58885265                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      58641206                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  29760600                       # num instructions producing a value
system.cpu.iew.wb_consumers                  41260135                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.377922                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.721292                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        12542077                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          661272                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            769434                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    146251910                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.384089                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.283290                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    126403677     86.43%     86.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      7969213      5.45%     91.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4187918      2.86%     94.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2256490      1.54%     96.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1756984      1.20%     97.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       633259      0.43%     97.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       482491      0.33%     98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       524954      0.36%     98.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2036924      1.39%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    146251910                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56173766                       # Number of instructions committed
system.cpu.commit.committedOps               56173766                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15471338                       # Number of memory references committed
system.cpu.commit.loads                       9093043                       # Number of loads committed
system.cpu.commit.membars                      226379                       # Number of memory barriers committed
system.cpu.commit.branches                    8441154                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52023017                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740601                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      3198096      5.69%      5.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         36220454     64.48%     70.17% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           60663      0.11%     70.28% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead         9319422     16.59%     86.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        6384252     11.37%     98.31% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess        949158      1.69%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          56173766                       # Class of committed instruction
system.cpu.commit.bw_lim_events               2036924                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    212681294                       # The number of ROB reads
system.cpu.rob.rob_writes                   139606986                       # The number of ROB writes
system.cpu.timesIdled                          557347                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         6745166                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3598421416                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52982943                       # Number of Instructions Simulated
system.cpu.committedOps                      52982943                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               2.928632                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.928632                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.341456                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.341456                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 77864960                       # number of integer regfile reads
system.cpu.int_regfile_writes                42584488                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166613                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   175794                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 2001927                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 939529                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1405900                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.992670                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            12627832                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1406412                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              8.978757                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          36569500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.992670                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          414                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          67144149                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         67144149                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      8017767                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         8017767                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4181578                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4181578                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       212474                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       212474                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215675                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215675                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      12199345                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         12199345                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     12199345                       # number of overall hits
system.cpu.dcache.overall_hits::total        12199345                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1817411                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1817411                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1966241                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1966241                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        23192                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        23192                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           96                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           96                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3783652                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3783652                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3783652                       # number of overall misses
system.cpu.dcache.overall_misses::total       3783652                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  57696836500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  57696836500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 116764719993                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    411714000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    411714000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data      1875000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total      1875000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 174461556493                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 174461556493                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 174461556493                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 174461556493                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9835178                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9835178                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6147819                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6147819                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       235666                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       235666                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215771                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215771                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15982997                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15982997                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15982997                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15982997                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184787                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.184787                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319827                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.319827                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.098410                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.098410                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000445                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000445                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.236730                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.236730                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.236730                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.236730                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46109.302994                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46109.302994                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      7149027                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         5119                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs            133846                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              35                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.412332                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   146.257143                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       843569                       # number of writebacks
system.cpu.dcache.writebacks::total            843569                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       717041                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       717041                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1676919                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1676919                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6351                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         6351                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2393960                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2393960                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2393960                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2393960                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1100370                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1100370                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289322                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289322                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16841                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        16841                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           96                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           96                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1389692                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1389692                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1389692                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1389692                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44732838000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  44732838000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18336828964                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  18336828964                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    214607500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    214607500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data      1779000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total      1779000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63069666964                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  63069666964                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63069666964                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  63069666964                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528639000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528639000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2154562000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2154562000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3683201000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3683201000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111881                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111881                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047061                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047061                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.071461                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.071461                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000445                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000445                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.086948                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.086948                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.086948                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.086948                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1074186                       # number of replacements
system.cpu.icache.tags.tagsinuse           507.868793                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8786985                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1074694                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.176267                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       42323300500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   507.868793                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.991931                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.991931                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          366                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          11005600                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         11005600                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8786985                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8786985                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8786985                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8786985                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8786985                       # number of overall hits
system.cpu.icache.overall_hits::total         8786985                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1143615                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1143615                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1143615                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1143615                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1143615                       # number of overall misses
system.cpu.icache.overall_misses::total       1143615                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  17001547978                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  17001547978                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  17001547978                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  17001547978                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  17001547978                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  17001547978                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9930600                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9930600                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9930600                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9930600                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9930600                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9930600                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115161                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.115161                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.115161                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.115161                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.115161                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.115161                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14866.496136                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14866.496136                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        12933                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               342                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    37.815789                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks      1074186                       # number of writebacks
system.cpu.icache.writebacks::total           1074186                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68615                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        68615                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        68615                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        68615                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        68615                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        68615                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1075000                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1075000                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1075000                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1075000                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1075000                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1075000                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14900351984                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  14900351984                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14900351984                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  14900351984                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14900351984                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  14900351984                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108251                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.108251                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.108251                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           338591                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65285.567334                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4253578                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           403759                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            10.534943                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       9186566000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5255.268427                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  7006.243291                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.809083                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080189                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.106907                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996179                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3471                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3347                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2431                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55427                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         40379667                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        40379667                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks       843569                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       843569                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1073682                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1073682                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           35                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           35                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           88                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total           88                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185036                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185036                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1059597                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1059597                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       832111                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       832111                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1059597                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1017147                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2076744                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1059597                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1017147                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2076744                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           45                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           45                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            8                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            8                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       114791                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       114791                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15028                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        15028                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       274518                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       274518                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15028                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389309                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404337                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15028                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389309                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404337                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       866000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       866000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       547500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       547500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16017370500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16017370500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2025075000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2025075000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34108164000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  34108164000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2025075000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  50125534500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  52150609500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2025075000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  50125534500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  52150609500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       843569                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       843569                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1073682                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1073682                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           80                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           80                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           96                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           96                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       299827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       299827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1074625                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1074625                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1106629                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1106629                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1074625                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1406456                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2481081                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1074625                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1406456                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2481081                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.562500                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.562500                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.083333                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.083333                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382857                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.382857                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.013984                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.013984                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248067                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248067                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.013984                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.276801                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.162968                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.013984                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.276801                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.162968                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19244.444444                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19244.444444                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 68437.500000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 68437.500000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139535.072436                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139535.072436                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134753.460208                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134753.460208                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124247.459183                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124247.459183                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134753.460208                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128755.139234                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128978.078929                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134753.460208                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128978.078929                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        76108                       # number of writebacks
system.cpu.l2cache.writebacks::total            76108                       # number of writebacks
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           45                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           45                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            8                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            8                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114791                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       114791                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15028                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15028                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274518                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274518                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15028                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389309                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404337                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15028                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389309                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404337                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3100000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3100000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       546000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       546000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14869460001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14869460001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1874795000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1874795000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31368563001                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31368563001                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1874795000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46238023002                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  48112818002                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1874795000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46238023002                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  48112818002                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442000500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442000500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2044145000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2044145000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486145500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486145500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.562500                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.562500                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.083333                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.083333                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382857                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382857                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013984                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248067                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248067                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276801                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.162968                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276801                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.162968                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      4961718                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2480443                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2186                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1198                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1198                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2188672                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9599                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9599                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       961198                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1074186                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       824987                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           80                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq           96                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          176                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       299827                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       299827                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1075000                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106802                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           43                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3223811                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4252378                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7476189                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137523904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144052988                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          281576892                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      422541                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2920171                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.001264                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.035530                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2916480     99.87%     99.87% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               3691      0.13%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2920171                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4411678000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1613546403                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2121618679                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51151                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51151                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33058                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116508                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20216                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total        44156                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2705764                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              5364000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               818000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              177000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            14181000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             2178000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             6052000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               91500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           215700163                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23459000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.249213                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1726973394000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.249213                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078076                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078076                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
system.iocache.overall_misses::total              173                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21828883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21828883                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide   5246443280                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5246443280                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide     21828883                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     21828883                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide     21828883                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     21828883                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126178.514451                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126178.514451                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126178.514451                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             7                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13178883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     13178883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3167048471                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3167048471                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide     13178883                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     13178883                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide     13178883                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     13178883                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76178.514451                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76178.514451                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
system.membus.trans_dist::ReadResp             296606                       # Transaction distribution
system.membus.trans_dist::WriteReq               9599                       # Transaction distribution
system.membus.trans_dist::WriteResp              9599                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       117620                       # Transaction distribution
system.membus.trans_dist::CleanEvict           261864                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              278                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            114558                       # Transaction distribution
system.membus.trans_dist::ReadExResp           114558                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        289719                       # Transaction distribution
system.membus.trans_dist::BadAddressError           43                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33058                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145930                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           86                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1262499                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44156                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30713088                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30757244                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                33414972                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              438                       # Total snoops (count)
system.membus.snoop_fanout::samples            842137                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  842137    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              842137                       # Request fanout histogram
system.membus.reqLayer0.occupancy            28883000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1314388710                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               54000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2138626000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy             918617                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6438                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211036                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74670     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1881      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105584     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182266                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73303     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1881      1.27%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73303     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148618                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1818987792000     96.92%     96.92% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                67503500      0.00%     96.92% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               563118000      0.03%     96.95% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             57175249500      3.05%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1876793663000                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981693                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694262                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815391                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175147     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6785      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5106      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191994                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5854                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326273                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394302                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        30164955000      1.61%      1.61% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2918722500      0.16%      1.76% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1843709977500     98.24%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------