stats.txt revision 11201
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 1.875760 # Number of seconds simulated 411201Sandreas.hansson@arm.comsim_ticks 1875760362000 # Number of ticks simulated 511201Sandreas.hansson@arm.comfinal_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711201Sandreas.hansson@arm.comhost_inst_rate 133605 # Simulator instruction rate (inst/s) 811201Sandreas.hansson@arm.comhost_op_rate 133605 # Simulator op (including micro ops) rate (op/s) 911201Sandreas.hansson@arm.comhost_tick_rate 4730094094 # Simulator tick rate (ticks/s) 1011201Sandreas.hansson@arm.comhost_mem_usage 378388 # Number of bytes of host memory used 1111201Sandreas.hansson@arm.comhost_seconds 396.56 # Real time elapsed on the host 1211201Sandreas.hansson@arm.comsim_insts 52982087 # Number of instructions simulated 1311201Sandreas.hansson@arm.comsim_ops 52982087 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24881088 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25840256 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7524736 # Number of bytes written to this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7524736 # Number of bytes written to this memory 2411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory 2511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388767 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2711201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 403754 # Number of read requests responded to by this memory 2811201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117574 # Number of write requests responded to by this memory 2911201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117574 # Number of write requests responded to by this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 510837 # Total read bandwidth from this memory (bytes/s) 3111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13264534 # Total read bandwidth from this memory (bytes/s) 3211138Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 3311201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13775883 # Total read bandwidth from this memory (bytes/s) 3411201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 510837 # Instruction read bandwidth from this memory (bytes/s) 3511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 510837 # Instruction read bandwidth from this memory (bytes/s) 3611201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4011566 # Write bandwidth from this memory (bytes/s) 3711201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4011566 # Write bandwidth from this memory (bytes/s) 3811201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4011566 # Total bandwidth to/from this memory (bytes/s) 3911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 510837 # Total bandwidth to/from this memory (bytes/s) 4011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13264534 # Total bandwidth to/from this memory (bytes/s) 4111138Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 4211201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17787449 # Total bandwidth to/from this memory (bytes/s) 4311201Sandreas.hansson@arm.comsystem.physmem.readReqs 403754 # Number of read requests accepted 4411201Sandreas.hansson@arm.comsystem.physmem.writeReqs 117574 # Number of write requests accepted 4511201Sandreas.hansson@arm.comsystem.physmem.readBursts 403754 # Number of DRAM read bursts, including those serviced by the write queue 4611201Sandreas.hansson@arm.comsystem.physmem.writeBursts 117574 # Number of DRAM write bursts, including those merged in the write queue 4711201Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25832192 # Total number of bytes read from DRAM 4811201Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue 4911201Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7523264 # Total number of bytes written to DRAM 5011201Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25840256 # Total read bytes from the system interface side 5111201Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7524736 # Total written bytes from the system interface side 5211201Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue 5310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5411201Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 303613 # Number of requests that are neither read nor write 5511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 25610 # Per bank write bursts 5611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25424 # Per bank write bursts 5711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25555 # Per bank write bursts 5811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 25501 # Per bank write bursts 5911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 25379 # Per bank write bursts 6011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 24724 # Per bank write bursts 6111201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 24941 # Per bank write bursts 6211201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 25082 # Per bank write bursts 6311201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 24938 # Per bank write bursts 6411201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25020 # Per bank write bursts 6511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25562 # Per bank write bursts 6611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24881 # Per bank write bursts 6711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 24459 # Per bank write bursts 6811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25275 # Per bank write bursts 6911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25708 # Per bank write bursts 7011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25569 # Per bank write bursts 7111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 7930 # Per bank write bursts 7211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 7523 # Per bank write bursts 7311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 7959 # Per bank write bursts 7411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 7525 # Per bank write bursts 7511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 7322 # Per bank write bursts 7611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6662 # Per bank write bursts 7711201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6770 # Per bank write bursts 7811138Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6719 # Per bank write bursts 7911201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 7147 # Per bank write bursts 8011201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6703 # Per bank write bursts 8111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7409 # Per bank write bursts 8211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 6974 # Per bank write bursts 8311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 7145 # Per bank write bursts 8411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7893 # Per bank write bursts 8511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 8063 # Per bank write bursts 8611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7807 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811201Sandreas.hansson@arm.comsystem.physmem.numWrRetry 20 # Number of times write queue was full causing retry 8911201Sandreas.hansson@arm.comsystem.physmem.totGap 1875755162500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611201Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 403754 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311201Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117574 # Write request sizes (log2) 10411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 315453 # What read queue length does an incoming req see 10511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see 10611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 28173 # What read queue length does an incoming req see 10711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 23971 # What read queue length does an incoming req see 10811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see 10911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see 11010726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 11110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 11210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 11310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 11410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 11510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 11610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see 15211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 1903 # What write queue length does an incoming req see 15311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 3242 # What write queue length does an incoming req see 15411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see 15511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see 15611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see 15711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 6002 # What write queue length does an incoming req see 15811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 6433 # What write queue length does an incoming req see 15911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 7853 # What write queue length does an incoming req see 16011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see 16111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see 16211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see 16311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see 16411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 8334 # What write queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see 16911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see 17011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see 17111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see 17211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 237 # What write queue length does an incoming req see 17311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 220 # What write queue length does an incoming req see 17411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 108 # What write queue length does an incoming req see 17511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see 17611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see 17711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see 17811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see 17911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see 18011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see 18111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see 18211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see 18311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see 18411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see 18511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see 18611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see 18711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see 18811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see 18911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 107 # What write queue length does an incoming req see 19011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 193 # What write queue length does an incoming req see 19111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see 19211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see 19311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see 19411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see 19511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see 19611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see 19711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see 19811138Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see 19911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see 20011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 62202 # Bytes accessed per row activation 20111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 536.237934 # Bytes accessed per row activation 20211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 330.496904 # Bytes accessed per row activation 20311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 411.905259 # Bytes accessed per row activation 20411201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13738 22.09% 22.09% # Bytes accessed per row activation 20511201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 10541 16.95% 39.03% # Bytes accessed per row activation 20611201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation 20711201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 2730 4.39% 51.39% # Bytes accessed per row activation 20811201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2467 3.97% 55.36% # Bytes accessed per row activation 20911201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1593 2.56% 57.92% # Bytes accessed per row activation 21011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3726 5.99% 63.91% # Bytes accessed per row activation 21111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1160 1.86% 65.77% # Bytes accessed per row activation 21211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 21290 34.23% 100.00% # Bytes accessed per row activation 21311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 62202 # Bytes accessed per row activation 21411201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes 21511201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes 21611201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2240.859567 # Reads before turning the bus around for writes 21711201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes 21811201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes 21911201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes 22011201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes 22111201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 22211201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes 22311201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5203 # Reads before turning the bus around for writes 22411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5203 # Writes before turning the bus around for reads 22511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.592927 # Writes before turning the bus around for reads 22611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 19.087485 # Writes before turning the bus around for reads 22711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 21.896632 # Writes before turning the bus around for reads 22811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 4449 85.51% 85.51% # Writes before turning the bus around for reads 22911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 153 2.94% 88.45% # Writes before turning the bus around for reads 23011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 15 0.29% 88.74% # Writes before turning the bus around for reads 23111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 183 3.52% 92.25% # Writes before turning the bus around for reads 23211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 7 0.13% 92.39% # Writes before turning the bus around for reads 23311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 21 0.40% 92.79% # Writes before turning the bus around for reads 23411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 39 0.75% 93.54% # Writes before turning the bus around for reads 23511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 1 0.02% 93.56% # Writes before turning the bus around for reads 23611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 10 0.19% 93.75% # Writes before turning the bus around for reads 23711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 17 0.33% 94.08% # Writes before turning the bus around for reads 23811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 6 0.12% 94.20% # Writes before turning the bus around for reads 23911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 2 0.04% 94.23% # Writes before turning the bus around for reads 24011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 8 0.15% 94.39% # Writes before turning the bus around for reads 24111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 2 0.04% 94.43% # Writes before turning the bus around for reads 24211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 19 0.37% 94.79% # Writes before turning the bus around for reads 24311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 27 0.52% 95.31% # Writes before turning the bus around for reads 24411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 31 0.60% 95.91% # Writes before turning the bus around for reads 24511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.06% 95.96% # Writes before turning the bus around for reads 24611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 162 3.11% 99.08% # Writes before turning the bus around for reads 24711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads 24811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 1 0.02% 99.12% # Writes before turning the bus around for reads 24911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 7 0.13% 99.25% # Writes before turning the bus around for reads 25011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 2 0.04% 99.29% # Writes before turning the bus around for reads 25111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 4 0.08% 99.37% # Writes before turning the bus around for reads 25211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.02% 99.38% # Writes before turning the bus around for reads 25311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 3 0.06% 99.44% # Writes before turning the bus around for reads 25411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 2 0.04% 99.48% # Writes before turning the bus around for reads 25511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 4 0.08% 99.56% # Writes before turning the bus around for reads 25611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 4 0.08% 99.63% # Writes before turning the bus around for reads 25711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads 25811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 10 0.19% 99.85% # Writes before turning the bus around for reads 25911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 26011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads 26111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Writes before turning the bus around for reads 26211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads 26311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads 26411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads 26511201Sandreas.hansson@arm.comsystem.physmem.totQLat 4177241750 # Total ticks spent queuing 26611201Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11745266750 # Total ticks spent from burst creation until serviced by the DRAM 26711201Sandreas.hansson@arm.comsystem.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers 26811201Sandreas.hansson@arm.comsystem.physmem.avgQLat 10349.24 # Average queueing delay per DRAM burst 2699978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27011201Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 29099.24 # Average memory access latency per DRAM burst 27111138Sandreas.hansson@arm.comsystem.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 27211138Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 27311138Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 27411138Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 2759978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27610726Sandreas.hansson@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 27710352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 27810892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 27911201Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing 28011201Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing 28111201Sandreas.hansson@arm.comsystem.physmem.readRowHits 363742 # Number of row buffer hits during reads 28211201Sandreas.hansson@arm.comsystem.physmem.writeRowHits 95234 # Number of row buffer hits during writes 28311138Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads 28411201Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes 28511201Sandreas.hansson@arm.comsystem.physmem.avgGap 3598032.64 # Average gap between requests 28611201Sandreas.hansson@arm.comsystem.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined 28711201Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 232553160 # Energy for activate commands per rank (pJ) 28811201Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 126889125 # Energy for precharge commands per rank (pJ) 28911201Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) 29011201Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) 29111201Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 29211201Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 61473435525 # Energy for active background per rank (pJ) 29311201Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1071528687000 # Energy for precharge background per rank (pJ) 29411201Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 1257832501770 # Total energy per rank (pJ) 29511201Sandreas.hansson@arm.comsystem.physmem_0.averagePower 670.574130 # Core power per rank (mW) 29611201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 1782381530500 # Time in different power states 29711201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states 29810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 29911201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 30737512000 # Time in different power states 30010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30111201Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 237693960 # Energy for activate commands per rank (pJ) 30211201Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 129694125 # Energy for precharge commands per rank (pJ) 30311201Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) 30411201Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) 30511201Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) 30611201Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 61441070355 # Energy for active background per rank (pJ) 30711201Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1071557085750 # Energy for precharge background per rank (pJ) 30811201Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 1257834900030 # Total energy per rank (pJ) 30911201Sandreas.hansson@arm.comsystem.physmem_1.averagePower 670.575404 # Core power per rank (mW) 31011201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 1782427454500 # Time in different power states 31111201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states 31210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31311201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 30691601750 # Time in different power states 31410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 31511201Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 17943789 # Number of BP lookups 31611201Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 15652252 # Number of conditional branches predicted 31711201Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect 31811201Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 11526734 # Number of BTB lookups 31911201Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5853564 # Number of BTB hits 3209481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 32111201Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage 32211201Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. 32311201Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 21143 # Number of incorrect RAS predictions. 32410036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3258464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 3268464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 3278464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 3288464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 32911201Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 10250861 # DTB read hits 33011201Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41155 # DTB read misses 33111201Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 533 # DTB read access violations 33211201Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 965519 # DTB read accesses 33311201Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6643163 # DTB write hits 33411201Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 9679 # DTB write misses 33511201Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 405 # DTB write access violations 33611201Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 341919 # DTB write accesses 33711201Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16894024 # DTB hits 33811201Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 50834 # DTB misses 33911201Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 938 # DTB access violations 34011201Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1307438 # DTB accesses 34111201Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1771509 # ITB hits 34211201Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 27218 # ITB misses 34311201Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 651 # ITB acv 34411201Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1798727 # ITB accesses 3458464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3468464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3478464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3488464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3498464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3508464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3518464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3528464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3538464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3548464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3558464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3568464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 35711201Sandreas.hansson@arm.comsystem.cpu.numCycles 154312476 # number of cpu cycles simulated 3588464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3598464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 36011201Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 29589684 # Number of cycles fetch is stalled on an Icache miss 36111201Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 78040473 # Number of instructions fetch has processed 36211201Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 17943789 # Number of branches that fetch encountered 36311201Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6765691 # Number of branches that fetch has predicted taken 36411201Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 115537778 # Number of cycles fetch has run and was not squashing or blocked 36511201Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing 36611201Sandreas.hansson@arm.comsystem.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb 36711201Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 36811201Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps 36911201Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions 37011201Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR 37111201Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8990852 # Number of cache lines fetched 37211201Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed 37311201Sandreas.hansson@arm.comsystem.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 37411201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 147506364 # Number of instructions fetched each cycle (Total) 37511201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.529065 # Number of instructions fetched each cycle (Total) 37611201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.785295 # Number of instructions fetched each cycle (Total) 3778464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 37811201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 132982346 90.15% 90.15% # Number of instructions fetched each cycle (Total) 37911201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) 38011201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) 38111201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 905254 0.61% 92.72% # Number of instructions fetched each cycle (Total) 38211201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2772061 1.88% 94.60% # Number of instructions fetched each cycle (Total) 38311201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 613974 0.42% 95.02% # Number of instructions fetched each cycle (Total) 38411201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) 38511201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1009556 0.68% 96.19% # Number of instructions fetched each cycle (Total) 38611201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 5613005 3.81% 100.00% # Number of instructions fetched each cycle (Total) 3878464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3888464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3898464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 39011201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 147506364 # Number of instructions fetched each cycle (Total) 39111201Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle 39211201Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle 39311201Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 23997501 # Number of cycles decode is idle 39411201Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 111590886 # Number of cycles decode is blocked 39511201Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 9436404 # Number of cycles decode is running 39611201Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 1909016 # Number of cycles decode is unblocking 39711201Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing 39811201Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch 39911201Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction 40011201Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 68051611 # Number of instructions handled by decode 40111201Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode 40211201Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing 40311201Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 24921357 # Number of cycles rename is idle 40411201Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 78408678 # Number of cycles rename is blocking 40511201Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 21682628 # count of cycles rename stalled for serializing inst 40611201Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 10334897 # Number of cycles rename is running 40711201Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 11586246 # Number of cycles rename is unblocking 40811201Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65629261 # Number of instructions processed by rename 40911201Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full 41011201Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2094496 # Number of times rename has blocked due to IQ full 41111201Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 230878 # Number of times rename has blocked due to LQ full 41211201Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 7314004 # Number of times rename has blocked due to SQ full 41311201Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43742271 # Number of destination operands rename has renamed 41411201Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79592757 # Number of register rename lookups that rename has made 41511201Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79412100 # Number of integer rename lookups 41611201Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups 41711201Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed 41811201Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5560685 # Number of HB maps that are undone due to squashing 41911201Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed 42011201Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed 42111201Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 13566674 # count of insts added to the skid buffer 42211201Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. 42311201Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. 42411201Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. 42511201Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. 42611201Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58467931 # Number of instructions added to the IQ (excludes non-spec) 42711201Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2138048 # Number of non-speculative instructions added to the IQ 42811201Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 57495227 # Number of instructions issued 42911201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued 43011201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7623887 # Number of squashed instructions iterated over during squash; mainly for profiling 43111201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph 43211201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1476848 # Number of squashed non-spec instructions that were removed 43311201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 147506364 # Number of insts issued each cycle 43411201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.389781 # Number of insts issued each cycle 43511201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.113625 # Number of insts issued each cycle 4368464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 43711201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 123908569 84.00% 84.00% # Number of insts issued each cycle 43811201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10178941 6.90% 90.90% # Number of insts issued each cycle 43911201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 4283785 2.90% 93.81% # Number of insts issued each cycle 44011201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3020720 2.05% 95.85% # Number of insts issued each cycle 44111201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 3080791 2.09% 97.94% # Number of insts issued each cycle 44211201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1492273 1.01% 98.96% # Number of insts issued each cycle 44311201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 1011784 0.69% 99.64% # Number of insts issued each cycle 44411201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 404685 0.27% 99.92% # Number of insts issued each cycle 44511201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 124816 0.08% 100.00% # Number of insts issued each cycle 4468464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4478464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4488464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 44911201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 147506364 # Number of insts issued each cycle 4508464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 45111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 210138 18.65% 18.65% # attempts to use FU when none available 45211201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available 45311201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available 45411201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available 45511201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 18.65% # attempts to use FU when none available 45611201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 18.65% # attempts to use FU when none available 45711201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 18.65% # attempts to use FU when none available 45811201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 18.65% # attempts to use FU when none available 45911201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.65% # attempts to use FU when none available 46011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 18.65% # attempts to use FU when none available 46111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.65% # attempts to use FU when none available 46211201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 18.65% # attempts to use FU when none available 46311201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 18.65% # attempts to use FU when none available 46411201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 18.65% # attempts to use FU when none available 46511201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 18.65% # attempts to use FU when none available 46611201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 18.65% # attempts to use FU when none available 46711201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.65% # attempts to use FU when none available 46811201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 18.65% # attempts to use FU when none available 46911201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.65% # attempts to use FU when none available 47011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.65% # attempts to use FU when none available 47111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.65% # attempts to use FU when none available 47211201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.65% # attempts to use FU when none available 47311201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.65% # attempts to use FU when none available 47411201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.65% # attempts to use FU when none available 47511201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.65% # attempts to use FU when none available 47611201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # attempts to use FU when none available 47711201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available 47811201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available 47911201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available 48011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 541379 48.04% 66.69% # attempts to use FU when none available 48111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 375311 33.31% 100.00% # attempts to use FU when none available 4828464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4838464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 48411201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued 48511201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 39050505 67.92% 67.93% # Type of FU issued 48611201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued 48711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued 48811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued 48911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued 49011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued 49111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued 49211138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued 49311138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued 49411138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued 49511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued 49611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued 49711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued 49811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued 49911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued 50011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued 50111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued 50211138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued 50311138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued 50411138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued 50511138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued 50611138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued 50711138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued 50811138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued 50911138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued 51011138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued 51111138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued 51211138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued 51311138Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued 51411201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Type of FU issued 51511201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued 51611201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued 5178464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 51811201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 57495227 # Type of FU issued 51911201Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.372590 # Inst issue rate 52011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1126828 # FU busy when requested 52111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) 52211201Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 262968198 # Number of integer instruction queue reads 52311201Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 67912529 # Number of integer instruction queue writes 52411201Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55849103 # Number of integer instruction queue wakeup accesses 52511201Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads 52611201Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes 52711201Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses 52811201Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 58232052 # Number of integer alu accesses 52911201Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses 53011201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores 5318464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 53211201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1282102 # Number of loads squashed 53311201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3336 # Number of memory responses ignored because the instruction is squashed 53411201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations 53511201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 573763 # Number of stores squashed 5368464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5378464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 53811201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled 53911201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 460620 # Number of times an access to memory failed due to the cache being blocked 5408464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 54111201Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing 54211201Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 74664170 # Number of cycles IEW is blocking 54311201Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 1189821 # Number of cycles IEW is unblocking 54411201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 64295080 # Number of instructions dispatched to IQ 54511201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch 54611201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions 54711201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions 54811201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1890560 # Number of dispatched non-speculative instructions 54911201Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 43853 # Number of times the IQ has become full, causing a stall 55011201Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 943025 # Number of times the LSQ has become full, causing a stall 55111201Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations 55211201Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly 55311201Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly 55411201Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute 55511201Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56909008 # Number of executed instructions 55611201Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed 55711201Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute 5588464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 55911201Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3689101 # number of nop insts executed 56011201Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16987647 # number of memory reference insts executed 56111201Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8974026 # Number of branches executed 56211201Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6667947 # Number of stores executed 56311201Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.368791 # Inst execution rate 56411201Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56315336 # cumulative count of insts sent to commit 56511201Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 56178054 # cumulative count of insts written-back 56611201Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 28756989 # num instructions producing a value 56711201Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 39942344 # num instructions consuming a value 5688464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 56911201Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.364054 # insts written-back per cycle 57011201Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.719962 # average fanout of values written-back 5718464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 57211201Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 8005033 # The number of squashed insts skipped by commit 57311201Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards 57411201Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted 57511201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 146103821 # Number of insts commited each cycle 57611201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.384473 # Number of insts commited each cycle 57711201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.286210 # Number of insts commited each cycle 5788241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 57911201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 126321778 86.46% 86.46% # Number of insts commited each cycle 58011201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 7855301 5.38% 91.84% # Number of insts commited each cycle 58111201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4275066 2.93% 94.76% # Number of insts commited each cycle 58211201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2236699 1.53% 96.29% # Number of insts commited each cycle 58311201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1745226 1.19% 97.49% # Number of insts commited each cycle 58411201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 615725 0.42% 97.91% # Number of insts commited each cycle 58511201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 478401 0.33% 98.24% # Number of insts commited each cycle 58611201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 477554 0.33% 98.56% # Number of insts commited each cycle 58711201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 2098071 1.44% 100.00% # Number of insts commited each cycle 5888241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5898241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5908241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 59111201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 146103821 # Number of insts commited each cycle 59211201Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56172911 # Number of instructions committed 59311201Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed 5948464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 59511201Sandreas.hansson@arm.comsystem.cpu.commit.refs 15471230 # Number of memory references committed 59611201Sandreas.hansson@arm.comsystem.cpu.commit.loads 9092979 # Number of loads committed 59711201Sandreas.hansson@arm.comsystem.cpu.commit.membars 226353 # Number of memory barriers committed 59811201Sandreas.hansson@arm.comsystem.cpu.commit.branches 8440862 # Number of branches committed 59910892Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 60011201Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52022252 # Number of committed integer instructions. 60111201Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740590 # Number of function calls committed. 60211201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 3198097 5.69% 5.69% # Class of committed instruction 60311201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 36219833 64.48% 70.17% # Class of committed instruction 60411201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction 60510892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 60610892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 60710892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 60810892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 60910892Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 61011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 61111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 61211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 61311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 61411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 61511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 61611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 61711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 61811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 61911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 62011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 62111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 62211138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 62311138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 62411138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 62511138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 62611138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 62711138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 62811138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 62911138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 63011138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 63111138Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 63211201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 9319332 16.59% 86.95% # Class of committed instruction 63311201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Class of committed instruction 63411201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction 63510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 63611201Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 56172911 # Class of committed instruction 63711201Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 2098071 # number cycles where commit BW limit reached 63811201Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 207934044 # The number of ROB reads 63911201Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 129754094 # The number of ROB writes 64011201Sandreas.hansson@arm.comsystem.cpu.timesIdled 581359 # Number of times that the entire CPU went into an idle state and unscheduled itself 64111201Sandreas.hansson@arm.comsystem.cpu.idleCycles 6806112 # Total number of cycles that the CPU has spent unscheduled due to idling 64211201Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 64311201Sandreas.hansson@arm.comsystem.cpu.committedInsts 52982087 # Number of Instructions Simulated 64411201Sandreas.hansson@arm.comsystem.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated 64511201Sandreas.hansson@arm.comsystem.cpu.cpi 2.912541 # CPI: Cycles Per Instruction 64611201Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads 64711201Sandreas.hansson@arm.comsystem.cpu.ipc 0.343343 # IPC: Instructions Per Cycle 64811201Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads 64911201Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 74569026 # number of integer regfile reads 65011201Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40527111 # number of integer regfile writes 65111201Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166982 # number of floating regfile reads 65211201Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167538 # number of floating regfile writes 65311201Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1985520 # number of misc regfile reads 65411201Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 939432 # number of misc regfile writes 65511201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1401817 # number of replacements 65611201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use 65711201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11831384 # Total number of references to valid blocks. 65811201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1402329 # Sample count of references to valid blocks. 65911201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.436953 # Average number of references to valid blocks. 66011201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 66111201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor 66211138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 66311138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 66410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 66511138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 66611138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 66711138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 66810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 66911201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 63839342 # Number of tag accesses 67011201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 63839342 # Number of data accesses 67111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7238802 # number of ReadReq hits 67211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7238802 # number of ReadReq hits 67311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4190242 # number of WriteReq hits 67411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4190242 # number of WriteReq hits 67511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186215 # number of LoadLockedReq hits 67611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186215 # number of LoadLockedReq hits 67711201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215725 # number of StoreCondReq hits 67811201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215725 # number of StoreCondReq hits 67911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11429044 # number of demand (read+write) hits 68011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11429044 # number of demand (read+write) hits 68111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11429044 # number of overall hits 68211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11429044 # number of overall hits 68311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1797438 # number of ReadReq misses 68411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1797438 # number of ReadReq misses 68511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1957552 # number of WriteReq misses 68611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1957552 # number of WriteReq misses 68711201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 23250 # number of LoadLockedReq misses 68811201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 23250 # number of LoadLockedReq misses 68911201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses 69011201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses 69111201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3754990 # number of demand (read+write) misses 69211201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3754990 # number of demand (read+write) misses 69311201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3754990 # number of overall misses 69411201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3754990 # number of overall misses 69511201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 57215692000 # number of ReadReq miss cycles 69611201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 57215692000 # number of ReadReq miss cycles 69711201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 116805325608 # number of WriteReq miss cycles 69811201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 116805325608 # number of WriteReq miss cycles 69911201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447608000 # number of LoadLockedReq miss cycles 70011201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 447608000 # number of LoadLockedReq miss cycles 70111201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 892500 # number of StoreCondReq miss cycles 70211201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 892500 # number of StoreCondReq miss cycles 70311201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 174021017608 # number of demand (read+write) miss cycles 70411201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 174021017608 # number of demand (read+write) miss cycles 70511201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 174021017608 # number of overall miss cycles 70611201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 174021017608 # number of overall miss cycles 70711201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9036240 # number of ReadReq accesses(hits+misses) 70811201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9036240 # number of ReadReq accesses(hits+misses) 70911201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147794 # number of WriteReq accesses(hits+misses) 71011201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147794 # number of WriteReq accesses(hits+misses) 71111201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 209465 # number of LoadLockedReq accesses(hits+misses) 71211201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 209465 # number of LoadLockedReq accesses(hits+misses) 71311201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) 71411201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) 71511201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15184034 # number of demand (read+write) accesses 71611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15184034 # number of demand (read+write) accesses 71711201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15184034 # number of overall (read+write) accesses 71811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15184034 # number of overall (read+write) accesses 71911201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198914 # miss rate for ReadReq accesses 72011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.198914 # miss rate for ReadReq accesses 72111201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318415 # miss rate for WriteReq accesses 72211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.318415 # miss rate for WriteReq accesses 72311201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110997 # miss rate for LoadLockedReq accesses 72411201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.110997 # miss rate for LoadLockedReq accesses 72511201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses 72611201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses 72711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247299 # miss rate for demand accesses 72811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247299 # miss rate for demand accesses 72911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247299 # miss rate for overall accesses 73011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247299 # miss rate for overall accesses 73111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.802822 # average ReadReq miss latency 73211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 31831.802822 # average ReadReq miss latency 73311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59669.079344 # average WriteReq miss latency 73411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344 # average WriteReq miss latency 73511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency 73611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency 73711201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency 73811201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency 73911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency 74011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 46343.936364 # average overall miss latency 74111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency 74211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 46343.936364 # average overall miss latency 74311201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 7142845 # number of cycles access was blocked 74411201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked 74511201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 134029 # number of cycles access was blocked 74611201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked 74711201Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 53.293280 # average number of cycles each access was blocked 74811201Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked 74910585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 75010585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 75111201Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 841132 # number of writebacks 75211201Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 841132 # number of writebacks 75311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 703605 # number of ReadReq MSHR hits 75411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 703605 # number of ReadReq MSHR hits 75511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666863 # number of WriteReq MSHR hits 75611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1666863 # number of WriteReq MSHR hits 75711201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5233 # number of LoadLockedReq MSHR hits 75811201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5233 # number of LoadLockedReq MSHR hits 75911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2370468 # number of demand (read+write) MSHR hits 76011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2370468 # number of demand (read+write) MSHR hits 76111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2370468 # number of overall MSHR hits 76211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2370468 # number of overall MSHR hits 76311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093833 # number of ReadReq MSHR misses 76411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1093833 # number of ReadReq MSHR misses 76511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 290689 # number of WriteReq MSHR misses 76611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 290689 # number of WriteReq MSHR misses 76711201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18017 # number of LoadLockedReq MSHR misses 76811201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 18017 # number of LoadLockedReq MSHR misses 76911201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses 77011201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses 77111201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1384522 # number of demand (read+write) MSHR misses 77211201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1384522 # number of demand (read+write) MSHR misses 77311201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1384522 # number of overall MSHR misses 77411201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1384522 # number of overall MSHR misses 77510827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 77610827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 77711138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 77811138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 77911138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 78011138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 78111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44560858000 # number of ReadReq MSHR miss cycles 78211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 44560858000 # number of ReadReq MSHR miss cycles 78311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18438060220 # number of WriteReq MSHR miss cycles 78411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 18438060220 # number of WriteReq MSHR miss cycles 78511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229318500 # number of LoadLockedReq MSHR miss cycles 78611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229318500 # number of LoadLockedReq MSHR miss cycles 78711201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 863500 # number of StoreCondReq MSHR miss cycles 78811201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 863500 # number of StoreCondReq MSHR miss cycles 78911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 62998918220 # number of demand (read+write) MSHR miss cycles 79011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 62998918220 # number of demand (read+write) MSHR miss cycles 79111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998918220 # number of overall MSHR miss cycles 79211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 62998918220 # number of overall MSHR miss cycles 79311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529906000 # number of ReadReq MSHR uncacheable cycles 79411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529906000 # number of ReadReq MSHR uncacheable cycles 79511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154205500 # number of WriteReq MSHR uncacheable cycles 79611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154205500 # number of WriteReq MSHR uncacheable cycles 79711201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3684111500 # number of overall MSHR uncacheable cycles 79811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3684111500 # number of overall MSHR uncacheable cycles 79911201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121050 # mshr miss rate for ReadReq accesses 80011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121050 # mshr miss rate for ReadReq accesses 80111201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047283 # mshr miss rate for WriteReq accesses 80211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047283 # mshr miss rate for WriteReq accesses 80311201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086014 # mshr miss rate for LoadLockedReq accesses 80411201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086014 # mshr miss rate for LoadLockedReq accesses 80511201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses 80611201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses 80711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for demand accesses 80811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091183 # mshr miss rate for demand accesses 80911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for overall accesses 81011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091183 # mshr miss rate for overall accesses 81111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.264433 # average ReadReq mshr miss latency 81211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.264433 # average ReadReq mshr miss latency 81311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.819873 # average WriteReq mshr miss latency 81411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.819873 # average WriteReq mshr miss latency 81511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876 # average LoadLockedReq mshr miss latency 81611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876 # average LoadLockedReq mshr miss latency 81711201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069 # average StoreCondReq mshr miss latency 81811201Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069 # average StoreCondReq mshr miss latency 81911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.287591 # average overall mshr miss latency 82011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.287591 # average overall mshr miss latency 82111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.287591 # average overall mshr miss latency 82211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.287591 # average overall mshr miss latency 82311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220765.656566 # average ReadReq mshr uncacheable latency 82411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220765.656566 # average ReadReq mshr uncacheable latency 82511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243 # average WriteReq mshr uncacheable latency 82611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243 # average WriteReq mshr uncacheable latency 82711201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222901.228219 # average overall mshr uncacheable latency 82811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222901.228219 # average overall mshr uncacheable latency 82910585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 83011201Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1036098 # number of replacements 83111201Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 507.835115 # Cycle average of tags in use 83211201Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7900594 # Total number of references to valid blocks. 83311201Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1036606 # Sample count of references to valid blocks. 83411201Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.621598 # Average number of references to valid blocks. 83511201Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. 83611201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 507.835115 # Average occupied blocks per requestor 83711201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy 83811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy 83910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 84011201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 84111201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id 84211138Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id 84310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 84411201Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 10027828 # Number of tag accesses 84511201Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 10027828 # Number of data accesses 84611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7900595 # number of ReadReq hits 84711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7900595 # number of ReadReq hits 84811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7900595 # number of demand (read+write) hits 84911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7900595 # number of demand (read+write) hits 85011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7900595 # number of overall hits 85111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7900595 # number of overall hits 85211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1090254 # number of ReadReq misses 85311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1090254 # number of ReadReq misses 85411201Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1090254 # number of demand (read+write) misses 85511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1090254 # number of demand (read+write) misses 85611201Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1090254 # number of overall misses 85711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1090254 # number of overall misses 85811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16373491482 # number of ReadReq miss cycles 85911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16373491482 # number of ReadReq miss cycles 86011201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16373491482 # number of demand (read+write) miss cycles 86111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 16373491482 # number of demand (read+write) miss cycles 86211201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16373491482 # number of overall miss cycles 86311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 16373491482 # number of overall miss cycles 86411201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8990849 # number of ReadReq accesses(hits+misses) 86511201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8990849 # number of ReadReq accesses(hits+misses) 86611201Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8990849 # number of demand (read+write) accesses 86711201Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8990849 # number of demand (read+write) accesses 86811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8990849 # number of overall (read+write) accesses 86911201Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8990849 # number of overall (read+write) accesses 87011201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121263 # miss rate for ReadReq accesses 87111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.121263 # miss rate for ReadReq accesses 87211201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.121263 # miss rate for demand accesses 87311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.121263 # miss rate for demand accesses 87411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.121263 # miss rate for overall accesses 87511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.121263 # miss rate for overall accesses 87611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.052199 # average ReadReq miss latency 87711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 15018.052199 # average ReadReq miss latency 87811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.052199 # average overall miss latency 87911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 15018.052199 # average overall miss latency 88011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.052199 # average overall miss latency 88111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 15018.052199 # average overall miss latency 88211201Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 11165 # number of cycles access was blocked 88310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88411201Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 304 # number of cycles access was blocked 88510585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 88611201Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 36.726974 # average number of cycles each access was blocked 88710585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88810585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 88910585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 89011201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 1036098 # number of writebacks 89111201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 1036098 # number of writebacks 89211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 53275 # number of ReadReq MSHR hits 89311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 53275 # number of ReadReq MSHR hits 89411201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 53275 # number of demand (read+write) MSHR hits 89511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 53275 # number of demand (read+write) MSHR hits 89611201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 53275 # number of overall MSHR hits 89711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 53275 # number of overall MSHR hits 89811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036979 # number of ReadReq MSHR misses 89911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1036979 # number of ReadReq MSHR misses 90011201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1036979 # number of demand (read+write) MSHR misses 90111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1036979 # number of demand (read+write) MSHR misses 90211201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1036979 # number of overall MSHR misses 90311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1036979 # number of overall MSHR misses 90411201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14441674990 # number of ReadReq MSHR miss cycles 90511201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14441674990 # number of ReadReq MSHR miss cycles 90611201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14441674990 # number of demand (read+write) MSHR miss cycles 90711201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 14441674990 # number of demand (read+write) MSHR miss cycles 90811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14441674990 # number of overall MSHR miss cycles 90911201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 14441674990 # number of overall MSHR miss cycles 91011201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for ReadReq accesses 91111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.115337 # mshr miss rate for ReadReq accesses 91211201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for demand accesses 91311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.115337 # mshr miss rate for demand accesses 91411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for overall accesses 91511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.115337 # mshr miss rate for overall accesses 91611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.680280 # average ReadReq mshr miss latency 91711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280 # average ReadReq mshr miss latency 91811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency 91911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency 92011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency 92111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency 92210585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 92311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338547 # number of replacements 92411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65279.196063 # Cycle average of tags in use 92511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4167773 # Total number of references to valid blocks. 92611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403714 # Sample count of references to valid blocks. 92711201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 10.323578 # Average number of references to valid blocks. 92811201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 9186443000 # Cycle when the warmup percentage was hit. 92911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53290.316378 # Average occupied blocks per requestor 93011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5240.255410 # Average occupied blocks per requestor 93111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6748.624275 # Average occupied blocks per requestor 93211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.813146 # Average percentage of cache occupancy 93311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.079960 # Average percentage of cache occupancy 93411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.102976 # Average percentage of cache occupancy 93511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996081 # Average percentage of cache occupancy 93611138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 93711138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 93811201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3482 # Occupied blocks per task id 93911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3334 # Occupied blocks per task id 94011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2423 # Occupied blocks per task id 94111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55435 # Occupied blocks per task id 94211138Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 94311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 39707239 # Number of tag accesses 94411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 39707239 # Number of data accesses 94511201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 841132 # number of WritebackDirty hits 94611201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 841132 # number of WritebackDirty hits 94711201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1035547 # number of WritebackClean hits 94811201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1035547 # number of WritebackClean hits 94911201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 95011201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 95111201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 95211201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 95311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185951 # number of ReadExReq hits 95411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185951 # number of ReadExReq hits 95511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1021689 # number of ReadCleanReq hits 95611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1021689 # number of ReadCleanReq hits 95711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 827089 # number of ReadSharedReq hits 95811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 827089 # number of ReadSharedReq hits 95911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1021689 # number of demand (read+write) hits 96011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1013040 # number of demand (read+write) hits 96111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2034729 # number of demand (read+write) hits 96211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1021689 # number of overall hits 96311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1013040 # number of overall hits 96411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2034729 # number of overall hits 96511201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 101 # number of UpgradeReq misses 96611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 101 # number of UpgradeReq misses 96711138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses 96811138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses 96911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115511 # number of ReadExReq misses 97011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115511 # number of ReadExReq misses 97111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 14974 # number of ReadCleanReq misses 97211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 14974 # number of ReadCleanReq misses 97311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 273860 # number of ReadSharedReq misses 97411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 273860 # number of ReadSharedReq misses 97511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 14974 # number of demand (read+write) misses 97611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389371 # number of demand (read+write) misses 97711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404345 # number of demand (read+write) misses 97811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 14974 # number of overall misses 97911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389371 # number of overall misses 98011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404345 # number of overall misses 98111201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 815500 # number of UpgradeReq miss cycles 98211201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 815500 # number of UpgradeReq miss cycles 98311138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 243500 # number of SCUpgradeReq miss cycles 98411138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 243500 # number of SCUpgradeReq miss cycles 98511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16101364500 # number of ReadExReq miss cycles 98611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 16101364500 # number of ReadExReq miss cycles 98711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2016473000 # number of ReadCleanReq miss cycles 98811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 2016473000 # number of ReadCleanReq miss cycles 98911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34005457500 # number of ReadSharedReq miss cycles 99011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 34005457500 # number of ReadSharedReq miss cycles 99111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 2016473000 # number of demand (read+write) miss cycles 99211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 50106822000 # number of demand (read+write) miss cycles 99311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 52123295000 # number of demand (read+write) miss cycles 99411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 2016473000 # number of overall miss cycles 99511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 50106822000 # number of overall miss cycles 99611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 52123295000 # number of overall miss cycles 99711201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 841132 # number of WritebackDirty accesses(hits+misses) 99811201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 841132 # number of WritebackDirty accesses(hits+misses) 99911201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1035547 # number of WritebackClean accesses(hits+misses) 100011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1035547 # number of WritebackClean accesses(hits+misses) 100111201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 130 # number of UpgradeReq accesses(hits+misses) 100211201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 130 # number of UpgradeReq accesses(hits+misses) 100311201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 29 # number of SCUpgradeReq accesses(hits+misses) 100411201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses) 100511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 301462 # number of ReadExReq accesses(hits+misses) 100611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 301462 # number of ReadExReq accesses(hits+misses) 100711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1036663 # number of ReadCleanReq accesses(hits+misses) 100811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1036663 # number of ReadCleanReq accesses(hits+misses) 100911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1100949 # number of ReadSharedReq accesses(hits+misses) 101011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1100949 # number of ReadSharedReq accesses(hits+misses) 101111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1036663 # number of demand (read+write) accesses 101211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1402411 # number of demand (read+write) accesses 101311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2439074 # number of demand (read+write) accesses 101411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1036663 # number of overall (read+write) accesses 101511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1402411 # number of overall (read+write) accesses 101611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2439074 # number of overall (read+write) accesses 101711201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.776923 # miss rate for UpgradeReq accesses 101811201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.776923 # miss rate for UpgradeReq accesses 101911201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.241379 # miss rate for SCUpgradeReq accesses 102011201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.241379 # miss rate for SCUpgradeReq accesses 102111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383169 # miss rate for ReadExReq accesses 102211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383169 # miss rate for ReadExReq accesses 102311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014444 # miss rate for ReadCleanReq accesses 102411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014444 # miss rate for ReadCleanReq accesses 102511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248749 # miss rate for ReadSharedReq accesses 102611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248749 # miss rate for ReadSharedReq accesses 102711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014444 # miss rate for demand accesses 102811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277644 # miss rate for demand accesses 102911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.165778 # miss rate for demand accesses 103011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014444 # miss rate for overall accesses 103111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277644 # miss rate for overall accesses 103211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.165778 # miss rate for overall accesses 103311201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8074.257426 # average UpgradeReq miss latency 103411201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8074.257426 # average UpgradeReq miss latency 103511138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency 103611138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency 103711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.477773 # average ReadExReq miss latency 103811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.477773 # average ReadExReq miss latency 103911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134664.952584 # average ReadCleanReq miss latency 104011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134664.952584 # average ReadCleanReq miss latency 104111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124170.954137 # average ReadSharedReq miss latency 104211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124170.954137 # average ReadSharedReq miss latency 104311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134664.952584 # average overall miss latency 104411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 128686.579124 # average overall miss latency 104511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 128907.974626 # average overall miss latency 104611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134664.952584 # average overall miss latency 104711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 128686.579124 # average overall miss latency 104811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 128907.974626 # average overall miss latency 104910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 105010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 105210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 105310585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 105410585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 105510585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 105610585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 105711201Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 76062 # number of writebacks 105811201Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 76062 # number of writebacks 105910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 106010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 106110585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 106210585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 106310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 106410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 106511201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 101 # number of UpgradeReq MSHR misses 106611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 101 # number of UpgradeReq MSHR misses 106711138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses 106811138Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses 106911138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115511 # number of ReadExReq MSHR misses 107011138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115511 # number of ReadExReq MSHR misses 107111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 14973 # number of ReadCleanReq MSHR misses 107211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses 107311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273860 # number of ReadSharedReq MSHR misses 107411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 273860 # number of ReadSharedReq MSHR misses 107511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses 107611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389371 # number of demand (read+write) MSHR misses 107711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404344 # number of demand (read+write) MSHR misses 107811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses 107911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389371 # number of overall MSHR misses 108011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404344 # number of overall MSHR misses 108110827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 108210827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 108311138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 108411138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 108511138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 108611138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 108711201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7246500 # number of UpgradeReq MSHR miss cycles 108811201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7246500 # number of UpgradeReq MSHR miss cycles 108911201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 500000 # number of SCUpgradeReq MSHR miss cycles 109011201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 500000 # number of SCUpgradeReq MSHR miss cycles 109111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14946254500 # number of ReadExReq MSHR miss cycles 109211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14946254500 # number of ReadExReq MSHR miss cycles 109311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1866612000 # number of ReadCleanReq MSHR miss cycles 109411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1866612000 # number of ReadCleanReq MSHR miss cycles 109511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31277372000 # number of ReadSharedReq MSHR miss cycles 109611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31277372000 # number of ReadSharedReq MSHR miss cycles 109711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1866612000 # number of demand (read+write) MSHR miss cycles 109811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46223626500 # number of demand (read+write) MSHR miss cycles 109911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 48090238500 # number of demand (read+write) MSHR miss cycles 110011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1866612000 # number of overall MSHR miss cycles 110111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46223626500 # number of overall MSHR miss cycles 110211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 48090238500 # number of overall MSHR miss cycles 110311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443206500 # number of ReadReq MSHR uncacheable cycles 110411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443206500 # number of ReadReq MSHR uncacheable cycles 110511201Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043789000 # number of WriteReq MSHR uncacheable cycles 110611201Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043789000 # number of WriteReq MSHR uncacheable cycles 110711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486995500 # number of overall MSHR uncacheable cycles 110811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486995500 # number of overall MSHR uncacheable cycles 110911201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses 111011201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses 111111201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses 111211201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses 111311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383169 # mshr miss rate for ReadExReq accesses 111411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383169 # mshr miss rate for ReadExReq accesses 111511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for ReadCleanReq accesses 111611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014443 # mshr miss rate for ReadCleanReq accesses 111711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248749 # mshr miss rate for ReadSharedReq accesses 111811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248749 # mshr miss rate for ReadSharedReq accesses 111911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for demand accesses 112011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for demand accesses 112111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.165778 # mshr miss rate for demand accesses 112211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for overall accesses 112311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for overall accesses 112411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.165778 # mshr miss rate for overall accesses 112511201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752 # average UpgradeReq mshr miss latency 112611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752 # average UpgradeReq mshr miss latency 112711201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429 # average SCUpgradeReq mshr miss latency 112811201Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429 # average SCUpgradeReq mshr miss latency 112911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773 # average ReadExReq mshr miss latency 113011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773 # average ReadExReq mshr miss latency 113111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355 # average ReadCleanReq mshr miss latency 113211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355 # average ReadCleanReq mshr miss latency 113311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842 # average ReadSharedReq mshr miss latency 113411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842 # average ReadSharedReq mshr miss latency 113511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency 113611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency 113711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency 113811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency 113911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency 114011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency 114111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205 # average ReadReq mshr uncacheable latency 114211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205 # average ReadReq mshr uncacheable latency 114311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency 114411201Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency 114511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352 # average overall mshr uncacheable latency 114611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352 # average overall mshr uncacheable latency 114710585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 114811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4877464 # Total number of requests made to the snoop filter. 114911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2438379 # Number of requests hitting in the snoop filter with a single holder of the requested data. 115011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 115111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 115211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 115311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 115410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 115511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2144933 # Transaction distribution 115611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 115711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 115811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution 115911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1035547 # Transaction distribution 116011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution 116111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution 116211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution 116311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution 116411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution 116511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution 116611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1036979 # Transaction distribution 116711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution 116811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution 116910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 117011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109189 # Packet count per connected master and slave (bytes) 117111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) 117211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 7347980 # Packet count per connected master and slave (bytes) 117311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621440 # Cumulative packet size per connected master and slave (bytes) 117411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) 117511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 276257140 # Cumulative packet size per connected master and slave (bytes) 117611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 422449 # Total snoops (count) 117711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2878054 # Request fanout histogram 117811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram 117911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram 118010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 118111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2874297 99.87% 99.87% # Request fanout histogram 118211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram 118311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 118410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 118511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 118611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 118711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2878054 # Request fanout histogram 118811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4329025000 # Layer occupancy (ticks) 118910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 119011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 119110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 119211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1556715501 # Layer occupancy (ticks) 119310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 119411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2115441305 # Layer occupancy (ticks) 119510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 119610585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 119710585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 119810585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 119910585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 120010585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 120110585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 120210585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 120310585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 120410585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 120510585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 120610585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 120710585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 12089729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 12099729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 121011138Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51150 # Transaction distribution 121111138Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51150 # Transaction distribution 121211138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 12139729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 12149729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 12159729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 12169729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 12179729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 12189729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 12199729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 12209729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 12219729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 12229729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 12239729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 122411138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 12259729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 12269729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 122711138Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 122811138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 122910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 123010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 123110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 123210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 123310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 123410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 123510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 123610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 123710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 123810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 123910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 124011138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 124110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 124210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 124311138Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 124411201Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) 12459729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 124611201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 444000 # Layer occupancy (ticks) 12479729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 124811201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 12499729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 125011201Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 12519729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 125211201Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 180000 # Layer occupancy (ticks) 12539729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 125411201Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 14342000 # Layer occupancy (ticks) 12559729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 125611201Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) 12579729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 125811201Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) 12599729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 126011201Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 219000 # Layer occupancy (ticks) 12619729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 126211201Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 88000 # Layer occupancy (ticks) 12639729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 126411201Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 132500 # Layer occupancy (ticks) 12659729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 126611201Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 215036503 # Layer occupancy (ticks) 12679729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 126811201Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) 12699729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 127011138Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 12719729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 127210892Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 12739729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 127410585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 127511201Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.249428 # Cycle average of tags in use 127610585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 127710585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 127810585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 127911201Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1725995793000 # Cycle when the warmup percentage was hit. 128011201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.249428 # Average occupied blocks per requestor 128111201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy 128211201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy 128310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 128410585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 128510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 128610585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375525 # Number of tag accesses 128710585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375525 # Number of data accesses 128810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 128910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 129010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 129110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 129210585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 129310585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 173 # number of demand (read+write) misses 129410585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 173 # number of overall misses 129510585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 173 # number of overall misses 129611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles 129711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles 129811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 5430705120 # number of WriteLineReq miss cycles 129911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 5430705120 # number of WriteLineReq miss cycles 130011201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles 130111201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles 130211201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles 130311201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles 130410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 130510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 130610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 130710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 130810585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 130910585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 131010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 131110585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 131210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 131310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 131410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 131510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 131610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 131710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 131810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 131910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 132011201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency 132111201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency 132211201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923 # average WriteLineReq miss latency 132311201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 130696.599923 # average WriteLineReq miss latency 132411201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 132511201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency 132611201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency 132711201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency 132811201Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 216 # number of cycles access was blocked 132910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 133011201Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 17 # number of cycles access was blocked 133110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 133211201Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 12.705882 # average number of cycles each access was blocked 133310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 133410585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 133510585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 133610585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 133710585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 133810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 133910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 134010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 134110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 134210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 134310585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 134410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 134510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 134611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles 134711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles 134811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353105120 # number of WriteLineReq MSHR miss cycles 134911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 3353105120 # number of WriteLineReq MSHR miss cycles 135011201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles 135111201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles 135211201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles 135311201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles 135410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 135510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 135610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 135710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 135810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 135910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 136010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 136110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 136211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency 136311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency 136411201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923 # average WriteLineReq mshr miss latency 136511201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923 # average WriteLineReq mshr miss latency 136611201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 136711201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 136811201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency 136911201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency 137010585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 137110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6930 # Transaction distribution 137211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 295855 # Transaction distribution 137311138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9598 # Transaction distribution 137411138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9598 # Transaction distribution 137511201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 117574 # Transaction distribution 137611201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 261706 # Transaction distribution 137711201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 351 # Transaction distribution 137811138Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution 137911201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 358 # Transaction distribution 138011201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 115261 # Transaction distribution 138111201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 115261 # Transaction distribution 138211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 289006 # Transaction distribution 138311201Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 81 # Transaction distribution 138410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 138510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 138611138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 138711201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146220 # Packet count per connected master and slave (bytes) 138811201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) 138911201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179438 # Packet count per connected master and slave (bytes) 139010892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 139110892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) 139211201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1304255 # Packet count per connected master and slave (bytes) 139311138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 139411201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707264 # Cumulative packet size per connected master and slave (bytes) 139511201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751412 # Cumulative packet size per connected master and slave (bytes) 139610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 139710892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 139811201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 33409140 # Cumulative packet size per connected master and slave (bytes) 139910585Sandreas.hansson@arm.comsystem.membus.snoops 435 # Total snoops (count) 140011201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 842165 # Request fanout histogram 140110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 140210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 140310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 140410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 140511201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 842165 100.00% 100.00% # Request fanout histogram 140610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 140710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 140810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 140910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 141011201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 842165 # Request fanout histogram 141111201Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) 141210585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 141311201Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1314315898 # Layer occupancy (ticks) 141410585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 141511201Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) 141610585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 141711201Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2139099889 # Layer occupancy (ticks) 141810726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 141911201Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) 142010585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 142110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 142210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 142310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 142410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 142510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 142610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 142710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 142810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 142910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 143010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 143110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 143210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 143310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 143410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 143510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 143610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 143710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 143810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 143910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 144010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 144110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 144210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 144310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 144410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 144510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 144610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 144710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 144810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 144910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 145010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 145110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 14525703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 145311201Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 145411201Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211011 # number of hwrei instructions executed 145511201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl 14569285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 145711138Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 145811201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105567 57.93% 100.00% # number of times we switched to this ipl 145911201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182242 # number of times we switched to this ipl 146011201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl 14619285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 146211138Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 146311201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl 146411201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl 146511201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1818035067000 96.92% 96.92% # number of cycles we spent at this ipl 146611201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl 146711201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl 146811201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 57098083500 3.04% 100.00% # number of cycles we spent at this ipl 146911201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl 147011201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 14716127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 14726127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 147311201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl 147411201Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815427 # fraction of swpipl calls that actually changed the ipl 14756291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 14766291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 14776291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 14786291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 14796291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 14806291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 14816291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 14826291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 14836291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 14846291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 14856291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 14866291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 14876291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 14886291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 14896291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 14906291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 14916291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 14926291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 14936291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 14946291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 14956291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 14966291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 14976291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 14986291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 14996291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 15006291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 15016291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 15026291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 15036291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 15046291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 15056127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 15068464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 15078464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 15088464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 15098464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 151010892Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 15119285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 15129199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 151311201Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175125 91.23% 93.43% # number of callpals executed 151411138Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed 15159285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 15169199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 15179285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 15189285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 151911138Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 15208464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 15218464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 152211201Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191970 # number of callpals executed 152311201Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches 152411201Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1738 # number of protection mode switches 152511201Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 152611201Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1908 152711201Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1738 15288517SN/Asystem.cpu.kern.mode_good::idle 170 152911201Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches 15308464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 153111201Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 153211201Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394011 # fraction of useful protection mode switches 153311201Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29997949500 1.60% 1.60% # number of ticks spent at the given mode 153411201Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2897677500 0.15% 1.75% # number of ticks spent at the given mode 153511201Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1842863901000 98.25% 100.00% # number of ticks spent at the given mode 153610892Sandreas.hansson@arm.comsystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 15375703SN/A 15385703SN/A---------- End Simulation Statistics ---------- 1539