xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.860188                       # Number of seconds simulated
sim_ticks                                1860187818000                       # Number of ticks simulated
final_tick                               1860187818000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 129673                       # Simulator instruction rate (inst/s)
host_op_rate                                   129673                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4553007725                       # Simulator tick rate (ticks/s)
host_mem_usage                                 348812                       # Number of bytes of host memory used
host_seconds                                   408.56                       # Real time elapsed on the host
sim_insts                                    52979638                       # Number of instructions simulated
sim_ops                                      52979638                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            963200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24881344                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28496832                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       963200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          963200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7516608                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7516608                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15050                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388771                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445263                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117447                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117447                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               517797                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13375716                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1425817                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15319331                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          517797                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             517797                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4040779                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4040779                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4040779                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              517797                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13375716                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1425817                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19360110                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445263                       # Number of read requests accepted
system.physmem.writeReqs                       117447                       # Number of write requests accepted
system.physmem.readBursts                      445263                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     117447                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28490624                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6208                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7515520                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28496832                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7516608                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       97                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            171                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28211                       # Per bank write bursts
system.physmem.perBankRdBursts::1               27992                       # Per bank write bursts
system.physmem.perBankRdBursts::2               28433                       # Per bank write bursts
system.physmem.perBankRdBursts::3               27987                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27796                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27217                       # Per bank write bursts
system.physmem.perBankRdBursts::6               27269                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27319                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27690                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27272                       # Per bank write bursts
system.physmem.perBankRdBursts::10              28021                       # Per bank write bursts
system.physmem.perBankRdBursts::11              27509                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27548                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28237                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28335                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28330                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7921                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7511                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7946                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7492                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7346                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6678                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6778                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6711                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7130                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6681                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7414                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6966                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7109                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7879                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8056                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7812                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
system.physmem.totGap                    1860182401000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  445263                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117447                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    316668                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59729                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     27667                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      5430                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2043                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3992                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2540                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2086                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1617                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1906                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1882                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     2139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1226                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      986                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      905                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5082                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6071                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      924                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1048                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1859                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2023                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       17                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        63749                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      564.805095                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     351.189585                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     419.649920                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          13350     20.94%     20.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        10335     16.21%     37.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4789      7.51%     44.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2797      4.39%     49.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2437      3.82%     52.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1576      2.47%     55.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1469      2.30%     57.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1613      2.53%     60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25383     39.82%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          63749                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6887                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        64.637723                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       16.523346                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2544.314640                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           6884     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6887                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6887                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.050966                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.814496                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.834643                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               5493     79.76%     79.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 28      0.41%     80.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                690     10.02%     90.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                216      3.14%     93.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                116      1.68%     95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 20      0.29%     95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 25      0.36%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 93      1.35%     97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 19      0.28%     97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 44      0.64%     97.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 11      0.16%     98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  7      0.10%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  8      0.12%     98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 16      0.23%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  2      0.03%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 14      0.20%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  9      0.13%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.01%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  1      0.01%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  3      0.04%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  2      0.03%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.01%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  1      0.01%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  2      0.03%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  7      0.10%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  4      0.06%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  2      0.03%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  3      0.04%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                  1      0.01%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45                  4      0.06%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  3      0.04%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  3      0.04%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  7      0.10%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  4      0.06%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51                  1      0.01%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53                  1      0.01%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54                  1      0.01%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56                  7      0.10%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57                 17      0.25%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6887                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8647566500                       # Total ticks spent queuing
system.physmem.totMemAccLat               16994429000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2225830000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19425.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38175.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.32                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.02                       # Average write queue length when enqueuing
system.physmem.readRowHits                     403062                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95784                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.54                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.56                       # Row buffer hit rate for writes
system.physmem.avgGap                      3305756.79                       # Average gap between requests
system.physmem.pageHitRate                      88.67                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     1761433244000                       # Time in different power states
system.physmem.memoryStateTime::REF       62115560000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       36633312250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     19402968                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              295944                       # Transaction distribution
system.membus.trans_dist::ReadResp             295866                       # Transaction distribution
system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
system.membus.trans_dist::Writeback            117447                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             174                       # Transaction distribution
system.membus.trans_dist::ReadExReq            156883                       # Transaction distribution
system.membus.trans_dist::ReadExResp           156883                       # Transaction distribution
system.membus.trans_dist::BadAddressError           78                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884195                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          156                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917405                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1042084                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30704384                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30748524                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36057580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36057580                       # Total data (bytes)
system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            29864500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1548275500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy               98000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3770327047                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376611244                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.261115                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1710335896000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.261115                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078820                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078820                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21272883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21272883                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  12456693929                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12456693929                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  12477966812                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12477966812                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  12477966812                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12477966812                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122964.641618                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 299785.664445                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 299052.529946                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 299052.529946                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        365915                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                28370                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.897956                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12274883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12274883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10293819441                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10293819441                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  10306094324                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10306094324                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  10306094324                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10306094324                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 247000.463128                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 247000.463128                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13846630                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11622667                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            398238                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9513264                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5817388                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             61.150284                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  900921                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              39034                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9912884                       # DTB read hits
system.cpu.dtb.read_misses                      41215                       # DTB read misses
system.cpu.dtb.read_acv                           553                       # DTB read access violations
system.cpu.dtb.read_accesses                   941108                       # DTB read accesses
system.cpu.dtb.write_hits                     6599017                       # DTB write hits
system.cpu.dtb.write_misses                     10339                       # DTB write misses
system.cpu.dtb.write_acv                          401                       # DTB write access violations
system.cpu.dtb.write_accesses                  338138                       # DTB write accesses
system.cpu.dtb.data_hits                     16511901                       # DTB hits
system.cpu.dtb.data_misses                      51554                       # DTB misses
system.cpu.dtb.data_acv                           954                       # DTB access violations
system.cpu.dtb.data_accesses                  1279246                       # DTB accesses
system.cpu.itb.fetch_hits                     1308304                       # ITB hits
system.cpu.itb.fetch_misses                     36786                       # ITB misses
system.cpu.itb.fetch_acv                         1079                       # ITB acv
system.cpu.itb.fetch_accesses                 1345090                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        121969353                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28022459                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70674133                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13846630                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6718309                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13243332                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1983249                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               37995640                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32164                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        254581                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       364654                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          235                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8542175                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                264688                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           81194854                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.870426                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.213908                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 67951522     83.69%     83.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   854853      1.05%     84.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1698258      2.09%     86.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   823227      1.01%     87.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2753963      3.39%     91.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   558188      0.69%     91.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   642929      0.79%     92.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1006595      1.24%     93.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4905319      6.04%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             81194854                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.113525                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.579442                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29206421                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37679452                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12104138                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                965352                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1239490                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               585042                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42720                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69357398                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129450                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1239490                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30354385                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                13996332                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       19984766                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11324382                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4295497                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65588313                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  7118                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 505148                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1530678                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43795306                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79617271                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79438234                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            166586                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38180209                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5615089                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1682372                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         239607                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12205686                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10422971                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6895231                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1319326                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           854507                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58152614                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2049745                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56795087                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued             97937                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6861282                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3503589                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1388801                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      81194854                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.699491                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.361721                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            56519522     69.61%     69.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10856431     13.37%     82.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5145956      6.34%     89.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3402319      4.19%     93.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2626681      3.24%     96.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1459376      1.80%     98.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              753323      0.93%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              333723      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               97523      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        81194854                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   92642     11.69%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 372744     47.05%     58.74% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                326922     41.26%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38726894     68.19%     68.20% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61723      0.11%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10344006     18.21%     86.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6676923     11.76%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949012      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56795087                       # Type of FU issued
system.cpu.iq.rate                           0.465650                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      792308                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013950                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          194982001                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66741051                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55566428                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              693271                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             336387                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327889                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57217918                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  362191                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           598643                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1330641                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         3245                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14147                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       517313                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17932                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        166827                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1239490                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                10213175                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                697716                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63724678                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            681593                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10422971                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6895231                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1805950                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 512370                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 16905                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14147                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         202448                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       409860                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               612308                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56329043                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts               9982328                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            466043                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3522319                       # number of nop insts executed
system.cpu.iew.exec_refs                     16606918                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8922931                       # Number of branches executed
system.cpu.iew.exec_stores                    6624590                       # Number of stores executed
system.cpu.iew.exec_rate                     0.461829                       # Inst execution rate
system.cpu.iew.wb_sent                       56008659                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55894317                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27713107                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37520284                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.458265                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.738617                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7436889                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660944                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            566942                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     79955364                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.702522                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.631936                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     59166975     74.00%     74.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8627079     10.79%     84.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4603678      5.76%     90.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2536989      3.17%     93.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1507337      1.89%     95.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       611638      0.76%     96.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       523619      0.65%     97.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       528614      0.66%     97.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1849435      2.31%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     79955364                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56170432                       # Number of instructions committed
system.cpu.commit.committedOps               56170432                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15470248                       # Number of memory references committed
system.cpu.commit.loads                       9092330                       # Number of loads committed
system.cpu.commit.membars                      226348                       # Number of memory barriers committed
system.cpu.commit.branches                    8439871                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52020070                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740568                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      3198067      5.69%      5.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         36230888     64.50%     70.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           60673      0.11%     70.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.30% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd          25607      0.05%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv           3636      0.01%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.36% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead         9318678     16.59%     86.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        6383871     11.37%     98.31% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess        949012      1.69%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          56170432                       # Class of committed instruction
system.cpu.commit.bw_lim_events               1849435                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    141463709                       # The number of ROB reads
system.cpu.rob.rob_writes                   128455843                       # The number of ROB writes
system.cpu.timesIdled                         1197783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        40774499                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3598399845                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52979638                       # Number of Instructions Simulated
system.cpu.committedOps                      52979638                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52979638                       # Number of Instructions Simulated
system.cpu.cpi                               2.302193                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.302193                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.434368                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.434368                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73867254                       # number of integer regfile reads
system.cpu.int_regfile_writes                40307997                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166020                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167441                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 2027897                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938938                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1454556                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116504                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20200                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44140                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2705748                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2705748                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4661000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           380172568                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43172756                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.toL2Bus.throughput               111944057                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2118154                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2118059                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       840946                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           62                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           64                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       342489                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       300938                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           78                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2020220                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3677927                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5698147                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64643392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143586284                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      208229676                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         208219628                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        17344                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2480508998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1518532368                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2189805164                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.icache.tags.replacements           1009436                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.668112                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7476172                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1009944                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.402561                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26651967250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.668112                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995446                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995446                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9552342                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9552342                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7476173                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7476173                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7476173                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7476173                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7476173                       # number of overall hits
system.cpu.icache.overall_hits::total         7476173                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1066002                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1066002                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1066002                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1066002                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1066002                       # number of overall misses
system.cpu.icache.overall_misses::total       1066002                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14786308436                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14786308436                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14786308436                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14786308436                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14786308436                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14786308436                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8542175                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8542175                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8542175                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8542175                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8542175                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8542175                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124793                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124793                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124793                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124793                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124793                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124793                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13870.807406                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13870.807406                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4221                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    23.065574                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        55835                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        55835                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        55835                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        55835                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        55835                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        55835                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1010167                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1010167                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1010167                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1010167                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1010167                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1010167                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12133097628                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12133097628                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12133097628                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12133097628                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12133097628                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12133097628                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118256                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118256                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118256                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.118256                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118256                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.118256                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           338321                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65341.789916                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2546336                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           403490                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.310778                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       5544203750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5292.784095                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6141.557358                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.822562                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080761                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.093713                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997037                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65169                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3494                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3325                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2414                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55443                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994400                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         26727783                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        26727783                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       995001                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       827094                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1822095                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840946                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840946                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           27                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           27                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185467                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185467                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       995001                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1012561                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2007562                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       995001                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1012561                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2007562                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15052                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273790                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288842                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           35                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           35                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115470                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115470                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15052                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389260                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404312                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15052                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389260                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404312                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1147195743                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17910681229                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  19057876972                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       262998                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       262998                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9445420357                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9445420357                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1147195743                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  27356101586                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28503297329                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1147195743                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  27356101586                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28503297329                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1010053                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100884                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2110937                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840946                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840946                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           62                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           62                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       300937                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       300937                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1010053                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1401821                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2411874                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1010053                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1401821                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2411874                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014902                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248700                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136831                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.564516                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.564516                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383702                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383702                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014902                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277682                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167634                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014902                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277682                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167634                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76215.502458                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65417.587308                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65980.283241                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  7514.228571                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  7514.228571                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81799.777925                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81799.777925                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76215.502458                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70277.196696                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70498.271951                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76215.502458                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70277.196696                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70498.271951                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75935                       # number of writebacks
system.cpu.l2cache.writebacks::total            75935                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15051                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273790                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288841                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           35                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           35                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115470                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115470                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15051                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389260                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404311                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15051                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389260                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404311                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    957328507                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14497719271                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15455047778                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       500032                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       500032                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8018115143                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8018115143                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    957328507                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22515834414                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23473162921                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    957328507                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22515834414                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23473162921                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333977500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333977500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882390000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882390000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216367500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216367500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014901                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248700                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136831                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.564516                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.564516                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383702                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383702                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014901                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277682                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167634                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014901                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277682                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167634                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63605.641286                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52951.967826                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53507.112141                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14286.628571                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14286.628571                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69438.946419                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69438.946419                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63605.641286                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57842.661496                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58057.195874                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63605.641286                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57842.661496                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58057.195874                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1401230                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.994514                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            11803041                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1401742                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              8.420266                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          25812000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.994514                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          417                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63715251                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63715251                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7198260                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7198260                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4203038                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4203038                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186010                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186010                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215511                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215511                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11401298                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11401298                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11401298                       # number of overall hits
system.cpu.dcache.overall_hits::total        11401298                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1808147                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1808147                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1944666                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1944666                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22743                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22743                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3752813                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3752813                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3752813                       # number of overall misses
system.cpu.dcache.overall_misses::total       3752813                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  40323855155                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  40323855155                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  76523868035                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  76523868035                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    322545000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    322545000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        26000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 116847723190                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 116847723190                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 116847723190                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 116847723190                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9006407                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9006407                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6147704                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6147704                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208753                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       208753                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215513                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215513                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15154111                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15154111                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15154111                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15154111                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200762                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.200762                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316324                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316324                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108947                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108947                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247643                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247643                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247643                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247643                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31136.036672                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31136.036672                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      3013190                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          829                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             80012                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.659226                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   118.428571                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840946                       # number of writebacks
system.cpu.dcache.writebacks::total            840946                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       724204                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       724204                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1644324                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1644324                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5146                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5146                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2368528                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2368528                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2368528                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2368528                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083943                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1083943                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300342                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300342                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17597                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17597                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1384285                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1384285                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1384285                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1384285                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27275514507                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  27275514507                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11674414609                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11674414609                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    201282500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    201282500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  38949929116                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  38949929116                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  38949929116                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  38949929116                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424067500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424067500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997567998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997567998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421635498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421635498                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120352                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120352                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048854                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048854                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084296                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084296                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091347                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091347                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091347                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091347                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211003                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74661     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105563     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182234                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73294     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1817873983000     97.73%     97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                64184500      0.00%     97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               553817500      0.03%     97.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             41694992500      2.24%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1860186977500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694315                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815424                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175119     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191963                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326384                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29561208000      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2704677000      0.15%      1.73% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1827921084500     98.27%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------