config.ini revision 9661
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000 15console=/dist/m5/system/binaries/console 16init_param=0 17kernel=/dist/m5/system/binaries/vmlinux 18load_addr_mask=1099511627775 19mem_mode=timing 20mem_ranges=0:134217727 21memories=system.physmem 22num_work_ids=16 23pal=/dist/m5/system/binaries/ts_osfpal 24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clock=500 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76fetchToDecodeDelay=1 77fetchTrapLatency=1 78fetchWidth=8 79forwardComSize=5 80fuPool=system.cpu.fuPool 81function_trace=false 82function_trace_start=0 83iewToCommitDelay=1 84iewToDecodeDelay=1 85iewToFetchDelay=1 86iewToRenameDelay=1 87interrupts=system.cpu.interrupts 88isa=system.cpu.isa 89issueToExecuteDelay=1 90issueWidth=8 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysFloatRegs=256 99numPhysIntRegs=256 100numROBEntries=192 101numRobs=1 102numThreads=1 103profile=0 104progress_interval=0 105renameToDecodeDelay=1 106renameToFetchDelay=1 107renameToIEWDelay=2 108renameToROBDelay=1 109renameWidth=8 110simpoint_start_insts= 111smtCommitPolicy=RoundRobin 112smtFetchPolicy=SingleThread 113smtIQPolicy=Partitioned 114smtIQThreshold=100 115smtLSQPolicy=Partitioned 116smtLSQThreshold=100 117smtNumFetchingThreads=1 118smtROBPolicy=Partitioned 119smtROBThreshold=100 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 128workload= 129dcache_port=system.cpu.dcache.cpu_side 130icache_port=system.cpu.icache.cpu_side 131 132[system.cpu.branchPred] 133type=BranchPredictor 134BTBEntries=4096 135BTBTagSize=16 136RASSize=16 137choiceCtrBits=2 138choicePredictorSize=8192 139globalCtrBits=2 140globalHistoryBits=13 141globalPredictorSize=8192 142instShiftAmt=2 143localCtrBits=2 144localHistoryBits=11 145localHistoryTableSize=2048 146localPredictorSize=2048 147numThreads=1 148predType=tournament 149 150[system.cpu.dcache] 151type=BaseCache 152addr_ranges=0:18446744073709551615 153assoc=4 154block_size=64 155clock=500 156forward_snoops=true 157hit_latency=2 158is_top_level=true 159max_miss_count=0 160mshrs=4 161prefetch_on_access=false 162prefetcher=Null 163response_latency=2 164size=32768 165system=system 166tgts_per_mshr=20 167two_queue=false 168write_buffers=8 169cpu_side=system.cpu.dcache_port 170mem_side=system.cpu.toL2Bus.slave[1] 171 172[system.cpu.dtb] 173type=AlphaTLB 174size=64 175 176[system.cpu.fuPool] 177type=FUPool 178children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 179FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 180 181[system.cpu.fuPool.FUList0] 182type=FUDesc 183children=opList 184count=6 185opList=system.cpu.fuPool.FUList0.opList 186 187[system.cpu.fuPool.FUList0.opList] 188type=OpDesc 189issueLat=1 190opClass=IntAlu 191opLat=1 192 193[system.cpu.fuPool.FUList1] 194type=FUDesc 195children=opList0 opList1 196count=2 197opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 198 199[system.cpu.fuPool.FUList1.opList0] 200type=OpDesc 201issueLat=1 202opClass=IntMult 203opLat=3 204 205[system.cpu.fuPool.FUList1.opList1] 206type=OpDesc 207issueLat=19 208opClass=IntDiv 209opLat=20 210 211[system.cpu.fuPool.FUList2] 212type=FUDesc 213children=opList0 opList1 opList2 214count=4 215opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 216 217[system.cpu.fuPool.FUList2.opList0] 218type=OpDesc 219issueLat=1 220opClass=FloatAdd 221opLat=2 222 223[system.cpu.fuPool.FUList2.opList1] 224type=OpDesc 225issueLat=1 226opClass=FloatCmp 227opLat=2 228 229[system.cpu.fuPool.FUList2.opList2] 230type=OpDesc 231issueLat=1 232opClass=FloatCvt 233opLat=2 234 235[system.cpu.fuPool.FUList3] 236type=FUDesc 237children=opList0 opList1 opList2 238count=2 239opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 240 241[system.cpu.fuPool.FUList3.opList0] 242type=OpDesc 243issueLat=1 244opClass=FloatMult 245opLat=4 246 247[system.cpu.fuPool.FUList3.opList1] 248type=OpDesc 249issueLat=12 250opClass=FloatDiv 251opLat=12 252 253[system.cpu.fuPool.FUList3.opList2] 254type=OpDesc 255issueLat=24 256opClass=FloatSqrt 257opLat=24 258 259[system.cpu.fuPool.FUList4] 260type=FUDesc 261children=opList 262count=0 263opList=system.cpu.fuPool.FUList4.opList 264 265[system.cpu.fuPool.FUList4.opList] 266type=OpDesc 267issueLat=1 268opClass=MemRead 269opLat=1 270 271[system.cpu.fuPool.FUList5] 272type=FUDesc 273children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 274count=4 275opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 276 277[system.cpu.fuPool.FUList5.opList00] 278type=OpDesc 279issueLat=1 280opClass=SimdAdd 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList01] 284type=OpDesc 285issueLat=1 286opClass=SimdAddAcc 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList02] 290type=OpDesc 291issueLat=1 292opClass=SimdAlu 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList03] 296type=OpDesc 297issueLat=1 298opClass=SimdCmp 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList04] 302type=OpDesc 303issueLat=1 304opClass=SimdCvt 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList05] 308type=OpDesc 309issueLat=1 310opClass=SimdMisc 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList06] 314type=OpDesc 315issueLat=1 316opClass=SimdMult 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList07] 320type=OpDesc 321issueLat=1 322opClass=SimdMultAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList08] 326type=OpDesc 327issueLat=1 328opClass=SimdShift 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList09] 332type=OpDesc 333issueLat=1 334opClass=SimdShiftAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList10] 338type=OpDesc 339issueLat=1 340opClass=SimdSqrt 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList11] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatAdd 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList12] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatAlu 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList13] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatCmp 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList14] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatCvt 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList15] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatDiv 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList16] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMisc 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList17] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatMult 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList18] 386type=OpDesc 387issueLat=1 388opClass=SimdFloatMultAcc 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList19] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatSqrt 395opLat=1 396 397[system.cpu.fuPool.FUList6] 398type=FUDesc 399children=opList 400count=0 401opList=system.cpu.fuPool.FUList6.opList 402 403[system.cpu.fuPool.FUList6.opList] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu.fuPool.FUList7] 410type=FUDesc 411children=opList0 opList1 412count=4 413opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 414 415[system.cpu.fuPool.FUList7.opList0] 416type=OpDesc 417issueLat=1 418opClass=MemRead 419opLat=1 420 421[system.cpu.fuPool.FUList7.opList1] 422type=OpDesc 423issueLat=1 424opClass=MemWrite 425opLat=1 426 427[system.cpu.fuPool.FUList8] 428type=FUDesc 429children=opList 430count=1 431opList=system.cpu.fuPool.FUList8.opList 432 433[system.cpu.fuPool.FUList8.opList] 434type=OpDesc 435issueLat=3 436opClass=IprAccess 437opLat=3 438 439[system.cpu.icache] 440type=BaseCache 441addr_ranges=0:18446744073709551615 442assoc=1 443block_size=64 444clock=500 445forward_snoops=true 446hit_latency=2 447is_top_level=true 448max_miss_count=0 449mshrs=4 450prefetch_on_access=false 451prefetcher=Null 452response_latency=2 453size=32768 454system=system 455tgts_per_mshr=20 456two_queue=false 457write_buffers=8 458cpu_side=system.cpu.icache_port 459mem_side=system.cpu.toL2Bus.slave[0] 460 461[system.cpu.interrupts] 462type=AlphaInterrupts 463 464[system.cpu.isa] 465type=AlphaISA 466 467[system.cpu.itb] 468type=AlphaTLB 469size=48 470 471[system.cpu.l2cache] 472type=BaseCache 473addr_ranges=0:18446744073709551615 474assoc=8 475block_size=64 476clock=500 477forward_snoops=true 478hit_latency=20 479is_top_level=false 480max_miss_count=0 481mshrs=20 482prefetch_on_access=false 483prefetcher=Null 484response_latency=20 485size=4194304 486system=system 487tgts_per_mshr=12 488two_queue=false 489write_buffers=8 490cpu_side=system.cpu.toL2Bus.master[0] 491mem_side=system.membus.slave[1] 492 493[system.cpu.toL2Bus] 494type=CoherentBus 495block_size=64 496clock=500 497header_cycles=1 498system=system 499use_default_range=false 500width=32 501master=system.cpu.l2cache.cpu_side 502slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 503 504[system.cpu.tracer] 505type=ExeTracer 506 507[system.disk0] 508type=IdeDisk 509children=image 510delay=1000000 511driveID=master 512image=system.disk0.image 513 514[system.disk0.image] 515type=CowDiskImage 516children=child 517child=system.disk0.image.child 518image_file= 519read_only=false 520table_size=65536 521 522[system.disk0.image.child] 523type=RawDiskImage 524image_file=/dist/m5/system/disks/linux-latest.img 525read_only=true 526 527[system.disk2] 528type=IdeDisk 529children=image 530delay=1000000 531driveID=master 532image=system.disk2.image 533 534[system.disk2.image] 535type=CowDiskImage 536children=child 537child=system.disk2.image.child 538image_file= 539read_only=false 540table_size=65536 541 542[system.disk2.image.child] 543type=RawDiskImage 544image_file=/dist/m5/system/disks/linux-bigswap2.img 545read_only=true 546 547[system.intrctrl] 548type=IntrControl 549sys=system 550 551[system.iobus] 552type=NoncoherentBus 553block_size=64 554clock=1000 555header_cycles=1 556use_default_range=true 557width=8 558default=system.tsunami.pciconfig.pio 559master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 560slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 561 562[system.iocache] 563type=BaseCache 564addr_ranges=0:134217727 565assoc=8 566block_size=64 567clock=1000 568forward_snoops=false 569hit_latency=50 570is_top_level=true 571max_miss_count=0 572mshrs=20 573prefetch_on_access=false 574prefetcher=Null 575response_latency=50 576size=1024 577system=system 578tgts_per_mshr=12 579two_queue=false 580write_buffers=8 581cpu_side=system.iobus.master[29] 582mem_side=system.membus.slave[2] 583 584[system.membus] 585type=CoherentBus 586children=badaddr_responder 587block_size=64 588clock=1000 589header_cycles=1 590system=system 591use_default_range=false 592width=8 593default=system.membus.badaddr_responder.pio 594master=system.bridge.slave system.physmem.port 595slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 596 597[system.membus.badaddr_responder] 598type=IsaFake 599clock=1000 600fake_mem=false 601pio_addr=0 602pio_latency=100000 603pio_size=8 604ret_bad_addr=true 605ret_data16=65535 606ret_data32=4294967295 607ret_data64=18446744073709551615 608ret_data8=255 609system=system 610update_data=false 611warn_access= 612pio=system.membus.default 613 614[system.physmem] 615type=SimpleDRAM 616activation_limit=4 617addr_mapping=openmap 618banks_per_rank=8 619channels=1 620clock=1000 621conf_table_reported=false 622in_addr_map=true 623lines_per_rowbuffer=32 624mem_sched_policy=frfcfs 625null=false 626page_policy=open 627range=0:134217727 628ranks_per_channel=2 629read_buffer_size=32 630tBURST=5000 631tCL=13750 632tRCD=13750 633tREFI=7800000 634tRFC=300000 635tRP=13750 636tWTR=7500 637tXAW=40000 638write_buffer_size=32 639write_thresh_perc=70 640zero=false 641port=system.membus.master[1] 642 643[system.simple_disk] 644type=SimpleDisk 645children=disk 646disk=system.simple_disk.disk 647system=system 648 649[system.simple_disk.disk] 650type=RawDiskImage 651image_file=/dist/m5/system/disks/linux-latest.img 652read_only=true 653 654[system.terminal] 655type=Terminal 656intr_control=system.intrctrl 657number=0 658output=true 659port=3456 660 661[system.tsunami] 662type=Tsunami 663children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 664intrctrl=system.intrctrl 665system=system 666 667[system.tsunami.backdoor] 668type=AlphaBackdoor 669clock=1000 670cpu=system.cpu 671disk=system.simple_disk 672pio_addr=8804682956800 673pio_latency=100000 674platform=system.tsunami 675system=system 676terminal=system.terminal 677pio=system.iobus.master[24] 678 679[system.tsunami.cchip] 680type=TsunamiCChip 681clock=1000 682pio_addr=8803072344064 683pio_latency=100000 684system=system 685tsunami=system.tsunami 686pio=system.iobus.master[0] 687 688[system.tsunami.ethernet] 689type=NSGigE 690BAR0=1 691BAR0LegacyIO=false 692BAR0Size=256 693BAR1=0 694BAR1LegacyIO=false 695BAR1Size=4096 696BAR2=0 697BAR2LegacyIO=false 698BAR2Size=0 699BAR3=0 700BAR3LegacyIO=false 701BAR3Size=0 702BAR4=0 703BAR4LegacyIO=false 704BAR4Size=0 705BAR5=0 706BAR5LegacyIO=false 707BAR5Size=0 708BIST=0 709CacheLineSize=0 710CardbusCIS=0 711ClassCode=2 712Command=0 713DeviceID=34 714ExpansionROM=0 715HeaderType=0 716InterruptLine=30 717InterruptPin=1 718LatencyTimer=0 719MaximumLatency=52 720MinimumGrant=176 721ProgIF=0 722Revision=0 723Status=656 724SubClassCode=0 725SubsystemID=0 726SubsystemVendorID=0 727VendorID=4107 728clock=2000 729config_latency=20000 730dma_data_free=false 731dma_desc_free=false 732dma_no_allocate=true 733dma_read_delay=0 734dma_read_factor=0 735dma_write_delay=0 736dma_write_factor=0 737hardware_address=00:90:00:00:00:01 738intr_delay=10000000 739pci_bus=0 740pci_dev=1 741pci_func=0 742pio_latency=30000 743platform=system.tsunami 744rss=false 745rx_delay=1000000 746rx_fifo_size=524288 747rx_filter=true 748rx_thread=false 749system=system 750tx_delay=1000000 751tx_fifo_size=524288 752tx_thread=false 753config=system.iobus.master[28] 754dma=system.iobus.slave[2] 755pio=system.iobus.master[27] 756 757[system.tsunami.fake_OROM] 758type=IsaFake 759clock=1000 760fake_mem=false 761pio_addr=8796093677568 762pio_latency=100000 763pio_size=393216 764ret_bad_addr=false 765ret_data16=65535 766ret_data32=4294967295 767ret_data64=18446744073709551615 768ret_data8=255 769system=system 770update_data=false 771warn_access= 772pio=system.iobus.master[8] 773 774[system.tsunami.fake_ata0] 775type=IsaFake 776clock=1000 777fake_mem=false 778pio_addr=8804615848432 779pio_latency=100000 780pio_size=8 781ret_bad_addr=false 782ret_data16=65535 783ret_data32=4294967295 784ret_data64=18446744073709551615 785ret_data8=255 786system=system 787update_data=false 788warn_access= 789pio=system.iobus.master[19] 790 791[system.tsunami.fake_ata1] 792type=IsaFake 793clock=1000 794fake_mem=false 795pio_addr=8804615848304 796pio_latency=100000 797pio_size=8 798ret_bad_addr=false 799ret_data16=65535 800ret_data32=4294967295 801ret_data64=18446744073709551615 802ret_data8=255 803system=system 804update_data=false 805warn_access= 806pio=system.iobus.master[20] 807 808[system.tsunami.fake_pnp_addr] 809type=IsaFake 810clock=1000 811fake_mem=false 812pio_addr=8804615848569 813pio_latency=100000 814pio_size=8 815ret_bad_addr=false 816ret_data16=65535 817ret_data32=4294967295 818ret_data64=18446744073709551615 819ret_data8=255 820system=system 821update_data=false 822warn_access= 823pio=system.iobus.master[9] 824 825[system.tsunami.fake_pnp_read0] 826type=IsaFake 827clock=1000 828fake_mem=false 829pio_addr=8804615848451 830pio_latency=100000 831pio_size=8 832ret_bad_addr=false 833ret_data16=65535 834ret_data32=4294967295 835ret_data64=18446744073709551615 836ret_data8=255 837system=system 838update_data=false 839warn_access= 840pio=system.iobus.master[11] 841 842[system.tsunami.fake_pnp_read1] 843type=IsaFake 844clock=1000 845fake_mem=false 846pio_addr=8804615848515 847pio_latency=100000 848pio_size=8 849ret_bad_addr=false 850ret_data16=65535 851ret_data32=4294967295 852ret_data64=18446744073709551615 853ret_data8=255 854system=system 855update_data=false 856warn_access= 857pio=system.iobus.master[12] 858 859[system.tsunami.fake_pnp_read2] 860type=IsaFake 861clock=1000 862fake_mem=false 863pio_addr=8804615848579 864pio_latency=100000 865pio_size=8 866ret_bad_addr=false 867ret_data16=65535 868ret_data32=4294967295 869ret_data64=18446744073709551615 870ret_data8=255 871system=system 872update_data=false 873warn_access= 874pio=system.iobus.master[13] 875 876[system.tsunami.fake_pnp_read3] 877type=IsaFake 878clock=1000 879fake_mem=false 880pio_addr=8804615848643 881pio_latency=100000 882pio_size=8 883ret_bad_addr=false 884ret_data16=65535 885ret_data32=4294967295 886ret_data64=18446744073709551615 887ret_data8=255 888system=system 889update_data=false 890warn_access= 891pio=system.iobus.master[14] 892 893[system.tsunami.fake_pnp_read4] 894type=IsaFake 895clock=1000 896fake_mem=false 897pio_addr=8804615848707 898pio_latency=100000 899pio_size=8 900ret_bad_addr=false 901ret_data16=65535 902ret_data32=4294967295 903ret_data64=18446744073709551615 904ret_data8=255 905system=system 906update_data=false 907warn_access= 908pio=system.iobus.master[15] 909 910[system.tsunami.fake_pnp_read5] 911type=IsaFake 912clock=1000 913fake_mem=false 914pio_addr=8804615848771 915pio_latency=100000 916pio_size=8 917ret_bad_addr=false 918ret_data16=65535 919ret_data32=4294967295 920ret_data64=18446744073709551615 921ret_data8=255 922system=system 923update_data=false 924warn_access= 925pio=system.iobus.master[16] 926 927[system.tsunami.fake_pnp_read6] 928type=IsaFake 929clock=1000 930fake_mem=false 931pio_addr=8804615848835 932pio_latency=100000 933pio_size=8 934ret_bad_addr=false 935ret_data16=65535 936ret_data32=4294967295 937ret_data64=18446744073709551615 938ret_data8=255 939system=system 940update_data=false 941warn_access= 942pio=system.iobus.master[17] 943 944[system.tsunami.fake_pnp_read7] 945type=IsaFake 946clock=1000 947fake_mem=false 948pio_addr=8804615848899 949pio_latency=100000 950pio_size=8 951ret_bad_addr=false 952ret_data16=65535 953ret_data32=4294967295 954ret_data64=18446744073709551615 955ret_data8=255 956system=system 957update_data=false 958warn_access= 959pio=system.iobus.master[18] 960 961[system.tsunami.fake_pnp_write] 962type=IsaFake 963clock=1000 964fake_mem=false 965pio_addr=8804615850617 966pio_latency=100000 967pio_size=8 968ret_bad_addr=false 969ret_data16=65535 970ret_data32=4294967295 971ret_data64=18446744073709551615 972ret_data8=255 973system=system 974update_data=false 975warn_access= 976pio=system.iobus.master[10] 977 978[system.tsunami.fake_ppc] 979type=IsaFake 980clock=1000 981fake_mem=false 982pio_addr=8804615848891 983pio_latency=100000 984pio_size=8 985ret_bad_addr=false 986ret_data16=65535 987ret_data32=4294967295 988ret_data64=18446744073709551615 989ret_data8=255 990system=system 991update_data=false 992warn_access= 993pio=system.iobus.master[7] 994 995[system.tsunami.fake_sm_chip] 996type=IsaFake 997clock=1000 998fake_mem=false 999pio_addr=8804615848816 1000pio_latency=100000 1001pio_size=8 1002ret_bad_addr=false 1003ret_data16=65535 1004ret_data32=4294967295 1005ret_data64=18446744073709551615 1006ret_data8=255 1007system=system 1008update_data=false 1009warn_access= 1010pio=system.iobus.master[2] 1011 1012[system.tsunami.fake_uart1] 1013type=IsaFake 1014clock=1000 1015fake_mem=false 1016pio_addr=8804615848696 1017pio_latency=100000 1018pio_size=8 1019ret_bad_addr=false 1020ret_data16=65535 1021ret_data32=4294967295 1022ret_data64=18446744073709551615 1023ret_data8=255 1024system=system 1025update_data=false 1026warn_access= 1027pio=system.iobus.master[3] 1028 1029[system.tsunami.fake_uart2] 1030type=IsaFake 1031clock=1000 1032fake_mem=false 1033pio_addr=8804615848936 1034pio_latency=100000 1035pio_size=8 1036ret_bad_addr=false 1037ret_data16=65535 1038ret_data32=4294967295 1039ret_data64=18446744073709551615 1040ret_data8=255 1041system=system 1042update_data=false 1043warn_access= 1044pio=system.iobus.master[4] 1045 1046[system.tsunami.fake_uart3] 1047type=IsaFake 1048clock=1000 1049fake_mem=false 1050pio_addr=8804615848680 1051pio_latency=100000 1052pio_size=8 1053ret_bad_addr=false 1054ret_data16=65535 1055ret_data32=4294967295 1056ret_data64=18446744073709551615 1057ret_data8=255 1058system=system 1059update_data=false 1060warn_access= 1061pio=system.iobus.master[5] 1062 1063[system.tsunami.fake_uart4] 1064type=IsaFake 1065clock=1000 1066fake_mem=false 1067pio_addr=8804615848944 1068pio_latency=100000 1069pio_size=8 1070ret_bad_addr=false 1071ret_data16=65535 1072ret_data32=4294967295 1073ret_data64=18446744073709551615 1074ret_data8=255 1075system=system 1076update_data=false 1077warn_access= 1078pio=system.iobus.master[6] 1079 1080[system.tsunami.fb] 1081type=BadDevice 1082clock=1000 1083devicename=FrameBuffer 1084pio_addr=8804615848912 1085pio_latency=100000 1086system=system 1087pio=system.iobus.master[21] 1088 1089[system.tsunami.ide] 1090type=IdeController 1091BAR0=1 1092BAR0LegacyIO=false 1093BAR0Size=8 1094BAR1=1 1095BAR1LegacyIO=false 1096BAR1Size=4 1097BAR2=1 1098BAR2LegacyIO=false 1099BAR2Size=8 1100BAR3=1 1101BAR3LegacyIO=false 1102BAR3Size=4 1103BAR4=1 1104BAR4LegacyIO=false 1105BAR4Size=16 1106BAR5=1 1107BAR5LegacyIO=false 1108BAR5Size=0 1109BIST=0 1110CacheLineSize=0 1111CardbusCIS=0 1112ClassCode=1 1113Command=0 1114DeviceID=28945 1115ExpansionROM=0 1116HeaderType=0 1117InterruptLine=31 1118InterruptPin=1 1119LatencyTimer=0 1120MaximumLatency=0 1121MinimumGrant=0 1122ProgIF=133 1123Revision=0 1124Status=640 1125SubClassCode=1 1126SubsystemID=0 1127SubsystemVendorID=0 1128VendorID=32902 1129clock=1000 1130config_latency=20000 1131ctrl_offset=0 1132disks=system.disk0 system.disk2 1133io_shift=0 1134pci_bus=0 1135pci_dev=0 1136pci_func=0 1137pio_latency=30000 1138platform=system.tsunami 1139system=system 1140config=system.iobus.master[26] 1141dma=system.iobus.slave[1] 1142pio=system.iobus.master[25] 1143 1144[system.tsunami.io] 1145type=TsunamiIO 1146clock=1000 1147frequency=976562500 1148pio_addr=8804615847936 1149pio_latency=100000 1150system=system 1151time=Thu Jan 1 00:00:00 2009 1152tsunami=system.tsunami 1153year_is_bcd=false 1154pio=system.iobus.master[22] 1155 1156[system.tsunami.pchip] 1157type=TsunamiPChip 1158clock=1000 1159pio_addr=8802535473152 1160pio_latency=100000 1161system=system 1162tsunami=system.tsunami 1163pio=system.iobus.master[1] 1164 1165[system.tsunami.pciconfig] 1166type=PciConfigAll 1167bus=0 1168clock=1000 1169pio_latency=30000 1170platform=system.tsunami 1171size=16777216 1172system=system 1173pio=system.iobus.default 1174 1175[system.tsunami.uart] 1176type=Uart8250 1177clock=1000 1178pio_addr=8804615848952 1179pio_latency=100000 1180platform=system.tsunami 1181system=system 1182terminal=system.terminal 1183pio=system.iobus.master[23] 1184 1185