config.ini revision 9620
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000 15console=/scratch/nilay/GEM5/system/binaries/console 16init_param=0 17kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 18load_addr_mask=1099511627775 19mem_mode=timing 20mem_ranges=0:134217727 21memories=system.physmem 22num_work_ids=16 23pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clock=500 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76fetchToDecodeDelay=1 77fetchTrapLatency=1 78fetchWidth=8 79forwardComSize=5 80fuPool=system.cpu.fuPool 81function_trace=false 82function_trace_start=0 83iewToCommitDelay=1 84iewToDecodeDelay=1 85iewToFetchDelay=1 86iewToRenameDelay=1 87interrupts=system.cpu.interrupts 88isa=system.cpu.isa 89issueToExecuteDelay=1 90issueWidth=8 91itb=system.cpu.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysFloatRegs=256 99numPhysIntRegs=256 100numROBEntries=192 101numRobs=1 102numThreads=1 103profile=0 104progress_interval=0 105renameToDecodeDelay=1 106renameToFetchDelay=1 107renameToIEWDelay=2 108renameToROBDelay=1 109renameWidth=8 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119squashWidth=8 120store_set_clear_period=250000 121switched_out=false 122system=system 123tracer=system.cpu.tracer 124trapLatency=13 125wbDepth=1 126wbWidth=8 127workload= 128dcache_port=system.cpu.dcache.cpu_side 129icache_port=system.cpu.icache.cpu_side 130 131[system.cpu.branchPred] 132type=BranchPredictor 133BTBEntries=4096 134BTBTagSize=16 135RASSize=16 136choiceCtrBits=2 137choicePredictorSize=8192 138globalCtrBits=2 139globalHistoryBits=13 140globalPredictorSize=8192 141instShiftAmt=2 142localCtrBits=2 143localHistoryBits=11 144localHistoryTableSize=2048 145localPredictorSize=2048 146numThreads=1 147predType=tournament 148 149[system.cpu.dcache] 150type=BaseCache 151addr_ranges=0:18446744073709551615 152assoc=4 153block_size=64 154clock=500 155forward_snoops=true 156hit_latency=2 157is_top_level=true 158max_miss_count=0 159mshrs=4 160prefetch_on_access=false 161prefetcher=Null 162response_latency=2 163size=32768 164system=system 165tgts_per_mshr=20 166two_queue=false 167write_buffers=8 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dtb] 172type=AlphaTLB 173size=64 174 175[system.cpu.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 179 180[system.cpu.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 184opList=system.cpu.fuPool.FUList0.opList 185 186[system.cpu.fuPool.FUList0.opList] 187type=OpDesc 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 196opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 197 198[system.cpu.fuPool.FUList1.opList0] 199type=OpDesc 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu.fuPool.FUList1.opList1] 205type=OpDesc 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 214opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 215 216[system.cpu.fuPool.FUList2.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu.fuPool.FUList2.opList1] 223type=OpDesc 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu.fuPool.FUList2.opList2] 229type=OpDesc 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 238opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 239 240[system.cpu.fuPool.FUList3.opList0] 241type=OpDesc 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu.fuPool.FUList3.opList1] 247type=OpDesc 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu.fuPool.FUList3.opList2] 253type=OpDesc 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 262opList=system.cpu.fuPool.FUList4.opList 263 264[system.cpu.fuPool.FUList4.opList] 265type=OpDesc 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 274opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 275 276[system.cpu.fuPool.FUList5.opList00] 277type=OpDesc 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList01] 283type=OpDesc 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList02] 289type=OpDesc 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList03] 295type=OpDesc 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList04] 301type=OpDesc 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList05] 307type=OpDesc 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList06] 313type=OpDesc 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList07] 319type=OpDesc 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList08] 325type=OpDesc 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList09] 331type=OpDesc 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList10] 337type=OpDesc 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList11] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList12] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList13] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList14] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList15] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList16] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList17] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList18] 385type=OpDesc 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList19] 391type=OpDesc 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 400opList=system.cpu.fuPool.FUList6.opList 401 402[system.cpu.fuPool.FUList6.opList] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 412opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 413 414[system.cpu.fuPool.FUList7.opList0] 415type=OpDesc 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu.fuPool.FUList7.opList1] 421type=OpDesc 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 430opList=system.cpu.fuPool.FUList8.opList 431 432[system.cpu.fuPool.FUList8.opList] 433type=OpDesc 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu.icache] 439type=BaseCache 440addr_ranges=0:18446744073709551615 441assoc=1 442block_size=64 443clock=500 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 452size=32768 453system=system 454tgts_per_mshr=20 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu.icache_port 458mem_side=system.cpu.toL2Bus.slave[0] 459 460[system.cpu.interrupts] 461type=AlphaInterrupts 462 463[system.cpu.isa] 464type=AlphaISA 465 466[system.cpu.itb] 467type=AlphaTLB 468size=48 469 470[system.cpu.l2cache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=8 474block_size=64 475clock=500 476forward_snoops=true 477hit_latency=20 478is_top_level=false 479max_miss_count=0 480mshrs=20 481prefetch_on_access=false 482prefetcher=Null 483response_latency=20 484size=4194304 485system=system 486tgts_per_mshr=12 487two_queue=false 488write_buffers=8 489cpu_side=system.cpu.toL2Bus.master[0] 490mem_side=system.membus.slave[1] 491 492[system.cpu.toL2Bus] 493type=CoherentBus 494block_size=64 495clock=500 496header_cycles=1 497system=system 498use_default_range=false 499width=32 500master=system.cpu.l2cache.cpu_side 501slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 502 503[system.cpu.tracer] 504type=ExeTracer 505 506[system.disk0] 507type=IdeDisk 508children=image 509delay=1000000 510driveID=master 511image=system.disk0.image 512 513[system.disk0.image] 514type=CowDiskImage 515children=child 516child=system.disk0.image.child 517image_file= 518read_only=false 519table_size=65536 520 521[system.disk0.image.child] 522type=RawDiskImage 523image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img 524read_only=true 525 526[system.disk2] 527type=IdeDisk 528children=image 529delay=1000000 530driveID=master 531image=system.disk2.image 532 533[system.disk2.image] 534type=CowDiskImage 535children=child 536child=system.disk2.image.child 537image_file= 538read_only=false 539table_size=65536 540 541[system.disk2.image.child] 542type=RawDiskImage 543image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img 544read_only=true 545 546[system.intrctrl] 547type=IntrControl 548sys=system 549 550[system.iobus] 551type=NoncoherentBus 552block_size=64 553clock=1000 554header_cycles=1 555use_default_range=true 556width=8 557default=system.tsunami.pciconfig.pio 558master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 559slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 560 561[system.iocache] 562type=BaseCache 563addr_ranges=0:134217727 564assoc=8 565block_size=64 566clock=1000 567forward_snoops=false 568hit_latency=50 569is_top_level=true 570max_miss_count=0 571mshrs=20 572prefetch_on_access=false 573prefetcher=Null 574response_latency=50 575size=1024 576system=system 577tgts_per_mshr=12 578two_queue=false 579write_buffers=8 580cpu_side=system.iobus.master[29] 581mem_side=system.membus.slave[2] 582 583[system.membus] 584type=CoherentBus 585children=badaddr_responder 586block_size=64 587clock=1000 588header_cycles=1 589system=system 590use_default_range=false 591width=8 592default=system.membus.badaddr_responder.pio 593master=system.bridge.slave system.physmem.port 594slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 595 596[system.membus.badaddr_responder] 597type=IsaFake 598clock=1000 599fake_mem=false 600pio_addr=0 601pio_latency=100000 602pio_size=8 603ret_bad_addr=true 604ret_data16=65535 605ret_data32=4294967295 606ret_data64=18446744073709551615 607ret_data8=255 608system=system 609update_data=false 610warn_access= 611pio=system.membus.default 612 613[system.physmem] 614type=SimpleDRAM 615activation_limit=4 616addr_mapping=openmap 617banks_per_rank=8 618channels=1 619clock=1000 620conf_table_reported=false 621in_addr_map=true 622lines_per_rowbuffer=32 623mem_sched_policy=frfcfs 624null=false 625page_policy=open 626range=0:134217727 627ranks_per_channel=2 628read_buffer_size=32 629tBURST=5000 630tCL=13750 631tRCD=13750 632tREFI=7800000 633tRFC=300000 634tRP=13750 635tWTR=7500 636tXAW=40000 637write_buffer_size=32 638write_thresh_perc=70 639zero=false 640port=system.membus.master[1] 641 642[system.simple_disk] 643type=SimpleDisk 644children=disk 645disk=system.simple_disk.disk 646system=system 647 648[system.simple_disk.disk] 649type=RawDiskImage 650image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img 651read_only=true 652 653[system.terminal] 654type=Terminal 655intr_control=system.intrctrl 656number=0 657output=true 658port=3456 659 660[system.tsunami] 661type=Tsunami 662children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 663intrctrl=system.intrctrl 664system=system 665 666[system.tsunami.backdoor] 667type=AlphaBackdoor 668clock=1000 669cpu=system.cpu 670disk=system.simple_disk 671pio_addr=8804682956800 672pio_latency=100000 673platform=system.tsunami 674system=system 675terminal=system.terminal 676pio=system.iobus.master[24] 677 678[system.tsunami.cchip] 679type=TsunamiCChip 680clock=1000 681pio_addr=8803072344064 682pio_latency=100000 683system=system 684tsunami=system.tsunami 685pio=system.iobus.master[0] 686 687[system.tsunami.ethernet] 688type=NSGigE 689BAR0=1 690BAR0LegacyIO=false 691BAR0Size=256 692BAR1=0 693BAR1LegacyIO=false 694BAR1Size=4096 695BAR2=0 696BAR2LegacyIO=false 697BAR2Size=0 698BAR3=0 699BAR3LegacyIO=false 700BAR3Size=0 701BAR4=0 702BAR4LegacyIO=false 703BAR4Size=0 704BAR5=0 705BAR5LegacyIO=false 706BAR5Size=0 707BIST=0 708CacheLineSize=0 709CardbusCIS=0 710ClassCode=2 711Command=0 712DeviceID=34 713ExpansionROM=0 714HeaderType=0 715InterruptLine=30 716InterruptPin=1 717LatencyTimer=0 718MaximumLatency=52 719MinimumGrant=176 720ProgIF=0 721Revision=0 722Status=656 723SubClassCode=0 724SubsystemID=0 725SubsystemVendorID=0 726VendorID=4107 727clock=2000 728config_latency=20000 729dma_data_free=false 730dma_desc_free=false 731dma_no_allocate=true 732dma_read_delay=0 733dma_read_factor=0 734dma_write_delay=0 735dma_write_factor=0 736hardware_address=00:90:00:00:00:01 737intr_delay=10000000 738pci_bus=0 739pci_dev=1 740pci_func=0 741pio_latency=30000 742platform=system.tsunami 743rss=false 744rx_delay=1000000 745rx_fifo_size=524288 746rx_filter=true 747rx_thread=false 748system=system 749tx_delay=1000000 750tx_fifo_size=524288 751tx_thread=false 752config=system.iobus.master[28] 753dma=system.iobus.slave[2] 754pio=system.iobus.master[27] 755 756[system.tsunami.fake_OROM] 757type=IsaFake 758clock=1000 759fake_mem=false 760pio_addr=8796093677568 761pio_latency=100000 762pio_size=393216 763ret_bad_addr=false 764ret_data16=65535 765ret_data32=4294967295 766ret_data64=18446744073709551615 767ret_data8=255 768system=system 769update_data=false 770warn_access= 771pio=system.iobus.master[8] 772 773[system.tsunami.fake_ata0] 774type=IsaFake 775clock=1000 776fake_mem=false 777pio_addr=8804615848432 778pio_latency=100000 779pio_size=8 780ret_bad_addr=false 781ret_data16=65535 782ret_data32=4294967295 783ret_data64=18446744073709551615 784ret_data8=255 785system=system 786update_data=false 787warn_access= 788pio=system.iobus.master[19] 789 790[system.tsunami.fake_ata1] 791type=IsaFake 792clock=1000 793fake_mem=false 794pio_addr=8804615848304 795pio_latency=100000 796pio_size=8 797ret_bad_addr=false 798ret_data16=65535 799ret_data32=4294967295 800ret_data64=18446744073709551615 801ret_data8=255 802system=system 803update_data=false 804warn_access= 805pio=system.iobus.master[20] 806 807[system.tsunami.fake_pnp_addr] 808type=IsaFake 809clock=1000 810fake_mem=false 811pio_addr=8804615848569 812pio_latency=100000 813pio_size=8 814ret_bad_addr=false 815ret_data16=65535 816ret_data32=4294967295 817ret_data64=18446744073709551615 818ret_data8=255 819system=system 820update_data=false 821warn_access= 822pio=system.iobus.master[9] 823 824[system.tsunami.fake_pnp_read0] 825type=IsaFake 826clock=1000 827fake_mem=false 828pio_addr=8804615848451 829pio_latency=100000 830pio_size=8 831ret_bad_addr=false 832ret_data16=65535 833ret_data32=4294967295 834ret_data64=18446744073709551615 835ret_data8=255 836system=system 837update_data=false 838warn_access= 839pio=system.iobus.master[11] 840 841[system.tsunami.fake_pnp_read1] 842type=IsaFake 843clock=1000 844fake_mem=false 845pio_addr=8804615848515 846pio_latency=100000 847pio_size=8 848ret_bad_addr=false 849ret_data16=65535 850ret_data32=4294967295 851ret_data64=18446744073709551615 852ret_data8=255 853system=system 854update_data=false 855warn_access= 856pio=system.iobus.master[12] 857 858[system.tsunami.fake_pnp_read2] 859type=IsaFake 860clock=1000 861fake_mem=false 862pio_addr=8804615848579 863pio_latency=100000 864pio_size=8 865ret_bad_addr=false 866ret_data16=65535 867ret_data32=4294967295 868ret_data64=18446744073709551615 869ret_data8=255 870system=system 871update_data=false 872warn_access= 873pio=system.iobus.master[13] 874 875[system.tsunami.fake_pnp_read3] 876type=IsaFake 877clock=1000 878fake_mem=false 879pio_addr=8804615848643 880pio_latency=100000 881pio_size=8 882ret_bad_addr=false 883ret_data16=65535 884ret_data32=4294967295 885ret_data64=18446744073709551615 886ret_data8=255 887system=system 888update_data=false 889warn_access= 890pio=system.iobus.master[14] 891 892[system.tsunami.fake_pnp_read4] 893type=IsaFake 894clock=1000 895fake_mem=false 896pio_addr=8804615848707 897pio_latency=100000 898pio_size=8 899ret_bad_addr=false 900ret_data16=65535 901ret_data32=4294967295 902ret_data64=18446744073709551615 903ret_data8=255 904system=system 905update_data=false 906warn_access= 907pio=system.iobus.master[15] 908 909[system.tsunami.fake_pnp_read5] 910type=IsaFake 911clock=1000 912fake_mem=false 913pio_addr=8804615848771 914pio_latency=100000 915pio_size=8 916ret_bad_addr=false 917ret_data16=65535 918ret_data32=4294967295 919ret_data64=18446744073709551615 920ret_data8=255 921system=system 922update_data=false 923warn_access= 924pio=system.iobus.master[16] 925 926[system.tsunami.fake_pnp_read6] 927type=IsaFake 928clock=1000 929fake_mem=false 930pio_addr=8804615848835 931pio_latency=100000 932pio_size=8 933ret_bad_addr=false 934ret_data16=65535 935ret_data32=4294967295 936ret_data64=18446744073709551615 937ret_data8=255 938system=system 939update_data=false 940warn_access= 941pio=system.iobus.master[17] 942 943[system.tsunami.fake_pnp_read7] 944type=IsaFake 945clock=1000 946fake_mem=false 947pio_addr=8804615848899 948pio_latency=100000 949pio_size=8 950ret_bad_addr=false 951ret_data16=65535 952ret_data32=4294967295 953ret_data64=18446744073709551615 954ret_data8=255 955system=system 956update_data=false 957warn_access= 958pio=system.iobus.master[18] 959 960[system.tsunami.fake_pnp_write] 961type=IsaFake 962clock=1000 963fake_mem=false 964pio_addr=8804615850617 965pio_latency=100000 966pio_size=8 967ret_bad_addr=false 968ret_data16=65535 969ret_data32=4294967295 970ret_data64=18446744073709551615 971ret_data8=255 972system=system 973update_data=false 974warn_access= 975pio=system.iobus.master[10] 976 977[system.tsunami.fake_ppc] 978type=IsaFake 979clock=1000 980fake_mem=false 981pio_addr=8804615848891 982pio_latency=100000 983pio_size=8 984ret_bad_addr=false 985ret_data16=65535 986ret_data32=4294967295 987ret_data64=18446744073709551615 988ret_data8=255 989system=system 990update_data=false 991warn_access= 992pio=system.iobus.master[7] 993 994[system.tsunami.fake_sm_chip] 995type=IsaFake 996clock=1000 997fake_mem=false 998pio_addr=8804615848816 999pio_latency=100000 1000pio_size=8 1001ret_bad_addr=false 1002ret_data16=65535 1003ret_data32=4294967295 1004ret_data64=18446744073709551615 1005ret_data8=255 1006system=system 1007update_data=false 1008warn_access= 1009pio=system.iobus.master[2] 1010 1011[system.tsunami.fake_uart1] 1012type=IsaFake 1013clock=1000 1014fake_mem=false 1015pio_addr=8804615848696 1016pio_latency=100000 1017pio_size=8 1018ret_bad_addr=false 1019ret_data16=65535 1020ret_data32=4294967295 1021ret_data64=18446744073709551615 1022ret_data8=255 1023system=system 1024update_data=false 1025warn_access= 1026pio=system.iobus.master[3] 1027 1028[system.tsunami.fake_uart2] 1029type=IsaFake 1030clock=1000 1031fake_mem=false 1032pio_addr=8804615848936 1033pio_latency=100000 1034pio_size=8 1035ret_bad_addr=false 1036ret_data16=65535 1037ret_data32=4294967295 1038ret_data64=18446744073709551615 1039ret_data8=255 1040system=system 1041update_data=false 1042warn_access= 1043pio=system.iobus.master[4] 1044 1045[system.tsunami.fake_uart3] 1046type=IsaFake 1047clock=1000 1048fake_mem=false 1049pio_addr=8804615848680 1050pio_latency=100000 1051pio_size=8 1052ret_bad_addr=false 1053ret_data16=65535 1054ret_data32=4294967295 1055ret_data64=18446744073709551615 1056ret_data8=255 1057system=system 1058update_data=false 1059warn_access= 1060pio=system.iobus.master[5] 1061 1062[system.tsunami.fake_uart4] 1063type=IsaFake 1064clock=1000 1065fake_mem=false 1066pio_addr=8804615848944 1067pio_latency=100000 1068pio_size=8 1069ret_bad_addr=false 1070ret_data16=65535 1071ret_data32=4294967295 1072ret_data64=18446744073709551615 1073ret_data8=255 1074system=system 1075update_data=false 1076warn_access= 1077pio=system.iobus.master[6] 1078 1079[system.tsunami.fb] 1080type=BadDevice 1081clock=1000 1082devicename=FrameBuffer 1083pio_addr=8804615848912 1084pio_latency=100000 1085system=system 1086pio=system.iobus.master[21] 1087 1088[system.tsunami.ide] 1089type=IdeController 1090BAR0=1 1091BAR0LegacyIO=false 1092BAR0Size=8 1093BAR1=1 1094BAR1LegacyIO=false 1095BAR1Size=4 1096BAR2=1 1097BAR2LegacyIO=false 1098BAR2Size=8 1099BAR3=1 1100BAR3LegacyIO=false 1101BAR3Size=4 1102BAR4=1 1103BAR4LegacyIO=false 1104BAR4Size=16 1105BAR5=1 1106BAR5LegacyIO=false 1107BAR5Size=0 1108BIST=0 1109CacheLineSize=0 1110CardbusCIS=0 1111ClassCode=1 1112Command=0 1113DeviceID=28945 1114ExpansionROM=0 1115HeaderType=0 1116InterruptLine=31 1117InterruptPin=1 1118LatencyTimer=0 1119MaximumLatency=0 1120MinimumGrant=0 1121ProgIF=133 1122Revision=0 1123Status=640 1124SubClassCode=1 1125SubsystemID=0 1126SubsystemVendorID=0 1127VendorID=32902 1128clock=1000 1129config_latency=20000 1130ctrl_offset=0 1131disks=system.disk0 system.disk2 1132io_shift=0 1133pci_bus=0 1134pci_dev=0 1135pci_func=0 1136pio_latency=30000 1137platform=system.tsunami 1138system=system 1139config=system.iobus.master[26] 1140dma=system.iobus.slave[1] 1141pio=system.iobus.master[25] 1142 1143[system.tsunami.io] 1144type=TsunamiIO 1145clock=1000 1146frequency=976562500 1147pio_addr=8804615847936 1148pio_latency=100000 1149system=system 1150time=Thu Jan 1 00:00:00 2009 1151tsunami=system.tsunami 1152year_is_bcd=false 1153pio=system.iobus.master[22] 1154 1155[system.tsunami.pchip] 1156type=TsunamiPChip 1157clock=1000 1158pio_addr=8802535473152 1159pio_latency=100000 1160system=system 1161tsunami=system.tsunami 1162pio=system.iobus.master[1] 1163 1164[system.tsunami.pciconfig] 1165type=PciConfigAll 1166bus=0 1167clock=1000 1168pio_latency=30000 1169platform=system.tsunami 1170size=16777216 1171system=system 1172pio=system.iobus.default 1173 1174[system.tsunami.uart] 1175type=Uart8250 1176clock=1000 1177pio_addr=8804615848952 1178pio_latency=100000 1179platform=system.tsunami 1180system=system 1181terminal=system.terminal 1182pio=system.iobus.master[23] 1183 1184