config.ini revision 9055:38f1926fb599
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14console=/dist/m5/system/binaries/console 15init_param=0 16kernel=/dist/m5/system/binaries/vmlinux 17load_addr_mask=1099511627775 18mem_mode=timing 19memories=system.physmem 20num_work_ids=16 21pal=/dist/m5/system/binaries/ts_osfpal 22readfile=tests/halt.sh 23symbolfile= 24system_rev=1024 25system_type=34 26work_begin_ckpt_count=0 27work_begin_cpu_id_exit=-1 28work_begin_exit_count=0 29work_cpus_ckpt_count=0 30work_end_ckpt_count=0 31work_end_exit_count=0 32work_item_id=-1 33system_port=system.membus.slave[0] 34 35[system.bridge] 36type=Bridge 37delay=50000 38nack_delay=4000 39ranges=8796093022208:18446744073709551615 40req_size=16 41resp_size=16 42write_ack=false 43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu] 47type=DerivO3CPU 48children=dcache dtb fuPool icache interrupts itb tracer 49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74defer_registration=false 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu.interrupts 96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu.itb 99localCtrBits=2 100localHistoryBits=11 101localHistoryTableSize=2048 102localPredictorSize=2048 103max_insts_all_threads=0 104max_insts_any_thread=0 105max_loads_all_threads=0 106max_loads_any_thread=0 107needsTSO=false 108numIQEntries=64 109numPhysFloatRegs=256 110numPhysIntRegs=256 111numROBEntries=192 112numRobs=1 113numThreads=1 114phase=0 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000 134system=system 135tracer=system.cpu.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu.dcache.cpu_side 141icache_port=system.cpu.icache.cpu_side 142 143[system.cpu.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64 148forward_snoops=true 149hash_delay=1 150is_top_level=true 151latency=1000 152max_miss_count=0 153mshrs=4 154prefetch_on_access=false 155prefetcher=Null 156prioritizeRequests=false 157repl=Null 158size=32768 159subblock_size=0 160system=system 161tgts_per_mshr=20 162trace_addr=0 163two_queue=false 164write_buffers=8 165cpu_side=system.cpu.dcache_port 166mem_side=system.toL2Bus.slave[1] 167 168[system.cpu.dtb] 169type=AlphaTLB 170size=64 171 172[system.cpu.fuPool] 173type=FUPool 174children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 175FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 176 177[system.cpu.fuPool.FUList0] 178type=FUDesc 179children=opList 180count=6 181opList=system.cpu.fuPool.FUList0.opList 182 183[system.cpu.fuPool.FUList0.opList] 184type=OpDesc 185issueLat=1 186opClass=IntAlu 187opLat=1 188 189[system.cpu.fuPool.FUList1] 190type=FUDesc 191children=opList0 opList1 192count=2 193opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 194 195[system.cpu.fuPool.FUList1.opList0] 196type=OpDesc 197issueLat=1 198opClass=IntMult 199opLat=3 200 201[system.cpu.fuPool.FUList1.opList1] 202type=OpDesc 203issueLat=19 204opClass=IntDiv 205opLat=20 206 207[system.cpu.fuPool.FUList2] 208type=FUDesc 209children=opList0 opList1 opList2 210count=4 211opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 212 213[system.cpu.fuPool.FUList2.opList0] 214type=OpDesc 215issueLat=1 216opClass=FloatAdd 217opLat=2 218 219[system.cpu.fuPool.FUList2.opList1] 220type=OpDesc 221issueLat=1 222opClass=FloatCmp 223opLat=2 224 225[system.cpu.fuPool.FUList2.opList2] 226type=OpDesc 227issueLat=1 228opClass=FloatCvt 229opLat=2 230 231[system.cpu.fuPool.FUList3] 232type=FUDesc 233children=opList0 opList1 opList2 234count=2 235opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 236 237[system.cpu.fuPool.FUList3.opList0] 238type=OpDesc 239issueLat=1 240opClass=FloatMult 241opLat=4 242 243[system.cpu.fuPool.FUList3.opList1] 244type=OpDesc 245issueLat=12 246opClass=FloatDiv 247opLat=12 248 249[system.cpu.fuPool.FUList3.opList2] 250type=OpDesc 251issueLat=24 252opClass=FloatSqrt 253opLat=24 254 255[system.cpu.fuPool.FUList4] 256type=FUDesc 257children=opList 258count=0 259opList=system.cpu.fuPool.FUList4.opList 260 261[system.cpu.fuPool.FUList4.opList] 262type=OpDesc 263issueLat=1 264opClass=MemRead 265opLat=1 266 267[system.cpu.fuPool.FUList5] 268type=FUDesc 269children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 270count=4 271opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 272 273[system.cpu.fuPool.FUList5.opList00] 274type=OpDesc 275issueLat=1 276opClass=SimdAdd 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList01] 280type=OpDesc 281issueLat=1 282opClass=SimdAddAcc 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList02] 286type=OpDesc 287issueLat=1 288opClass=SimdAlu 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList03] 292type=OpDesc 293issueLat=1 294opClass=SimdCmp 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList04] 298type=OpDesc 299issueLat=1 300opClass=SimdCvt 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList05] 304type=OpDesc 305issueLat=1 306opClass=SimdMisc 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList06] 310type=OpDesc 311issueLat=1 312opClass=SimdMult 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList07] 316type=OpDesc 317issueLat=1 318opClass=SimdMultAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList08] 322type=OpDesc 323issueLat=1 324opClass=SimdShift 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList09] 328type=OpDesc 329issueLat=1 330opClass=SimdShiftAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList10] 334type=OpDesc 335issueLat=1 336opClass=SimdSqrt 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList11] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAdd 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList12] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatAlu 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList13] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCmp 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList14] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatCvt 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList15] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatDiv 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList16] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMisc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList17] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMult 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList18] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatMultAcc 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList19] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatSqrt 391opLat=1 392 393[system.cpu.fuPool.FUList6] 394type=FUDesc 395children=opList 396count=0 397opList=system.cpu.fuPool.FUList6.opList 398 399[system.cpu.fuPool.FUList6.opList] 400type=OpDesc 401issueLat=1 402opClass=MemWrite 403opLat=1 404 405[system.cpu.fuPool.FUList7] 406type=FUDesc 407children=opList0 opList1 408count=4 409opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 410 411[system.cpu.fuPool.FUList7.opList0] 412type=OpDesc 413issueLat=1 414opClass=MemRead 415opLat=1 416 417[system.cpu.fuPool.FUList7.opList1] 418type=OpDesc 419issueLat=1 420opClass=MemWrite 421opLat=1 422 423[system.cpu.fuPool.FUList8] 424type=FUDesc 425children=opList 426count=1 427opList=system.cpu.fuPool.FUList8.opList 428 429[system.cpu.fuPool.FUList8.opList] 430type=OpDesc 431issueLat=3 432opClass=IprAccess 433opLat=3 434 435[system.cpu.icache] 436type=BaseCache 437addr_ranges=0:18446744073709551615 438assoc=1 439block_size=64 440forward_snoops=true 441hash_delay=1 442is_top_level=true 443latency=1000 444max_miss_count=0 445mshrs=4 446prefetch_on_access=false 447prefetcher=Null 448prioritizeRequests=false 449repl=Null 450size=32768 451subblock_size=0 452system=system 453tgts_per_mshr=20 454trace_addr=0 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu.icache_port 458mem_side=system.toL2Bus.slave[0] 459 460[system.cpu.interrupts] 461type=AlphaInterrupts 462 463[system.cpu.itb] 464type=AlphaTLB 465size=48 466 467[system.cpu.tracer] 468type=ExeTracer 469 470[system.disk0] 471type=IdeDisk 472children=image 473delay=1000000 474driveID=master 475image=system.disk0.image 476 477[system.disk0.image] 478type=CowDiskImage 479children=child 480child=system.disk0.image.child 481image_file= 482read_only=false 483table_size=65536 484 485[system.disk0.image.child] 486type=RawDiskImage 487image_file=/dist/m5/system/disks/linux-latest.img 488read_only=true 489 490[system.disk2] 491type=IdeDisk 492children=image 493delay=1000000 494driveID=master 495image=system.disk2.image 496 497[system.disk2.image] 498type=CowDiskImage 499children=child 500child=system.disk2.image.child 501image_file= 502read_only=false 503table_size=65536 504 505[system.disk2.image.child] 506type=RawDiskImage 507image_file=/dist/m5/system/disks/linux-bigswap2.img 508read_only=true 509 510[system.intrctrl] 511type=IntrControl 512sys=system 513 514[system.iobus] 515type=NoncoherentBus 516block_size=64 517clock=1000 518header_cycles=1 519use_default_range=true 520width=64 521default=system.tsunami.pciconfig.pio 522master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 523slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 524 525[system.iocache] 526type=BaseCache 527addr_ranges=0:8589934591 528assoc=8 529block_size=64 530forward_snoops=false 531hash_delay=1 532is_top_level=true 533latency=50000 534max_miss_count=0 535mshrs=20 536prefetch_on_access=false 537prefetcher=Null 538prioritizeRequests=false 539repl=Null 540size=1024 541subblock_size=0 542system=system 543tgts_per_mshr=12 544trace_addr=0 545two_queue=false 546write_buffers=8 547cpu_side=system.iobus.master[29] 548mem_side=system.membus.slave[1] 549 550[system.l2c] 551type=BaseCache 552addr_ranges=0:18446744073709551615 553assoc=8 554block_size=64 555forward_snoops=true 556hash_delay=1 557is_top_level=false 558latency=10000 559max_miss_count=0 560mshrs=92 561prefetch_on_access=false 562prefetcher=Null 563prioritizeRequests=false 564repl=Null 565size=4194304 566subblock_size=0 567system=system 568tgts_per_mshr=16 569trace_addr=0 570two_queue=false 571write_buffers=8 572cpu_side=system.toL2Bus.master[0] 573mem_side=system.membus.slave[2] 574 575[system.membus] 576type=CoherentBus 577children=badaddr_responder 578block_size=64 579clock=1000 580header_cycles=1 581use_default_range=false 582width=64 583default=system.membus.badaddr_responder.pio 584master=system.bridge.slave system.physmem.port[0] 585slave=system.system_port system.iocache.mem_side system.l2c.mem_side 586 587[system.membus.badaddr_responder] 588type=IsaFake 589fake_mem=false 590pio_addr=0 591pio_latency=1000 592pio_size=8 593ret_bad_addr=true 594ret_data16=65535 595ret_data32=4294967295 596ret_data64=18446744073709551615 597ret_data8=255 598system=system 599update_data=false 600warn_access= 601pio=system.membus.default 602 603[system.physmem] 604type=SimpleMemory 605conf_table_reported=false 606file= 607in_addr_map=true 608latency=30000 609latency_var=0 610null=false 611range=0:134217727 612zero=false 613port=system.membus.master[1] 614 615[system.simple_disk] 616type=SimpleDisk 617children=disk 618disk=system.simple_disk.disk 619system=system 620 621[system.simple_disk.disk] 622type=RawDiskImage 623image_file=/dist/m5/system/disks/linux-latest.img 624read_only=true 625 626[system.terminal] 627type=Terminal 628intr_control=system.intrctrl 629number=0 630output=true 631port=3456 632 633[system.toL2Bus] 634type=CoherentBus 635block_size=64 636clock=1000 637header_cycles=1 638use_default_range=false 639width=64 640master=system.l2c.cpu_side 641slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 642 643[system.tsunami] 644type=Tsunami 645children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 646intrctrl=system.intrctrl 647system=system 648 649[system.tsunami.backdoor] 650type=AlphaBackdoor 651cpu=system.cpu 652disk=system.simple_disk 653pio_addr=8804682956800 654pio_latency=1000 655platform=system.tsunami 656system=system 657terminal=system.terminal 658pio=system.iobus.master[24] 659 660[system.tsunami.cchip] 661type=TsunamiCChip 662pio_addr=8803072344064 663pio_latency=1000 664system=system 665tsunami=system.tsunami 666pio=system.iobus.master[0] 667 668[system.tsunami.ethernet] 669type=NSGigE 670BAR0=1 671BAR0LegacyIO=false 672BAR0Size=256 673BAR1=0 674BAR1LegacyIO=false 675BAR1Size=4096 676BAR2=0 677BAR2LegacyIO=false 678BAR2Size=0 679BAR3=0 680BAR3LegacyIO=false 681BAR3Size=0 682BAR4=0 683BAR4LegacyIO=false 684BAR4Size=0 685BAR5=0 686BAR5LegacyIO=false 687BAR5Size=0 688BIST=0 689CacheLineSize=0 690CardbusCIS=0 691ClassCode=2 692Command=0 693DeviceID=34 694ExpansionROM=0 695HeaderType=0 696InterruptLine=30 697InterruptPin=1 698LatencyTimer=0 699MaximumLatency=52 700MinimumGrant=176 701ProgIF=0 702Revision=0 703Status=656 704SubClassCode=0 705SubsystemID=0 706SubsystemVendorID=0 707VendorID=4107 708clock=0 709config_latency=20000 710dma_data_free=false 711dma_desc_free=false 712dma_no_allocate=true 713dma_read_delay=0 714dma_read_factor=0 715dma_write_delay=0 716dma_write_factor=0 717hardware_address=00:90:00:00:00:01 718intr_delay=10000000 719max_backoff_delay=10000000 720min_backoff_delay=4000 721pci_bus=0 722pci_dev=1 723pci_func=0 724pio_latency=1000 725platform=system.tsunami 726rss=false 727rx_delay=1000000 728rx_fifo_size=524288 729rx_filter=true 730rx_thread=false 731system=system 732tx_delay=1000000 733tx_fifo_size=524288 734tx_thread=false 735config=system.iobus.master[28] 736dma=system.iobus.slave[2] 737pio=system.iobus.master[27] 738 739[system.tsunami.fake_OROM] 740type=IsaFake 741fake_mem=false 742pio_addr=8796093677568 743pio_latency=1000 744pio_size=393216 745ret_bad_addr=false 746ret_data16=65535 747ret_data32=4294967295 748ret_data64=18446744073709551615 749ret_data8=255 750system=system 751update_data=false 752warn_access= 753pio=system.iobus.master[8] 754 755[system.tsunami.fake_ata0] 756type=IsaFake 757fake_mem=false 758pio_addr=8804615848432 759pio_latency=1000 760pio_size=8 761ret_bad_addr=false 762ret_data16=65535 763ret_data32=4294967295 764ret_data64=18446744073709551615 765ret_data8=255 766system=system 767update_data=false 768warn_access= 769pio=system.iobus.master[19] 770 771[system.tsunami.fake_ata1] 772type=IsaFake 773fake_mem=false 774pio_addr=8804615848304 775pio_latency=1000 776pio_size=8 777ret_bad_addr=false 778ret_data16=65535 779ret_data32=4294967295 780ret_data64=18446744073709551615 781ret_data8=255 782system=system 783update_data=false 784warn_access= 785pio=system.iobus.master[20] 786 787[system.tsunami.fake_pnp_addr] 788type=IsaFake 789fake_mem=false 790pio_addr=8804615848569 791pio_latency=1000 792pio_size=8 793ret_bad_addr=false 794ret_data16=65535 795ret_data32=4294967295 796ret_data64=18446744073709551615 797ret_data8=255 798system=system 799update_data=false 800warn_access= 801pio=system.iobus.master[9] 802 803[system.tsunami.fake_pnp_read0] 804type=IsaFake 805fake_mem=false 806pio_addr=8804615848451 807pio_latency=1000 808pio_size=8 809ret_bad_addr=false 810ret_data16=65535 811ret_data32=4294967295 812ret_data64=18446744073709551615 813ret_data8=255 814system=system 815update_data=false 816warn_access= 817pio=system.iobus.master[11] 818 819[system.tsunami.fake_pnp_read1] 820type=IsaFake 821fake_mem=false 822pio_addr=8804615848515 823pio_latency=1000 824pio_size=8 825ret_bad_addr=false 826ret_data16=65535 827ret_data32=4294967295 828ret_data64=18446744073709551615 829ret_data8=255 830system=system 831update_data=false 832warn_access= 833pio=system.iobus.master[12] 834 835[system.tsunami.fake_pnp_read2] 836type=IsaFake 837fake_mem=false 838pio_addr=8804615848579 839pio_latency=1000 840pio_size=8 841ret_bad_addr=false 842ret_data16=65535 843ret_data32=4294967295 844ret_data64=18446744073709551615 845ret_data8=255 846system=system 847update_data=false 848warn_access= 849pio=system.iobus.master[13] 850 851[system.tsunami.fake_pnp_read3] 852type=IsaFake 853fake_mem=false 854pio_addr=8804615848643 855pio_latency=1000 856pio_size=8 857ret_bad_addr=false 858ret_data16=65535 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.iobus.master[14] 866 867[system.tsunami.fake_pnp_read4] 868type=IsaFake 869fake_mem=false 870pio_addr=8804615848707 871pio_latency=1000 872pio_size=8 873ret_bad_addr=false 874ret_data16=65535 875ret_data32=4294967295 876ret_data64=18446744073709551615 877ret_data8=255 878system=system 879update_data=false 880warn_access= 881pio=system.iobus.master[15] 882 883[system.tsunami.fake_pnp_read5] 884type=IsaFake 885fake_mem=false 886pio_addr=8804615848771 887pio_latency=1000 888pio_size=8 889ret_bad_addr=false 890ret_data16=65535 891ret_data32=4294967295 892ret_data64=18446744073709551615 893ret_data8=255 894system=system 895update_data=false 896warn_access= 897pio=system.iobus.master[16] 898 899[system.tsunami.fake_pnp_read6] 900type=IsaFake 901fake_mem=false 902pio_addr=8804615848835 903pio_latency=1000 904pio_size=8 905ret_bad_addr=false 906ret_data16=65535 907ret_data32=4294967295 908ret_data64=18446744073709551615 909ret_data8=255 910system=system 911update_data=false 912warn_access= 913pio=system.iobus.master[17] 914 915[system.tsunami.fake_pnp_read7] 916type=IsaFake 917fake_mem=false 918pio_addr=8804615848899 919pio_latency=1000 920pio_size=8 921ret_bad_addr=false 922ret_data16=65535 923ret_data32=4294967295 924ret_data64=18446744073709551615 925ret_data8=255 926system=system 927update_data=false 928warn_access= 929pio=system.iobus.master[18] 930 931[system.tsunami.fake_pnp_write] 932type=IsaFake 933fake_mem=false 934pio_addr=8804615850617 935pio_latency=1000 936pio_size=8 937ret_bad_addr=false 938ret_data16=65535 939ret_data32=4294967295 940ret_data64=18446744073709551615 941ret_data8=255 942system=system 943update_data=false 944warn_access= 945pio=system.iobus.master[10] 946 947[system.tsunami.fake_ppc] 948type=IsaFake 949fake_mem=false 950pio_addr=8804615848891 951pio_latency=1000 952pio_size=8 953ret_bad_addr=false 954ret_data16=65535 955ret_data32=4294967295 956ret_data64=18446744073709551615 957ret_data8=255 958system=system 959update_data=false 960warn_access= 961pio=system.iobus.master[7] 962 963[system.tsunami.fake_sm_chip] 964type=IsaFake 965fake_mem=false 966pio_addr=8804615848816 967pio_latency=1000 968pio_size=8 969ret_bad_addr=false 970ret_data16=65535 971ret_data32=4294967295 972ret_data64=18446744073709551615 973ret_data8=255 974system=system 975update_data=false 976warn_access= 977pio=system.iobus.master[2] 978 979[system.tsunami.fake_uart1] 980type=IsaFake 981fake_mem=false 982pio_addr=8804615848696 983pio_latency=1000 984pio_size=8 985ret_bad_addr=false 986ret_data16=65535 987ret_data32=4294967295 988ret_data64=18446744073709551615 989ret_data8=255 990system=system 991update_data=false 992warn_access= 993pio=system.iobus.master[3] 994 995[system.tsunami.fake_uart2] 996type=IsaFake 997fake_mem=false 998pio_addr=8804615848936 999pio_latency=1000 1000pio_size=8 1001ret_bad_addr=false 1002ret_data16=65535 1003ret_data32=4294967295 1004ret_data64=18446744073709551615 1005ret_data8=255 1006system=system 1007update_data=false 1008warn_access= 1009pio=system.iobus.master[4] 1010 1011[system.tsunami.fake_uart3] 1012type=IsaFake 1013fake_mem=false 1014pio_addr=8804615848680 1015pio_latency=1000 1016pio_size=8 1017ret_bad_addr=false 1018ret_data16=65535 1019ret_data32=4294967295 1020ret_data64=18446744073709551615 1021ret_data8=255 1022system=system 1023update_data=false 1024warn_access= 1025pio=system.iobus.master[5] 1026 1027[system.tsunami.fake_uart4] 1028type=IsaFake 1029fake_mem=false 1030pio_addr=8804615848944 1031pio_latency=1000 1032pio_size=8 1033ret_bad_addr=false 1034ret_data16=65535 1035ret_data32=4294967295 1036ret_data64=18446744073709551615 1037ret_data8=255 1038system=system 1039update_data=false 1040warn_access= 1041pio=system.iobus.master[6] 1042 1043[system.tsunami.fb] 1044type=BadDevice 1045devicename=FrameBuffer 1046pio_addr=8804615848912 1047pio_latency=1000 1048system=system 1049pio=system.iobus.master[21] 1050 1051[system.tsunami.ide] 1052type=IdeController 1053BAR0=1 1054BAR0LegacyIO=false 1055BAR0Size=8 1056BAR1=1 1057BAR1LegacyIO=false 1058BAR1Size=4 1059BAR2=1 1060BAR2LegacyIO=false 1061BAR2Size=8 1062BAR3=1 1063BAR3LegacyIO=false 1064BAR3Size=4 1065BAR4=1 1066BAR4LegacyIO=false 1067BAR4Size=16 1068BAR5=1 1069BAR5LegacyIO=false 1070BAR5Size=0 1071BIST=0 1072CacheLineSize=0 1073CardbusCIS=0 1074ClassCode=1 1075Command=0 1076DeviceID=28945 1077ExpansionROM=0 1078HeaderType=0 1079InterruptLine=31 1080InterruptPin=1 1081LatencyTimer=0 1082MaximumLatency=0 1083MinimumGrant=0 1084ProgIF=133 1085Revision=0 1086Status=640 1087SubClassCode=1 1088SubsystemID=0 1089SubsystemVendorID=0 1090VendorID=32902 1091config_latency=20000 1092ctrl_offset=0 1093disks=system.disk0 system.disk2 1094io_shift=0 1095max_backoff_delay=10000000 1096min_backoff_delay=4000 1097pci_bus=0 1098pci_dev=0 1099pci_func=0 1100pio_latency=1000 1101platform=system.tsunami 1102system=system 1103config=system.iobus.master[26] 1104dma=system.iobus.slave[1] 1105pio=system.iobus.master[25] 1106 1107[system.tsunami.io] 1108type=TsunamiIO 1109frequency=976562500 1110pio_addr=8804615847936 1111pio_latency=1000 1112system=system 1113time=Thu Jan 1 00:00:00 2009 1114tsunami=system.tsunami 1115year_is_bcd=false 1116pio=system.iobus.master[22] 1117 1118[system.tsunami.pchip] 1119type=TsunamiPChip 1120pio_addr=8802535473152 1121pio_latency=1000 1122system=system 1123tsunami=system.tsunami 1124pio=system.iobus.master[1] 1125 1126[system.tsunami.pciconfig] 1127type=PciConfigAll 1128bus=0 1129pio_latency=1 1130platform=system.tsunami 1131size=16777216 1132system=system 1133pio=system.iobus.default 1134 1135[system.tsunami.uart] 1136type=Uart8250 1137pio_addr=8804615848952 1138pio_latency=1000 1139platform=system.tsunami 1140system=system 1141terminal=system.terminal 1142pio=system.iobus.master[23] 1143 1144