config.ini revision 7761
110259SAndrew.Bardsley@arm.com[root] 210259SAndrew.Bardsley@arm.comtype=Root 310259SAndrew.Bardsley@arm.comchildren=system 410259SAndrew.Bardsley@arm.comdummy=0 510259SAndrew.Bardsley@arm.com 610259SAndrew.Bardsley@arm.com[system] 710259SAndrew.Bardsley@arm.comtype=LinuxAlphaSystem 810259SAndrew.Bardsley@arm.comchildren=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 910259SAndrew.Bardsley@arm.comboot_cpu_frequency=500 1010259SAndrew.Bardsley@arm.comboot_osflags=root=/dev/hda1 console=ttyS0 1110259SAndrew.Bardsley@arm.comconsole=/dist/m5/system/binaries/console 1210259SAndrew.Bardsley@arm.cominit_param=0 1310259SAndrew.Bardsley@arm.comkernel=/dist/m5/system/binaries/vmlinux 1410259SAndrew.Bardsley@arm.comload_addr_mask=1099511627775 1510259SAndrew.Bardsley@arm.commem_mode=timing 1610259SAndrew.Bardsley@arm.compal=/dist/m5/system/binaries/ts_osfpal 1710259SAndrew.Bardsley@arm.comphysmem=system.physmem 1810259SAndrew.Bardsley@arm.comreadfile=tests/halt.sh 1910259SAndrew.Bardsley@arm.comsymbolfile= 2010259SAndrew.Bardsley@arm.comsystem_rev=1024 2110259SAndrew.Bardsley@arm.comsystem_type=34 2210259SAndrew.Bardsley@arm.com 2310259SAndrew.Bardsley@arm.com[system.bridge] 2410259SAndrew.Bardsley@arm.comtype=Bridge 2510259SAndrew.Bardsley@arm.comdelay=50000 2610259SAndrew.Bardsley@arm.comfilter_ranges_a=0:18446744073709551615 2710259SAndrew.Bardsley@arm.comfilter_ranges_b=0:8589934591 2810259SAndrew.Bardsley@arm.comnack_delay=4000 2910259SAndrew.Bardsley@arm.comreq_size_a=16 3010259SAndrew.Bardsley@arm.comreq_size_b=16 3110259SAndrew.Bardsley@arm.comresp_size_a=16 3210259SAndrew.Bardsley@arm.comresp_size_b=16 3310259SAndrew.Bardsley@arm.comwrite_ack=false 3410259SAndrew.Bardsley@arm.comside_a=system.iobus.port[0] 3510259SAndrew.Bardsley@arm.comside_b=system.membus.port[0] 3610259SAndrew.Bardsley@arm.com 3710259SAndrew.Bardsley@arm.com[system.cpu] 3810259SAndrew.Bardsley@arm.comtype=DerivO3CPU 3910259SAndrew.Bardsley@arm.comchildren=dcache dtb fuPool icache interrupts itb tracer 4010259SAndrew.Bardsley@arm.comBTBEntries=4096 4110259SAndrew.Bardsley@arm.comBTBTagSize=16 4210259SAndrew.Bardsley@arm.comLFSTSize=1024 4310259SAndrew.Bardsley@arm.comLQEntries=32 4410259SAndrew.Bardsley@arm.comRASSize=16 4510259SAndrew.Bardsley@arm.comSQEntries=32 4610259SAndrew.Bardsley@arm.comSSITSize=1024 4710259SAndrew.Bardsley@arm.comactivity=0 4810259SAndrew.Bardsley@arm.combackComSize=5 4910259SAndrew.Bardsley@arm.comcachePorts=200 5010259SAndrew.Bardsley@arm.comchecker=Null 5110259SAndrew.Bardsley@arm.comchoiceCtrBits=2 5210259SAndrew.Bardsley@arm.comchoicePredictorSize=8192 5310259SAndrew.Bardsley@arm.comclock=500 5410259SAndrew.Bardsley@arm.comcommitToDecodeDelay=1 5510259SAndrew.Bardsley@arm.comcommitToFetchDelay=1 5610259SAndrew.Bardsley@arm.comcommitToIEWDelay=1 5710259SAndrew.Bardsley@arm.comcommitToRenameDelay=1 5810259SAndrew.Bardsley@arm.comcommitWidth=8 5910259SAndrew.Bardsley@arm.comcpu_id=0 6010259SAndrew.Bardsley@arm.comdecodeToFetchDelay=1 6110259SAndrew.Bardsley@arm.comdecodeToRenameDelay=1 6210259SAndrew.Bardsley@arm.comdecodeWidth=8 6310259SAndrew.Bardsley@arm.comdefer_registration=false 6410259SAndrew.Bardsley@arm.comdispatchWidth=8 6510259SAndrew.Bardsley@arm.comdo_checkpoint_insts=true 6610259SAndrew.Bardsley@arm.comdo_quiesce=true 6710259SAndrew.Bardsley@arm.comdo_statistics_insts=true 6810259SAndrew.Bardsley@arm.comdtb=system.cpu.dtb 6910259SAndrew.Bardsley@arm.comfetchToDecodeDelay=1 7010259SAndrew.Bardsley@arm.comfetchTrapLatency=1 7110259SAndrew.Bardsley@arm.comfetchWidth=8 7210259SAndrew.Bardsley@arm.comforwardComSize=5 7310259SAndrew.Bardsley@arm.comfuPool=system.cpu.fuPool 7410259SAndrew.Bardsley@arm.comfunction_trace=false 7510259SAndrew.Bardsley@arm.comfunction_trace_start=0 7610259SAndrew.Bardsley@arm.comglobalCtrBits=2 7710259SAndrew.Bardsley@arm.comglobalHistoryBits=13 7810259SAndrew.Bardsley@arm.comglobalPredictorSize=8192 7910259SAndrew.Bardsley@arm.comiewToCommitDelay=1 8010259SAndrew.Bardsley@arm.comiewToDecodeDelay=1 8110259SAndrew.Bardsley@arm.comiewToFetchDelay=1 8210259SAndrew.Bardsley@arm.comiewToRenameDelay=1 8310259SAndrew.Bardsley@arm.cominstShiftAmt=2 8410259SAndrew.Bardsley@arm.cominterrupts=system.cpu.interrupts 8510259SAndrew.Bardsley@arm.comissueToExecuteDelay=1 8610259SAndrew.Bardsley@arm.comissueWidth=8 8710259SAndrew.Bardsley@arm.comitb=system.cpu.itb 8810259SAndrew.Bardsley@arm.comlocalCtrBits=2 8910259SAndrew.Bardsley@arm.comlocalHistoryBits=11 9010259SAndrew.Bardsley@arm.comlocalHistoryTableSize=2048 9110259SAndrew.Bardsley@arm.comlocalPredictorSize=2048 9210259SAndrew.Bardsley@arm.commax_insts_all_threads=0 9310259SAndrew.Bardsley@arm.commax_insts_any_thread=0 9410259SAndrew.Bardsley@arm.commax_loads_all_threads=0 9510259SAndrew.Bardsley@arm.commax_loads_any_thread=0 9610259SAndrew.Bardsley@arm.comnumIQEntries=64 9710259SAndrew.Bardsley@arm.comnumPhysFloatRegs=256 9810259SAndrew.Bardsley@arm.comnumPhysIntRegs=256 9910259SAndrew.Bardsley@arm.comnumROBEntries=192 10010259SAndrew.Bardsley@arm.comnumRobs=1 10110259SAndrew.Bardsley@arm.comnumThreads=1 10210259SAndrew.Bardsley@arm.comphase=0 10310259SAndrew.Bardsley@arm.compredType=tournament 10410259SAndrew.Bardsley@arm.comprofile=0 10510259SAndrew.Bardsley@arm.comprogress_interval=0 10610259SAndrew.Bardsley@arm.comrenameToDecodeDelay=1 10710259SAndrew.Bardsley@arm.comrenameToFetchDelay=1 10810259SAndrew.Bardsley@arm.comrenameToIEWDelay=2 10910259SAndrew.Bardsley@arm.comrenameToROBDelay=1 11010259SAndrew.Bardsley@arm.comrenameWidth=8 11110259SAndrew.Bardsley@arm.comsmtCommitPolicy=RoundRobin 11210259SAndrew.Bardsley@arm.comsmtFetchPolicy=SingleThread 11310259SAndrew.Bardsley@arm.comsmtIQPolicy=Partitioned 11410259SAndrew.Bardsley@arm.comsmtIQThreshold=100 11510259SAndrew.Bardsley@arm.comsmtLSQPolicy=Partitioned 11610259SAndrew.Bardsley@arm.comsmtLSQThreshold=100 11710259SAndrew.Bardsley@arm.comsmtNumFetchingThreads=1 11810913Sandreas.sandberg@arm.comsmtROBPolicy=Partitioned 11910259SAndrew.Bardsley@arm.comsmtROBThreshold=100 12010259SAndrew.Bardsley@arm.comsquashWidth=8 12110259SAndrew.Bardsley@arm.comsystem=system 12210259SAndrew.Bardsley@arm.comtracer=system.cpu.tracer 12310259SAndrew.Bardsley@arm.comtrapLatency=13 12410259SAndrew.Bardsley@arm.comwbDepth=1 12510259SAndrew.Bardsley@arm.comwbWidth=8 12610259SAndrew.Bardsley@arm.comdcache_port=system.cpu.dcache.cpu_side 12710259SAndrew.Bardsley@arm.comicache_port=system.cpu.icache.cpu_side 12810259SAndrew.Bardsley@arm.com 12910464SAndreas.Sandberg@ARM.com[system.cpu.dcache] 13010464SAndreas.Sandberg@ARM.comtype=BaseCache 13110464SAndreas.Sandberg@ARM.comaddr_range=0:18446744073709551615 13210464SAndreas.Sandberg@ARM.comassoc=4 13310464SAndreas.Sandberg@ARM.comblock_size=64 13410259SAndrew.Bardsley@arm.comforward_snoops=true 13510259SAndrew.Bardsley@arm.comhash_delay=1 13610259SAndrew.Bardsley@arm.comlatency=1000 13710259SAndrew.Bardsley@arm.commax_miss_count=0 13810259SAndrew.Bardsley@arm.commshrs=4 13910259SAndrew.Bardsley@arm.comnum_cpus=1 14010259SAndrew.Bardsley@arm.comprefetch_data_accesses_only=false 14110259SAndrew.Bardsley@arm.comprefetch_degree=1 14210259SAndrew.Bardsley@arm.comprefetch_latency=10000 14310259SAndrew.Bardsley@arm.comprefetch_on_access=false 14410259SAndrew.Bardsley@arm.comprefetch_past_page=false 14510259SAndrew.Bardsley@arm.comprefetch_policy=none 14610259SAndrew.Bardsley@arm.comprefetch_serial_squash=false 14710259SAndrew.Bardsley@arm.comprefetch_use_cpu_id=true 14810259SAndrew.Bardsley@arm.comprefetcher_size=100 14910259SAndrew.Bardsley@arm.comprioritizeRequests=false 15010259SAndrew.Bardsley@arm.comrepl=Null 151size=32768 152subblock_size=0 153tgts_per_mshr=20 154trace_addr=0 155two_queue=false 156write_buffers=8 157cpu_side=system.cpu.dcache_port 158mem_side=system.toL2Bus.port[2] 159 160[system.cpu.dtb] 161type=AlphaTLB 162size=64 163 164[system.cpu.fuPool] 165type=FUPool 166children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 167FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 168 169[system.cpu.fuPool.FUList0] 170type=FUDesc 171children=opList 172count=6 173opList=system.cpu.fuPool.FUList0.opList 174 175[system.cpu.fuPool.FUList0.opList] 176type=OpDesc 177issueLat=1 178opClass=IntAlu 179opLat=1 180 181[system.cpu.fuPool.FUList1] 182type=FUDesc 183children=opList0 opList1 184count=2 185opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 186 187[system.cpu.fuPool.FUList1.opList0] 188type=OpDesc 189issueLat=1 190opClass=IntMult 191opLat=3 192 193[system.cpu.fuPool.FUList1.opList1] 194type=OpDesc 195issueLat=19 196opClass=IntDiv 197opLat=20 198 199[system.cpu.fuPool.FUList2] 200type=FUDesc 201children=opList0 opList1 opList2 202count=4 203opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 204 205[system.cpu.fuPool.FUList2.opList0] 206type=OpDesc 207issueLat=1 208opClass=FloatAdd 209opLat=2 210 211[system.cpu.fuPool.FUList2.opList1] 212type=OpDesc 213issueLat=1 214opClass=FloatCmp 215opLat=2 216 217[system.cpu.fuPool.FUList2.opList2] 218type=OpDesc 219issueLat=1 220opClass=FloatCvt 221opLat=2 222 223[system.cpu.fuPool.FUList3] 224type=FUDesc 225children=opList0 opList1 opList2 226count=2 227opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 228 229[system.cpu.fuPool.FUList3.opList0] 230type=OpDesc 231issueLat=1 232opClass=FloatMult 233opLat=4 234 235[system.cpu.fuPool.FUList3.opList1] 236type=OpDesc 237issueLat=12 238opClass=FloatDiv 239opLat=12 240 241[system.cpu.fuPool.FUList3.opList2] 242type=OpDesc 243issueLat=24 244opClass=FloatSqrt 245opLat=24 246 247[system.cpu.fuPool.FUList4] 248type=FUDesc 249children=opList 250count=0 251opList=system.cpu.fuPool.FUList4.opList 252 253[system.cpu.fuPool.FUList4.opList] 254type=OpDesc 255issueLat=1 256opClass=MemRead 257opLat=1 258 259[system.cpu.fuPool.FUList5] 260type=FUDesc 261children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 262count=4 263opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 264 265[system.cpu.fuPool.FUList5.opList00] 266type=OpDesc 267issueLat=1 268opClass=SimdAdd 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList01] 272type=OpDesc 273issueLat=1 274opClass=SimdAddAcc 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList02] 278type=OpDesc 279issueLat=1 280opClass=SimdAlu 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList03] 284type=OpDesc 285issueLat=1 286opClass=SimdCmp 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList04] 290type=OpDesc 291issueLat=1 292opClass=SimdCvt 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList05] 296type=OpDesc 297issueLat=1 298opClass=SimdMisc 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList06] 302type=OpDesc 303issueLat=1 304opClass=SimdMult 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList07] 308type=OpDesc 309issueLat=1 310opClass=SimdMultAcc 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList08] 314type=OpDesc 315issueLat=1 316opClass=SimdShift 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList09] 320type=OpDesc 321issueLat=1 322opClass=SimdShiftAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList10] 326type=OpDesc 327issueLat=1 328opClass=SimdSqrt 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList11] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatAdd 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList12] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatAlu 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList13] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatCmp 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList14] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatCvt 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList15] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatDiv 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList16] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMisc 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList17] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMult 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList18] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMultAcc 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList19] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatSqrt 383opLat=1 384 385[system.cpu.fuPool.FUList6] 386type=FUDesc 387children=opList 388count=0 389opList=system.cpu.fuPool.FUList6.opList 390 391[system.cpu.fuPool.FUList6.opList] 392type=OpDesc 393issueLat=1 394opClass=MemWrite 395opLat=1 396 397[system.cpu.fuPool.FUList7] 398type=FUDesc 399children=opList0 opList1 400count=4 401opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 402 403[system.cpu.fuPool.FUList7.opList0] 404type=OpDesc 405issueLat=1 406opClass=MemRead 407opLat=1 408 409[system.cpu.fuPool.FUList7.opList1] 410type=OpDesc 411issueLat=1 412opClass=MemWrite 413opLat=1 414 415[system.cpu.fuPool.FUList8] 416type=FUDesc 417children=opList 418count=1 419opList=system.cpu.fuPool.FUList8.opList 420 421[system.cpu.fuPool.FUList8.opList] 422type=OpDesc 423issueLat=3 424opClass=IprAccess 425opLat=3 426 427[system.cpu.icache] 428type=BaseCache 429addr_range=0:18446744073709551615 430assoc=1 431block_size=64 432forward_snoops=true 433hash_delay=1 434latency=1000 435max_miss_count=0 436mshrs=4 437num_cpus=1 438prefetch_data_accesses_only=false 439prefetch_degree=1 440prefetch_latency=10000 441prefetch_on_access=false 442prefetch_past_page=false 443prefetch_policy=none 444prefetch_serial_squash=false 445prefetch_use_cpu_id=true 446prefetcher_size=100 447prioritizeRequests=false 448repl=Null 449size=32768 450subblock_size=0 451tgts_per_mshr=20 452trace_addr=0 453two_queue=false 454write_buffers=8 455cpu_side=system.cpu.icache_port 456mem_side=system.toL2Bus.port[1] 457 458[system.cpu.interrupts] 459type=AlphaInterrupts 460 461[system.cpu.itb] 462type=AlphaTLB 463size=48 464 465[system.cpu.tracer] 466type=ExeTracer 467 468[system.disk0] 469type=IdeDisk 470children=image 471delay=1000000 472driveID=master 473image=system.disk0.image 474 475[system.disk0.image] 476type=CowDiskImage 477children=child 478child=system.disk0.image.child 479image_file= 480read_only=false 481table_size=65536 482 483[system.disk0.image.child] 484type=RawDiskImage 485image_file=/dist/m5/system/disks/linux-latest.img 486read_only=true 487 488[system.disk2] 489type=IdeDisk 490children=image 491delay=1000000 492driveID=master 493image=system.disk2.image 494 495[system.disk2.image] 496type=CowDiskImage 497children=child 498child=system.disk2.image.child 499image_file= 500read_only=false 501table_size=65536 502 503[system.disk2.image.child] 504type=RawDiskImage 505image_file=/dist/m5/system/disks/linux-bigswap2.img 506read_only=true 507 508[system.intrctrl] 509type=IntrControl 510sys=system 511 512[system.iobus] 513type=Bus 514block_size=64 515bus_id=0 516clock=1000 517header_cycles=1 518use_default_range=true 519width=64 520default=system.tsunami.pciconfig.pio 521port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma 522 523[system.iocache] 524type=BaseCache 525addr_range=0:8589934591 526assoc=8 527block_size=64 528forward_snoops=false 529hash_delay=1 530latency=50000 531max_miss_count=0 532mshrs=20 533num_cpus=1 534prefetch_data_accesses_only=false 535prefetch_degree=1 536prefetch_latency=500000 537prefetch_on_access=false 538prefetch_past_page=false 539prefetch_policy=none 540prefetch_serial_squash=false 541prefetch_use_cpu_id=true 542prefetcher_size=100 543prioritizeRequests=false 544repl=Null 545size=1024 546subblock_size=0 547tgts_per_mshr=12 548trace_addr=0 549two_queue=false 550write_buffers=8 551cpu_side=system.iobus.port[28] 552mem_side=system.membus.port[2] 553 554[system.l2c] 555type=BaseCache 556addr_range=0:18446744073709551615 557assoc=8 558block_size=64 559forward_snoops=true 560hash_delay=1 561latency=10000 562max_miss_count=0 563mshrs=92 564num_cpus=1 565prefetch_data_accesses_only=false 566prefetch_degree=1 567prefetch_latency=100000 568prefetch_on_access=false 569prefetch_past_page=false 570prefetch_policy=none 571prefetch_serial_squash=false 572prefetch_use_cpu_id=true 573prefetcher_size=100 574prioritizeRequests=false 575repl=Null 576size=4194304 577subblock_size=0 578tgts_per_mshr=16 579trace_addr=0 580two_queue=false 581write_buffers=8 582cpu_side=system.toL2Bus.port[0] 583mem_side=system.membus.port[3] 584 585[system.membus] 586type=Bus 587children=badaddr_responder 588block_size=64 589bus_id=1 590clock=1000 591header_cycles=1 592use_default_range=false 593width=64 594default=system.membus.badaddr_responder.pio 595port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side 596 597[system.membus.badaddr_responder] 598type=IsaFake 599pio_addr=0 600pio_latency=1000 601pio_size=8 602platform=system.tsunami 603ret_bad_addr=true 604ret_data16=65535 605ret_data32=4294967295 606ret_data64=18446744073709551615 607ret_data8=255 608system=system 609update_data=false 610warn_access= 611pio=system.membus.default 612 613[system.physmem] 614type=PhysicalMemory 615file= 616latency=30000 617latency_var=0 618null=false 619range=0:134217727 620zero=false 621port=system.membus.port[1] 622 623[system.simple_disk] 624type=SimpleDisk 625children=disk 626disk=system.simple_disk.disk 627system=system 628 629[system.simple_disk.disk] 630type=RawDiskImage 631image_file=/dist/m5/system/disks/linux-latest.img 632read_only=true 633 634[system.terminal] 635type=Terminal 636intr_control=system.intrctrl 637number=0 638output=true 639port=3456 640 641[system.toL2Bus] 642type=Bus 643block_size=64 644bus_id=0 645clock=1000 646header_cycles=1 647use_default_range=false 648width=64 649port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side 650 651[system.tsunami] 652type=Tsunami 653children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 654intrctrl=system.intrctrl 655system=system 656 657[system.tsunami.backdoor] 658type=AlphaBackdoor 659cpu=system.cpu 660disk=system.simple_disk 661pio_addr=8804682956800 662pio_latency=1000 663platform=system.tsunami 664system=system 665terminal=system.terminal 666pio=system.iobus.port[25] 667 668[system.tsunami.cchip] 669type=TsunamiCChip 670pio_addr=8803072344064 671pio_latency=1000 672platform=system.tsunami 673system=system 674tsunami=system.tsunami 675pio=system.iobus.port[1] 676 677[system.tsunami.ethernet] 678type=NSGigE 679BAR0=1 680BAR0LegacyIO=false 681BAR0Size=256 682BAR1=0 683BAR1LegacyIO=false 684BAR1Size=4096 685BAR2=0 686BAR2LegacyIO=false 687BAR2Size=0 688BAR3=0 689BAR3LegacyIO=false 690BAR3Size=0 691BAR4=0 692BAR4LegacyIO=false 693BAR4Size=0 694BAR5=0 695BAR5LegacyIO=false 696BAR5Size=0 697BIST=0 698CacheLineSize=0 699CardbusCIS=0 700ClassCode=2 701Command=0 702DeviceID=34 703ExpansionROM=0 704HeaderType=0 705InterruptLine=30 706InterruptPin=1 707LatencyTimer=0 708MaximumLatency=52 709MinimumGrant=176 710ProgIF=0 711Revision=0 712Status=656 713SubClassCode=0 714SubsystemID=0 715SubsystemVendorID=0 716VendorID=4107 717clock=0 718config_latency=20000 719dma_data_free=false 720dma_desc_free=false 721dma_no_allocate=true 722dma_read_delay=0 723dma_read_factor=0 724dma_write_delay=0 725dma_write_factor=0 726hardware_address=00:90:00:00:00:01 727intr_delay=10000000 728max_backoff_delay=10000000 729min_backoff_delay=4000 730pci_bus=0 731pci_dev=1 732pci_func=0 733pio_latency=1000 734platform=system.tsunami 735rss=false 736rx_delay=1000000 737rx_fifo_size=524288 738rx_filter=true 739rx_thread=false 740system=system 741tx_delay=1000000 742tx_fifo_size=524288 743tx_thread=false 744config=system.iobus.port[29] 745dma=system.iobus.port[30] 746pio=system.iobus.port[27] 747 748[system.tsunami.fake_OROM] 749type=IsaFake 750pio_addr=8796093677568 751pio_latency=1000 752pio_size=393216 753platform=system.tsunami 754ret_bad_addr=false 755ret_data16=65535 756ret_data32=4294967295 757ret_data64=18446744073709551615 758ret_data8=255 759system=system 760update_data=false 761warn_access= 762pio=system.iobus.port[9] 763 764[system.tsunami.fake_ata0] 765type=IsaFake 766pio_addr=8804615848432 767pio_latency=1000 768pio_size=8 769platform=system.tsunami 770ret_bad_addr=false 771ret_data16=65535 772ret_data32=4294967295 773ret_data64=18446744073709551615 774ret_data8=255 775system=system 776update_data=false 777warn_access= 778pio=system.iobus.port[20] 779 780[system.tsunami.fake_ata1] 781type=IsaFake 782pio_addr=8804615848304 783pio_latency=1000 784pio_size=8 785platform=system.tsunami 786ret_bad_addr=false 787ret_data16=65535 788ret_data32=4294967295 789ret_data64=18446744073709551615 790ret_data8=255 791system=system 792update_data=false 793warn_access= 794pio=system.iobus.port[21] 795 796[system.tsunami.fake_pnp_addr] 797type=IsaFake 798pio_addr=8804615848569 799pio_latency=1000 800pio_size=8 801platform=system.tsunami 802ret_bad_addr=false 803ret_data16=65535 804ret_data32=4294967295 805ret_data64=18446744073709551615 806ret_data8=255 807system=system 808update_data=false 809warn_access= 810pio=system.iobus.port[10] 811 812[system.tsunami.fake_pnp_read0] 813type=IsaFake 814pio_addr=8804615848451 815pio_latency=1000 816pio_size=8 817platform=system.tsunami 818ret_bad_addr=false 819ret_data16=65535 820ret_data32=4294967295 821ret_data64=18446744073709551615 822ret_data8=255 823system=system 824update_data=false 825warn_access= 826pio=system.iobus.port[12] 827 828[system.tsunami.fake_pnp_read1] 829type=IsaFake 830pio_addr=8804615848515 831pio_latency=1000 832pio_size=8 833platform=system.tsunami 834ret_bad_addr=false 835ret_data16=65535 836ret_data32=4294967295 837ret_data64=18446744073709551615 838ret_data8=255 839system=system 840update_data=false 841warn_access= 842pio=system.iobus.port[13] 843 844[system.tsunami.fake_pnp_read2] 845type=IsaFake 846pio_addr=8804615848579 847pio_latency=1000 848pio_size=8 849platform=system.tsunami 850ret_bad_addr=false 851ret_data16=65535 852ret_data32=4294967295 853ret_data64=18446744073709551615 854ret_data8=255 855system=system 856update_data=false 857warn_access= 858pio=system.iobus.port[14] 859 860[system.tsunami.fake_pnp_read3] 861type=IsaFake 862pio_addr=8804615848643 863pio_latency=1000 864pio_size=8 865platform=system.tsunami 866ret_bad_addr=false 867ret_data16=65535 868ret_data32=4294967295 869ret_data64=18446744073709551615 870ret_data8=255 871system=system 872update_data=false 873warn_access= 874pio=system.iobus.port[15] 875 876[system.tsunami.fake_pnp_read4] 877type=IsaFake 878pio_addr=8804615848707 879pio_latency=1000 880pio_size=8 881platform=system.tsunami 882ret_bad_addr=false 883ret_data16=65535 884ret_data32=4294967295 885ret_data64=18446744073709551615 886ret_data8=255 887system=system 888update_data=false 889warn_access= 890pio=system.iobus.port[16] 891 892[system.tsunami.fake_pnp_read5] 893type=IsaFake 894pio_addr=8804615848771 895pio_latency=1000 896pio_size=8 897platform=system.tsunami 898ret_bad_addr=false 899ret_data16=65535 900ret_data32=4294967295 901ret_data64=18446744073709551615 902ret_data8=255 903system=system 904update_data=false 905warn_access= 906pio=system.iobus.port[17] 907 908[system.tsunami.fake_pnp_read6] 909type=IsaFake 910pio_addr=8804615848835 911pio_latency=1000 912pio_size=8 913platform=system.tsunami 914ret_bad_addr=false 915ret_data16=65535 916ret_data32=4294967295 917ret_data64=18446744073709551615 918ret_data8=255 919system=system 920update_data=false 921warn_access= 922pio=system.iobus.port[18] 923 924[system.tsunami.fake_pnp_read7] 925type=IsaFake 926pio_addr=8804615848899 927pio_latency=1000 928pio_size=8 929platform=system.tsunami 930ret_bad_addr=false 931ret_data16=65535 932ret_data32=4294967295 933ret_data64=18446744073709551615 934ret_data8=255 935system=system 936update_data=false 937warn_access= 938pio=system.iobus.port[19] 939 940[system.tsunami.fake_pnp_write] 941type=IsaFake 942pio_addr=8804615850617 943pio_latency=1000 944pio_size=8 945platform=system.tsunami 946ret_bad_addr=false 947ret_data16=65535 948ret_data32=4294967295 949ret_data64=18446744073709551615 950ret_data8=255 951system=system 952update_data=false 953warn_access= 954pio=system.iobus.port[11] 955 956[system.tsunami.fake_ppc] 957type=IsaFake 958pio_addr=8804615848891 959pio_latency=1000 960pio_size=8 961platform=system.tsunami 962ret_bad_addr=false 963ret_data16=65535 964ret_data32=4294967295 965ret_data64=18446744073709551615 966ret_data8=255 967system=system 968update_data=false 969warn_access= 970pio=system.iobus.port[8] 971 972[system.tsunami.fake_sm_chip] 973type=IsaFake 974pio_addr=8804615848816 975pio_latency=1000 976pio_size=8 977platform=system.tsunami 978ret_bad_addr=false 979ret_data16=65535 980ret_data32=4294967295 981ret_data64=18446744073709551615 982ret_data8=255 983system=system 984update_data=false 985warn_access= 986pio=system.iobus.port[3] 987 988[system.tsunami.fake_uart1] 989type=IsaFake 990pio_addr=8804615848696 991pio_latency=1000 992pio_size=8 993platform=system.tsunami 994ret_bad_addr=false 995ret_data16=65535 996ret_data32=4294967295 997ret_data64=18446744073709551615 998ret_data8=255 999system=system 1000update_data=false 1001warn_access= 1002pio=system.iobus.port[4] 1003 1004[system.tsunami.fake_uart2] 1005type=IsaFake 1006pio_addr=8804615848936 1007pio_latency=1000 1008pio_size=8 1009platform=system.tsunami 1010ret_bad_addr=false 1011ret_data16=65535 1012ret_data32=4294967295 1013ret_data64=18446744073709551615 1014ret_data8=255 1015system=system 1016update_data=false 1017warn_access= 1018pio=system.iobus.port[5] 1019 1020[system.tsunami.fake_uart3] 1021type=IsaFake 1022pio_addr=8804615848680 1023pio_latency=1000 1024pio_size=8 1025platform=system.tsunami 1026ret_bad_addr=false 1027ret_data16=65535 1028ret_data32=4294967295 1029ret_data64=18446744073709551615 1030ret_data8=255 1031system=system 1032update_data=false 1033warn_access= 1034pio=system.iobus.port[6] 1035 1036[system.tsunami.fake_uart4] 1037type=IsaFake 1038pio_addr=8804615848944 1039pio_latency=1000 1040pio_size=8 1041platform=system.tsunami 1042ret_bad_addr=false 1043ret_data16=65535 1044ret_data32=4294967295 1045ret_data64=18446744073709551615 1046ret_data8=255 1047system=system 1048update_data=false 1049warn_access= 1050pio=system.iobus.port[7] 1051 1052[system.tsunami.fb] 1053type=BadDevice 1054devicename=FrameBuffer 1055pio_addr=8804615848912 1056pio_latency=1000 1057platform=system.tsunami 1058system=system 1059pio=system.iobus.port[22] 1060 1061[system.tsunami.ide] 1062type=IdeController 1063BAR0=1 1064BAR0LegacyIO=false 1065BAR0Size=8 1066BAR1=1 1067BAR1LegacyIO=false 1068BAR1Size=4 1069BAR2=1 1070BAR2LegacyIO=false 1071BAR2Size=8 1072BAR3=1 1073BAR3LegacyIO=false 1074BAR3Size=4 1075BAR4=1 1076BAR4LegacyIO=false 1077BAR4Size=16 1078BAR5=1 1079BAR5LegacyIO=false 1080BAR5Size=0 1081BIST=0 1082CacheLineSize=0 1083CardbusCIS=0 1084ClassCode=1 1085Command=0 1086DeviceID=28945 1087ExpansionROM=0 1088HeaderType=0 1089InterruptLine=31 1090InterruptPin=1 1091LatencyTimer=0 1092MaximumLatency=0 1093MinimumGrant=0 1094ProgIF=133 1095Revision=0 1096Status=640 1097SubClassCode=1 1098SubsystemID=0 1099SubsystemVendorID=0 1100VendorID=32902 1101config_latency=20000 1102ctrl_offset=0 1103disks=system.disk0 system.disk2 1104io_shift=0 1105max_backoff_delay=10000000 1106min_backoff_delay=4000 1107pci_bus=0 1108pci_dev=0 1109pci_func=0 1110pio_latency=1000 1111platform=system.tsunami 1112system=system 1113config=system.iobus.port[31] 1114dma=system.iobus.port[32] 1115pio=system.iobus.port[26] 1116 1117[system.tsunami.io] 1118type=TsunamiIO 1119frequency=976562500 1120pio_addr=8804615847936 1121pio_latency=1000 1122platform=system.tsunami 1123system=system 1124time=Thu Jan 1 00:00:00 2009 1125tsunami=system.tsunami 1126year_is_bcd=false 1127pio=system.iobus.port[23] 1128 1129[system.tsunami.pchip] 1130type=TsunamiPChip 1131pio_addr=8802535473152 1132pio_latency=1000 1133platform=system.tsunami 1134system=system 1135tsunami=system.tsunami 1136pio=system.iobus.port[2] 1137 1138[system.tsunami.pciconfig] 1139type=PciConfigAll 1140bus=0 1141pio_latency=1 1142platform=system.tsunami 1143size=16777216 1144system=system 1145pio=system.iobus.default 1146 1147[system.tsunami.uart] 1148type=Uart8250 1149pio_addr=8804615848952 1150pio_latency=1000 1151platform=system.tsunami 1152system=system 1153terminal=system.terminal 1154pio=system.iobus.port[24] 1155 1156