stats.txt revision 9314:63e7cfff4188
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.896908 # Number of seconds simulated 4sim_ticks 1896907607500 # Number of ticks simulated 5final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 91997 # Simulator instruction rate (inst/s) 8host_op_rate 91997 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3111116066 # Simulator tick rate (ticks/s) 10host_mem_usage 330780 # Number of bytes of host memory used 11host_seconds 609.72 # Real time elapsed on the host 12sim_insts 56092592 # Number of instructions simulated 13sim_ops 56092592 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 193664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 376046 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41397 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 3026 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 17115 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 449911 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 577445 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 102095 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4091948 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 415902 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12687462 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1396698 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 102095 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 577445 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 449911 # Total number of read requests seen 52system.physmem.writeReqs 121282 # Total number of write requests seen 53system.physmem.cpureqs 578344 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28794304 # Total number of bytes read from memory 55system.physmem.bytesWritten 7762048 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28022 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 27737 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27975 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28585 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28318 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28204 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 28175 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28470 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28412 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28316 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28619 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28149 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 27813 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27389 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27281 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7339 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7747 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7422 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7940 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7694 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7599 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7607 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7865 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7795 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7764 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 8092 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7767 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7407 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 6913 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 6820 # Track writes on a per bank basis 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 93system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1896888917000 # Total gap between requests 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes 101system.physmem.readPktSize::6 449911 # Categorize read packet sizes 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes 110system.physmem.writePktSize::6 121595 # categorize write packet sizes 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::6 3357 # categorize neither packet sizes 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 122system.physmem.rdQLenPdf::0 322755 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 66156 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 30830 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 6523 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2879 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2466 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1798 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1693 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1990 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1579 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1551 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1787 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1472 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 908 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 124 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 4069 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 4980 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5100 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5144 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5219 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5235 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5267 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5267 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5268 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5273 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5273 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5273 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5273 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5273 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5273 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5273 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5273 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5273 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5273 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5273 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5273 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5273 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5273 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 1205 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 294 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 174 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 188system.physmem.totQLat 6417421318 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 13706967318 # Sum of mem lat for all requests 190system.physmem.totBusLat 1799432000 # Total cycles spent in databus access 191system.physmem.totBankLat 5490114000 # Total cycles spent in bank access 192system.physmem.avgQLat 14265.44 # Average queueing delay per request 193system.physmem.avgBankLat 12204.10 # Average bank access latency per request 194system.physmem.avgBusLat 4000.00 # Average bus latency per request 195system.physmem.avgMemAccLat 30469.54 # Average memory access latency 196system.physmem.avgRdBW 15.18 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 15.18 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time 203system.physmem.avgWrQLen 10.19 # Average write queue length over time 204system.physmem.readRowHits 429697 # Number of row buffer hits during reads 205system.physmem.writeRowHits 77704 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 64.07 # Row buffer hit rate for writes 208system.physmem.avgGap 3320924.66 # Average gap between requests 209system.l2c.replacements 342985 # number of replacements 210system.l2c.tagsinuse 65321.507443 # Cycle average of tags in use 211system.l2c.total_refs 2664537 # Total number of references to valid blocks. 212system.l2c.sampled_refs 407990 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.530888 # Average number of references to valid blocks. 214system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. 215system.l2c.occ_blocks::writebacks 53803.345548 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4275.017757 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 5362.992247 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 1295.991254 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 584.160637 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.820974 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.065232 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.081833 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.019775 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.008914 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.996727 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 631150 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 433289 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 452366 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 409982 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1926787 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 859408 # number of Writeback hits 232system.l2c.Writeback_hits::total 859408 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 132 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 86 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 35 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 121498 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 74869 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 196367 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 631150 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 554787 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 452366 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 484851 # number of demand (read+write) hits 246system.l2c.demand_hits::total 2123154 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 631150 # number of overall hits 248system.l2c.overall_hits::cpu0.data 554787 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 452366 # number of overall hits 250system.l2c.overall_hits::cpu1.data 484851 # number of overall hits 251system.l2c.overall_hits::total 2123154 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 12329 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 272557 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 3043 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 1706 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 289635 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2549 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 508 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 3057 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 48 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 90 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 138 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 103909 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 15834 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 119743 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 12329 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 376466 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 3043 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 17540 # number of demand (read+write) misses 270system.l2c.demand_misses::total 409378 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 12329 # number of overall misses 272system.l2c.overall_misses::cpu0.data 376466 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 3043 # number of overall misses 274system.l2c.overall_misses::cpu1.data 17540 # number of overall misses 275system.l2c.overall_misses::total 409378 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 738936500 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11707644000 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 199188500 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 90303499 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12736072499 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 388500 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 888500 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 1277000 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 198500 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 312500 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 7293917000 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 1622405000 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 8916322000 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 738936500 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 19001561000 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 199188500 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 1712708499 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 21652394499 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 738936500 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 19001561000 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 199188500 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 1712708499 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 21652394499 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 643479 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 705846 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 455409 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 411688 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2216422 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 859408 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 859408 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 2681 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 594 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 3275 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 206 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 225407 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 90703 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 316110 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 643479 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 931253 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 455409 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 502391 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2532532 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 643479 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 931253 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 455409 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 502391 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2532532 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.019160 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.386142 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.006682 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.004144 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.130677 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950765 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855219 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.933435 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.592593 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720000 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.669903 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.460984 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.174570 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.378802 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.019160 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.404257 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.006682 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.034913 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.161648 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.019160 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.404257 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.006682 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.034913 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.161648 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59934.828453 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 42954.846142 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65457.936247 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 52932.883353 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 43972.836498 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 152.412711 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1749.015748 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 417.729800 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4135.416667 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1266.666667 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 2264.492754 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70195.238141 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102463.369963 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 74462.156452 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 59934.828453 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 50473.511552 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 65457.936247 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 97645.866534 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 52890.957743 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 59934.828453 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 50473.511552 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 65457.936247 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 97645.866534 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 52890.957743 # average overall miss latency 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed 382system.l2c.writebacks::writebacks 79759 # number of writebacks 383system.l2c.writebacks::total 79759 # number of writebacks 384system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 385system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 386system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 387system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 388system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 389system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 390system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 391system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 392system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 393system.l2c.ReadReq_mshr_misses::cpu0.inst 12328 # number of ReadReq MSHR misses 394system.l2c.ReadReq_mshr_misses::cpu0.data 272557 # number of ReadReq MSHR misses 395system.l2c.ReadReq_mshr_misses::cpu1.inst 3026 # number of ReadReq MSHR misses 396system.l2c.ReadReq_mshr_misses::cpu1.data 1706 # number of ReadReq MSHR misses 397system.l2c.ReadReq_mshr_misses::total 289617 # number of ReadReq MSHR misses 398system.l2c.UpgradeReq_mshr_misses::cpu0.data 2549 # number of UpgradeReq MSHR misses 399system.l2c.UpgradeReq_mshr_misses::cpu1.data 508 # number of UpgradeReq MSHR misses 400system.l2c.UpgradeReq_mshr_misses::total 3057 # number of UpgradeReq MSHR misses 401system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 48 # number of SCUpgradeReq MSHR misses 402system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 90 # number of SCUpgradeReq MSHR misses 403system.l2c.SCUpgradeReq_mshr_misses::total 138 # number of SCUpgradeReq MSHR misses 404system.l2c.ReadExReq_mshr_misses::cpu0.data 103909 # number of ReadExReq MSHR misses 405system.l2c.ReadExReq_mshr_misses::cpu1.data 15834 # number of ReadExReq MSHR misses 406system.l2c.ReadExReq_mshr_misses::total 119743 # number of ReadExReq MSHR misses 407system.l2c.demand_mshr_misses::cpu0.inst 12328 # number of demand (read+write) MSHR misses 408system.l2c.demand_mshr_misses::cpu0.data 376466 # number of demand (read+write) MSHR misses 409system.l2c.demand_mshr_misses::cpu1.inst 3026 # number of demand (read+write) MSHR misses 410system.l2c.demand_mshr_misses::cpu1.data 17540 # number of demand (read+write) MSHR misses 411system.l2c.demand_mshr_misses::total 409360 # number of demand (read+write) MSHR misses 412system.l2c.overall_mshr_misses::cpu0.inst 12328 # number of overall MSHR misses 413system.l2c.overall_mshr_misses::cpu0.data 376466 # number of overall MSHR misses 414system.l2c.overall_mshr_misses::cpu1.inst 3026 # number of overall MSHR misses 415system.l2c.overall_mshr_misses::cpu1.data 17540 # number of overall MSHR misses 416system.l2c.overall_mshr_misses::total 409360 # number of overall MSHR misses 417system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 583232769 # number of ReadReq MSHR miss cycles 418system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8178123323 # number of ReadReq MSHR miss cycles 419system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 160268481 # number of ReadReq MSHR miss cycles 420system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113657266 # number of ReadReq MSHR miss cycles 421system.l2c.ReadReq_mshr_miss_latency::total 9035281839 # number of ReadReq MSHR miss cycles 422system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25542512 # number of UpgradeReq MSHR miss cycles 423system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5088001 # number of UpgradeReq MSHR miss cycles 424system.l2c.UpgradeReq_mshr_miss_latency::total 30630513 # number of UpgradeReq MSHR miss cycles 425system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 501546 # number of SCUpgradeReq MSHR miss cycles 426system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 901090 # number of SCUpgradeReq MSHR miss cycles 427system.l2c.SCUpgradeReq_mshr_miss_latency::total 1402636 # number of SCUpgradeReq MSHR miss cycles 428system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6022075568 # number of ReadExReq MSHR miss cycles 429system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1425456611 # number of ReadExReq MSHR miss cycles 430system.l2c.ReadExReq_mshr_miss_latency::total 7447532179 # number of ReadExReq MSHR miss cycles 431system.l2c.demand_mshr_miss_latency::cpu0.inst 583232769 # number of demand (read+write) MSHR miss cycles 432system.l2c.demand_mshr_miss_latency::cpu0.data 14200198891 # number of demand (read+write) MSHR miss cycles 433system.l2c.demand_mshr_miss_latency::cpu1.inst 160268481 # number of demand (read+write) MSHR miss cycles 434system.l2c.demand_mshr_miss_latency::cpu1.data 1539113877 # number of demand (read+write) MSHR miss cycles 435system.l2c.demand_mshr_miss_latency::total 16482814018 # number of demand (read+write) MSHR miss cycles 436system.l2c.overall_mshr_miss_latency::cpu0.inst 583232769 # number of overall MSHR miss cycles 437system.l2c.overall_mshr_miss_latency::cpu0.data 14200198891 # number of overall MSHR miss cycles 438system.l2c.overall_mshr_miss_latency::cpu1.inst 160268481 # number of overall MSHR miss cycles 439system.l2c.overall_mshr_miss_latency::cpu1.data 1539113877 # number of overall MSHR miss cycles 440system.l2c.overall_mshr_miss_latency::total 16482814018 # number of overall MSHR miss cycles 441system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936128000 # number of ReadReq MSHR uncacheable cycles 442system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 454553000 # number of ReadReq MSHR uncacheable cycles 443system.l2c.ReadReq_mshr_uncacheable_latency::total 1390681000 # number of ReadReq MSHR uncacheable cycles 444system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1589336500 # number of WriteReq MSHR uncacheable cycles 445system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 869577500 # number of WriteReq MSHR uncacheable cycles 446system.l2c.WriteReq_mshr_uncacheable_latency::total 2458914000 # number of WriteReq MSHR uncacheable cycles 447system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2525464500 # number of overall MSHR uncacheable cycles 448system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1324130500 # number of overall MSHR uncacheable cycles 449system.l2c.overall_mshr_uncacheable_latency::total 3849595000 # number of overall MSHR uncacheable cycles 450system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.386142 # mshr miss rate for ReadReq accesses 452system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for ReadReq accesses 453system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.004144 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::total 0.130669 # mshr miss rate for ReadReq accesses 455system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950765 # mshr miss rate for UpgradeReq accesses 456system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855219 # mshr miss rate for UpgradeReq accesses 457system.l2c.UpgradeReq_mshr_miss_rate::total 0.933435 # mshr miss rate for UpgradeReq accesses 458system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.592593 # mshr miss rate for SCUpgradeReq accesses 459system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.720000 # mshr miss rate for SCUpgradeReq accesses 460system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.669903 # mshr miss rate for SCUpgradeReq accesses 461system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.460984 # mshr miss rate for ReadExReq accesses 462system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.174570 # mshr miss rate for ReadExReq accesses 463system.l2c.ReadExReq_mshr_miss_rate::total 0.378802 # mshr miss rate for ReadExReq accesses 464system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::cpu0.data 0.404257 # mshr miss rate for demand accesses 466system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for demand accesses 467system.l2c.demand_mshr_miss_rate::cpu1.data 0.034913 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::total 0.161641 # mshr miss rate for demand accesses 469system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::cpu0.data 0.404257 # mshr miss rate for overall accesses 471system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for overall accesses 472system.l2c.overall_mshr_miss_rate::cpu1.data 0.034913 # mshr miss rate for overall accesses 473system.l2c.overall_mshr_miss_rate::total 0.161641 # mshr miss rate for overall accesses 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average ReadReq mshr miss latency 475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30005.185422 # average ReadReq mshr miss latency 476system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average ReadReq mshr miss latency 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66622.078546 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::total 31197.346285 # average ReadReq mshr miss latency 479system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.601020 # average UpgradeReq mshr miss latency 480system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.750000 # average UpgradeReq mshr miss latency 481system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.794897 # average UpgradeReq mshr miss latency 482system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10448.875000 # average SCUpgradeReq mshr miss latency 483system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.111111 # average SCUpgradeReq mshr miss latency 484system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10164.028986 # average SCUpgradeReq mshr miss latency 485system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57955.283642 # average ReadExReq mshr miss latency 486system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90025.048061 # average ReadExReq mshr miss latency 487system.l2c.ReadExReq_avg_mshr_miss_latency::total 62195.971197 # average ReadExReq mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37719.738014 # average overall mshr miss latency 490system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average overall mshr miss latency 491system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87748.795724 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::total 40264.837840 # average overall mshr miss latency 493system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average overall mshr miss latency 494system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37719.738014 # average overall mshr miss latency 495system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average overall mshr miss latency 496system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87748.795724 # average overall mshr miss latency 497system.l2c.overall_avg_mshr_miss_latency::total 40264.837840 # average overall mshr miss latency 498system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 499system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 500system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 501system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 502system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 503system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 504system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 505system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 506system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 507system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 508system.iocache.replacements 41699 # number of replacements 509system.iocache.tagsinuse 0.478350 # Cycle average of tags in use 510system.iocache.total_refs 0 # Total number of references to valid blocks. 511system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. 512system.iocache.avg_refs 0 # Average number of references to valid blocks. 513system.iocache.warmup_cycle 1705464300000 # Cycle when the warmup percentage was hit. 514system.iocache.occ_blocks::tsunami.ide 0.478350 # Average occupied blocks per requestor 515system.iocache.occ_percent::tsunami.ide 0.029897 # Average percentage of cache occupancy 516system.iocache.occ_percent::total 0.029897 # Average percentage of cache occupancy 517system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 518system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 519system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 520system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 521system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 522system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 523system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 524system.iocache.overall_misses::total 41728 # number of overall misses 525system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles 526system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles 527system.iocache.WriteReq_miss_latency::tsunami.ide 9523967806 # number of WriteReq miss cycles 528system.iocache.WriteReq_miss_latency::total 9523967806 # number of WriteReq miss cycles 529system.iocache.demand_miss_latency::tsunami.ide 9545236804 # number of demand (read+write) miss cycles 530system.iocache.demand_miss_latency::total 9545236804 # number of demand (read+write) miss cycles 531system.iocache.overall_miss_latency::tsunami.ide 9545236804 # number of overall miss cycles 532system.iocache.overall_miss_latency::total 9545236804 # number of overall miss cycles 533system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 534system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 535system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 536system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 537system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 538system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 539system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 540system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 541system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 542system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 543system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 544system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 545system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 546system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 547system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 548system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 549system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency 550system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency 551system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229206.002262 # average WriteReq miss latency 552system.iocache.WriteReq_avg_miss_latency::total 229206.002262 # average WriteReq miss latency 553system.iocache.demand_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency 554system.iocache.demand_avg_miss_latency::total 228748.964820 # average overall miss latency 555system.iocache.overall_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency 556system.iocache.overall_avg_miss_latency::total 228748.964820 # average overall miss latency 557system.iocache.blocked_cycles::no_mshrs 193065 # number of cycles access was blocked 558system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.iocache.blocked::no_mshrs 23193 # number of cycles access was blocked 560system.iocache.blocked::no_targets 0 # number of cycles access was blocked 561system.iocache.avg_blocked_cycles::no_mshrs 8.324279 # average number of cycles each access was blocked 562system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 563system.iocache.fast_writes 0 # number of fast writes performed 564system.iocache.cache_copies 0 # number of cache copies performed 565system.iocache.writebacks::writebacks 41523 # number of writebacks 566system.iocache.writebacks::total 41523 # number of writebacks 567system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 568system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 569system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 570system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 571system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 572system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 573system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 574system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 575system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles 576system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles 577system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7361197521 # number of WriteReq MSHR miss cycles 578system.iocache.WriteReq_mshr_miss_latency::total 7361197521 # number of WriteReq MSHR miss cycles 579system.iocache.demand_mshr_miss_latency::tsunami.ide 7373313521 # number of demand (read+write) MSHR miss cycles 580system.iocache.demand_mshr_miss_latency::total 7373313521 # number of demand (read+write) MSHR miss cycles 581system.iocache.overall_mshr_miss_latency::tsunami.ide 7373313521 # number of overall MSHR miss cycles 582system.iocache.overall_mshr_miss_latency::total 7373313521 # number of overall MSHR miss cycles 583system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 584system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 585system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 586system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 587system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 588system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 589system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 590system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 591system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency 592system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency 593system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177156.274572 # average WriteReq mshr miss latency 594system.iocache.WriteReq_avg_mshr_miss_latency::total 177156.274572 # average WriteReq mshr miss latency 595system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency 596system.iocache.demand_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency 597system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency 598system.iocache.overall_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency 599system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 600system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 601system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 602system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 603system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 604system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 605system.disk0.dma_write_txs 395 # Number of DMA write transactions. 606system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 607system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 608system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 609system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 610system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 611system.disk2.dma_write_txs 1 # Number of DMA write transactions. 612system.cpu0.dtb.fetch_hits 0 # ITB hits 613system.cpu0.dtb.fetch_misses 0 # ITB misses 614system.cpu0.dtb.fetch_acv 0 # ITB acv 615system.cpu0.dtb.fetch_accesses 0 # ITB accesses 616system.cpu0.dtb.read_hits 7007258 # DTB read hits 617system.cpu0.dtb.read_misses 29214 # DTB read misses 618system.cpu0.dtb.read_acv 555 # DTB read access violations 619system.cpu0.dtb.read_accesses 627494 # DTB read accesses 620system.cpu0.dtb.write_hits 4619142 # DTB write hits 621system.cpu0.dtb.write_misses 6985 # DTB write misses 622system.cpu0.dtb.write_acv 345 # DTB write access violations 623system.cpu0.dtb.write_accesses 208744 # DTB write accesses 624system.cpu0.dtb.data_hits 11626400 # DTB hits 625system.cpu0.dtb.data_misses 36199 # DTB misses 626system.cpu0.dtb.data_acv 900 # DTB access violations 627system.cpu0.dtb.data_accesses 836238 # DTB accesses 628system.cpu0.itb.fetch_hits 888386 # ITB hits 629system.cpu0.itb.fetch_misses 27286 # ITB misses 630system.cpu0.itb.fetch_acv 998 # ITB acv 631system.cpu0.itb.fetch_accesses 915672 # ITB accesses 632system.cpu0.itb.read_hits 0 # DTB read hits 633system.cpu0.itb.read_misses 0 # DTB read misses 634system.cpu0.itb.read_acv 0 # DTB read access violations 635system.cpu0.itb.read_accesses 0 # DTB read accesses 636system.cpu0.itb.write_hits 0 # DTB write hits 637system.cpu0.itb.write_misses 0 # DTB write misses 638system.cpu0.itb.write_acv 0 # DTB write access violations 639system.cpu0.itb.write_accesses 0 # DTB write accesses 640system.cpu0.itb.data_hits 0 # DTB hits 641system.cpu0.itb.data_misses 0 # DTB misses 642system.cpu0.itb.data_acv 0 # DTB access violations 643system.cpu0.itb.data_accesses 0 # DTB accesses 644system.cpu0.numCycles 83155415 # number of cpu cycles simulated 645system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 646system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 647system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups 648system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted 649system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect 650system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups 651system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits 652system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 653system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target. 654system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions. 655system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss 656system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed 657system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered 658system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken 659system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked 660system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing 661system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked 662system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 663system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps 664system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions 665system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR 666system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched 667system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed 668system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total) 669system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total) 670system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total) 671system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total) 673system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total) 674system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total) 675system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total) 676system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total) 677system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total) 678system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total) 679system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total) 680system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total) 681system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 682system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 683system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 684system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total) 685system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle 686system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle 687system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle 688system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked 689system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running 690system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking 691system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing 692system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch 693system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction 694system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode 695system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode 696system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing 697system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle 698system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking 699system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst 700system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running 701system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking 702system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename 703system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full 704system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full 705system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full 706system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed 707system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made 708system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups 709system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups 710system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed 711system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing 712system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed 713system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed 714system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer 715system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit. 716system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit. 717system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads. 718system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores. 719system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec) 720system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ 721system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued 722system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued 723system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling 724system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph 725system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed 726system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle 727system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle 728system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle 729system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle 731system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle 732system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle 733system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle 734system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle 735system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle 736system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle 737system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle 738system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle 739system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 740system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 741system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 742system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle 743system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 744system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available 745system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available 746system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available 747system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available 748system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available 749system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available 750system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available 751system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available 752system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available 753system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available 754system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available 755system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available 762system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available 763system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available 764system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available 765system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available 766system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available 767system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available 768system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available 769system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available 770system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available 771system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available 772system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available 773system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available 774system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available 775system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 776system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 777system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued 778system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued 779system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued 780system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued 781system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued 782system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued 783system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued 784system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued 785system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued 786system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued 787system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued 788system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued 789system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued 796system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued 797system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued 798system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued 799system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued 800system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued 801system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued 802system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued 803system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued 804system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued 805system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued 806system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued 807system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued 808system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued 809system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued 810system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 811system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued 812system.cpu0.iq.rate 0.487352 # Inst issue rate 813system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested 814system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst) 815system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads 816system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes 817system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses 818system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads 819system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes 820system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses 821system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses 822system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses 823system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores 824system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 825system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed 826system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed 827system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations 828system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed 829system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 830system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 831system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled 832system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked 833system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 834system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing 835system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking 836system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking 837system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ 838system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch 839system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions 840system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions 841system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions 842system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall 843system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall 844system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations 845system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly 846system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly 847system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute 848system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions 849system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed 850system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute 851system.cpu0.iew.exec_swp 0 # number of swp insts executed 852system.cpu0.iew.exec_nop 2446064 # number of nop insts executed 853system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed 854system.cpu0.iew.exec_branches 6330042 # Number of branches executed 855system.cpu0.iew.exec_stores 4636142 # Number of stores executed 856system.cpu0.iew.exec_rate 0.483213 # Inst execution rate 857system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit 858system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back 859system.cpu0.iew.wb_producers 19855593 # num instructions producing a value 860system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value 861system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 862system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle 863system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back 864system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 865system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit 866system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards 867system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted 868system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle 869system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle 870system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle 871system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle 873system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle 874system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle 875system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle 876system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle 877system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle 878system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle 879system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle 880system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle 881system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 882system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 883system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 884system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle 885system.cpu0.commit.committedInsts 40051259 # Number of instructions committed 886system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed 887system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 888system.cpu0.commit.refs 10855795 # Number of memory references committed 889system.cpu0.commit.loads 6384070 # Number of loads committed 890system.cpu0.commit.membars 151085 # Number of memory barriers committed 891system.cpu0.commit.branches 6007416 # Number of branches committed 892system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions. 893system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions. 894system.cpu0.commit.function_calls 489523 # Number of function calls committed. 895system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached 896system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 897system.cpu0.rob.rob_reads 101537476 # The number of ROB reads 898system.cpu0.rob.rob_writes 91770556 # The number of ROB writes 899system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself 900system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling 901system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 902system.cpu0.committedInsts 37835874 # Number of Instructions Simulated 903system.cpu0.committedOps 37835874 # Number of Ops (including micro ops) Simulated 904system.cpu0.committedInsts_total 37835874 # Number of Instructions Simulated 905system.cpu0.cpi 2.197793 # CPI: Cycles Per Instruction 906system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads 907system.cpu0.ipc 0.455002 # IPC: Instructions Per Cycle 908system.cpu0.ipc_total 0.455002 # IPC: Total IPC of All Threads 909system.cpu0.int_regfile_reads 52969279 # number of integer regfile reads 910system.cpu0.int_regfile_writes 28937240 # number of integer regfile writes 911system.cpu0.fp_regfile_reads 87038 # number of floating regfile reads 912system.cpu0.fp_regfile_writes 87248 # number of floating regfile writes 913system.cpu0.misc_regfile_reads 1306578 # number of misc regfile reads 914system.cpu0.misc_regfile_writes 663412 # number of misc regfile writes 915system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 916system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 917system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 918system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 919system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 920system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 921system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 922system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 923system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 924system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 925system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 926system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 927system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 928system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 929system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 930system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 931system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 932system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 933system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 934system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 935system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 936system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 937system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 938system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 939system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 940system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 941system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 942system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 943system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 944system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 945system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 946system.cpu0.icache.replacements 642913 # number of replacements 947system.cpu0.icache.tagsinuse 510.325206 # Cycle average of tags in use 948system.cpu0.icache.total_refs 5670885 # Total number of references to valid blocks. 949system.cpu0.icache.sampled_refs 643421 # Sample count of references to valid blocks. 950system.cpu0.icache.avg_refs 8.813646 # Average number of references to valid blocks. 951system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit. 952system.cpu0.icache.occ_blocks::cpu0.inst 510.325206 # Average occupied blocks per requestor 953system.cpu0.icache.occ_percent::cpu0.inst 0.996729 # Average percentage of cache occupancy 954system.cpu0.icache.occ_percent::total 0.996729 # Average percentage of cache occupancy 955system.cpu0.icache.ReadReq_hits::cpu0.inst 5670885 # number of ReadReq hits 956system.cpu0.icache.ReadReq_hits::total 5670885 # number of ReadReq hits 957system.cpu0.icache.demand_hits::cpu0.inst 5670885 # number of demand (read+write) hits 958system.cpu0.icache.demand_hits::total 5670885 # number of demand (read+write) hits 959system.cpu0.icache.overall_hits::cpu0.inst 5670885 # number of overall hits 960system.cpu0.icache.overall_hits::total 5670885 # number of overall hits 961system.cpu0.icache.ReadReq_misses::cpu0.inst 678650 # number of ReadReq misses 962system.cpu0.icache.ReadReq_misses::total 678650 # number of ReadReq misses 963system.cpu0.icache.demand_misses::cpu0.inst 678650 # number of demand (read+write) misses 964system.cpu0.icache.demand_misses::total 678650 # number of demand (read+write) misses 965system.cpu0.icache.overall_misses::cpu0.inst 678650 # number of overall misses 966system.cpu0.icache.overall_misses::total 678650 # number of overall misses 967system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9582412994 # number of ReadReq miss cycles 968system.cpu0.icache.ReadReq_miss_latency::total 9582412994 # number of ReadReq miss cycles 969system.cpu0.icache.demand_miss_latency::cpu0.inst 9582412994 # number of demand (read+write) miss cycles 970system.cpu0.icache.demand_miss_latency::total 9582412994 # number of demand (read+write) miss cycles 971system.cpu0.icache.overall_miss_latency::cpu0.inst 9582412994 # number of overall miss cycles 972system.cpu0.icache.overall_miss_latency::total 9582412994 # number of overall miss cycles 973system.cpu0.icache.ReadReq_accesses::cpu0.inst 6349535 # number of ReadReq accesses(hits+misses) 974system.cpu0.icache.ReadReq_accesses::total 6349535 # number of ReadReq accesses(hits+misses) 975system.cpu0.icache.demand_accesses::cpu0.inst 6349535 # number of demand (read+write) accesses 976system.cpu0.icache.demand_accesses::total 6349535 # number of demand (read+write) accesses 977system.cpu0.icache.overall_accesses::cpu0.inst 6349535 # number of overall (read+write) accesses 978system.cpu0.icache.overall_accesses::total 6349535 # number of overall (read+write) accesses 979system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.106882 # miss rate for ReadReq accesses 980system.cpu0.icache.ReadReq_miss_rate::total 0.106882 # miss rate for ReadReq accesses 981system.cpu0.icache.demand_miss_rate::cpu0.inst 0.106882 # miss rate for demand accesses 982system.cpu0.icache.demand_miss_rate::total 0.106882 # miss rate for demand accesses 983system.cpu0.icache.overall_miss_rate::cpu0.inst 0.106882 # miss rate for overall accesses 984system.cpu0.icache.overall_miss_rate::total 0.106882 # miss rate for overall accesses 985system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14119.815802 # average ReadReq miss latency 986system.cpu0.icache.ReadReq_avg_miss_latency::total 14119.815802 # average ReadReq miss latency 987system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency 988system.cpu0.icache.demand_avg_miss_latency::total 14119.815802 # average overall miss latency 989system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency 990system.cpu0.icache.overall_avg_miss_latency::total 14119.815802 # average overall miss latency 991system.cpu0.icache.blocked_cycles::no_mshrs 2234 # number of cycles access was blocked 992system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 993system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked 994system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 995system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.406897 # average number of cycles each access was blocked 996system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 997system.cpu0.icache.fast_writes 0 # number of fast writes performed 998system.cpu0.icache.cache_copies 0 # number of cache copies performed 999system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 35068 # number of ReadReq MSHR hits 1000system.cpu0.icache.ReadReq_mshr_hits::total 35068 # number of ReadReq MSHR hits 1001system.cpu0.icache.demand_mshr_hits::cpu0.inst 35068 # number of demand (read+write) MSHR hits 1002system.cpu0.icache.demand_mshr_hits::total 35068 # number of demand (read+write) MSHR hits 1003system.cpu0.icache.overall_mshr_hits::cpu0.inst 35068 # number of overall MSHR hits 1004system.cpu0.icache.overall_mshr_hits::total 35068 # number of overall MSHR hits 1005system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 643582 # number of ReadReq MSHR misses 1006system.cpu0.icache.ReadReq_mshr_misses::total 643582 # number of ReadReq MSHR misses 1007system.cpu0.icache.demand_mshr_misses::cpu0.inst 643582 # number of demand (read+write) MSHR misses 1008system.cpu0.icache.demand_mshr_misses::total 643582 # number of demand (read+write) MSHR misses 1009system.cpu0.icache.overall_mshr_misses::cpu0.inst 643582 # number of overall MSHR misses 1010system.cpu0.icache.overall_mshr_misses::total 643582 # number of overall MSHR misses 1011system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7877266496 # number of ReadReq MSHR miss cycles 1012system.cpu0.icache.ReadReq_mshr_miss_latency::total 7877266496 # number of ReadReq MSHR miss cycles 1013system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7877266496 # number of demand (read+write) MSHR miss cycles 1014system.cpu0.icache.demand_mshr_miss_latency::total 7877266496 # number of demand (read+write) MSHR miss cycles 1015system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7877266496 # number of overall MSHR miss cycles 1016system.cpu0.icache.overall_mshr_miss_latency::total 7877266496 # number of overall MSHR miss cycles 1017system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for ReadReq accesses 1018system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101359 # mshr miss rate for ReadReq accesses 1019system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for demand accesses 1020system.cpu0.icache.demand_mshr_miss_rate::total 0.101359 # mshr miss rate for demand accesses 1021system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for overall accesses 1022system.cpu0.icache.overall_mshr_miss_rate::total 0.101359 # mshr miss rate for overall accesses 1023system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average ReadReq mshr miss latency 1024system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12239.724691 # average ReadReq mshr miss latency 1025system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency 1026system.cpu0.icache.demand_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency 1027system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency 1028system.cpu0.icache.overall_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency 1029system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1030system.cpu0.dcache.replacements 932591 # number of replacements 1031system.cpu0.dcache.tagsinuse 478.331784 # Cycle average of tags in use 1032system.cpu0.dcache.total_refs 8251917 # Total number of references to valid blocks. 1033system.cpu0.dcache.sampled_refs 933103 # Sample count of references to valid blocks. 1034system.cpu0.dcache.avg_refs 8.843522 # Average number of references to valid blocks. 1035system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit. 1036system.cpu0.dcache.occ_blocks::cpu0.data 478.331784 # Average occupied blocks per requestor 1037system.cpu0.dcache.occ_percent::cpu0.data 0.934242 # Average percentage of cache occupancy 1038system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy 1039system.cpu0.dcache.ReadReq_hits::cpu0.data 5164945 # number of ReadReq hits 1040system.cpu0.dcache.ReadReq_hits::total 5164945 # number of ReadReq hits 1041system.cpu0.dcache.WriteReq_hits::cpu0.data 2787881 # number of WriteReq hits 1042system.cpu0.dcache.WriteReq_hits::total 2787881 # number of WriteReq hits 1043system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136688 # number of LoadLockedReq hits 1044system.cpu0.dcache.LoadLockedReq_hits::total 136688 # number of LoadLockedReq hits 1045system.cpu0.dcache.StoreCondReq_hits::cpu0.data 157014 # number of StoreCondReq hits 1046system.cpu0.dcache.StoreCondReq_hits::total 157014 # number of StoreCondReq hits 1047system.cpu0.dcache.demand_hits::cpu0.data 7952826 # number of demand (read+write) hits 1048system.cpu0.dcache.demand_hits::total 7952826 # number of demand (read+write) hits 1049system.cpu0.dcache.overall_hits::cpu0.data 7952826 # number of overall hits 1050system.cpu0.dcache.overall_hits::total 7952826 # number of overall hits 1051system.cpu0.dcache.ReadReq_misses::cpu0.data 1127907 # number of ReadReq misses 1052system.cpu0.dcache.ReadReq_misses::total 1127907 # number of ReadReq misses 1053system.cpu0.dcache.WriteReq_misses::cpu0.data 1514074 # number of WriteReq misses 1054system.cpu0.dcache.WriteReq_misses::total 1514074 # number of WriteReq misses 1055system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12708 # number of LoadLockedReq misses 1056system.cpu0.dcache.LoadLockedReq_misses::total 12708 # number of LoadLockedReq misses 1057system.cpu0.dcache.StoreCondReq_misses::cpu0.data 640 # number of StoreCondReq misses 1058system.cpu0.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses 1059system.cpu0.dcache.demand_misses::cpu0.data 2641981 # number of demand (read+write) misses 1060system.cpu0.dcache.demand_misses::total 2641981 # number of demand (read+write) misses 1061system.cpu0.dcache.overall_misses::cpu0.data 2641981 # number of overall misses 1062system.cpu0.dcache.overall_misses::total 2641981 # number of overall misses 1063system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26996447000 # number of ReadReq miss cycles 1064system.cpu0.dcache.ReadReq_miss_latency::total 26996447000 # number of ReadReq miss cycles 1065system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62901501244 # number of WriteReq miss cycles 1066system.cpu0.dcache.WriteReq_miss_latency::total 62901501244 # number of WriteReq miss cycles 1067system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 187201000 # number of LoadLockedReq miss cycles 1068system.cpu0.dcache.LoadLockedReq_miss_latency::total 187201000 # number of LoadLockedReq miss cycles 1069system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3956000 # number of StoreCondReq miss cycles 1070system.cpu0.dcache.StoreCondReq_miss_latency::total 3956000 # number of StoreCondReq miss cycles 1071system.cpu0.dcache.demand_miss_latency::cpu0.data 89897948244 # number of demand (read+write) miss cycles 1072system.cpu0.dcache.demand_miss_latency::total 89897948244 # number of demand (read+write) miss cycles 1073system.cpu0.dcache.overall_miss_latency::cpu0.data 89897948244 # number of overall miss cycles 1074system.cpu0.dcache.overall_miss_latency::total 89897948244 # number of overall miss cycles 1075system.cpu0.dcache.ReadReq_accesses::cpu0.data 6292852 # number of ReadReq accesses(hits+misses) 1076system.cpu0.dcache.ReadReq_accesses::total 6292852 # number of ReadReq accesses(hits+misses) 1077system.cpu0.dcache.WriteReq_accesses::cpu0.data 4301955 # number of WriteReq accesses(hits+misses) 1078system.cpu0.dcache.WriteReq_accesses::total 4301955 # number of WriteReq accesses(hits+misses) 1079system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 149396 # number of LoadLockedReq accesses(hits+misses) 1080system.cpu0.dcache.LoadLockedReq_accesses::total 149396 # number of LoadLockedReq accesses(hits+misses) 1081system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157654 # number of StoreCondReq accesses(hits+misses) 1082system.cpu0.dcache.StoreCondReq_accesses::total 157654 # number of StoreCondReq accesses(hits+misses) 1083system.cpu0.dcache.demand_accesses::cpu0.data 10594807 # number of demand (read+write) accesses 1084system.cpu0.dcache.demand_accesses::total 10594807 # number of demand (read+write) accesses 1085system.cpu0.dcache.overall_accesses::cpu0.data 10594807 # number of overall (read+write) accesses 1086system.cpu0.dcache.overall_accesses::total 10594807 # number of overall (read+write) accesses 1087system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.179236 # miss rate for ReadReq accesses 1088system.cpu0.dcache.ReadReq_miss_rate::total 0.179236 # miss rate for ReadReq accesses 1089system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351950 # miss rate for WriteReq accesses 1090system.cpu0.dcache.WriteReq_miss_rate::total 0.351950 # miss rate for WriteReq accesses 1091system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085063 # miss rate for LoadLockedReq accesses 1092system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085063 # miss rate for LoadLockedReq accesses 1093system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004060 # miss rate for StoreCondReq accesses 1094system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004060 # miss rate for StoreCondReq accesses 1095system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249366 # miss rate for demand accesses 1096system.cpu0.dcache.demand_miss_rate::total 0.249366 # miss rate for demand accesses 1097system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249366 # miss rate for overall accesses 1098system.cpu0.dcache.overall_miss_rate::total 0.249366 # miss rate for overall accesses 1099system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23934.993754 # average ReadReq miss latency 1100system.cpu0.dcache.ReadReq_avg_miss_latency::total 23934.993754 # average ReadReq miss latency 1101system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41544.535633 # average WriteReq miss latency 1102system.cpu0.dcache.WriteReq_avg_miss_latency::total 41544.535633 # average WriteReq miss latency 1103system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.956878 # average LoadLockedReq miss latency 1104system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.956878 # average LoadLockedReq miss latency 1105system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6181.250000 # average StoreCondReq miss latency 1106system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6181.250000 # average StoreCondReq miss latency 1107system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency 1108system.cpu0.dcache.demand_avg_miss_latency::total 34026.720194 # average overall miss latency 1109system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency 1110system.cpu0.dcache.overall_avg_miss_latency::total 34026.720194 # average overall miss latency 1111system.cpu0.dcache.blocked_cycles::no_mshrs 2213633 # number of cycles access was blocked 1112system.cpu0.dcache.blocked_cycles::no_targets 2219 # number of cycles access was blocked 1113system.cpu0.dcache.blocked::no_mshrs 43644 # number of cycles access was blocked 1114system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 1115system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.720214 # average number of cycles each access was blocked 1116system.cpu0.dcache.avg_blocked_cycles::no_targets 317 # average number of cycles each access was blocked 1117system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1118system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1119system.cpu0.dcache.writebacks::writebacks 453711 # number of writebacks 1120system.cpu0.dcache.writebacks::total 453711 # number of writebacks 1121system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 427154 # number of ReadReq MSHR hits 1122system.cpu0.dcache.ReadReq_mshr_hits::total 427154 # number of ReadReq MSHR hits 1123system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1285155 # number of WriteReq MSHR hits 1124system.cpu0.dcache.WriteReq_mshr_hits::total 1285155 # number of WriteReq MSHR hits 1125system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3146 # number of LoadLockedReq MSHR hits 1126system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3146 # number of LoadLockedReq MSHR hits 1127system.cpu0.dcache.demand_mshr_hits::cpu0.data 1712309 # number of demand (read+write) MSHR hits 1128system.cpu0.dcache.demand_mshr_hits::total 1712309 # number of demand (read+write) MSHR hits 1129system.cpu0.dcache.overall_mshr_hits::cpu0.data 1712309 # number of overall MSHR hits 1130system.cpu0.dcache.overall_mshr_hits::total 1712309 # number of overall MSHR hits 1131system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 700753 # number of ReadReq MSHR misses 1132system.cpu0.dcache.ReadReq_mshr_misses::total 700753 # number of ReadReq MSHR misses 1133system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 228919 # number of WriteReq MSHR misses 1134system.cpu0.dcache.WriteReq_mshr_misses::total 228919 # number of WriteReq MSHR misses 1135system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9562 # number of LoadLockedReq MSHR misses 1136system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9562 # number of LoadLockedReq MSHR misses 1137system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses 1138system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses 1139system.cpu0.dcache.demand_mshr_misses::cpu0.data 929672 # number of demand (read+write) MSHR misses 1140system.cpu0.dcache.demand_mshr_misses::total 929672 # number of demand (read+write) MSHR misses 1141system.cpu0.dcache.overall_mshr_misses::cpu0.data 929672 # number of overall MSHR misses 1142system.cpu0.dcache.overall_mshr_misses::total 929672 # number of overall MSHR misses 1143system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17299108000 # number of ReadReq MSHR miss cycles 1144system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17299108000 # number of ReadReq MSHR miss cycles 1145system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9077949457 # number of WriteReq MSHR miss cycles 1146system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9077949457 # number of WriteReq MSHR miss cycles 1147system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117930500 # number of LoadLockedReq MSHR miss cycles 1148system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117930500 # number of LoadLockedReq MSHR miss cycles 1149system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2676000 # number of StoreCondReq MSHR miss cycles 1150system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2676000 # number of StoreCondReq MSHR miss cycles 1151system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26377057457 # number of demand (read+write) MSHR miss cycles 1152system.cpu0.dcache.demand_mshr_miss_latency::total 26377057457 # number of demand (read+write) MSHR miss cycles 1153system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26377057457 # number of overall MSHR miss cycles 1154system.cpu0.dcache.overall_mshr_miss_latency::total 26377057457 # number of overall MSHR miss cycles 1155system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998607000 # number of ReadReq MSHR uncacheable cycles 1156system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998607000 # number of ReadReq MSHR uncacheable cycles 1157system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1686748998 # number of WriteReq MSHR uncacheable cycles 1158system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1686748998 # number of WriteReq MSHR uncacheable cycles 1159system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2685355998 # number of overall MSHR uncacheable cycles 1160system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2685355998 # number of overall MSHR uncacheable cycles 1161system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111357 # mshr miss rate for ReadReq accesses 1162system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111357 # mshr miss rate for ReadReq accesses 1163system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053213 # mshr miss rate for WriteReq accesses 1164system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053213 # mshr miss rate for WriteReq accesses 1165system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064004 # mshr miss rate for LoadLockedReq accesses 1166system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064004 # mshr miss rate for LoadLockedReq accesses 1167system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004060 # mshr miss rate for StoreCondReq accesses 1168system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004060 # mshr miss rate for StoreCondReq accesses 1169system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for demand accesses 1170system.cpu0.dcache.demand_mshr_miss_rate::total 0.087748 # mshr miss rate for demand accesses 1171system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for overall accesses 1172system.cpu0.dcache.overall_mshr_miss_rate::total 0.087748 # mshr miss rate for overall accesses 1173system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24686.455855 # average ReadReq mshr miss latency 1174system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24686.455855 # average ReadReq mshr miss latency 1175system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39655.727384 # average WriteReq mshr miss latency 1176system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39655.727384 # average WriteReq mshr miss latency 1177system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12333.246183 # average LoadLockedReq mshr miss latency 1178system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12333.246183 # average LoadLockedReq mshr miss latency 1179system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4181.250000 # average StoreCondReq mshr miss latency 1180system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4181.250000 # average StoreCondReq mshr miss latency 1181system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency 1182system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency 1183system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency 1184system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency 1185system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1186system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1187system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1188system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1189system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1190system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1191system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu1.dtb.fetch_hits 0 # ITB hits 1193system.cpu1.dtb.fetch_misses 0 # ITB misses 1194system.cpu1.dtb.fetch_acv 0 # ITB acv 1195system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1196system.cpu1.dtb.read_hits 3713266 # DTB read hits 1197system.cpu1.dtb.read_misses 14359 # DTB read misses 1198system.cpu1.dtb.read_acv 33 # DTB read access violations 1199system.cpu1.dtb.read_accesses 328215 # DTB read accesses 1200system.cpu1.dtb.write_hits 2351870 # DTB write hits 1201system.cpu1.dtb.write_misses 2326 # DTB write misses 1202system.cpu1.dtb.write_acv 62 # DTB write access violations 1203system.cpu1.dtb.write_accesses 130566 # DTB write accesses 1204system.cpu1.dtb.data_hits 6065136 # DTB hits 1205system.cpu1.dtb.data_misses 16685 # DTB misses 1206system.cpu1.dtb.data_acv 95 # DTB access violations 1207system.cpu1.dtb.data_accesses 458781 # DTB accesses 1208system.cpu1.itb.fetch_hits 552396 # ITB hits 1209system.cpu1.itb.fetch_misses 7861 # ITB misses 1210system.cpu1.itb.fetch_acv 226 # ITB acv 1211system.cpu1.itb.fetch_accesses 560257 # ITB accesses 1212system.cpu1.itb.read_hits 0 # DTB read hits 1213system.cpu1.itb.read_misses 0 # DTB read misses 1214system.cpu1.itb.read_acv 0 # DTB read access violations 1215system.cpu1.itb.read_accesses 0 # DTB read accesses 1216system.cpu1.itb.write_hits 0 # DTB write hits 1217system.cpu1.itb.write_misses 0 # DTB write misses 1218system.cpu1.itb.write_acv 0 # DTB write access violations 1219system.cpu1.itb.write_accesses 0 # DTB write accesses 1220system.cpu1.itb.data_hits 0 # DTB hits 1221system.cpu1.itb.data_misses 0 # DTB misses 1222system.cpu1.itb.data_acv 0 # DTB access violations 1223system.cpu1.itb.data_accesses 0 # DTB accesses 1224system.cpu1.numCycles 34615367 # number of cpu cycles simulated 1225system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1226system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1227system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups 1228system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted 1229system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect 1230system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups 1231system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits 1232system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1233system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target. 1234system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions. 1235system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss 1236system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed 1237system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered 1238system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken 1239system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked 1240system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing 1241system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked 1242system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1243system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps 1244system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions 1245system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR 1246system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched 1247system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed 1248system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total) 1249system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total) 1250system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total) 1251system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total) 1254system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total) 1256system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total) 1257system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total) 1258system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total) 1259system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total) 1260system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1263system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1264system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total) 1265system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle 1266system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle 1267system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle 1268system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked 1269system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running 1270system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking 1271system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing 1272system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch 1273system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction 1274system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode 1275system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode 1276system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing 1277system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle 1278system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking 1279system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst 1280system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running 1281system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking 1282system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename 1283system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full 1284system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full 1285system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full 1286system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed 1287system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made 1288system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups 1289system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups 1290system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed 1291system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing 1292system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed 1293system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed 1294system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer 1295system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit. 1296system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit. 1297system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads. 1298system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores. 1299system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec) 1300system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ 1301system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued 1302system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued 1303system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling 1304system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph 1305system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed 1306system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle 1307system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle 1308system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle 1309system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle 1312system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle 1313system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle 1314system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle 1315system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle 1316system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle 1317system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle 1318system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle 1319system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1320system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1321system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1322system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle 1323system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available 1325system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available 1326system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available 1327system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available 1345system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available 1347system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available 1348system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available 1349system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available 1350system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available 1351system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available 1352system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available 1353system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available 1354system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1357system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued 1358system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued 1359system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued 1360system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued 1361system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued 1362system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued 1363system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued 1364system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued 1365system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued 1366system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued 1367system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued 1368system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued 1369system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued 1377system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued 1378system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued 1379system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued 1380system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued 1381system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued 1382system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued 1383system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued 1384system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued 1385system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued 1386system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued 1387system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued 1388system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued 1389system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued 1390system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1391system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued 1392system.cpu1.iq.rate 0.575485 # Inst issue rate 1393system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested 1394system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst) 1395system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads 1396system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes 1397system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses 1398system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads 1399system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes 1400system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses 1401system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses 1402system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses 1403system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores 1404system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1405system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed 1406system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed 1407system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations 1408system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed 1409system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1410system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1411system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled 1412system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked 1413system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1414system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing 1415system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking 1416system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking 1417system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ 1418system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch 1419system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions 1420system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions 1421system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions 1422system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall 1423system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall 1424system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations 1425system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly 1426system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly 1427system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute 1428system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions 1429system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed 1430system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute 1431system.cpu1.iew.exec_swp 0 # number of swp insts executed 1432system.cpu1.iew.exec_nop 1269370 # number of nop insts executed 1433system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed 1434system.cpu1.iew.exec_branches 3128191 # Number of branches executed 1435system.cpu1.iew.exec_stores 2361866 # Number of stores executed 1436system.cpu1.iew.exec_rate 0.569357 # Inst execution rate 1437system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit 1438system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back 1439system.cpu1.iew.wb_producers 9462232 # num instructions producing a value 1440system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value 1441system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1442system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle 1443system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back 1444system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1445system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit 1446system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards 1447system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted 1448system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle 1449system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle 1450system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle 1451system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle 1454system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle 1455system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle 1456system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle 1457system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle 1458system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle 1459system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle 1460system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle 1461system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1462system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1463system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1464system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle 1465system.cpu1.commit.committedInsts 19375400 # Number of instructions committed 1466system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed 1467system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1468system.cpu1.commit.refs 5615142 # Number of memory references committed 1469system.cpu1.commit.loads 3365090 # Number of loads committed 1470system.cpu1.commit.membars 85627 # Number of memory barriers committed 1471system.cpu1.commit.branches 2912516 # Number of branches committed 1472system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions. 1473system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions. 1474system.cpu1.commit.function_calls 300496 # Number of function calls committed. 1475system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached 1476system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1477system.cpu1.rob.rob_reads 52972716 # The number of ROB reads 1478system.cpu1.rob.rob_writes 45818344 # The number of ROB writes 1479system.cpu1.timesIdled 377037 # Number of times that the entire CPU went into an idle state and unscheduled itself 1480system.cpu1.idleCycles 3044283 # Total number of cycles that the CPU has spent unscheduled due to idling 1481system.cpu1.quiesceCycles 3758611040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1482system.cpu1.committedInsts 18256718 # Number of Instructions Simulated 1483system.cpu1.committedOps 18256718 # Number of Ops (including micro ops) Simulated 1484system.cpu1.committedInsts_total 18256718 # Number of Instructions Simulated 1485system.cpu1.cpi 1.896034 # CPI: Cycles Per Instruction 1486system.cpu1.cpi_total 1.896034 # CPI: Total CPI of All Threads 1487system.cpu1.ipc 0.527417 # IPC: Instructions Per Cycle 1488system.cpu1.ipc_total 0.527417 # IPC: Total IPC of All Threads 1489system.cpu1.int_regfile_reads 25482349 # number of integer regfile reads 1490system.cpu1.int_regfile_writes 13944369 # number of integer regfile writes 1491system.cpu1.fp_regfile_reads 81651 # number of floating regfile reads 1492system.cpu1.fp_regfile_writes 82372 # number of floating regfile writes 1493system.cpu1.misc_regfile_reads 840995 # number of misc regfile reads 1494system.cpu1.misc_regfile_writes 357443 # number of misc regfile writes 1495system.cpu1.icache.replacements 454861 # number of replacements 1496system.cpu1.icache.tagsinuse 506.121737 # Cycle average of tags in use 1497system.cpu1.icache.total_refs 2515591 # Total number of references to valid blocks. 1498system.cpu1.icache.sampled_refs 455373 # Sample count of references to valid blocks. 1499system.cpu1.icache.avg_refs 5.524243 # Average number of references to valid blocks. 1500system.cpu1.icache.warmup_cycle 42848278000 # Cycle when the warmup percentage was hit. 1501system.cpu1.icache.occ_blocks::cpu1.inst 506.121737 # Average occupied blocks per requestor 1502system.cpu1.icache.occ_percent::cpu1.inst 0.988519 # Average percentage of cache occupancy 1503system.cpu1.icache.occ_percent::total 0.988519 # Average percentage of cache occupancy 1504system.cpu1.icache.ReadReq_hits::cpu1.inst 2515591 # number of ReadReq hits 1505system.cpu1.icache.ReadReq_hits::total 2515591 # number of ReadReq hits 1506system.cpu1.icache.demand_hits::cpu1.inst 2515591 # number of demand (read+write) hits 1507system.cpu1.icache.demand_hits::total 2515591 # number of demand (read+write) hits 1508system.cpu1.icache.overall_hits::cpu1.inst 2515591 # number of overall hits 1509system.cpu1.icache.overall_hits::total 2515591 # number of overall hits 1510system.cpu1.icache.ReadReq_misses::cpu1.inst 476773 # number of ReadReq misses 1511system.cpu1.icache.ReadReq_misses::total 476773 # number of ReadReq misses 1512system.cpu1.icache.demand_misses::cpu1.inst 476773 # number of demand (read+write) misses 1513system.cpu1.icache.demand_misses::total 476773 # number of demand (read+write) misses 1514system.cpu1.icache.overall_misses::cpu1.inst 476773 # number of overall misses 1515system.cpu1.icache.overall_misses::total 476773 # number of overall misses 1516system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6462749000 # number of ReadReq miss cycles 1517system.cpu1.icache.ReadReq_miss_latency::total 6462749000 # number of ReadReq miss cycles 1518system.cpu1.icache.demand_miss_latency::cpu1.inst 6462749000 # number of demand (read+write) miss cycles 1519system.cpu1.icache.demand_miss_latency::total 6462749000 # number of demand (read+write) miss cycles 1520system.cpu1.icache.overall_miss_latency::cpu1.inst 6462749000 # number of overall miss cycles 1521system.cpu1.icache.overall_miss_latency::total 6462749000 # number of overall miss cycles 1522system.cpu1.icache.ReadReq_accesses::cpu1.inst 2992364 # number of ReadReq accesses(hits+misses) 1523system.cpu1.icache.ReadReq_accesses::total 2992364 # number of ReadReq accesses(hits+misses) 1524system.cpu1.icache.demand_accesses::cpu1.inst 2992364 # number of demand (read+write) accesses 1525system.cpu1.icache.demand_accesses::total 2992364 # number of demand (read+write) accesses 1526system.cpu1.icache.overall_accesses::cpu1.inst 2992364 # number of overall (read+write) accesses 1527system.cpu1.icache.overall_accesses::total 2992364 # number of overall (read+write) accesses 1528system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.159330 # miss rate for ReadReq accesses 1529system.cpu1.icache.ReadReq_miss_rate::total 0.159330 # miss rate for ReadReq accesses 1530system.cpu1.icache.demand_miss_rate::cpu1.inst 0.159330 # miss rate for demand accesses 1531system.cpu1.icache.demand_miss_rate::total 0.159330 # miss rate for demand accesses 1532system.cpu1.icache.overall_miss_rate::cpu1.inst 0.159330 # miss rate for overall accesses 1533system.cpu1.icache.overall_miss_rate::total 0.159330 # miss rate for overall accesses 1534system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13555.190835 # average ReadReq miss latency 1535system.cpu1.icache.ReadReq_avg_miss_latency::total 13555.190835 # average ReadReq miss latency 1536system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency 1537system.cpu1.icache.demand_avg_miss_latency::total 13555.190835 # average overall miss latency 1538system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency 1539system.cpu1.icache.overall_avg_miss_latency::total 13555.190835 # average overall miss latency 1540system.cpu1.icache.blocked_cycles::no_mshrs 884 # number of cycles access was blocked 1541system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1542system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked 1543system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1544system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.808511 # average number of cycles each access was blocked 1545system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1546system.cpu1.icache.fast_writes 0 # number of fast writes performed 1547system.cpu1.icache.cache_copies 0 # number of cache copies performed 1548system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21323 # number of ReadReq MSHR hits 1549system.cpu1.icache.ReadReq_mshr_hits::total 21323 # number of ReadReq MSHR hits 1550system.cpu1.icache.demand_mshr_hits::cpu1.inst 21323 # number of demand (read+write) MSHR hits 1551system.cpu1.icache.demand_mshr_hits::total 21323 # number of demand (read+write) MSHR hits 1552system.cpu1.icache.overall_mshr_hits::cpu1.inst 21323 # number of overall MSHR hits 1553system.cpu1.icache.overall_mshr_hits::total 21323 # number of overall MSHR hits 1554system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455450 # number of ReadReq MSHR misses 1555system.cpu1.icache.ReadReq_mshr_misses::total 455450 # number of ReadReq MSHR misses 1556system.cpu1.icache.demand_mshr_misses::cpu1.inst 455450 # number of demand (read+write) MSHR misses 1557system.cpu1.icache.demand_mshr_misses::total 455450 # number of demand (read+write) MSHR misses 1558system.cpu1.icache.overall_mshr_misses::cpu1.inst 455450 # number of overall MSHR misses 1559system.cpu1.icache.overall_mshr_misses::total 455450 # number of overall MSHR misses 1560system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5356907000 # number of ReadReq MSHR miss cycles 1561system.cpu1.icache.ReadReq_mshr_miss_latency::total 5356907000 # number of ReadReq MSHR miss cycles 1562system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5356907000 # number of demand (read+write) MSHR miss cycles 1563system.cpu1.icache.demand_mshr_miss_latency::total 5356907000 # number of demand (read+write) MSHR miss cycles 1564system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5356907000 # number of overall MSHR miss cycles 1565system.cpu1.icache.overall_mshr_miss_latency::total 5356907000 # number of overall MSHR miss cycles 1566system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for ReadReq accesses 1567system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152204 # mshr miss rate for ReadReq accesses 1568system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for demand accesses 1569system.cpu1.icache.demand_mshr_miss_rate::total 0.152204 # mshr miss rate for demand accesses 1570system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for overall accesses 1571system.cpu1.icache.overall_mshr_miss_rate::total 0.152204 # mshr miss rate for overall accesses 1572system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average ReadReq mshr miss latency 1573system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11761.789439 # average ReadReq mshr miss latency 1574system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency 1575system.cpu1.icache.demand_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency 1576system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency 1577system.cpu1.icache.overall_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency 1578system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1579system.cpu1.dcache.replacements 520860 # number of replacements 1580system.cpu1.dcache.tagsinuse 498.284346 # Cycle average of tags in use 1581system.cpu1.dcache.total_refs 4488456 # Total number of references to valid blocks. 1582system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks. 1583system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks. 1584system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit. 1585system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor 1586system.cpu1.dcache.occ_percent::cpu1.data 0.973212 # Average percentage of cache occupancy 1587system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy 1588system.cpu1.dcache.ReadReq_hits::cpu1.data 2711578 # number of ReadReq hits 1589system.cpu1.dcache.ReadReq_hits::total 2711578 # number of ReadReq hits 1590system.cpu1.dcache.WriteReq_hits::cpu1.data 1652227 # number of WriteReq hits 1591system.cpu1.dcache.WriteReq_hits::total 1652227 # number of WriteReq hits 1592system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59380 # number of LoadLockedReq hits 1593system.cpu1.dcache.LoadLockedReq_hits::total 59380 # number of LoadLockedReq hits 1594system.cpu1.dcache.StoreCondReq_hits::cpu1.data 66046 # number of StoreCondReq hits 1595system.cpu1.dcache.StoreCondReq_hits::total 66046 # number of StoreCondReq hits 1596system.cpu1.dcache.demand_hits::cpu1.data 4363805 # number of demand (read+write) hits 1597system.cpu1.dcache.demand_hits::total 4363805 # number of demand (read+write) hits 1598system.cpu1.dcache.overall_hits::cpu1.data 4363805 # number of overall hits 1599system.cpu1.dcache.overall_hits::total 4363805 # number of overall hits 1600system.cpu1.dcache.ReadReq_misses::cpu1.data 735473 # number of ReadReq misses 1601system.cpu1.dcache.ReadReq_misses::total 735473 # number of ReadReq misses 1602system.cpu1.dcache.WriteReq_misses::cpu1.data 523667 # number of WriteReq misses 1603system.cpu1.dcache.WriteReq_misses::total 523667 # number of WriteReq misses 1604system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12800 # number of LoadLockedReq misses 1605system.cpu1.dcache.LoadLockedReq_misses::total 12800 # number of LoadLockedReq misses 1606system.cpu1.dcache.StoreCondReq_misses::cpu1.data 689 # number of StoreCondReq misses 1607system.cpu1.dcache.StoreCondReq_misses::total 689 # number of StoreCondReq misses 1608system.cpu1.dcache.demand_misses::cpu1.data 1259140 # number of demand (read+write) misses 1609system.cpu1.dcache.demand_misses::total 1259140 # number of demand (read+write) misses 1610system.cpu1.dcache.overall_misses::cpu1.data 1259140 # number of overall misses 1611system.cpu1.dcache.overall_misses::total 1259140 # number of overall misses 1612system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11275775500 # number of ReadReq miss cycles 1613system.cpu1.dcache.ReadReq_miss_latency::total 11275775500 # number of ReadReq miss cycles 1614system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16995132775 # number of WriteReq miss cycles 1615system.cpu1.dcache.WriteReq_miss_latency::total 16995132775 # number of WriteReq miss cycles 1616system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 186282500 # number of LoadLockedReq miss cycles 1617system.cpu1.dcache.LoadLockedReq_miss_latency::total 186282500 # number of LoadLockedReq miss cycles 1618system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5003500 # number of StoreCondReq miss cycles 1619system.cpu1.dcache.StoreCondReq_miss_latency::total 5003500 # number of StoreCondReq miss cycles 1620system.cpu1.dcache.demand_miss_latency::cpu1.data 28270908275 # number of demand (read+write) miss cycles 1621system.cpu1.dcache.demand_miss_latency::total 28270908275 # number of demand (read+write) miss cycles 1622system.cpu1.dcache.overall_miss_latency::cpu1.data 28270908275 # number of overall miss cycles 1623system.cpu1.dcache.overall_miss_latency::total 28270908275 # number of overall miss cycles 1624system.cpu1.dcache.ReadReq_accesses::cpu1.data 3447051 # number of ReadReq accesses(hits+misses) 1625system.cpu1.dcache.ReadReq_accesses::total 3447051 # number of ReadReq accesses(hits+misses) 1626system.cpu1.dcache.WriteReq_accesses::cpu1.data 2175894 # number of WriteReq accesses(hits+misses) 1627system.cpu1.dcache.WriteReq_accesses::total 2175894 # number of WriteReq accesses(hits+misses) 1628system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72180 # number of LoadLockedReq accesses(hits+misses) 1629system.cpu1.dcache.LoadLockedReq_accesses::total 72180 # number of LoadLockedReq accesses(hits+misses) 1630system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 66735 # number of StoreCondReq accesses(hits+misses) 1631system.cpu1.dcache.StoreCondReq_accesses::total 66735 # number of StoreCondReq accesses(hits+misses) 1632system.cpu1.dcache.demand_accesses::cpu1.data 5622945 # number of demand (read+write) accesses 1633system.cpu1.dcache.demand_accesses::total 5622945 # number of demand (read+write) accesses 1634system.cpu1.dcache.overall_accesses::cpu1.data 5622945 # number of overall (read+write) accesses 1635system.cpu1.dcache.overall_accesses::total 5622945 # number of overall (read+write) accesses 1636system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.213363 # miss rate for ReadReq accesses 1637system.cpu1.dcache.ReadReq_miss_rate::total 0.213363 # miss rate for ReadReq accesses 1638system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.240668 # miss rate for WriteReq accesses 1639system.cpu1.dcache.WriteReq_miss_rate::total 0.240668 # miss rate for WriteReq accesses 1640system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177334 # miss rate for LoadLockedReq accesses 1641system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177334 # miss rate for LoadLockedReq accesses 1642system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.010324 # miss rate for StoreCondReq accesses 1643system.cpu1.dcache.StoreCondReq_miss_rate::total 0.010324 # miss rate for StoreCondReq accesses 1644system.cpu1.dcache.demand_miss_rate::cpu1.data 0.223929 # miss rate for demand accesses 1645system.cpu1.dcache.demand_miss_rate::total 0.223929 # miss rate for demand accesses 1646system.cpu1.dcache.overall_miss_rate::cpu1.data 0.223929 # miss rate for overall accesses 1647system.cpu1.dcache.overall_miss_rate::total 0.223929 # miss rate for overall accesses 1648system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15331.324875 # average ReadReq miss latency 1649system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency 1650system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32454.083941 # average WriteReq miss latency 1651system.cpu1.dcache.WriteReq_avg_miss_latency::total 32454.083941 # average WriteReq miss latency 1652system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14553.320312 # average LoadLockedReq miss latency 1653system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14553.320312 # average LoadLockedReq miss latency 1654system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7261.973875 # average StoreCondReq miss latency 1655system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7261.973875 # average StoreCondReq miss latency 1656system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency 1657system.cpu1.dcache.demand_avg_miss_latency::total 22452.553548 # average overall miss latency 1658system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency 1659system.cpu1.dcache.overall_avg_miss_latency::total 22452.553548 # average overall miss latency 1660system.cpu1.dcache.blocked_cycles::no_mshrs 551348 # number of cycles access was blocked 1661system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1662system.cpu1.dcache.blocked::no_mshrs 10411 # number of cycles access was blocked 1663system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1664system.cpu1.dcache.avg_blocked_cycles::no_mshrs 52.958217 # average number of cycles each access was blocked 1665system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1666system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1667system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1668system.cpu1.dcache.writebacks::writebacks 405697 # number of writebacks 1669system.cpu1.dcache.writebacks::total 405697 # number of writebacks 1670system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 310580 # number of ReadReq MSHR hits 1671system.cpu1.dcache.ReadReq_mshr_hits::total 310580 # number of ReadReq MSHR hits 1672system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 431476 # number of WriteReq MSHR hits 1673system.cpu1.dcache.WriteReq_mshr_hits::total 431476 # number of WriteReq MSHR hits 1674system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2432 # number of LoadLockedReq MSHR hits 1675system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2432 # number of LoadLockedReq MSHR hits 1676system.cpu1.dcache.demand_mshr_hits::cpu1.data 742056 # number of demand (read+write) MSHR hits 1677system.cpu1.dcache.demand_mshr_hits::total 742056 # number of demand (read+write) MSHR hits 1678system.cpu1.dcache.overall_mshr_hits::cpu1.data 742056 # number of overall MSHR hits 1679system.cpu1.dcache.overall_mshr_hits::total 742056 # number of overall MSHR hits 1680system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 424893 # number of ReadReq MSHR misses 1681system.cpu1.dcache.ReadReq_mshr_misses::total 424893 # number of ReadReq MSHR misses 1682system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92191 # number of WriteReq MSHR misses 1683system.cpu1.dcache.WriteReq_mshr_misses::total 92191 # number of WriteReq MSHR misses 1684system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 10368 # number of LoadLockedReq MSHR misses 1685system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10368 # number of LoadLockedReq MSHR misses 1686system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 689 # number of StoreCondReq MSHR misses 1687system.cpu1.dcache.StoreCondReq_mshr_misses::total 689 # number of StoreCondReq MSHR misses 1688system.cpu1.dcache.demand_mshr_misses::cpu1.data 517084 # number of demand (read+write) MSHR misses 1689system.cpu1.dcache.demand_mshr_misses::total 517084 # number of demand (read+write) MSHR misses 1690system.cpu1.dcache.overall_mshr_misses::cpu1.data 517084 # number of overall MSHR misses 1691system.cpu1.dcache.overall_mshr_misses::total 517084 # number of overall MSHR misses 1692system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5584148500 # number of ReadReq MSHR miss cycles 1693system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5584148500 # number of ReadReq MSHR miss cycles 1694system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2607634127 # number of WriteReq MSHR miss cycles 1695system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2607634127 # number of WriteReq MSHR miss cycles 1696system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126008000 # number of LoadLockedReq MSHR miss cycles 1697system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126008000 # number of LoadLockedReq MSHR miss cycles 1698system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3625500 # number of StoreCondReq MSHR miss cycles 1699system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3625500 # number of StoreCondReq MSHR miss cycles 1700system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8191782627 # number of demand (read+write) MSHR miss cycles 1701system.cpu1.dcache.demand_mshr_miss_latency::total 8191782627 # number of demand (read+write) MSHR miss cycles 1702system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8191782627 # number of overall MSHR miss cycles 1703system.cpu1.dcache.overall_mshr_miss_latency::total 8191782627 # number of overall MSHR miss cycles 1704system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485715000 # number of ReadReq MSHR uncacheable cycles 1705system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485715000 # number of ReadReq MSHR uncacheable cycles 1706system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 920480500 # number of WriteReq MSHR uncacheable cycles 1707system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 920480500 # number of WriteReq MSHR uncacheable cycles 1708system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1406195500 # number of overall MSHR uncacheable cycles 1709system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1406195500 # number of overall MSHR uncacheable cycles 1710system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.123263 # mshr miss rate for ReadReq accesses 1711system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.123263 # mshr miss rate for ReadReq accesses 1712system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042369 # mshr miss rate for WriteReq accesses 1713system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042369 # mshr miss rate for WriteReq accesses 1714system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.143641 # mshr miss rate for LoadLockedReq accesses 1715system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.143641 # mshr miss rate for LoadLockedReq accesses 1716system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.010324 # mshr miss rate for StoreCondReq accesses 1717system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.010324 # mshr miss rate for StoreCondReq accesses 1718system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for demand accesses 1719system.cpu1.dcache.demand_mshr_miss_rate::total 0.091960 # mshr miss rate for demand accesses 1720system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for overall accesses 1721system.cpu1.dcache.overall_mshr_miss_rate::total 0.091960 # mshr miss rate for overall accesses 1722system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13142.481754 # average ReadReq mshr miss latency 1723system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency 1724system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency 1725system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency 1726system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency 1727system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency 1728system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency 1729system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency 1730system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency 1731system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency 1732system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency 1733system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency 1734system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1735system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1736system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1737system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1738system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1739system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1740system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1741system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1742system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed 1743system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed 1744system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl 1745system.cpu0.kern.ipl_count::21 133 0.11% 39.24% # number of times we switched to this ipl 1746system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl 1747system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl 1748system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl 1749system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl 1750system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl 1751system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl 1752system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl 1753system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl 1754system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl 1755system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl 1756system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl 1757system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl 1758system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl 1759system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl 1760system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl 1761system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl 1762system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl 1763system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1764system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1765system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1766system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl 1767system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl 1768system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed 1769system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed 1770system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed 1771system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed 1772system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed 1773system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed 1774system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed 1775system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed 1776system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed 1777system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed 1778system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed 1779system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed 1780system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed 1781system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed 1782system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed 1783system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed 1784system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed 1785system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed 1786system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed 1787system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed 1788system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed 1789system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed 1790system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed 1791system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed 1792system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed 1793system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed 1794system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed 1795system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed 1796system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed 1797system.cpu0.kern.syscall::total 211 # number of syscalls executed 1798system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1799system.cpu0.kern.callpal::wripir 97 0.07% 0.08% # number of callpals executed 1800system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed 1801system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed 1802system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed 1803system.cpu0.kern.callpal::swpctx 2435 1.87% 1.95% # number of callpals executed 1804system.cpu0.kern.callpal::tbi 48 0.04% 1.98% # number of callpals executed 1805system.cpu0.kern.callpal::wrent 7 0.01% 1.99% # number of callpals executed 1806system.cpu0.kern.callpal::swpipl 116655 89.61% 91.60% # number of callpals executed 1807system.cpu0.kern.callpal::rdps 6417 4.93% 96.53% # number of callpals executed 1808system.cpu0.kern.callpal::wrkgp 1 0.00% 96.53% # number of callpals executed 1809system.cpu0.kern.callpal::wrusp 4 0.00% 96.54% # number of callpals executed 1810system.cpu0.kern.callpal::rdusp 8 0.01% 96.54% # number of callpals executed 1811system.cpu0.kern.callpal::whami 2 0.00% 96.54% # number of callpals executed 1812system.cpu0.kern.callpal::rti 4017 3.09% 99.63% # number of callpals executed 1813system.cpu0.kern.callpal::callsys 345 0.27% 99.89% # number of callpals executed 1814system.cpu0.kern.callpal::imb 137 0.11% 100.00% # number of callpals executed 1815system.cpu0.kern.callpal::total 130177 # number of callpals executed 1816system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches 1817system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches 1818system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1819system.cpu0.kern.mode_good::kernel 1286 1820system.cpu0.kern.mode_good::user 1287 1821system.cpu0.kern.mode_good::idle 0 1822system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches 1823system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1824system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 1825system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches 1826system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode 1827system.cpu0.kern.mode_ticks::user 1913489000 0.10% 100.00% # number of ticks spent at the given mode 1828system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1829system.cpu0.kern.swap_context 2436 # number of times the context was actually changed 1830system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1831system.cpu1.kern.inst.quiesce 3786 # number of quiesce instructions executed 1832system.cpu1.kern.inst.hwrei 92502 # number of hwrei instructions executed 1833system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl 1834system.cpu1.kern.ipl_count::22 1921 2.30% 42.42% # number of times we switched to this ipl 1835system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl 1836system.cpu1.kern.ipl_count::31 48058 57.46% 100.00% # number of times we switched to this ipl 1837system.cpu1.kern.ipl_count::total 83636 # number of times we switched to this ipl 1838system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl 1839system.cpu1.kern.ipl_good::22 1921 2.84% 51.42% # number of times we switched to this ipl from a different ipl 1840system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl 1841system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl 1842system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl 1843system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl 1844system.cpu1.kern.ipl_ticks::22 533283000 0.03% 98.48% # number of cycles we spent at this ipl 1845system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl 1846system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl 1847system.cpu1.kern.ipl_ticks::total 1896615081500 # number of cycles we spent at this ipl 1848system.cpu1.kern.ipl_used::0 0.978665 # fraction of swpipl calls that actually changed the ipl 1849system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1850system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1851system.cpu1.kern.ipl_used::31 0.681406 # fraction of swpipl calls that actually changed the ipl 1852system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl 1853system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed 1854system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed 1855system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed 1856system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed 1857system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed 1858system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed 1859system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed 1860system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed 1861system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed 1862system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed 1863system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed 1864system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed 1865system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed 1866system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed 1867system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed 1868system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed 1869system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed 1870system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed 1871system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed 1872system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed 1873system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed 1874system.cpu1.kern.syscall::total 115 # number of syscalls executed 1875system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1876system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed 1877system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed 1878system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed 1879system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed 1880system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed 1881system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed 1882system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed 1883system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed 1884system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed 1885system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed 1886system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed 1887system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed 1888system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed 1889system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed 1890system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed 1891system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1892system.cpu1.kern.callpal::total 86022 # number of callpals executed 1893system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches 1894system.cpu1.kern.mode_switch::user 459 # number of protection mode switches 1895system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches 1896system.cpu1.kern.mode_good::kernel 518 1897system.cpu1.kern.mode_good::user 459 1898system.cpu1.kern.mode_good::idle 59 1899system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches 1900system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1901system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches 1902system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches 1903system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode 1904system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode 1905system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode 1906system.cpu1.kern.swap_context 1814 # number of times the context was actually changed 1907 1908---------- End Simulation Statistics ---------- 1909