linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.903548                       # Number of seconds simulated
sim_ticks                                1903548166500                       # Number of ticks simulated
final_tick                               1903548166500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 123505                       # Simulator instruction rate (inst/s)
host_op_rate                                   123505                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4187441182                       # Simulator tick rate (ticks/s)
host_mem_usage                                 303204                       # Number of bytes of host memory used
host_seconds                                   454.59                       # Real time elapsed on the host
sim_insts                                    56143492                       # Number of instructions simulated
sim_ops                                      56143492                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           879488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24796480                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2649664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           101696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           559552                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28986880                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       879488                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       101696                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          981184                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7925376                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7925376                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13742                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            387445                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41401                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1589                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8743                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                452920                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          123834                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123834                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              462026                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            13026453                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1391961                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               53424                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              293952                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15227815                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         462026                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53424                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             515450                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4163475                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4163475                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4163475                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             462026                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           13026453                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1391961                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              53424                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             293952                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19391291                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        346033                       # number of replacements
system.l2c.tagsinuse                     65330.743124                       # Cycle average of tags in use
system.l2c.total_refs                         2608063                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        411178                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.342905                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    6380526000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53708.225390                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5276.213951                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          6113.589929                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           198.792297                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            33.921558                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.819522                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.080509                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.093286                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.003033                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000518                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996868                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             970913                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             780748                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             107670                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              39067                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1898398                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          832636                       # number of Writeback hits
system.l2c.Writeback_hits::total               832636                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             184                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              54                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 238                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            27                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            29                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                56                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           168538                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            13567                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               182105                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              970913                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              949286                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              107670                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               52634                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2080503                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             970913                       # number of overall hits
system.l2c.overall_hits::cpu0.data             949286                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             107670                       # number of overall hits
system.l2c.overall_hits::cpu1.data              52634                       # number of overall hits
system.l2c.overall_hits::total                2080503                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13744                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           272909                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1606                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              887                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289146                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2478                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           531                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3009                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           43                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           77                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             120                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         114968                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7955                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             122923                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13744                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            387877                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1606                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8842                       # number of demand (read+write) misses
system.l2c.demand_misses::total                412069                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13744                       # number of overall misses
system.l2c.overall_misses::cpu0.data           387877                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1606                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8842                       # number of overall misses
system.l2c.overall_misses::total               412069                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    731783998                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  14210594000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     85626000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     48439997                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15076443995                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      2486000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1250500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      3736500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       522000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       156500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       678500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6190320497                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    441967499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6632287996                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    731783998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20400914497                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     85626000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    490407496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21708731991                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    731783998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20400914497                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     85626000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    490407496                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21708731991                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         984657                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1053657                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         109276                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          39954                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2187544                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       832636                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           832636                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2662                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          585                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3247                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           70                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          106                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           176                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       283506                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        21522                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           305028                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          984657                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1337163                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          109276                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           61476                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2492572                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         984657                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1337163                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         109276                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          61476                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2492572                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013958                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.259011                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.014697                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.022201                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.132178                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.930879                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.907692                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.926702                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.614286                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.726415                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.681818                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.405522                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.369622                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.402989                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013958                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.290075                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.014697                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.143828                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.165319                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013958                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.290075                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.014697                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.143828                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.165319                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53243.888097                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52141.285008                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1003.228410                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2354.990584                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1241.774676                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2032.467532                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5654.166667                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53843.856525                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53954.817211                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52596.350124                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53316.313823                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 55463.412803                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52682.274063                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53243.888097                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52596.350124                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53316.313823                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 55463.412803                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52682.274063                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               82314                       # number of writebacks
system.l2c.writebacks::total                    82314                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13743                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       272909                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1589                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          887                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289128                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2478                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          531                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3009                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           43                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           77                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          120                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       114968                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7955                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        122923                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13743                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       387877                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1589                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8842                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           412051                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13743                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       387877                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1589                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8842                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          412051                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    563800998                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10943970500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     65437000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     37722500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11610930998                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     99235500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     21259000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    120494500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1720000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3080000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      4800000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4801585997                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    345787499                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5147373496                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    563800998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  15745556497                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     65437000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    383509999                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16758304494                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    563800998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  15745556497                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     65437000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    383509999                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16758304494                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1363601000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     23660000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1387261000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1941911500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    514448500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2456360000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3305512500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    538108500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3843621000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013957                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.259011                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014541                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022201                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.132170                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.930879                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.907692                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.926702                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.614286                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.726415                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.681818                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.405522                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.369622                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.402989                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013957                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.290075                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014541                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.143828                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.165312                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013957                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.290075                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014541                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.143828                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.165312                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41024.594193                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40101.171086                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41181.246067                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42528.184893                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40158.445388                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40046.610169                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40035.781544                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40044.699236                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41764.543151                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43467.944563                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41874.779301                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41024.594193                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40594.199958                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41181.246067                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43373.671002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40670.461894                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41024.594193                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40594.199958                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41181.246067                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43373.671002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40670.461894                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41696                       # number of replacements
system.iocache.tagsinuse                     0.468369                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41712                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1712293009000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.468369                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.029273                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.029273                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
system.iocache.overall_misses::total            41728                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21012998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21012998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  11487114806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  11487114806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  11508127804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  11508127804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  11508127804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  11508127804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119392.034091                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276451.550010                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 276451.550010                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 275789.105732                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 275789.105732                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 275789.105732                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 275789.105732                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs     201643000                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                24752                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  8146.533613                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11860000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11860000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   9326257976                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   9326257976                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   9338117976                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9338117976                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   9338117976                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9338117976                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 223785.419287                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 223785.419287                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9377828                       # DTB read hits
system.cpu0.dtb.read_misses                     33360                       # DTB read misses
system.cpu0.dtb.read_acv                          521                       # DTB read access violations
system.cpu0.dtb.read_accesses                  633373                       # DTB read accesses
system.cpu0.dtb.write_hits                    6221809                       # DTB write hits
system.cpu0.dtb.write_misses                     7167                       # DTB write misses
system.cpu0.dtb.write_acv                         341                       # DTB write access violations
system.cpu0.dtb.write_accesses                 216042                       # DTB write accesses
system.cpu0.dtb.data_hits                    15599637                       # DTB hits
system.cpu0.dtb.data_misses                     40527                       # DTB misses
system.cpu0.dtb.data_acv                          862                       # DTB access violations
system.cpu0.dtb.data_accesses                  849415                       # DTB accesses
system.cpu0.itb.fetch_hits                    1073423                       # ITB hits
system.cpu0.itb.fetch_misses                    26403                       # ITB misses
system.cpu0.itb.fetch_acv                        1051                       # ITB acv
system.cpu0.itb.fetch_accesses                1099826                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       120667689                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                13362893                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted          11185412                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            402804                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              9622475                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5627170                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  884758                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              37477                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          30221705                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      67571030                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   13362893                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6511928                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12734942                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1928304                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              41309111                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               28714                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       205220                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       305503                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          225                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  8304621                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               277902                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          86063714                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.785128                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.113854                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                73328772     85.20%     85.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  837915      0.97%     86.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1666262      1.94%     88.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  768356      0.89%     89.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2658731      3.09%     92.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  585060      0.68%     92.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  622966      0.72%     93.50% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  967713      1.12%     94.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4627939      5.38%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            86063714                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.110741                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.559976                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                31149327                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             41124977                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 11584676                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               985581                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1219152                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              571369                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                39493                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              66407813                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               120728                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1219152                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                32233219                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               16872016                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      20344281                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10880828                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4514216                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              62880643                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6942                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                700700                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1661735                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           42005938                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             76144064                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        75702119                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           441945                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             36517182                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 5488748                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1574453                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        239002                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12018911                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9888186                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6523659                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1201517                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          824194                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  55665948                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1995313                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 54317533                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           112244                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6696159                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3338542                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1358752                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     86063714                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.631132                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.280124                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           61486843     71.44%     71.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           11432526     13.28%     84.73% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            5063556      5.88%     90.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3287093      3.82%     94.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2517985      2.93%     97.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1255115      1.46%     98.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             648079      0.75%     99.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             319509      0.37%     99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              53008      0.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       86063714                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  73354     10.53%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.53% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                330176     47.38%     57.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               293358     42.10%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3296      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             37287239     68.65%     68.65% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               60152      0.11%     68.76% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.76% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15662      0.03%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1646      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.80% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9781142     18.01%     86.80% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6293081     11.59%     98.39% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            875315      1.61%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              54317533                       # Type of FU issued
system.cpu0.iq.rate                          0.450141                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     696889                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.012830                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         194880881                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         64065914                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     53156794                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             627031                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            303977                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       294706                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              54682626                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 328500                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          571695                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1271953                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2828                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        12731                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       517788                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18545                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       107284                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1219152                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               12163042                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               861940                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           61112544                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           659342                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9888186                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6523659                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1757966                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                617572                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 9941                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         12731                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        210191                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       389993                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              600184                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             53834482                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9436308                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           483050                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3451283                       # number of nop insts executed
system.cpu0.iew.exec_refs                    15679571                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8587439                       # Number of branches executed
system.cpu0.iew.exec_stores                   6243263                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.446138                       # Inst execution rate
system.cpu0.iew.wb_sent                      53546468                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     53451500                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 26356174                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35593959                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.442964                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.740468                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        7303960                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         636561                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           562819                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     84844562                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.633202                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.547709                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     64556270     76.09%     76.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8510919     10.03%     86.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4635841      5.46%     91.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2494817      2.94%     94.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1390539      1.64%     96.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       576056      0.68%     96.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       484846      0.57%     97.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       456978      0.54%     97.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1738296      2.05%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     84844562                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            53723778                       # Number of instructions committed
system.cpu0.commit.committedOps              53723778                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14622104                       # Number of memory references committed
system.cpu0.commit.loads                      8616233                       # Number of loads committed
system.cpu0.commit.membars                     216543                       # Number of memory barriers committed
system.cpu0.commit.branches                   8113778                       # Number of branches committed
system.cpu0.commit.fp_insts                    292474                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 49705714                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              703203                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1738296                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   143945633                       # The number of ROB reads
system.cpu0.rob.rob_writes                  123274808                       # The number of ROB writes
system.cpu0.timesIdled                        1363780                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       34603975                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3686422279                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   50608732                       # Number of Instructions Simulated
system.cpu0.committedOps                     50608732                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             50608732                       # Number of Instructions Simulated
system.cpu0.cpi                              2.384325                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.384325                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.419406                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.419406                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                70600527                       # number of integer regfile reads
system.cpu0.int_regfile_writes               38607300                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   144193                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  146198                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1863622                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                886886                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                984085                       # number of replacements
system.cpu0.icache.tagsinuse               509.993322                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 7264923                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                984594                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.378598                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23948219000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   509.993322                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996081                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996081                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      7264923                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7264923                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      7264923                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7264923                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      7264923                       # number of overall hits
system.cpu0.icache.overall_hits::total        7264923                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1039697                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1039697                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1039697                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1039697                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1039697                       # number of overall misses
system.cpu0.icache.overall_misses::total      1039697                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  16868456488                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  16868456488                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  16868456488                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  16868456488                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  16868456488                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  16868456488                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      8304620                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8304620                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      8304620                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8304620                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      8304620                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8304620                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125195                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.125195                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125195                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.125195                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125195                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.125195                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16224.396616                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16224.396616                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 16224.396616                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 16224.396616                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1612994                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              171                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  9432.713450                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54925                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        54925                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        54925                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        54925                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        54925                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        54925                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       984772                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       984772                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       984772                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       984772                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       984772                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       984772                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13041683494                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  13041683494                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13041683494                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  13041683494                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13041683494                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  13041683494                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.118581                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.118581                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.118581                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.118581                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.118581                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.118581                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13243.353278                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13243.353278                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13243.353278                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1341345                       # number of replacements
system.cpu0.dcache.tagsinuse               506.494858                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                11161433                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1341857                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.317900                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              23750000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   506.494858                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.989248                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.989248                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6822568                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6822568                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3942957                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3942957                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       181355                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       181355                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       208341                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       208341                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10765525                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10765525                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10765525                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10765525                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1719034                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1719034                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1839372                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1839372                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22429                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22429                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          711                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          711                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3558406                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3558406                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3558406                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3558406                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  46470872000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  46470872000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  71479264510                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  71479264510                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    406558000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    406558000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      6746500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      6746500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 117950136510                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 117950136510                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 117950136510                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 117950136510                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8541602                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8541602                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5782329                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5782329                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       203784                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       203784                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       209052                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       209052                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14323931                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14323931                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14323931                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14323931                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.201254                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.201254                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.318102                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.318102                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110063                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110063                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003401                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003401                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248424                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.248424                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248424                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.248424                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27033.131398                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27033.131398                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38860.689686                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38860.689686                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18126.443444                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18126.443444                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9488.748242                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9488.748242                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33146.902436                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33146.902436                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33146.902436                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33146.902436                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    754476476                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       245500                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            70452                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              9                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10709.085278                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 27277.777778                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       796119                       # number of writebacks
system.cpu0.dcache.writebacks::total           796119                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       675047                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       675047                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1552745                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1552745                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5057                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5057                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2227792                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2227792                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2227792                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2227792                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1043987                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1043987                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       286627                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       286627                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        17372                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        17372                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          711                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          711                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1330614                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1330614                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1330614                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1330614                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27461612037                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27461612037                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9493856805                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9493856805                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    250184001                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    250184001                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      4525001                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      4525001                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36955468842                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  36955468842                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36955468842                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  36955468842                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1456541500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1456541500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2062903998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2062903998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3519445498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3519445498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122224                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122224                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049569                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049569                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085247                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085247                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003401                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003401                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092894                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.092894                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092894                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.092894                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26304.553636                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26304.553636                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33122.688389                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33122.688389                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14401.565796                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14401.565796                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6364.277075                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6364.277075                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27773.245165                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27773.245165                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27773.245165                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27773.245165                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1298594                       # DTB read hits
system.cpu1.dtb.read_misses                     11503                       # DTB read misses
system.cpu1.dtb.read_acv                            6                       # DTB read access violations
system.cpu1.dtb.read_accesses                  332098                       # DTB read accesses
system.cpu1.dtb.write_hits                     765153                       # DTB write hits
system.cpu1.dtb.write_misses                     2957                       # DTB write misses
system.cpu1.dtb.write_acv                          47                       # DTB write access violations
system.cpu1.dtb.write_accesses                 125840                       # DTB write accesses
system.cpu1.dtb.data_hits                     2063747                       # DTB hits
system.cpu1.dtb.data_misses                     14460                       # DTB misses
system.cpu1.dtb.data_acv                           53                       # DTB access violations
system.cpu1.dtb.data_accesses                  457938                       # DTB accesses
system.cpu1.itb.fetch_hits                     372513                       # ITB hits
system.cpu1.itb.fetch_misses                     8563                       # ITB misses
system.cpu1.itb.fetch_acv                         155                       # ITB acv
system.cpu1.itb.fetch_accesses                 381076                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        10640951                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 1701905                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           1402674                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect             62577                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups               862370                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                  552113                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  115027                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect               5500                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           3435420                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                       8139615                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    1701905                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            667140                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      1472350                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 326710                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               4537469                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               24627                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        73138                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        47601                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1039363                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                39149                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples           9806707                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.830005                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.196976                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                 8334357     84.99%     84.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   78230      0.80%     85.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  173812      1.77%     87.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  130927      1.34%     88.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  215769      2.20%     91.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   90418      0.92%     92.01% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                   98526      1.00%     93.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   62686      0.64%     93.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  621982      6.34%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total             9806707                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.159939                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.764933                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 3510066                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              4639401                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1367694                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                78184                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                211361                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved               75357                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 4832                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts               7943726                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                14591                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                211361                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 3646380                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 524692                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       3638231                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1300485                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               485556                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts               7343826                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  139                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 57550                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               136110                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            4921664                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups              8958013                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups         8905584                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            52429                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              3978815                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                  942849                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            306458                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         22346                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1365387                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1395502                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores             827989                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           138090                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           96967                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   6484639                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             311488                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  6173957                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            24546                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1207593                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       679802                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        236614                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples      9806707                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.629565                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.304884                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            7075152     72.15%     72.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1257607     12.82%     84.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             548751      5.60%     90.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             366543      3.74%     94.30% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             274418      2.80%     97.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             146525      1.49%     98.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6              78833      0.80%     99.40% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              55100      0.56%     99.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8               3778      0.04%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total        9806707                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   2937      2.09%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      2.09% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 77829     55.26%     57.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                60078     42.66%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3992      0.06%      0.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              3816770     61.82%     61.89% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               10118      0.16%     62.05% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.05% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10095      0.16%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.21% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1996      0.03%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.24% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1354962     21.95%     84.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite             784960     12.71%     96.91% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            191064      3.09%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               6173957                       # Type of FU issued
system.cpu1.iq.rate                          0.580207                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     140844                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.022813                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          22242262                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes          7966601                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      5994284                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              77749                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             38725                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        37333                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               6270612                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  40197                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           68178                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       253497                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          450                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1694                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       109535                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          346                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked         8387                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                211361                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 294243                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                17071                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            7057887                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           102198                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1395502                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts              827989                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            289869                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  6102                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3806                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1694                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         30581                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        71547                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              102128                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              6103512                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1313696                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            70445                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       261760                       # number of nop insts executed
system.cpu1.iew.exec_refs                     2085126                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                  894247                       # Number of branches executed
system.cpu1.iew.exec_stores                    771430                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.573587                       # Inst execution rate
system.cpu1.iew.wb_sent                       6061366                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      6031617                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  2917806                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  4086073                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.566831                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.714086                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1232464                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls          74874                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts            96289                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples      9595346                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.599743                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.518608                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0      7360615     76.71%     76.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1091727     11.38%     88.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       382276      3.98%     92.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       236221      2.46%     94.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       149500      1.56%     96.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        68368      0.71%     96.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        77096      0.80%     97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        48958      0.51%     98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       180585      1.88%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total      9595346                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             5754744                       # Number of instructions committed
system.cpu1.commit.committedOps               5754744                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       1860459                       # Number of memory references committed
system.cpu1.commit.loads                      1142005                       # Number of loads committed
system.cpu1.commit.membars                      20259                       # Number of memory barriers committed
system.cpu1.commit.branches                    814036                       # Number of branches committed
system.cpu1.commit.fp_insts                     36051                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  5384897                       # Number of committed integer instructions.
system.cpu1.commit.function_calls               87726                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               180585                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    16310969                       # The number of ROB reads
system.cpu1.rob.rob_writes                   14184459                       # The number of ROB writes
system.cpu1.timesIdled                          82580                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         834244                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3796004491                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    5534760                       # Number of Instructions Simulated
system.cpu1.committedOps                      5534760                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total              5534760                       # Number of Instructions Simulated
system.cpu1.cpi                              1.922568                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.922568                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.520138                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.520138                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                 7951221                       # number of integer regfile reads
system.cpu1.int_regfile_writes                4345022                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    24272                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   22982                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 283160                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                134137                       # number of misc regfile writes
system.cpu1.icache.replacements                108736                       # number of replacements
system.cpu1.icache.tagsinuse               452.848051                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  924017                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                109246                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  8.458131                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1880838222000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   452.848051                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.884469                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.884469                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst       924017                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         924017                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       924017                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          924017                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       924017                       # number of overall hits
system.cpu1.icache.overall_hits::total         924017                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       115346                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       115346                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       115346                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        115346                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       115346                       # number of overall misses
system.cpu1.icache.overall_misses::total       115346                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1915256999                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1915256999                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1915256999                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1915256999                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1915256999                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1915256999                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1039363                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1039363                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1039363                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1039363                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1039363                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1039363                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.110978                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.110978                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.110978                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.110978                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.110978                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.110978                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16604.450948                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 16604.450948                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 16604.450948                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       222999                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               30                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  7433.300000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         6038                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         6038                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         6038                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         6038                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         6038                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         6038                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       109308                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       109308                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       109308                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       109308                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       109308                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       109308                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1491398999                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   1491398999                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1491398999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   1491398999                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1491398999                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   1491398999                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.105168                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.105168                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.105168                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.105168                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.105168                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.105168                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13644.005919                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 61811                       # number of replacements
system.cpu1.dcache.tagsinuse               423.387508                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1665798                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 62157                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 26.799846                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1880297158000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   423.387508                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.826929                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.826929                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1100458                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1100458                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       541491                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        541491                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        16674                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        16674                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        14757                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        14757                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1641949                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1641949                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1641949                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1641949                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       110209                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       110209                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       156496                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       156496                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1520                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1520                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          666                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          666                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       266705                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        266705                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       266705                       # number of overall misses
system.cpu1.dcache.overall_misses::total       266705                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2207117500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2207117500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6428377585                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   6428377585                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     25057000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     25057000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8004500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      8004500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8635495085                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8635495085                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8635495085                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8635495085                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1210667                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1210667                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       697987                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       697987                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        18194                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        18194                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        15423                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        15423                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      1908654                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1908654                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      1908654                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1908654                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.091032                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.091032                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.224210                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.224210                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.083544                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.083544                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.043182                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.043182                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.139735                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.139735                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.139735                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.139735                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20026.653903                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 20026.653903                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41076.945002                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41076.945002                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16484.868421                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16484.868421                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12018.768769                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12018.768769                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32378.452166                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 32378.452166                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32378.452166                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 32378.452166                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     48117991                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             4997                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9629.375825                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        36517                       # number of writebacks
system.cpu1.dcache.writebacks::total            36517                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        66699                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        66699                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       133155                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       133155                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          347                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          347                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       199854                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       199854                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       199854                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       199854                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        43510                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        43510                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        23341                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        23341                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1173                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1173                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          665                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          665                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        66851                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        66851                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        66851                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        66851                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    664874003                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    664874003                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    774412476                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    774412476                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     13964500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     13964500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5940500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5940500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1439286479                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1439286479                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1439286479                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1439286479                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     25429000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     25429000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    545455000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    545455000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    570884000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    570884000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035939                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035939                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033440                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.033440                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064472                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064472                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.043117                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.043117                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.035025                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.035025                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035025                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035025                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15280.946978                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15280.946978                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33178.204704                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33178.204704                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11904.944587                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.944587                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  8933.082707                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  8933.082707                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21529.767378                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21529.767378                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21529.767378                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21529.767378                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    199157                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   71465     40.61%     40.61% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    131      0.07%     40.69% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1927      1.10%     41.78% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      9      0.01%     41.79% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 102444     58.21%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              175976                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    70100     49.28%     49.28% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     131      0.09%     49.37% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1927      1.35%     50.72% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       9      0.01%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   70091     49.27%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               142258                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1862744375000     97.86%     97.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               69542000      0.00%     97.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              583001500      0.03%     97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                5982500      0.00%     97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            40144359500      2.11%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1903547260500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.980900                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.684188                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808394                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.65%      3.65% # number of syscalls executed
system.cpu0.kern.syscall::3                        19      8.68%     12.33% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.37%     13.70% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.61%     28.31% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.46%     28.77% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      3.65%     32.42% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.57%     36.99% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.74%     39.73% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.46%     40.18% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.37%     41.55% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      2.74%     44.29% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.91%     45.21% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     16.44%     61.64% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.37%     63.01% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.57%     67.58% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.57%     72.15% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.46%     72.60% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.74%     75.34% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.50%     85.84% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.37%     87.21% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.74%     89.95% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.46%     90.41% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.37%     91.78% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.11%     95.89% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.91%     96.80% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.91%     97.72% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.46%     98.17% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.91%     99.09% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.91%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   219                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  101      0.05%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3850      2.08%      2.14% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.17% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.17% # number of callpals executed
system.cpu0.kern.callpal::swpipl               169235     91.57%     93.74% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6384      3.45%     97.19% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     97.19% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
system.cpu0.kern.callpal::rti                    4673      2.53%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 373      0.20%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     133      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                184824                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7179                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1251                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1250
system.cpu0.kern.mode_good::user                 1251
system.cpu0.kern.mode_good::idle                    0
system.cpu0.kern.mode_switch_good::kernel     0.174119                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.296679                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1901642531000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1904721500      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3851                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2262                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     38430                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   10197     33.29%     33.29% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1926      6.29%     39.58% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    101      0.33%     39.91% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  18406     60.09%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               30630                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    10185     45.68%     45.68% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1926      8.64%     54.32% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     101      0.45%     54.77% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   10084     45.23%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                22296                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1876291886000     98.58%     98.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              533607500      0.03%     98.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               52904000      0.00%     98.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            26445439500      1.39%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1903323837000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998823                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.547865                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.727914                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        11     10.28%     10.28% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.93%     11.21% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.35%     20.56% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.93%     21.50% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      6.54%     28.04% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.80%     30.84% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.80%     33.64% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      4.67%     38.32% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     16.82%     55.14% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.80%     57.94% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.93%     58.88% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     28.97%     87.85% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.35%     97.20% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.80%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   107                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    9      0.03%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.04% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  385      1.22%      1.26% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.27% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.29% # number of callpals executed
system.cpu1.kern.callpal::swpipl                26077     82.56%     83.85% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2376      7.52%     91.38% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.38% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.02%     91.39% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     91.40% # number of callpals executed
system.cpu1.kern.callpal::rti                    2525      7.99%     99.40% # number of callpals executed
system.cpu1.kern.callpal::callsys                 142      0.45%     99.85% # number of callpals executed
system.cpu1.kern.callpal::imb                      47      0.15%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 31584                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              861                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                488                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2051                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                514
system.cpu1.kern.mode_good::user                  488
system.cpu1.kern.mode_good::idle                   26
system.cpu1.kern.mode_switch_good::kernel     0.596980                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.012677                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.302353                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        2103355500      0.11%      0.11% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           871184500      0.05%      0.16% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1899849485000     99.84%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     386                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------