linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.903503                       # Number of seconds simulated
sim_ticks                                1903503020500                       # Number of ticks simulated
final_tick                               1903503020500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 196271                       # Simulator instruction rate (inst/s)
host_op_rate                                   196271                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6657053225                       # Simulator tick rate (ticks/s)
host_mem_usage                                 303260                       # Number of bytes of host memory used
host_seconds                                   285.94                       # Real time elapsed on the host
sim_insts                                    56121257                       # Number of instructions simulated
sim_ops                                      56121257                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst           882432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24721216                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2649664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           100416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           648960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             29002688                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       882432                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       100416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          982848                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7936064                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7936064                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst             13788                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            386269                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41401                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1569                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             10140                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                453167                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124001                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               124001                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst              463583                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data            12987222                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1391994                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52753                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              340929                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15236481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         463583                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52753                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             516336                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4169189                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4169189                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4169189                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             463583                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data           12987222                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1391994                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52753                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             340929                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19405670                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        346253                       # number of replacements
system.l2c.tagsinuse                     65331.229324                       # Cycle average of tags in use
system.l2c.total_refs                         2603754                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        411399                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          6.329024                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    6380524000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        53709.821247                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          5286.136461                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          6105.466815                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst           198.491400                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data            31.313401                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.819547                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.080660                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.093162                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.003029                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.000478                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.996875                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst             965065                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             779439                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             111820                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              39391                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1895715                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          831921                       # number of Writeback hits
system.l2c.Writeback_hits::total               831921                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              73                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 245                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            28                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            28                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                56                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           165704                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            16093                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               181797                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst              965065                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              945143                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              111820                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               55484                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2077512                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst             965065                       # number of overall hits
system.l2c.overall_hits::cpu0.data             945143                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             111820                       # number of overall hits
system.l2c.overall_hits::cpu1.data              55484                       # number of overall hits
system.l2c.overall_hits::total                2077512                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst            13790                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           273025                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1586                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              787                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               289188                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          2478                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           547                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3025                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           39                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           78                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             117                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         113756                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           9451                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             123207                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst             13790                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            386781                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1586                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             10238                       # number of demand (read+write) misses
system.l2c.demand_misses::total                412395                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst            13790                       # number of overall misses
system.l2c.overall_misses::cpu0.data           386781                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1586                       # number of overall misses
system.l2c.overall_misses::cpu1.data            10238                       # number of overall misses
system.l2c.overall_misses::total               412395                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst    734208497                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  14217029000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     84954500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     43255499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15079447496                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      2117000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2247500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      4364500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       418000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       208000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       626000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6097259996                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    516851999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6614111995                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst    734208497                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  20314288996                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     84954500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    560107498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     21693559491                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst    734208497                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  20314288996                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     84954500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    560107498                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    21693559491                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst         978855                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        1052464                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         113406                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          40178                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2184903                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       831921                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           831921                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         2650                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          620                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3270                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data           67                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          106                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           173                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       279460                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        25544                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           305004                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst          978855                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1331924                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          113406                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           65722                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2489907                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         978855                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1331924                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         113406                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          65722                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2489907                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014088                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.259415                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.013985                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.019588                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.132357                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.935094                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.882258                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.925076                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.582090                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.735849                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.676301                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.407056                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.369989                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.403952                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014088                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.290393                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.013985                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.155777                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.165627                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014088                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.290393                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.013985                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.155777                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.165627                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53242.095504                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.260782                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53565.258512                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54962.514612                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52144.098289                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   854.317998                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4108.775137                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1442.809917                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10717.948718                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2666.666667                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5350.427350                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53599.458455                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54687.546186                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53682.923819                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53242.095504                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52521.424258                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53565.258512                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 54708.683141                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52603.837319                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53242.095504                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52521.424258                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53565.258512                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 54708.683141                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52603.837319                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               82481                       # number of writebacks
system.l2c.writebacks::total                    82481                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst        13789                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       273025                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1569                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          787                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          289170                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         2478                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          547                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3025                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           39                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           78                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          117                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       113756                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         9451                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        123207                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        13789                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       386781                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1569                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        10238                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           412377                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        13789                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       386781                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1569                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        10238                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          412377                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    565634498                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10948899500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     65008500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     33728000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  11613270498                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     99222000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     21905000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    121127000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1560000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3120000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      4680000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4723374496                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    402418000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5125792496                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    565634498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  15672273996                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     65008500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    436146000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16739062994                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    565634498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  15672273996                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     65008500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    436146000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16739062994                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1361916000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     24780000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   1386696000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1936832500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    518088500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2454921000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3298748500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    542868500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   3841617000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.259415                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.013835                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.019588                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.132349                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.935094                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.882258                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.925076                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.582090                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.735849                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.676301                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.407056                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.369989                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.403952                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.290393                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.013835                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.155777                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.165619                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.290393                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.013835                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.155777                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.165619                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41020.704765                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40102.186613                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41433.078394                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42856.416773                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40160.703040                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.162228                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40045.703839                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40041.983471                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41521.981223                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42579.409586                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41603.094759                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41020.704765                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40519.761819                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41433.078394                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42600.703262                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40591.650344                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41020.704765                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40519.761819                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41433.078394                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42600.703262                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40591.650344                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41696                       # number of replacements
system.iocache.tagsinuse                     0.468001                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41712                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1712293423000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide       0.468001                       # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide      0.029250                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.029250                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
system.iocache.overall_misses::total            41728                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21012998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21012998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide   7634627806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   7634627806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide   7655640804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   7655640804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide   7655640804                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   7655640804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119392.034091                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183736.710772                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 183736.710772                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 183465.318347                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183465.318347                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 183465.318347                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183465.318347                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs       7744000                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7100                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  1090.704225                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41520                       # number of writebacks
system.iocache.writebacks::total                41520                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11860000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     11860000                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5473770000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   5473770000                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide   5485630000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   5485630000                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide   5485630000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   5485630000                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131733.009241                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 131733.009241                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131461.608512                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131461.608512                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131461.608512                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131461.608512                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9362822                       # DTB read hits
system.cpu0.dtb.read_misses                     32776                       # DTB read misses
system.cpu0.dtb.read_acv                          407                       # DTB read access violations
system.cpu0.dtb.read_accesses                  655429                       # DTB read accesses
system.cpu0.dtb.write_hits                    6177998                       # DTB write hits
system.cpu0.dtb.write_misses                     6927                       # DTB write misses
system.cpu0.dtb.write_acv                         263                       # DTB write access violations
system.cpu0.dtb.write_accesses                 211643                       # DTB write accesses
system.cpu0.dtb.data_hits                    15540820                       # DTB hits
system.cpu0.dtb.data_misses                     39703                       # DTB misses
system.cpu0.dtb.data_acv                          670                       # DTB access violations
system.cpu0.dtb.data_accesses                  867072                       # DTB accesses
system.cpu0.itb.fetch_hits                    1071612                       # ITB hits
system.cpu0.itb.fetch_misses                    26818                       # ITB misses
system.cpu0.itb.fetch_acv                         827                       # ITB acv
system.cpu0.itb.fetch_accesses                1098430                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       120285579                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                13328375                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted          11156715                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            403301                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              9703007                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5627426                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  881916                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              36485                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          30082863                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      67323144                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   13328375                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           6509342                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     12704270                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                1925792                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              41150259                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               29396                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       190626                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       307717                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          171                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  8274450                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               278264                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          85724819                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.785340                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.113356                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                73020549     85.18%     85.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  838460      0.98%     86.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1676934      1.96%     88.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  765061      0.89%     89.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2646040      3.09%     92.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  584012      0.68%     92.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  626464      0.73%     93.51% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  965763      1.13%     94.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4601536      5.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            85724819                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.110806                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.559694                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                31004655                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             40959879                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 11547285                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               992195                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1220804                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              569651                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                39042                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              66162079                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               119714                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1220804                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                32084617                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               16798713                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      20265121                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10859034                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4496528                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              62667463                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6952                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                714166                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1644224                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           41889226                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             75909055                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        75455060                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           453995                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             36387256                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 5501970                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1564601                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        238699                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 11969460                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             9870474                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6474014                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1213478                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          815744                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  55487857                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1996787                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 54121133                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           111429                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        6732221                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3352698                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1361171                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     85724819                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.631336                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.279357                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           61209229     71.40%     71.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           11417613     13.32%     84.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            5048858      5.89%     90.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3283375      3.83%     94.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2508461      2.93%     97.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1248570      1.46%     98.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             634570      0.74%     99.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             321579      0.38%     99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              52564      0.06%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       85724819                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  72995     10.68%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.68% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                324242     47.46%     58.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               285988     41.86%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             4465      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             37158612     68.66%     68.67% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               60272      0.11%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              18564      0.03%     68.81% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.81% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.81% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.81% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               2231      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9761868     18.04%     86.85% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6247803     11.54%     98.40% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            867318      1.60%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              54121133                       # Type of FU issued
system.cpu0.iq.rate                          0.449939                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     683225                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.012624                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         194116788                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         63916247                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     52959668                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             644951                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            312925                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       303605                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              54462198                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 337695                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          568272                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1280116                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2462                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        12570                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       515440                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18537                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       100807                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1220804                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               12124657                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               860720                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           60917526                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           643294                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              9870474                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6474014                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1758330                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                617908                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 8871                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         12570                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        212626                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       388253                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              600879                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             53642657                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9419598                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           478476                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3432882                       # number of nop insts executed
system.cpu0.iew.exec_refs                    15618436                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8560068                       # Number of branches executed
system.cpu0.iew.exec_stores                   6198838                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.445961                       # Inst execution rate
system.cpu0.iew.wb_sent                      53356597                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     53263273                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 26352404                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35613133                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.442807                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.739963                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        7330810                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         635616                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           562628                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     84504015                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.633112                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.546448                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     64274948     76.06%     76.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8494337     10.05%     86.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4620943      5.47%     91.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2493253      2.95%     94.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1382716      1.64%     96.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       578306      0.68%     96.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       482831      0.57%     97.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       448312      0.53%     97.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1728369      2.05%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     84504015                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            53500498                       # Number of instructions committed
system.cpu0.commit.committedOps              53500498                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14548932                       # Number of memory references committed
system.cpu0.commit.loads                      8590358                       # Number of loads committed
system.cpu0.commit.membars                     216685                       # Number of memory barriers committed
system.cpu0.commit.branches                   8083038                       # Number of branches committed
system.cpu0.commit.fp_insts                    301061                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 49495422                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              700509                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1728369                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   143428116                       # The number of ROB reads
system.cpu0.rob.rob_writes                  122883641                       # The number of ROB writes
system.cpu0.timesIdled                        1359099                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       34560760                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3686357913                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   50400239                       # Number of Instructions Simulated
system.cpu0.committedOps                     50400239                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             50400239                       # Number of Instructions Simulated
system.cpu0.cpi                              2.386607                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.386607                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.419005                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.419005                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                70355564                       # number of integer regfile reads
system.cpu0.int_regfile_writes               38486142                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   150309                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  151918                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1870359                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                881938                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                978272                       # number of replacements
system.cpu0.icache.tagsinuse               509.990128                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 7239988                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                978784                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.396921                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23947377000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   509.990128                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.996074                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.996074                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst      7239988                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7239988                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      7239988                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7239988                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      7239988                       # number of overall hits
system.cpu0.icache.overall_hits::total        7239988                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1034461                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1034461                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1034461                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1034461                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1034461                       # number of overall misses
system.cpu0.icache.overall_misses::total      1034461                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  16768248492                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  16768248492                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  16768248492                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  16768248492                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  16768248492                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  16768248492                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      8274449                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8274449                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      8274449                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8274449                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      8274449                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8274449                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125019                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.125019                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125019                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.125019                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125019                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.125019                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16209.647819                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 16209.647819                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16209.647819                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 16209.647819                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16209.647819                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 16209.647819                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1517995                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              159                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  9547.138365                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        55484                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        55484                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        55484                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        55484                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        55484                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        55484                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       978977                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       978977                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       978977                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       978977                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       978977                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       978977                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12951368495                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  12951368495                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12951368495                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  12951368495                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12951368495                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  12951368495                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.118313                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.118313                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.118313                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.118313                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.118313                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.118313                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13229.492108                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13229.492108                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13229.492108                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13229.492108                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13229.492108                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13229.492108                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1336500                       # number of replacements
system.cpu0.dcache.tagsinuse               506.465908                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                11143271                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1336941                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.334901                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              23748000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   506.465908                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.989191                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.989191                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6824660                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6824660                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3928020                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3928020                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       181318                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       181318                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       208014                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       208014                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10752680                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10752680                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10752680                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10752680                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      1708787                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1708787                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1807599                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1807599                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22179                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22179                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data          632                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          632                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3516386                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3516386                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3516386                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3516386                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  46211851500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  46211851500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  69878054952                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  69878054952                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    400322000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    400322000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      6190000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total      6190000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 116089906452                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 116089906452                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 116089906452                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 116089906452                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      8533447                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8533447                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5735619                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5735619                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       203497                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       203497                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       208646                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       208646                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     14269066                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14269066                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     14269066                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14269066                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.200246                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.200246                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.315153                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.315153                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.108989                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.108989                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003029                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003029                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.246434                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.246434                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.246434                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.246434                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27043.658162                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27043.658162                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38657.940700                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38657.940700                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18049.596465                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18049.596465                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9794.303797                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9794.303797                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33013.982666                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33013.982666                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33013.982666                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33013.982666                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    743236979                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       140000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            67742                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              5                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10971.583050                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        28000                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       787469                       # number of writebacks
system.cpu0.dcache.writebacks::total           787469                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       665447                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       665447                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1525035                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1525035                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4877                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4877                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      2190482                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      2190482                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      2190482                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      2190482                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1043340                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      1043340                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       282564                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       282564                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        17302                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        17302                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          632                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total          632                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      1325904                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      1325904                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      1325904                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      1325904                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27425552538                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27425552538                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9314976366                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9314976366                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    247730500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    247730500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      4222000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      4222000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36740528904                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  36740528904                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36740528904                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  36740528904                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1454814000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1454814000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2057449498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2057449498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3512263498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3512263498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122265                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122265                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049265                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049265                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085023                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085023                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003029                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003029                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092922                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.092922                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092922                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.092922                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26286.304118                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26286.304118                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32965.899287                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32965.899287                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14318.026818                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14318.026818                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6680.379747                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6680.379747                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27709.795659                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27709.795659                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27709.795659                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27709.795659                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1316259                       # DTB read hits
system.cpu1.dtb.read_misses                     12259                       # DTB read misses
system.cpu1.dtb.read_acv                          114                       # DTB read access violations
system.cpu1.dtb.read_accesses                  313045                       # DTB read accesses
system.cpu1.dtb.write_hits                     810694                       # DTB write hits
system.cpu1.dtb.write_misses                     3210                       # DTB write misses
system.cpu1.dtb.write_acv                         140                       # DTB write access violations
system.cpu1.dtb.write_accesses                 130863                       # DTB write accesses
system.cpu1.dtb.data_hits                     2126953                       # DTB hits
system.cpu1.dtb.data_misses                     15469                       # DTB misses
system.cpu1.dtb.data_acv                          254                       # DTB access violations
system.cpu1.dtb.data_accesses                  443908                       # DTB accesses
system.cpu1.itb.fetch_hits                     378821                       # ITB hits
system.cpu1.itb.fetch_misses                     8734                       # ITB misses
system.cpu1.itb.fetch_acv                         397                       # ITB acv
system.cpu1.itb.fetch_accesses                 387555                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                        10995031                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 1761936                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           1452774                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect             65512                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups               889011                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                  565473                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  118681                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect               6179                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           3538328                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                       8413663                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    1761936                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            684154                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      1515563                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 337074                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               4688566                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               24381                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        85396                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        48035                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           31                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1081640                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                43091                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples          10121394                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.831275                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.201855                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                 8605831     85.03%     85.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                   83210      0.82%     85.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  170185      1.68%     87.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  136768      1.35%     88.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  220692      2.18%     91.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   89992      0.89%     91.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  103416      1.02%     92.97% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   63845      0.63%     93.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  647455      6.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            10121394                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.160248                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.765224                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 3636179                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              4783124                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1407347                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                79113                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                215630                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved               78857                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 5594                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts               8201368                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                16988                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                215630                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 3774532                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 581193                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       3715501                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1338240                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               496296                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts               7575516                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  144                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 44770                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               149873                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            5044245                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups              9199948                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups         9159980                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            39968                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              4092104                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                  952133                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            317142                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         23346                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1397635                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1414528                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores             877825                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           136527                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          116556                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   6675821                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             314231                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  6372058                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            25577                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1212482                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       668533                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        238569                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     10121394                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.629563                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.309947                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            7322432     72.35%     72.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1274873     12.60%     84.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             565463      5.59%     90.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             381432      3.77%     94.30% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             276297      2.73%     97.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             150290      1.48%     98.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6              93014      0.92%     99.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              53503      0.53%     99.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8               4090      0.04%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       10121394                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   2751      1.84%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.84% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 83898     56.09%     57.93% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                62938     42.07%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             2823      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              3945332     61.92%     61.96% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                9935      0.16%     62.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd               7188      0.11%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.23% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1411      0.02%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.25% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1374762     21.57%     83.83% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite             831632     13.05%     96.88% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            198975      3.12%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               6372058                       # Type of FU issued
system.cpu1.iq.rate                          0.579540                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     149587                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.023475                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          22982123                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes          8175044                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      6195827                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              58550                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             29266                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        28229                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               6488697                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  30125                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           71376                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       250758                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          518                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1865                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       114138                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          364                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        10621                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                215630                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 327250                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                19053                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            7270048                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           103390                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1414528                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts              877825                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            292634                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  6157                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 4769                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1865                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         31136                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        75519                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              106655                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              6299419                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1333225                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            72638                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       279996                       # number of nop insts executed
system.cpu1.iew.exec_refs                     2150860                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                  922163                       # Number of branches executed
system.cpu1.iew.exec_stores                    817635                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.572933                       # Inst execution rate
system.cpu1.iew.wb_sent                       6254968                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      6224056                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  2925555                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  4065237                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.566079                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.719652                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        1244518                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls          75662                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts            99560                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples      9905764                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.601159                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.526173                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0      7610675     76.83%     76.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1117297     11.28%     88.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       392466      3.96%     92.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       237967      2.40%     94.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       150669      1.52%     96.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        70627      0.71%     96.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        80896      0.82%     97.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        63718      0.64%     98.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       181449      1.83%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total      9905764                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts             5954935                       # Number of instructions committed
system.cpu1.commit.committedOps               5954935                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       1927457                       # Number of memory references committed
system.cpu1.commit.loads                      1163770                       # Number of loads committed
system.cpu1.commit.membars                      20047                       # Number of memory barriers committed
system.cpu1.commit.branches                    840841                       # Number of branches committed
system.cpu1.commit.fp_insts                     27263                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  5573216                       # Number of committed integer instructions.
system.cpu1.commit.function_calls               89926                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               181449                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    16822912                       # The number of ROB reads
system.cpu1.rob.rob_writes                   14613272                       # The number of ROB writes
system.cpu1.timesIdled                          86532                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         873637                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3796008743                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    5721018                       # Number of Instructions Simulated
system.cpu1.committedOps                      5721018                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total              5721018                       # Number of Instructions Simulated
system.cpu1.cpi                              1.921866                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.921866                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.520328                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.520328                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                 8196384                       # number of integer regfile reads
system.cpu1.int_regfile_writes                4468767                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    18086                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   17123                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 275818                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                138963                       # number of misc regfile writes
system.cpu1.icache.replacements                112877                       # number of replacements
system.cpu1.icache.tagsinuse               455.325853                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  961616                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                113389                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  8.480682                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1880828738000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   455.325853                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.889308                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.889308                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst       961616                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         961616                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst       961616                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          961616                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst       961616                       # number of overall hits
system.cpu1.icache.overall_hits::total         961616                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       120024                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       120024                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       120024                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        120024                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       120024                       # number of overall misses
system.cpu1.icache.overall_misses::total       120024                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1993076499                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   1993076499                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   1993076499                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   1993076499                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   1993076499                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   1993076499                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst      1081640                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1081640                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst      1081640                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1081640                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst      1081640                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1081640                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.110965                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.110965                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.110965                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.110965                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.110965                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.110965                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16605.649695                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 16605.649695                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16605.649695                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 16605.649695                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16605.649695                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 16605.649695                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       288999                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               50                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  5779.980000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         6586                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total         6586                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst         6586                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total         6586                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst         6586                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total         6586                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       113438                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       113438                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       113438                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       113438                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       113438                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       113438                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550619499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   1550619499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1550619499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   1550619499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1550619499                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   1550619499                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.104876                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.104876                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.104876                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.104876                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.104876                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.104876                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13669.312744                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13669.312744                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13669.312744                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13669.312744                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13669.312744                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13669.312744                       # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 66353                       # number of replacements
system.cpu1.dcache.tagsinuse               422.855509                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1693567                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 66865                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 25.328154                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1880297916000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   422.855509                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.825890                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.825890                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      1103263                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1103263                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data       554602                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        554602                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        16904                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        16904                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        15090                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        15090                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      1657865                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1657865                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      1657865                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1657865                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       120863                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       120863                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       188065                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       188065                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1871                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1871                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data          714                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          714                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       308928                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        308928                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       308928                       # number of overall misses
system.cpu1.dcache.overall_misses::total       308928                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2422870500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2422870500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7680920661                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   7680920661                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     31721000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     31721000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8263500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total      8263500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  10103791161                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  10103791161                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  10103791161                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  10103791161                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      1224126                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1224126                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data       742667                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       742667                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        18775                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        18775                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        15804                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        15804                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      1966793                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1966793                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      1966793                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1966793                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.098734                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.098734                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.253229                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.253229                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.099654                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.099654                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.045178                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.045178                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.157072                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.157072                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.157072                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.157072                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20046.420327                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 20046.420327                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40841.840114                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 40841.840114                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16954.035275                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16954.035275                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11573.529412                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11573.529412                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32705.974081                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 32705.974081                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32705.974081                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 32705.974081                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     54269989                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             6147                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8828.695136                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks        44452                       # number of writebacks
system.cpu1.dcache.writebacks::total            44452                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        76735                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        76735                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       160629                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       160629                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          625                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total          625                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       237364                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       237364                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       237364                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       237364                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        44128                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total        44128                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        27436                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        27436                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1246                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1246                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          712                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total          712                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data        71564                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total        71564                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data        71564                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total        71564                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    680335003                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total    680335003                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    908440847                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total    908440847                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     14899501                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     14899501                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      6048501                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      6048501                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1588775850                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   1588775850                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1588775850                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   1588775850                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     26654500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     26654500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    549434000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    549434000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    576088500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    576088500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036049                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036049                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036943                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036943                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066365                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066365                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.045052                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.045052                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.036386                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.036386                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.036386                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.036386                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15417.308806                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15417.308806                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33111.271577                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33111.271577                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11957.865971                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.865971                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  8495.085674                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  8495.085674                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22200.769242                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22200.769242                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22200.769242                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22200.769242                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6363                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    198040                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   71346     40.60%     40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    130      0.07%     40.67% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1927      1.10%     41.77% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      6      0.00%     41.77% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 102331     58.23%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              175740                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    69979     49.28%     49.28% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     130      0.09%     49.37% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1927      1.36%     50.72% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   69973     49.27%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               142015                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1862552849000     97.86%     97.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               68272000      0.00%     97.86% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              582924500      0.03%     97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                4256000      0.00%     97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            40116611000      2.11%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1903324912500                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.980840                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.683791                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total             0.808097                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         5      2.35%      2.35% # number of syscalls executed
system.cpu0.kern.syscall::3                        18      8.45%     10.80% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.41%     12.21% # number of syscalls executed
system.cpu0.kern.syscall::6                        28     13.15%     25.35% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.47%     25.82% # number of syscalls executed
system.cpu0.kern.syscall::15                        1      0.47%     26.29% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.23%     30.52% # number of syscalls executed
system.cpu0.kern.syscall::19                        5      2.35%     32.86% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.88%     34.74% # number of syscalls executed
system.cpu0.kern.syscall::23                        2      0.94%     35.68% # number of syscalls executed
system.cpu0.kern.syscall::24                        4      1.88%     37.56% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.29%     40.85% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.94%     41.78% # number of syscalls executed
system.cpu0.kern.syscall::45                       38     17.84%     59.62% # number of syscalls executed
system.cpu0.kern.syscall::47                        4      1.88%     61.50% # number of syscalls executed
system.cpu0.kern.syscall::48                        6      2.82%     64.32% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.23%     68.54% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.47%     69.01% # number of syscalls executed
system.cpu0.kern.syscall::59                        4      1.88%     70.89% # number of syscalls executed
system.cpu0.kern.syscall::71                       32     15.02%     85.92% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.41%     87.32% # number of syscalls executed
system.cpu0.kern.syscall::74                        9      4.23%     91.55% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.47%     92.02% # number of syscalls executed
system.cpu0.kern.syscall::90                        1      0.47%     92.49% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.29%     95.77% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.94%     96.71% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.94%     97.65% # number of syscalls executed
system.cpu0.kern.syscall::132                       2      0.94%     98.59% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.47%     99.06% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.94%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   213                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  103      0.06%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3753      2.03%      2.09% # number of callpals executed
system.cpu0.kern.callpal::tbi                      37      0.02%      2.11% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.12% # number of callpals executed
system.cpu0.kern.callpal::swpipl               169151     91.71%     93.83% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6371      3.45%     97.28% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.28% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     97.28% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     6      0.00%     97.29% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.29% # number of callpals executed
system.cpu0.kern.callpal::rti                    4525      2.45%     99.74% # number of callpals executed
system.cpu0.kern.callpal::callsys                 331      0.18%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     146      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                184440                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             6935                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1104                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1104
system.cpu0.kern.mode_good::user                 1104
system.cpu0.kern.mode_good::idle                    0
system.cpu0.kern.mode_switch_good::kernel     0.159193                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     0.274661                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1900909928000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1870692000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3754                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2268                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     39512                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   10294     33.41%     33.41% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1926      6.25%     39.66% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    103      0.33%     40.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  18486     60.00%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               30809                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    10284     45.72%     45.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1926      8.56%     54.28% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     103      0.46%     54.74% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   10181     45.26%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                22494                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1876458068500     98.58%     98.58% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              533952000      0.03%     98.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               54130500      0.00%     98.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            26455983000      1.39%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1903502134000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.999029                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.550741                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total             0.730111                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2                         3      2.65%      2.65% # number of syscalls executed
system.cpu1.kern.syscall::3                        12     10.62%     13.27% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.88%     14.16% # number of syscalls executed
system.cpu1.kern.syscall::6                        14     12.39%     26.55% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      5.31%     31.86% # number of syscalls executed
system.cpu1.kern.syscall::19                        5      4.42%     36.28% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.77%     38.05% # number of syscalls executed
system.cpu1.kern.syscall::23                        2      1.77%     39.82% # number of syscalls executed
system.cpu1.kern.syscall::24                        2      1.77%     41.59% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.54%     45.13% # number of syscalls executed
system.cpu1.kern.syscall::45                       16     14.16%     59.29% # number of syscalls executed
system.cpu1.kern.syscall::47                        2      1.77%     61.06% # number of syscalls executed
system.cpu1.kern.syscall::48                        4      3.54%     64.60% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.88%     65.49% # number of syscalls executed
system.cpu1.kern.syscall::59                        3      2.65%     68.14% # number of syscalls executed
system.cpu1.kern.syscall::71                       22     19.47%     87.61% # number of syscalls executed
system.cpu1.kern.syscall::74                        7      6.19%     93.81% # number of syscalls executed
system.cpu1.kern.syscall::90                        2      1.77%     95.58% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.77%     97.35% # number of syscalls executed
system.cpu1.kern.syscall::132                       2      1.77%     99.12% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.88%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   113                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  478      1.50%      1.53% # number of callpals executed
system.cpu1.kern.callpal::tbi                      16      0.05%      1.58% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.60% # number of callpals executed
system.cpu1.kern.callpal::swpipl                26108     81.82%     83.42% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2389      7.49%     90.91% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.91% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     90.92% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     3      0.01%     90.93% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     90.94% # number of callpals executed
system.cpu1.kern.callpal::rti                    2671      8.37%     99.31% # number of callpals executed
system.cpu1.kern.callpal::callsys                 184      0.58%     99.89% # number of callpals executed
system.cpu1.kern.callpal::imb                      34      0.11%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 31908                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel             1099                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                634                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2051                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                660
system.cpu1.kern.mode_good::user                  634
system.cpu1.kern.mode_good::idle                   26
system.cpu1.kern.mode_switch_good::kernel     0.600546                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.012677                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     0.348837                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        2247097500      0.12%      0.12% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           912883500      0.05%      0.17% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1900342145000     99.83%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     479                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------