stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.899401 # Number of seconds simulated 4sim_ticks 1899401490000 # Number of ticks simulated 5final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 124517 # Simulator instruction rate (inst/s) 8host_op_rate 124517 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4182952627 # Simulator tick rate (ticks/s) 10host_mem_usage 300876 # Number of bytes of host memory used 11host_seconds 454.08 # Real time elapsed on the host 12sim_insts 56540749 # Number of instructions simulated 13sim_ops 56540749 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 865216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 25431680 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650496 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 268160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 1206144 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30421696 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 865216 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 268160 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1133376 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 10508736 # Number of bytes written to this memory 24system.physmem.bytes_written::total 10508736 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13519 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 397370 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41414 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 4190 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 18846 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 475339 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 164199 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 164199 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 455520 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 13389312 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1395437 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 141181 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 635013 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 16016464 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 455520 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 141181 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 596702 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 5532657 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 5532657 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 5532657 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 455520 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 13389312 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1395437 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 141181 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 635013 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 21549121 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 397771 # number of replacements 52system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use 53system.l2c.total_refs 2469954 # Total number of references to valid blocks. 54system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. 55system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 117817 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1870693 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 806294 # number of Writeback hits 74system.l2c.Writeback_hits::total 806294 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 126 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 295 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 154146 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 17714 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 171860 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 910711 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 822730 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 173581 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 135531 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2042553 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 910711 # number of overall hits 90system.l2c.overall_hits::cpu0.data 822730 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 173581 # number of overall hits 92system.l2c.overall_hits::cpu1.data 135531 # number of overall hits 93system.l2c.overall_hits::total 2042553 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13521 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 288493 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 4207 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 3184 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 309405 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2939 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 698 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 3637 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 248 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 292 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 540 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 109252 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 15963 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 125215 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13521 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 397745 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 4207 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 19147 # number of demand (read+write) misses 112system.l2c.demand_misses::total 434620 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13521 # number of overall misses 114system.l2c.overall_misses::cpu0.data 397745 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 4207 # number of overall misses 116system.l2c.overall_misses::cpu1.data 19147 # number of overall misses 117system.l2c.overall_misses::total 434620 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 707237500 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 15013277500 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 220139500 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 161535500 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 16102190000 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2036500 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 2558500 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 4595000 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4304500 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1626000 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 5930500 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 5731732500 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 836680000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6568412500 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 707237500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20745010000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 220139500 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 998215500 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 22670602500 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 707237500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20745010000 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 220139500 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 998215500 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 22670602500 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 924232 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 957077 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 177788 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 121001 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2180098 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 806294 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 806294 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 824 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 3932 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 286 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 324 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 610 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 263398 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 33677 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 297075 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 924232 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1220475 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 177788 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 154678 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2477173 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 924232 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1220475 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 177788 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 154678 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2477173 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.014629 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.301431 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.023663 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.026314 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.141923 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945624 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847087 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.924975 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.867133 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901235 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.885246 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.414779 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.474003 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.421493 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.014629 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.325894 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.023663 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.123786 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.175450 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.014629 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.325894 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.023663 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.123786 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.175450 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52306.597145 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52040.352799 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52326.955075 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 50733.511307 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52042.436289 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 692.922763 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3665.472779 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 1263.403904 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17356.854839 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5568.493151 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 10982.407407 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52463.410281 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52413.706697 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52457.073833 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52161.894298 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52161.894298 # average overall miss latency 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed 224system.l2c.writebacks::writebacks 122679 # number of writebacks 225system.l2c.writebacks::total 122679 # number of writebacks 226system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 228system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 229system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 230system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 231system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 232system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 233system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 234system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 235system.l2c.ReadReq_mshr_misses::cpu0.inst 13520 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::cpu0.data 288493 # number of ReadReq MSHR misses 237system.l2c.ReadReq_mshr_misses::cpu1.inst 4190 # number of ReadReq MSHR misses 238system.l2c.ReadReq_mshr_misses::cpu1.data 3184 # number of ReadReq MSHR misses 239system.l2c.ReadReq_mshr_misses::total 309387 # number of ReadReq MSHR misses 240system.l2c.UpgradeReq_mshr_misses::cpu0.data 2939 # number of UpgradeReq MSHR misses 241system.l2c.UpgradeReq_mshr_misses::cpu1.data 698 # number of UpgradeReq MSHR misses 242system.l2c.UpgradeReq_mshr_misses::total 3637 # number of UpgradeReq MSHR misses 243system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 248 # number of SCUpgradeReq MSHR misses 244system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 292 # number of SCUpgradeReq MSHR misses 245system.l2c.SCUpgradeReq_mshr_misses::total 540 # number of SCUpgradeReq MSHR misses 246system.l2c.ReadExReq_mshr_misses::cpu0.data 109252 # number of ReadExReq MSHR misses 247system.l2c.ReadExReq_mshr_misses::cpu1.data 15963 # number of ReadExReq MSHR misses 248system.l2c.ReadExReq_mshr_misses::total 125215 # number of ReadExReq MSHR misses 249system.l2c.demand_mshr_misses::cpu0.inst 13520 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::cpu0.data 397745 # number of demand (read+write) MSHR misses 251system.l2c.demand_mshr_misses::cpu1.inst 4190 # number of demand (read+write) MSHR misses 252system.l2c.demand_mshr_misses::cpu1.data 19147 # number of demand (read+write) MSHR misses 253system.l2c.demand_mshr_misses::total 434602 # number of demand (read+write) MSHR misses 254system.l2c.overall_mshr_misses::cpu0.inst 13520 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::cpu0.data 397745 # number of overall MSHR misses 256system.l2c.overall_mshr_misses::cpu1.inst 4190 # number of overall MSHR misses 257system.l2c.overall_mshr_misses::cpu1.data 19147 # number of overall MSHR misses 258system.l2c.overall_mshr_misses::total 434602 # number of overall MSHR misses 259system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 541689500 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11548328000 # number of ReadReq MSHR miss cycles 261system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 167980000 # number of ReadReq MSHR miss cycles 262system.l2c.ReadReq_mshr_miss_latency::cpu1.data 125604000 # number of ReadReq MSHR miss cycles 263system.l2c.ReadReq_mshr_miss_latency::total 12383601500 # number of ReadReq MSHR miss cycles 264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117566000 # number of UpgradeReq MSHR miss cycles 265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27923000 # number of UpgradeReq MSHR miss cycles 266system.l2c.UpgradeReq_mshr_miss_latency::total 145489000 # number of UpgradeReq MSHR miss cycles 267system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9921000 # number of SCUpgradeReq MSHR miss cycles 268system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11680500 # number of SCUpgradeReq MSHR miss cycles 269system.l2c.SCUpgradeReq_mshr_miss_latency::total 21601500 # number of SCUpgradeReq MSHR miss cycles 270system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4402693000 # number of ReadExReq MSHR miss cycles 271system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 641940500 # number of ReadExReq MSHR miss cycles 272system.l2c.ReadExReq_mshr_miss_latency::total 5044633500 # number of ReadExReq MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu0.inst 541689500 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::cpu0.data 15951021000 # number of demand (read+write) MSHR miss cycles 275system.l2c.demand_mshr_miss_latency::cpu1.inst 167980000 # number of demand (read+write) MSHR miss cycles 276system.l2c.demand_mshr_miss_latency::cpu1.data 767544500 # number of demand (read+write) MSHR miss cycles 277system.l2c.demand_mshr_miss_latency::total 17428235000 # number of demand (read+write) MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu0.inst 541689500 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::cpu0.data 15951021000 # number of overall MSHR miss cycles 280system.l2c.overall_mshr_miss_latency::cpu1.inst 167980000 # number of overall MSHR miss cycles 281system.l2c.overall_mshr_miss_latency::cpu1.data 767544500 # number of overall MSHR miss cycles 282system.l2c.overall_mshr_miss_latency::total 17428235000 # number of overall MSHR miss cycles 283system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 568678500 # number of ReadReq MSHR uncacheable cycles 284system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269407000 # number of ReadReq MSHR uncacheable cycles 285system.l2c.ReadReq_mshr_uncacheable_latency::total 838085500 # number of ReadReq MSHR uncacheable cycles 286system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 961824498 # number of WriteReq MSHR uncacheable cycles 287system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 507055500 # number of WriteReq MSHR uncacheable cycles 288system.l2c.WriteReq_mshr_uncacheable_latency::total 1468879998 # number of WriteReq MSHR uncacheable cycles 289system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1530502998 # number of overall MSHR uncacheable cycles 290system.l2c.overall_mshr_uncacheable_latency::cpu1.data 776462500 # number of overall MSHR uncacheable cycles 291system.l2c.overall_mshr_uncacheable_latency::total 2306965498 # number of overall MSHR uncacheable cycles 292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.301431 # mshr miss rate for ReadReq accesses 294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for ReadReq accesses 295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026314 # mshr miss rate for ReadReq accesses 296system.l2c.ReadReq_mshr_miss_rate::total 0.141914 # mshr miss rate for ReadReq accesses 297system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.945624 # mshr miss rate for UpgradeReq accesses 298system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847087 # mshr miss rate for UpgradeReq accesses 299system.l2c.UpgradeReq_mshr_miss_rate::total 0.924975 # mshr miss rate for UpgradeReq accesses 300system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.867133 # mshr miss rate for SCUpgradeReq accesses 301system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.901235 # mshr miss rate for SCUpgradeReq accesses 302system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.885246 # mshr miss rate for SCUpgradeReq accesses 303system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.414779 # mshr miss rate for ReadExReq accesses 304system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.474003 # mshr miss rate for ReadExReq accesses 305system.l2c.ReadExReq_mshr_miss_rate::total 0.421493 # mshr miss rate for ReadExReq accesses 306system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for demand accesses 308system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for demand accesses 309system.l2c.demand_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for demand accesses 310system.l2c.demand_mshr_miss_rate::total 0.175443 # mshr miss rate for demand accesses 311system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014628 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::cpu0.data 0.325894 # mshr miss rate for overall accesses 313system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023567 # mshr miss rate for overall accesses 314system.l2c.overall_mshr_miss_rate::cpu1.data 0.123786 # mshr miss rate for overall accesses 315system.l2c.overall_mshr_miss_rate::total 0.175443 # mshr miss rate for overall accesses 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.837812 # average ReadReq mshr miss latency 318system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average ReadReq mshr miss latency 319system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39448.492462 # average ReadReq mshr miss latency 320system.l2c.ReadReq_avg_mshr_miss_latency::total 40026.250295 # average ReadReq mshr miss latency 321system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.041511 # average UpgradeReq mshr miss latency 322system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40004.297994 # average UpgradeReq mshr miss latency 323system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40002.474567 # average UpgradeReq mshr miss latency 324system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40004.032258 # average SCUpgradeReq mshr miss latency 325system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.712329 # average SCUpgradeReq mshr miss latency 326system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40002.777778 # average SCUpgradeReq mshr miss latency 327system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40298.511698 # average ReadExReq mshr miss latency 328system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40214.276765 # average ReadExReq mshr miss latency 329system.l2c.ReadExReq_avg_mshr_miss_latency::total 40287.773030 # average ReadExReq mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency 332system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency 333system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency 334system.l2c.demand_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.791420 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.636752 # average overall mshr miss latency 337system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40090.692124 # average overall mshr miss latency 338system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40086.932679 # average overall mshr miss latency 339system.l2c.overall_avg_mshr_miss_latency::total 40101.598704 # average overall mshr miss latency 340system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 341system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 342system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 343system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 344system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 345system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 346system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 347system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 348system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 349system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 350system.iocache.replacements 41698 # number of replacements 351system.iocache.tagsinuse 0.205020 # Cycle average of tags in use 352system.iocache.total_refs 0 # Total number of references to valid blocks. 353system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. 354system.iocache.avg_refs 0 # Average number of references to valid blocks. 355system.iocache.warmup_cycle 1708344834000 # Cycle when the warmup percentage was hit. 356system.iocache.occ_blocks::tsunami.ide 0.205020 # Average occupied blocks per requestor 357system.iocache.occ_percent::tsunami.ide 0.012814 # Average percentage of cache occupancy 358system.iocache.occ_percent::total 0.012814 # Average percentage of cache occupancy 359system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 178 # number of ReadReq misses 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 363system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41730 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 366system.iocache.overall_misses::total 41730 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 20513998 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 20513998 # number of ReadReq miss cycles 369system.iocache.WriteReq_miss_latency::tsunami.ide 5720296806 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 5720296806 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 5740810804 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 5740810804 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 5740810804 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 5740810804 # number of overall miss cycles 375system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 379system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.179775 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 115247.179775 # average ReadReq miss latency 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 137665.980121 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 137570.352360 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 137570.352360 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked 403system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41520 # number of writebacks 408system.iocache.writebacks::total 41520 # number of writebacks 409system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 413system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11257998 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 11257998 # number of ReadReq MSHR miss cycles 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559437998 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 3559437998 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 3570695996 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 3570695996 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 3570695996 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 3570695996 # number of overall MSHR miss cycles 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.179775 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.179775 # average ReadReq mshr miss latency 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.254476 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 85662.254476 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.642607 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 85566.642607 # average overall mshr miss latency 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu0.dtb.fetch_hits 0 # ITB hits 455system.cpu0.dtb.fetch_misses 0 # ITB misses 456system.cpu0.dtb.fetch_acv 0 # ITB acv 457system.cpu0.dtb.fetch_accesses 0 # ITB accesses 458system.cpu0.dtb.read_hits 8814586 # DTB read hits 459system.cpu0.dtb.read_misses 32972 # DTB read misses 460system.cpu0.dtb.read_acv 518 # DTB read access violations 461system.cpu0.dtb.read_accesses 619797 # DTB read accesses 462system.cpu0.dtb.write_hits 5858085 # DTB write hits 463system.cpu0.dtb.write_misses 6892 # DTB write misses 464system.cpu0.dtb.write_acv 315 # DTB write access violations 465system.cpu0.dtb.write_accesses 207416 # DTB write accesses 466system.cpu0.dtb.data_hits 14672671 # DTB hits 467system.cpu0.dtb.data_misses 39864 # DTB misses 468system.cpu0.dtb.data_acv 833 # DTB access violations 469system.cpu0.dtb.data_accesses 827213 # DTB accesses 470system.cpu0.itb.fetch_hits 1034325 # ITB hits 471system.cpu0.itb.fetch_misses 27665 # ITB misses 472system.cpu0.itb.fetch_acv 1025 # ITB acv 473system.cpu0.itb.fetch_accesses 1061990 # ITB accesses 474system.cpu0.itb.read_hits 0 # DTB read hits 475system.cpu0.itb.read_misses 0 # DTB read misses 476system.cpu0.itb.read_acv 0 # DTB read access violations 477system.cpu0.itb.read_accesses 0 # DTB read accesses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.write_acv 0 # DTB write access violations 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.data_hits 0 # DTB hits 483system.cpu0.itb.data_misses 0 # DTB misses 484system.cpu0.itb.data_acv 0 # DTB access violations 485system.cpu0.itb.data_accesses 0 # DTB accesses 486system.cpu0.numCycles 105407779 # number of cpu cycles simulated 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 489system.cpu0.BPredUnit.lookups 12543533 # Number of BP lookups 490system.cpu0.BPredUnit.condPredicted 10518625 # Number of conditional branches predicted 491system.cpu0.BPredUnit.condIncorrect 389841 # Number of conditional branches incorrect 492system.cpu0.BPredUnit.BTBLookups 9001573 # Number of BTB lookups 493system.cpu0.BPredUnit.BTBHits 5310644 # Number of BTB hits 494system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 495system.cpu0.BPredUnit.usedRAS 819125 # Number of times the RAS was used to get a target. 496system.cpu0.BPredUnit.RASInCorrect 58295 # Number of incorrect RAS predictions. 497system.cpu0.fetch.icacheStallCycles 26579965 # Number of cycles fetch is stalled on an Icache miss 498system.cpu0.fetch.Insts 63634622 # Number of instructions fetch has processed 499system.cpu0.fetch.Branches 12543533 # Number of branches that fetch encountered 500system.cpu0.fetch.predictedBranches 6129769 # Number of branches that fetch has predicted taken 501system.cpu0.fetch.Cycles 12006508 # Number of cycles fetch has run and was not squashing or blocked 502system.cpu0.fetch.SquashCycles 1822886 # Number of cycles fetch has spent squashing 503system.cpu0.fetch.BlockedCycles 32559683 # Number of cycles fetch has spent blocked 504system.cpu0.fetch.MiscStallCycles 31957 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 505system.cpu0.fetch.PendingTrapStallCycles 177706 # Number of stall cycles due to pending traps 506system.cpu0.fetch.PendingQuiesceStallCycles 213013 # Number of stall cycles due to pending quiesce instructions 507system.cpu0.fetch.IcacheWaitRetryStallCycles 154 # Number of stall cycles due to full MSHR 508system.cpu0.fetch.CacheLines 7876403 # Number of cache lines fetched 509system.cpu0.fetch.IcacheSquashes 267953 # Number of outstanding Icache misses that were squashed 510system.cpu0.fetch.rateDist::samples 72741022 # Number of instructions fetched each cycle (Total) 511system.cpu0.fetch.rateDist::mean 0.874811 # Number of instructions fetched each cycle (Total) 512system.cpu0.fetch.rateDist::stdev 2.212644 # Number of instructions fetched each cycle (Total) 513system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 514system.cpu0.fetch.rateDist::0 60734514 83.49% 83.49% # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::1 798536 1.10% 84.59% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::2 1573590 2.16% 86.76% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::3 701435 0.96% 87.72% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::4 2536566 3.49% 91.21% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::5 541598 0.74% 91.95% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::6 587478 0.81% 92.76% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::7 932961 1.28% 94.04% # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::8 4334344 5.96% 100.00% # Number of instructions fetched each cycle (Total) 523system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 526system.cpu0.fetch.rateDist::total 72741022 # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.branchRate 0.119000 # Number of branch fetches per cycle 528system.cpu0.fetch.rate 0.603699 # Number of inst fetches per cycle 529system.cpu0.decode.IdleCycles 27434990 # Number of cycles decode is idle 530system.cpu0.decode.BlockedCycles 32338165 # Number of cycles decode is blocked 531system.cpu0.decode.RunCycles 10959738 # Number of cycles decode is running 532system.cpu0.decode.UnblockCycles 873036 # Number of cycles decode is unblocking 533system.cpu0.decode.SquashCycles 1135092 # Number of cycles decode is squashing 534system.cpu0.decode.BranchResolved 524168 # Number of times decode resolved a branch 535system.cpu0.decode.BranchMispred 38246 # Number of times decode detected a branch misprediction 536system.cpu0.decode.DecodedInsts 62454506 # Number of instructions handled by decode 537system.cpu0.decode.SquashedInsts 104596 # Number of squashed instructions handled by decode 538system.cpu0.rename.SquashCycles 1135092 # Number of cycles rename is squashing 539system.cpu0.rename.IdleCycles 28444580 # Number of cycles rename is idle 540system.cpu0.rename.BlockCycles 11348794 # Number of cycles rename is blocking 541system.cpu0.rename.serializeStallCycles 17719135 # count of cycles rename stalled for serializing inst 542system.cpu0.rename.RunCycles 10252710 # Number of cycles rename is running 543system.cpu0.rename.UnblockCycles 3840709 # Number of cycles rename is unblocking 544system.cpu0.rename.RenamedInsts 59087115 # Number of instructions processed by rename 545system.cpu0.rename.ROBFullEvents 6759 # Number of times rename has blocked due to ROB full 546system.cpu0.rename.IQFullEvents 385226 # Number of times rename has blocked due to IQ full 547system.cpu0.rename.LSQFullEvents 1425299 # Number of times rename has blocked due to LSQ full 548system.cpu0.rename.RenamedOperands 39461950 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 71535536 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 71092330 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 443206 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 34168968 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 5292982 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 1501174 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 229517 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 10778320 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 9311808 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 6175617 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 1139122 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 734045 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 52101492 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 1888432 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 50847383 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 113537 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 6290735 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 3199038 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 1282649 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 72741022 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.699019 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.352112 # Number of insts issued each cycle 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 572system.cpu0.iq.issued_per_cycle::0 50396766 69.28% 69.28% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 9972815 13.71% 82.99% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 4663131 6.41% 89.40% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 3055348 4.20% 93.60% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 2346789 3.23% 96.83% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 1299072 1.79% 98.62% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 640768 0.88% 99.50% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 275526 0.38% 99.88% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 90807 0.12% 100.00% # Number of insts issued each cycle 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 584system.cpu0.iq.issued_per_cycle::total 72741022 # Number of insts issued each cycle 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 586system.cpu0.iq.fu_full::IntAlu 76308 11.21% 11.21% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 321562 47.25% 58.46% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 282678 41.54% 100.00% # attempts to use FU when none available 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 619system.cpu0.iq.FU_type_0::No_OpClass 3304 0.01% 0.01% # Type of FU issued 620system.cpu0.iq.FU_type_0::IntAlu 34794736 68.43% 68.44% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 54066 0.11% 68.54% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.54% # Type of FU issued 623system.cpu0.iq.FU_type_0::FloatAdd 15533 0.03% 68.57% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 1651 0.00% 68.58% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.58% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.58% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.58% # Type of FU issued 631system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.58% # Type of FU issued 632system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.58% # Type of FU issued 633system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.58% # Type of FU issued 634system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.58% # Type of FU issued 635system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.58% # Type of FU issued 636system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.58% # Type of FU issued 637system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.58% # Type of FU issued 638system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.58% # Type of FU issued 639system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.58% # Type of FU issued 640system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.58% # Type of FU issued 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.58% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.58% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.58% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.58% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.58% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.58% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.58% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.58% # Type of FU issued 649system.cpu0.iq.FU_type_0::MemRead 9216611 18.13% 86.70% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 5928101 11.66% 98.36% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 833381 1.64% 100.00% # Type of FU issued 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 653system.cpu0.iq.FU_type_0::total 50847383 # Type of FU issued 654system.cpu0.iq.rate 0.482387 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 680548 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.013384 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 174615866 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 59997059 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 49635166 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 614007 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 294188 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 289709 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 51201778 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 322849 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 529914 # Number of loads that had data forwarded from stores 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 667system.cpu0.iew.lsq.thread0.squashedLoads 1228237 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 2717 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 10847 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 496354 # Number of stores squashed 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 673system.cpu0.iew.lsq.thread0.rescheduledLoads 15126 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 162620 # Number of times an access to memory failed due to the cache being blocked 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 676system.cpu0.iew.iewSquashCycles 1135092 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 7799066 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 574299 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 57208008 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 766721 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 9311808 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 6175617 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 1662895 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 472481 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 9295 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 10847 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 216142 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 364728 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 580870 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 50321201 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 8875076 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 526182 # Number of squashed instructions skipped in execute 693system.cpu0.iew.exec_swp 0 # number of swp insts executed 694system.cpu0.iew.exec_nop 3218084 # number of nop insts executed 695system.cpu0.iew.exec_refs 14754207 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 7980527 # Number of branches executed 697system.cpu0.iew.exec_stores 5879131 # Number of stores executed 698system.cpu0.iew.exec_rate 0.477396 # Inst execution rate 699system.cpu0.iew.wb_sent 50024045 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 49924875 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 24623982 # num instructions producing a value 702system.cpu0.iew.wb_consumers 33198875 # num instructions consuming a value 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 704system.cpu0.iew.wb_rate 0.473636 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.741711 # average fanout of values written-back 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 707system.cpu0.commit.commitCommittedInsts 50284711 # The number of committed instructions 708system.cpu0.commit.commitCommittedOps 50284711 # The number of committed instructions 709system.cpu0.commit.commitSquashedInsts 6832336 # The number of squashed insts skipped by commit 710system.cpu0.commit.commitNonSpecStalls 605783 # The number of times commit has been forced to stall to communicate backwards 711system.cpu0.commit.branchMispredicts 542146 # The number of times a branch was mispredicted 712system.cpu0.commit.committed_per_cycle::samples 71605930 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::mean 0.702242 # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::stdev 1.623363 # Number of insts commited each cycle 715system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 716system.cpu0.commit.committed_per_cycle::0 52797293 73.73% 73.73% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::1 7885539 11.01% 84.75% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::2 4166098 5.82% 90.56% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::3 2329305 3.25% 93.82% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::4 1331723 1.86% 95.68% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::5 575927 0.80% 96.48% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::6 415417 0.58% 97.06% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::7 456992 0.64% 97.70% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::8 1647636 2.30% 100.00% # Number of insts commited each cycle 725system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 727system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 728system.cpu0.commit.committed_per_cycle::total 71605930 # Number of insts commited each cycle 729system.cpu0.commit.committedInsts 50284711 # Number of instructions committed 730system.cpu0.commit.committedOps 50284711 # Number of ops (including micro ops) committed 731system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 732system.cpu0.commit.refs 13762834 # Number of memory references committed 733system.cpu0.commit.loads 8083571 # Number of loads committed 734system.cpu0.commit.membars 205088 # Number of memory barriers committed 735system.cpu0.commit.branches 7564309 # Number of branches committed 736system.cpu0.commit.fp_insts 287246 # Number of committed floating point instructions. 737system.cpu0.commit.int_insts 46527621 # Number of committed integer instructions. 738system.cpu0.commit.function_calls 644133 # Number of function calls committed. 739system.cpu0.commit.bw_lim_events 1647636 # number cycles where commit BW limit reached 740system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 741system.cpu0.rob.rob_reads 126892294 # The number of ROB reads 742system.cpu0.rob.rob_writes 115369853 # The number of ROB writes 743system.cpu0.timesIdled 1161435 # Number of times that the entire CPU went into an idle state and unscheduled itself 744system.cpu0.idleCycles 32666757 # Total number of cycles that the CPU has spent unscheduled due to idling 745system.cpu0.quiesceCycles 3693390286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 746system.cpu0.committedInsts 47376653 # Number of Instructions Simulated 747system.cpu0.committedOps 47376653 # Number of Ops (including micro ops) Simulated 748system.cpu0.committedInsts_total 47376653 # Number of Instructions Simulated 749system.cpu0.cpi 2.224889 # CPI: Cycles Per Instruction 750system.cpu0.cpi_total 2.224889 # CPI: Total CPI of All Threads 751system.cpu0.ipc 0.449461 # IPC: Instructions Per Cycle 752system.cpu0.ipc_total 0.449461 # IPC: Total IPC of All Threads 753system.cpu0.int_regfile_reads 65983871 # number of integer regfile reads 754system.cpu0.int_regfile_writes 36054560 # number of integer regfile writes 755system.cpu0.fp_regfile_reads 141566 # number of floating regfile reads 756system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes 757system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads 758system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes 759system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 760system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 761system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 762system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 763system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 764system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 765system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 766system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 767system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 768system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 769system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 770system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 771system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 772system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 773system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 774system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 775system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 776system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 777system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 778system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 779system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 780system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 781system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 782system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 783system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 784system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 785system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 786system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 787system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 788system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 789system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 790system.cpu0.icache.replacements 923652 # number of replacements 791system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use 792system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. 793system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. 794system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. 795system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. 796system.cpu0.icache.occ_blocks::cpu0.inst 510.006511 # Average occupied blocks per requestor 797system.cpu0.icache.occ_percent::cpu0.inst 0.996106 # Average percentage of cache occupancy 798system.cpu0.icache.occ_percent::total 0.996106 # Average percentage of cache occupancy 799system.cpu0.icache.ReadReq_hits::cpu0.inst 6902434 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 6902434 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 6902434 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 6902434 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 6902434 # number of overall hits 804system.cpu0.icache.overall_hits::total 6902434 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 973969 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 973969 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 973969 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 973969 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 973969 # number of overall misses 810system.cpu0.icache.overall_misses::total 973969 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14544794497 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 14544794497 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 14544794497 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 14544794497 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 14544794497 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 14544794497 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 7876403 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 7876403 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 7876403 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 7876403 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 7876403 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 7876403 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123657 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.123657 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123657 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.123657 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123657 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.123657 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 14933.529195 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 14933.529195 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 14933.529195 # average overall miss latency 835system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed 843system.cpu0.icache.writebacks::writebacks 196 # number of writebacks 844system.cpu0.icache.writebacks::total 196 # number of writebacks 845system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits 846system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits 847system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits 848system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits 849system.cpu0.icache.overall_mshr_hits::cpu0.inst 49660 # number of overall MSHR hits 850system.cpu0.icache.overall_mshr_hits::total 49660 # number of overall MSHR hits 851system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 924309 # number of ReadReq MSHR misses 852system.cpu0.icache.ReadReq_mshr_misses::total 924309 # number of ReadReq MSHR misses 853system.cpu0.icache.demand_mshr_misses::cpu0.inst 924309 # number of demand (read+write) MSHR misses 854system.cpu0.icache.demand_mshr_misses::total 924309 # number of demand (read+write) MSHR misses 855system.cpu0.icache.overall_mshr_misses::cpu0.inst 924309 # number of overall MSHR misses 856system.cpu0.icache.overall_mshr_misses::total 924309 # number of overall MSHR misses 857system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11020233999 # number of ReadReq MSHR miss cycles 858system.cpu0.icache.ReadReq_mshr_miss_latency::total 11020233999 # number of ReadReq MSHR miss cycles 859system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11020233999 # number of demand (read+write) MSHR miss cycles 860system.cpu0.icache.demand_mshr_miss_latency::total 11020233999 # number of demand (read+write) MSHR miss cycles 861system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11020233999 # number of overall MSHR miss cycles 862system.cpu0.icache.overall_mshr_miss_latency::total 11020233999 # number of overall MSHR miss cycles 863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.117352 # mshr miss rate for ReadReq accesses 865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for demand accesses 866system.cpu0.icache.demand_mshr_miss_rate::total 0.117352 # mshr miss rate for demand accesses 867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.117352 # mshr miss rate for overall accesses 868system.cpu0.icache.overall_mshr_miss_rate::total 0.117352 # mshr miss rate for overall accesses 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average ReadReq mshr miss latency 870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11922.673044 # average ReadReq mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency 872system.cpu0.icache.demand_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11922.673044 # average overall mshr miss latency 874system.cpu0.icache.overall_avg_mshr_miss_latency::total 11922.673044 # average overall mshr miss latency 875system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 876system.cpu0.dcache.replacements 1225027 # number of replacements 877system.cpu0.dcache.tagsinuse 491.225534 # Cycle average of tags in use 878system.cpu0.dcache.total_refs 10607012 # Total number of references to valid blocks. 879system.cpu0.dcache.sampled_refs 1225539 # Sample count of references to valid blocks. 880system.cpu0.dcache.avg_refs 8.654977 # Average number of references to valid blocks. 881system.cpu0.dcache.warmup_cycle 19420000 # Cycle when the warmup percentage was hit. 882system.cpu0.dcache.occ_blocks::cpu0.data 491.225534 # Average occupied blocks per requestor 883system.cpu0.dcache.occ_percent::cpu0.data 0.959425 # Average percentage of cache occupancy 884system.cpu0.dcache.occ_percent::total 0.959425 # Average percentage of cache occupancy 885system.cpu0.dcache.ReadReq_hits::cpu0.data 6460129 # number of ReadReq hits 886system.cpu0.dcache.ReadReq_hits::total 6460129 # number of ReadReq hits 887system.cpu0.dcache.WriteReq_hits::cpu0.data 3759204 # number of WriteReq hits 888system.cpu0.dcache.WriteReq_hits::total 3759204 # number of WriteReq hits 889system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177511 # number of LoadLockedReq hits 890system.cpu0.dcache.LoadLockedReq_hits::total 177511 # number of LoadLockedReq hits 891system.cpu0.dcache.StoreCondReq_hits::cpu0.data 200041 # number of StoreCondReq hits 892system.cpu0.dcache.StoreCondReq_hits::total 200041 # number of StoreCondReq hits 893system.cpu0.dcache.demand_hits::cpu0.data 10219333 # number of demand (read+write) hits 894system.cpu0.dcache.demand_hits::total 10219333 # number of demand (read+write) hits 895system.cpu0.dcache.overall_hits::cpu0.data 10219333 # number of overall hits 896system.cpu0.dcache.overall_hits::total 10219333 # number of overall hits 897system.cpu0.dcache.ReadReq_misses::cpu0.data 1549115 # number of ReadReq misses 898system.cpu0.dcache.ReadReq_misses::total 1549115 # number of ReadReq misses 899system.cpu0.dcache.WriteReq_misses::cpu0.data 1704606 # number of WriteReq misses 900system.cpu0.dcache.WriteReq_misses::total 1704606 # number of WriteReq misses 901system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20750 # number of LoadLockedReq misses 902system.cpu0.dcache.LoadLockedReq_misses::total 20750 # number of LoadLockedReq misses 903system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2030 # number of StoreCondReq misses 904system.cpu0.dcache.StoreCondReq_misses::total 2030 # number of StoreCondReq misses 905system.cpu0.dcache.demand_misses::cpu0.data 3253721 # number of demand (read+write) misses 906system.cpu0.dcache.demand_misses::total 3253721 # number of demand (read+write) misses 907system.cpu0.dcache.overall_misses::cpu0.data 3253721 # number of overall misses 908system.cpu0.dcache.overall_misses::total 3253721 # number of overall misses 909system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34776889000 # number of ReadReq miss cycles 910system.cpu0.dcache.ReadReq_miss_latency::total 34776889000 # number of ReadReq miss cycles 911system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52688012248 # number of WriteReq miss cycles 912system.cpu0.dcache.WriteReq_miss_latency::total 52688012248 # number of WriteReq miss cycles 913system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301583000 # number of LoadLockedReq miss cycles 914system.cpu0.dcache.LoadLockedReq_miss_latency::total 301583000 # number of LoadLockedReq miss cycles 915system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 24841500 # number of StoreCondReq miss cycles 916system.cpu0.dcache.StoreCondReq_miss_latency::total 24841500 # number of StoreCondReq miss cycles 917system.cpu0.dcache.demand_miss_latency::cpu0.data 87464901248 # number of demand (read+write) miss cycles 918system.cpu0.dcache.demand_miss_latency::total 87464901248 # number of demand (read+write) miss cycles 919system.cpu0.dcache.overall_miss_latency::cpu0.data 87464901248 # number of overall miss cycles 920system.cpu0.dcache.overall_miss_latency::total 87464901248 # number of overall miss cycles 921system.cpu0.dcache.ReadReq_accesses::cpu0.data 8009244 # number of ReadReq accesses(hits+misses) 922system.cpu0.dcache.ReadReq_accesses::total 8009244 # number of ReadReq accesses(hits+misses) 923system.cpu0.dcache.WriteReq_accesses::cpu0.data 5463810 # number of WriteReq accesses(hits+misses) 924system.cpu0.dcache.WriteReq_accesses::total 5463810 # number of WriteReq accesses(hits+misses) 925system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 198261 # number of LoadLockedReq accesses(hits+misses) 926system.cpu0.dcache.LoadLockedReq_accesses::total 198261 # number of LoadLockedReq accesses(hits+misses) 927system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 202071 # number of StoreCondReq accesses(hits+misses) 928system.cpu0.dcache.StoreCondReq_accesses::total 202071 # number of StoreCondReq accesses(hits+misses) 929system.cpu0.dcache.demand_accesses::cpu0.data 13473054 # number of demand (read+write) accesses 930system.cpu0.dcache.demand_accesses::total 13473054 # number of demand (read+write) accesses 931system.cpu0.dcache.overall_accesses::cpu0.data 13473054 # number of overall (read+write) accesses 932system.cpu0.dcache.overall_accesses::total 13473054 # number of overall (read+write) accesses 933system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193416 # miss rate for ReadReq accesses 934system.cpu0.dcache.ReadReq_miss_rate::total 0.193416 # miss rate for ReadReq accesses 935system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.311981 # miss rate for WriteReq accesses 936system.cpu0.dcache.WriteReq_miss_rate::total 0.311981 # miss rate for WriteReq accesses 937system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104660 # miss rate for LoadLockedReq accesses 938system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104660 # miss rate for LoadLockedReq accesses 939system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.010046 # miss rate for StoreCondReq accesses 940system.cpu0.dcache.StoreCondReq_miss_rate::total 0.010046 # miss rate for StoreCondReq accesses 941system.cpu0.dcache.demand_miss_rate::cpu0.data 0.241498 # miss rate for demand accesses 942system.cpu0.dcache.demand_miss_rate::total 0.241498 # miss rate for demand accesses 943system.cpu0.dcache.overall_miss_rate::cpu0.data 0.241498 # miss rate for overall accesses 944system.cpu0.dcache.overall_miss_rate::total 0.241498 # miss rate for overall accesses 945system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22449.520533 # average ReadReq miss latency 946system.cpu0.dcache.ReadReq_avg_miss_latency::total 22449.520533 # average ReadReq miss latency 947system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30909.202624 # average WriteReq miss latency 948system.cpu0.dcache.WriteReq_avg_miss_latency::total 30909.202624 # average WriteReq miss latency 949system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14534.120482 # average LoadLockedReq miss latency 950system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14534.120482 # average LoadLockedReq miss latency 951system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12237.192118 # average StoreCondReq miss latency 952system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12237.192118 # average StoreCondReq miss latency 953system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency 954system.cpu0.dcache.demand_avg_miss_latency::total 26881.500057 # average overall miss latency 955system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26881.500057 # average overall miss latency 956system.cpu0.dcache.overall_avg_miss_latency::total 26881.500057 # average overall miss latency 957system.cpu0.dcache.blocked_cycles::no_mshrs 862708394 # number of cycles access was blocked 958system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked 959system.cpu0.dcache.blocked::no_mshrs 97003 # number of cycles access was blocked 960system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked 961system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8893.625908 # average number of cycles each access was blocked 962system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked 963system.cpu0.dcache.fast_writes 0 # number of fast writes performed 964system.cpu0.dcache.cache_copies 0 # number of cache copies performed 965system.cpu0.dcache.writebacks::writebacks 689568 # number of writebacks 966system.cpu0.dcache.writebacks::total 689568 # number of writebacks 967system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 597617 # number of ReadReq MSHR hits 968system.cpu0.dcache.ReadReq_mshr_hits::total 597617 # number of ReadReq MSHR hits 969system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436241 # number of WriteReq MSHR hits 970system.cpu0.dcache.WriteReq_mshr_hits::total 1436241 # number of WriteReq MSHR hits 971system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4277 # number of LoadLockedReq MSHR hits 972system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4277 # number of LoadLockedReq MSHR hits 973system.cpu0.dcache.demand_mshr_hits::cpu0.data 2033858 # number of demand (read+write) MSHR hits 974system.cpu0.dcache.demand_mshr_hits::total 2033858 # number of demand (read+write) MSHR hits 975system.cpu0.dcache.overall_mshr_hits::cpu0.data 2033858 # number of overall MSHR hits 976system.cpu0.dcache.overall_mshr_hits::total 2033858 # number of overall MSHR hits 977system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 951498 # number of ReadReq MSHR misses 978system.cpu0.dcache.ReadReq_mshr_misses::total 951498 # number of ReadReq MSHR misses 979system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 268365 # number of WriteReq MSHR misses 980system.cpu0.dcache.WriteReq_mshr_misses::total 268365 # number of WriteReq MSHR misses 981system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16473 # number of LoadLockedReq MSHR misses 982system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16473 # number of LoadLockedReq MSHR misses 983system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2030 # number of StoreCondReq MSHR misses 984system.cpu0.dcache.StoreCondReq_mshr_misses::total 2030 # number of StoreCondReq MSHR misses 985system.cpu0.dcache.demand_mshr_misses::cpu0.data 1219863 # number of demand (read+write) MSHR misses 986system.cpu0.dcache.demand_mshr_misses::total 1219863 # number of demand (read+write) MSHR misses 987system.cpu0.dcache.overall_mshr_misses::cpu0.data 1219863 # number of overall MSHR misses 988system.cpu0.dcache.overall_mshr_misses::total 1219863 # number of overall MSHR misses 989system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22991247500 # number of ReadReq MSHR miss cycles 990system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22991247500 # number of ReadReq MSHR miss cycles 991system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7905411394 # number of WriteReq MSHR miss cycles 992system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7905411394 # number of WriteReq MSHR miss cycles 993system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183295500 # number of LoadLockedReq MSHR miss cycles 994system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183295500 # number of LoadLockedReq MSHR miss cycles 995system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18744000 # number of StoreCondReq MSHR miss cycles 996system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18744000 # number of StoreCondReq MSHR miss cycles 997system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30896658894 # number of demand (read+write) MSHR miss cycles 998system.cpu0.dcache.demand_mshr_miss_latency::total 30896658894 # number of demand (read+write) MSHR miss cycles 999system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30896658894 # number of overall MSHR miss cycles 1000system.cpu0.dcache.overall_mshr_miss_latency::total 30896658894 # number of overall MSHR miss cycles 1001system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 635008500 # number of ReadReq MSHR uncacheable cycles 1002system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 635008500 # number of ReadReq MSHR uncacheable cycles 1003system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1065246998 # number of WriteReq MSHR uncacheable cycles 1004system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1065246998 # number of WriteReq MSHR uncacheable cycles 1005system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1700255498 # number of overall MSHR uncacheable cycles 1006system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1700255498 # number of overall MSHR uncacheable cycles 1007system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118800 # mshr miss rate for ReadReq accesses 1008system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118800 # mshr miss rate for ReadReq accesses 1009system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049117 # mshr miss rate for WriteReq accesses 1010system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049117 # mshr miss rate for WriteReq accesses 1011system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083087 # mshr miss rate for LoadLockedReq accesses 1012system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083087 # mshr miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.010046 # mshr miss rate for StoreCondReq accesses 1014system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.010046 # mshr miss rate for StoreCondReq accesses 1015system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for demand accesses 1016system.cpu0.dcache.demand_mshr_miss_rate::total 0.090541 # mshr miss rate for demand accesses 1017system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090541 # mshr miss rate for overall accesses 1018system.cpu0.dcache.overall_mshr_miss_rate::total 0.090541 # mshr miss rate for overall accesses 1019system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24163.211588 # average ReadReq mshr miss latency 1020system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24163.211588 # average ReadReq mshr miss latency 1021system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29457.684102 # average WriteReq mshr miss latency 1022system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29457.684102 # average WriteReq mshr miss latency 1023system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11127.026043 # average LoadLockedReq mshr miss latency 1024system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11127.026043 # average LoadLockedReq mshr miss latency 1025system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9233.497537 # average StoreCondReq mshr miss latency 1026system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9233.497537 # average StoreCondReq mshr miss latency 1027system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency 1028system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency 1029system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25327.974448 # average overall mshr miss latency 1030system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25327.974448 # average overall mshr miss latency 1031system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1032system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1033system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1034system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1035system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1036system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1037system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu1.dtb.fetch_hits 0 # ITB hits 1039system.cpu1.dtb.fetch_misses 0 # ITB misses 1040system.cpu1.dtb.fetch_acv 0 # ITB acv 1041system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1042system.cpu1.dtb.read_hits 1967803 # DTB read hits 1043system.cpu1.dtb.read_misses 13979 # DTB read misses 1044system.cpu1.dtb.read_acv 50 # DTB read access violations 1045system.cpu1.dtb.read_accesses 344857 # DTB read accesses 1046system.cpu1.dtb.write_hits 1156959 # DTB write hits 1047system.cpu1.dtb.write_misses 3426 # DTB write misses 1048system.cpu1.dtb.write_acv 86 # DTB write access violations 1049system.cpu1.dtb.write_accesses 133134 # DTB write accesses 1050system.cpu1.dtb.data_hits 3124762 # DTB hits 1051system.cpu1.dtb.data_misses 17405 # DTB misses 1052system.cpu1.dtb.data_acv 136 # DTB access violations 1053system.cpu1.dtb.data_accesses 477991 # DTB accesses 1054system.cpu1.itb.fetch_hits 421916 # ITB hits 1055system.cpu1.itb.fetch_misses 9109 # ITB misses 1056system.cpu1.itb.fetch_acv 356 # ITB acv 1057system.cpu1.itb.fetch_accesses 431025 # ITB accesses 1058system.cpu1.itb.read_hits 0 # DTB read hits 1059system.cpu1.itb.read_misses 0 # DTB read misses 1060system.cpu1.itb.read_acv 0 # DTB read access violations 1061system.cpu1.itb.read_accesses 0 # DTB read accesses 1062system.cpu1.itb.write_hits 0 # DTB write hits 1063system.cpu1.itb.write_misses 0 # DTB write misses 1064system.cpu1.itb.write_acv 0 # DTB write access violations 1065system.cpu1.itb.write_accesses 0 # DTB write accesses 1066system.cpu1.itb.data_hits 0 # DTB hits 1067system.cpu1.itb.data_misses 0 # DTB misses 1068system.cpu1.itb.data_acv 0 # DTB access violations 1069system.cpu1.itb.data_accesses 0 # DTB accesses 1070system.cpu1.numCycles 16642884 # number of cpu cycles simulated 1071system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1072system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1073system.cpu1.BPredUnit.lookups 2705570 # Number of BP lookups 1074system.cpu1.BPredUnit.condPredicted 2183133 # Number of conditional branches predicted 1075system.cpu1.BPredUnit.condIncorrect 103658 # Number of conditional branches incorrect 1076system.cpu1.BPredUnit.BTBLookups 1600081 # Number of BTB lookups 1077system.cpu1.BPredUnit.BTBHits 956693 # Number of BTB hits 1078system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1079system.cpu1.BPredUnit.usedRAS 205000 # Number of times the RAS was used to get a target. 1080system.cpu1.BPredUnit.RASInCorrect 11458 # Number of incorrect RAS predictions. 1081system.cpu1.fetch.icacheStallCycles 5302876 # Number of cycles fetch is stalled on an Icache miss 1082system.cpu1.fetch.Insts 13307049 # Number of instructions fetch has processed 1083system.cpu1.fetch.Branches 2705570 # Number of branches that fetch encountered 1084system.cpu1.fetch.predictedBranches 1161693 # Number of branches that fetch has predicted taken 1085system.cpu1.fetch.Cycles 2441613 # Number of cycles fetch has run and was not squashing or blocked 1086system.cpu1.fetch.SquashCycles 501707 # Number of cycles fetch has spent squashing 1087system.cpu1.fetch.BlockedCycles 6356468 # Number of cycles fetch has spent blocked 1088system.cpu1.fetch.MiscStallCycles 26216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1089system.cpu1.fetch.PendingTrapStallCycles 74919 # Number of stall cycles due to pending traps 1090system.cpu1.fetch.PendingQuiesceStallCycles 150190 # Number of stall cycles due to pending quiesce instructions 1091system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR 1092system.cpu1.fetch.CacheLines 1679881 # Number of cache lines fetched 1093system.cpu1.fetch.IcacheSquashes 61959 # Number of outstanding Icache misses that were squashed 1094system.cpu1.fetch.rateDist::samples 14687135 # Number of instructions fetched each cycle (Total) 1095system.cpu1.fetch.rateDist::mean 0.906034 # Number of instructions fetched each cycle (Total) 1096system.cpu1.fetch.rateDist::stdev 2.268778 # Number of instructions fetched each cycle (Total) 1097system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1098system.cpu1.fetch.rateDist::0 12245522 83.38% 83.38% # Number of instructions fetched each cycle (Total) 1099system.cpu1.fetch.rateDist::1 134693 0.92% 84.29% # Number of instructions fetched each cycle (Total) 1100system.cpu1.fetch.rateDist::2 301692 2.05% 86.35% # Number of instructions fetched each cycle (Total) 1101system.cpu1.fetch.rateDist::3 210681 1.43% 87.78% # Number of instructions fetched each cycle (Total) 1102system.cpu1.fetch.rateDist::4 386391 2.63% 90.41% # Number of instructions fetched each cycle (Total) 1103system.cpu1.fetch.rateDist::5 150965 1.03% 91.44% # Number of instructions fetched each cycle (Total) 1104system.cpu1.fetch.rateDist::6 158556 1.08% 92.52% # Number of instructions fetched each cycle (Total) 1105system.cpu1.fetch.rateDist::7 103876 0.71% 93.23% # Number of instructions fetched each cycle (Total) 1106system.cpu1.fetch.rateDist::8 994759 6.77% 100.00% # Number of instructions fetched each cycle (Total) 1107system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1108system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1109system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1110system.cpu1.fetch.rateDist::total 14687135 # Number of instructions fetched each cycle (Total) 1111system.cpu1.fetch.branchRate 0.162566 # Number of branch fetches per cycle 1112system.cpu1.fetch.rate 0.799564 # Number of inst fetches per cycle 1113system.cpu1.decode.IdleCycles 5465828 # Number of cycles decode is idle 1114system.cpu1.decode.BlockedCycles 6500437 # Number of cycles decode is blocked 1115system.cpu1.decode.RunCycles 2284956 # Number of cycles decode is running 1116system.cpu1.decode.UnblockCycles 109363 # Number of cycles decode is unblocking 1117system.cpu1.decode.SquashCycles 326550 # Number of cycles decode is squashing 1118system.cpu1.decode.BranchResolved 135471 # Number of times decode resolved a branch 1119system.cpu1.decode.BranchMispred 8440 # Number of times decode detected a branch misprediction 1120system.cpu1.decode.DecodedInsts 12979059 # Number of instructions handled by decode 1121system.cpu1.decode.SquashedInsts 22096 # Number of squashed instructions handled by decode 1122system.cpu1.rename.SquashCycles 326550 # Number of cycles rename is squashing 1123system.cpu1.rename.IdleCycles 5675549 # Number of cycles rename is idle 1124system.cpu1.rename.BlockCycles 1529515 # Number of cycles rename is blocking 1125system.cpu1.rename.serializeStallCycles 4345584 # count of cycles rename stalled for serializing inst 1126system.cpu1.rename.RunCycles 2134958 # Number of cycles rename is running 1127system.cpu1.rename.UnblockCycles 674977 # Number of cycles rename is unblocking 1128system.cpu1.rename.RenamedInsts 12129764 # Number of instructions processed by rename 1129system.cpu1.rename.ROBFullEvents 166 # Number of times rename has blocked due to ROB full 1130system.cpu1.rename.IQFullEvents 128005 # Number of times rename has blocked due to IQ full 1131system.cpu1.rename.LSQFullEvents 129891 # Number of times rename has blocked due to LSQ full 1132system.cpu1.rename.RenamedOperands 8170378 # Number of destination operands rename has renamed 1133system.cpu1.rename.RenameLookups 14771785 # Number of register rename lookups that rename has made 1134system.cpu1.rename.int_rename_lookups 14690250 # Number of integer rename lookups 1135system.cpu1.rename.fp_rename_lookups 81535 # Number of floating rename lookups 1136system.cpu1.rename.CommittedMaps 6624020 # Number of HB maps that are committed 1137system.cpu1.rename.UndoneMaps 1546358 # Number of HB maps that are undone due to squashing 1138system.cpu1.rename.serializingInsts 396407 # count of serializing insts renamed 1139system.cpu1.rename.tempSerializingInsts 33332 # count of temporary serializing insts renamed 1140system.cpu1.rename.skidInsts 2062542 # count of insts added to the skid buffer 1141system.cpu1.memDep0.insertedLoads 2114945 # Number of loads inserted to the mem dependence unit. 1142system.cpu1.memDep0.insertedStores 1244442 # Number of stores inserted to the mem dependence unit. 1143system.cpu1.memDep0.conflictingLoads 252990 # Number of conflicting loads. 1144system.cpu1.memDep0.conflictingStores 158890 # Number of conflicting stores. 1145system.cpu1.iq.iqInstsAdded 10689942 # Number of instructions added to the IQ (excludes non-spec) 1146system.cpu1.iq.iqNonSpecInstsAdded 428775 # Number of non-speculative instructions added to the IQ 1147system.cpu1.iq.iqInstsIssued 10217833 # Number of instructions issued 1148system.cpu1.iq.iqSquashedInstsIssued 32007 # Number of squashed instructions issued 1149system.cpu1.iq.iqSquashedInstsExamined 1868726 # Number of squashed instructions iterated over during squash; mainly for profiling 1150system.cpu1.iq.iqSquashedOperandsExamined 1009548 # Number of squashed operands that are examined and possibly removed from graph 1151system.cpu1.iq.iqSquashedNonSpecRemoved 314972 # Number of squashed non-spec instructions that were removed 1152system.cpu1.iq.issued_per_cycle::samples 14687135 # Number of insts issued each cycle 1153system.cpu1.iq.issued_per_cycle::mean 0.695700 # Number of insts issued each cycle 1154system.cpu1.iq.issued_per_cycle::stdev 1.377163 # Number of insts issued each cycle 1155system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1156system.cpu1.iq.issued_per_cycle::0 10355359 70.51% 70.51% # Number of insts issued each cycle 1157system.cpu1.iq.issued_per_cycle::1 1845686 12.57% 83.07% # Number of insts issued each cycle 1158system.cpu1.iq.issued_per_cycle::2 877719 5.98% 89.05% # Number of insts issued each cycle 1159system.cpu1.iq.issued_per_cycle::3 637269 4.34% 93.39% # Number of insts issued each cycle 1160system.cpu1.iq.issued_per_cycle::4 497555 3.39% 96.78% # Number of insts issued each cycle 1161system.cpu1.iq.issued_per_cycle::5 237687 1.62% 98.39% # Number of insts issued each cycle 1162system.cpu1.iq.issued_per_cycle::6 141618 0.96% 99.36% # Number of insts issued each cycle 1163system.cpu1.iq.issued_per_cycle::7 77397 0.53% 99.89% # Number of insts issued each cycle 1164system.cpu1.iq.issued_per_cycle::8 16845 0.11% 100.00% # Number of insts issued each cycle 1165system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1166system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1167system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1168system.cpu1.iq.issued_per_cycle::total 14687135 # Number of insts issued each cycle 1169system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1170system.cpu1.iq.fu_full::IntAlu 13419 6.74% 6.74% # attempts to use FU when none available 1171system.cpu1.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available 1172system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available 1173system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available 1174system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available 1175system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available 1176system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available 1177system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available 1178system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available 1179system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available 1180system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available 1181system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available 1182system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available 1183system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available 1184system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available 1185system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available 1186system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available 1187system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available 1188system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available 1189system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available 1190system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available 1191system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available 1192system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available 1193system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available 1194system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available 1195system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available 1196system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available 1197system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available 1198system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available 1199system.cpu1.iq.fu_full::MemRead 108426 54.48% 61.22% # attempts to use FU when none available 1200system.cpu1.iq.fu_full::MemWrite 77176 38.78% 100.00% # attempts to use FU when none available 1201system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1202system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1203system.cpu1.iq.FU_type_0::No_OpClass 3982 0.04% 0.04% # Type of FU issued 1204system.cpu1.iq.FU_type_0::IntAlu 6701010 65.58% 65.62% # Type of FU issued 1205system.cpu1.iq.FU_type_0::IntMult 17534 0.17% 65.79% # Type of FU issued 1206system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued 1207system.cpu1.iq.FU_type_0::FloatAdd 10648 0.10% 65.90% # Type of FU issued 1208system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued 1209system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued 1210system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued 1211system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 65.92% # Type of FU issued 1212system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued 1213system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued 1214system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued 1215system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued 1216system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued 1217system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued 1218system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued 1219system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued 1220system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued 1221system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued 1222system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued 1223system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued 1224system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued 1225system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued 1226system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued 1227system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued 1228system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued 1229system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued 1230system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued 1231system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued 1232system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued 1233system.cpu1.iq.FU_type_0::MemRead 2057377 20.14% 86.05% # Type of FU issued 1234system.cpu1.iq.FU_type_0::MemWrite 1183005 11.58% 97.63% # Type of FU issued 1235system.cpu1.iq.FU_type_0::IprAccess 242286 2.37% 100.00% # Type of FU issued 1236system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1237system.cpu1.iq.FU_type_0::total 10217833 # Type of FU issued 1238system.cpu1.iq.rate 0.613946 # Inst issue rate 1239system.cpu1.iq.fu_busy_cnt 199021 # FU busy when requested 1240system.cpu1.iq.fu_busy_rate 0.019478 # FU busy rate (busy events/executed inst) 1241system.cpu1.iq.int_inst_queue_reads 35235052 # Number of integer instruction queue reads 1242system.cpu1.iq.int_inst_queue_writes 12931686 # Number of integer instruction queue writes 1243system.cpu1.iq.int_inst_queue_wakeup_accesses 9924010 # Number of integer instruction queue wakeup accesses 1244system.cpu1.iq.fp_inst_queue_reads 118777 # Number of floating instruction queue reads 1245system.cpu1.iq.fp_inst_queue_writes 58514 # Number of floating instruction queue writes 1246system.cpu1.iq.fp_inst_queue_wakeup_accesses 57042 # Number of floating instruction queue wakeup accesses 1247system.cpu1.iq.int_alu_accesses 10351384 # Number of integer alu accesses 1248system.cpu1.iq.fp_alu_accesses 61488 # Number of floating point alu accesses 1249system.cpu1.iew.lsq.thread0.forwLoads 101325 # Number of loads that had data forwarded from stores 1250system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1251system.cpu1.iew.lsq.thread0.squashedLoads 375645 # Number of loads squashed 1252system.cpu1.iew.lsq.thread0.ignoredResponses 853 # Number of memory responses ignored because the instruction is squashed 1253system.cpu1.iew.lsq.thread0.memOrderViolation 2882 # Number of memory ordering violations 1254system.cpu1.iew.lsq.thread0.squashedStores 159755 # Number of stores squashed 1255system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1256system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1257system.cpu1.iew.lsq.thread0.rescheduledLoads 4092 # Number of loads that were rescheduled 1258system.cpu1.iew.lsq.thread0.cacheBlocked 23338 # Number of times an access to memory failed due to the cache being blocked 1259system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1260system.cpu1.iew.iewSquashCycles 326550 # Number of cycles IEW is squashing 1261system.cpu1.iew.iewBlockCycles 1215619 # Number of cycles IEW is blocking 1262system.cpu1.iew.iewUnblockCycles 41484 # Number of cycles IEW is unblocking 1263system.cpu1.iew.iewDispatchedInsts 11650788 # Number of instructions dispatched to IQ 1264system.cpu1.iew.iewDispSquashedInsts 153391 # Number of squashed instructions skipped by dispatch 1265system.cpu1.iew.iewDispLoadInsts 2114945 # Number of dispatched load instructions 1266system.cpu1.iew.iewDispStoreInsts 1244442 # Number of dispatched store instructions 1267system.cpu1.iew.iewDispNonSpecInsts 389086 # Number of dispatched non-speculative instructions 1268system.cpu1.iew.iewIQFullEvents 9620 # Number of times the IQ has become full, causing a stall 1269system.cpu1.iew.iewLSQFullEvents 6598 # Number of times the LSQ has become full, causing a stall 1270system.cpu1.iew.memOrderViolationEvents 2882 # Number of memory order violations 1271system.cpu1.iew.predictedTakenIncorrect 57079 # Number of branches that were predicted taken incorrectly 1272system.cpu1.iew.predictedNotTakenIncorrect 98765 # Number of branches that were predicted not taken incorrectly 1273system.cpu1.iew.branchMispredicts 155844 # Number of branch mispredicts detected at execute 1274system.cpu1.iew.iewExecutedInsts 10093188 # Number of executed instructions 1275system.cpu1.iew.iewExecLoadInsts 1987752 # Number of load instructions executed 1276system.cpu1.iew.iewExecSquashedInsts 124645 # Number of squashed instructions skipped in execute 1277system.cpu1.iew.exec_swp 0 # number of swp insts executed 1278system.cpu1.iew.exec_nop 532071 # number of nop insts executed 1279system.cpu1.iew.exec_refs 3152815 # number of memory reference insts executed 1280system.cpu1.iew.exec_branches 1559516 # Number of branches executed 1281system.cpu1.iew.exec_stores 1165063 # Number of stores executed 1282system.cpu1.iew.exec_rate 0.606457 # Inst execution rate 1283system.cpu1.iew.wb_sent 10020459 # cumulative count of insts sent to commit 1284system.cpu1.iew.wb_count 9981052 # cumulative count of insts written-back 1285system.cpu1.iew.wb_producers 4916782 # num instructions producing a value 1286system.cpu1.iew.wb_consumers 6843934 # num instructions consuming a value 1287system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1288system.cpu1.iew.wb_rate 0.599719 # insts written-back per cycle 1289system.cpu1.iew.wb_fanout 0.718415 # average fanout of values written-back 1290system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1291system.cpu1.commit.commitCommittedInsts 9615778 # The number of committed instructions 1292system.cpu1.commit.commitCommittedOps 9615778 # The number of committed instructions 1293system.cpu1.commit.commitSquashedInsts 1958417 # The number of squashed insts skipped by commit 1294system.cpu1.commit.commitNonSpecStalls 113803 # The number of times commit has been forced to stall to communicate backwards 1295system.cpu1.commit.branchMispredicts 145209 # The number of times a branch was mispredicted 1296system.cpu1.commit.committed_per_cycle::samples 14360585 # Number of insts commited each cycle 1297system.cpu1.commit.committed_per_cycle::mean 0.669595 # Number of insts commited each cycle 1298system.cpu1.commit.committed_per_cycle::stdev 1.592350 # Number of insts commited each cycle 1299system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1300system.cpu1.commit.committed_per_cycle::0 10743360 74.81% 74.81% # Number of insts commited each cycle 1301system.cpu1.commit.committed_per_cycle::1 1616043 11.25% 86.06% # Number of insts commited each cycle 1302system.cpu1.commit.committed_per_cycle::2 700215 4.88% 90.94% # Number of insts commited each cycle 1303system.cpu1.commit.committed_per_cycle::3 397241 2.77% 93.71% # Number of insts commited each cycle 1304system.cpu1.commit.committed_per_cycle::4 279128 1.94% 95.65% # Number of insts commited each cycle 1305system.cpu1.commit.committed_per_cycle::5 129549 0.90% 96.55% # Number of insts commited each cycle 1306system.cpu1.commit.committed_per_cycle::6 113540 0.79% 97.34% # Number of insts commited each cycle 1307system.cpu1.commit.committed_per_cycle::7 89987 0.63% 97.97% # Number of insts commited each cycle 1308system.cpu1.commit.committed_per_cycle::8 291522 2.03% 100.00% # Number of insts commited each cycle 1309system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1310system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1311system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1312system.cpu1.commit.committed_per_cycle::total 14360585 # Number of insts commited each cycle 1313system.cpu1.commit.committedInsts 9615778 # Number of instructions committed 1314system.cpu1.commit.committedOps 9615778 # Number of ops (including micro ops) committed 1315system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1316system.cpu1.commit.refs 2823987 # Number of memory references committed 1317system.cpu1.commit.loads 1739300 # Number of loads committed 1318system.cpu1.commit.membars 35653 # Number of memory barriers committed 1319system.cpu1.commit.branches 1422938 # Number of branches committed 1320system.cpu1.commit.fp_insts 55483 # Number of committed floating point instructions. 1321system.cpu1.commit.int_insts 8948473 # Number of committed integer instructions. 1322system.cpu1.commit.function_calls 153476 # Number of function calls committed. 1323system.cpu1.commit.bw_lim_events 291522 # number cycles where commit BW limit reached 1324system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1325system.cpu1.rob.rob_reads 25542136 # The number of ROB reads 1326system.cpu1.rob.rob_writes 23473924 # The number of ROB writes 1327system.cpu1.timesIdled 165614 # Number of times that the entire CPU went into an idle state and unscheduled itself 1328system.cpu1.idleCycles 1955749 # Total number of cycles that the CPU has spent unscheduled due to idling 1329system.cpu1.quiesceCycles 3781507254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1330system.cpu1.committedInsts 9164096 # Number of Instructions Simulated 1331system.cpu1.committedOps 9164096 # Number of Ops (including micro ops) Simulated 1332system.cpu1.committedInsts_total 9164096 # Number of Instructions Simulated 1333system.cpu1.cpi 1.816097 # CPI: Cycles Per Instruction 1334system.cpu1.cpi_total 1.816097 # CPI: Total CPI of All Threads 1335system.cpu1.ipc 0.550631 # IPC: Instructions Per Cycle 1336system.cpu1.ipc_total 0.550631 # IPC: Total IPC of All Threads 1337system.cpu1.int_regfile_reads 13179031 # number of integer regfile reads 1338system.cpu1.int_regfile_writes 7231354 # number of integer regfile writes 1339system.cpu1.fp_regfile_reads 33888 # number of floating regfile reads 1340system.cpu1.fp_regfile_writes 32897 # number of floating regfile writes 1341system.cpu1.misc_regfile_reads 392068 # number of misc regfile reads 1342system.cpu1.misc_regfile_writes 179438 # number of misc regfile writes 1343system.cpu1.icache.replacements 177236 # number of replacements 1344system.cpu1.icache.tagsinuse 505.128292 # Cycle average of tags in use 1345system.cpu1.icache.total_refs 1491482 # Total number of references to valid blocks. 1346system.cpu1.icache.sampled_refs 177747 # Sample count of references to valid blocks. 1347system.cpu1.icache.avg_refs 8.391039 # Average number of references to valid blocks. 1348system.cpu1.icache.warmup_cycle 108399350000 # Cycle when the warmup percentage was hit. 1349system.cpu1.icache.occ_blocks::cpu1.inst 505.128292 # Average occupied blocks per requestor 1350system.cpu1.icache.occ_percent::cpu1.inst 0.986579 # Average percentage of cache occupancy 1351system.cpu1.icache.occ_percent::total 0.986579 # Average percentage of cache occupancy 1352system.cpu1.icache.ReadReq_hits::cpu1.inst 1491482 # number of ReadReq hits 1353system.cpu1.icache.ReadReq_hits::total 1491482 # number of ReadReq hits 1354system.cpu1.icache.demand_hits::cpu1.inst 1491482 # number of demand (read+write) hits 1355system.cpu1.icache.demand_hits::total 1491482 # number of demand (read+write) hits 1356system.cpu1.icache.overall_hits::cpu1.inst 1491482 # number of overall hits 1357system.cpu1.icache.overall_hits::total 1491482 # number of overall hits 1358system.cpu1.icache.ReadReq_misses::cpu1.inst 188398 # number of ReadReq misses 1359system.cpu1.icache.ReadReq_misses::total 188398 # number of ReadReq misses 1360system.cpu1.icache.demand_misses::cpu1.inst 188398 # number of demand (read+write) misses 1361system.cpu1.icache.demand_misses::total 188398 # number of demand (read+write) misses 1362system.cpu1.icache.overall_misses::cpu1.inst 188398 # number of overall misses 1363system.cpu1.icache.overall_misses::total 188398 # number of overall misses 1364system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2886679000 # number of ReadReq miss cycles 1365system.cpu1.icache.ReadReq_miss_latency::total 2886679000 # number of ReadReq miss cycles 1366system.cpu1.icache.demand_miss_latency::cpu1.inst 2886679000 # number of demand (read+write) miss cycles 1367system.cpu1.icache.demand_miss_latency::total 2886679000 # number of demand (read+write) miss cycles 1368system.cpu1.icache.overall_miss_latency::cpu1.inst 2886679000 # number of overall miss cycles 1369system.cpu1.icache.overall_miss_latency::total 2886679000 # number of overall miss cycles 1370system.cpu1.icache.ReadReq_accesses::cpu1.inst 1679880 # number of ReadReq accesses(hits+misses) 1371system.cpu1.icache.ReadReq_accesses::total 1679880 # number of ReadReq accesses(hits+misses) 1372system.cpu1.icache.demand_accesses::cpu1.inst 1679880 # number of demand (read+write) accesses 1373system.cpu1.icache.demand_accesses::total 1679880 # number of demand (read+write) accesses 1374system.cpu1.icache.overall_accesses::cpu1.inst 1679880 # number of overall (read+write) accesses 1375system.cpu1.icache.overall_accesses::total 1679880 # number of overall (read+write) accesses 1376system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112150 # miss rate for ReadReq accesses 1377system.cpu1.icache.ReadReq_miss_rate::total 0.112150 # miss rate for ReadReq accesses 1378system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112150 # miss rate for demand accesses 1379system.cpu1.icache.demand_miss_rate::total 0.112150 # miss rate for demand accesses 1380system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112150 # miss rate for overall accesses 1381system.cpu1.icache.overall_miss_rate::total 0.112150 # miss rate for overall accesses 1382system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency 1383system.cpu1.icache.ReadReq_avg_miss_latency::total 15322.238028 # average ReadReq miss latency 1384system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency 1385system.cpu1.icache.demand_avg_miss_latency::total 15322.238028 # average overall miss latency 1386system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency 1387system.cpu1.icache.overall_avg_miss_latency::total 15322.238028 # average overall miss latency 1388system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked 1389system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1390system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked 1391system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1392system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked 1393system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1394system.cpu1.icache.fast_writes 0 # number of fast writes performed 1395system.cpu1.icache.cache_copies 0 # number of cache copies performed 1396system.cpu1.icache.writebacks::writebacks 52 # number of writebacks 1397system.cpu1.icache.writebacks::total 52 # number of writebacks 1398system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits 1399system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits 1400system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits 1401system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits 1402system.cpu1.icache.overall_mshr_hits::cpu1.inst 10580 # number of overall MSHR hits 1403system.cpu1.icache.overall_mshr_hits::total 10580 # number of overall MSHR hits 1404system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 177818 # number of ReadReq MSHR misses 1405system.cpu1.icache.ReadReq_mshr_misses::total 177818 # number of ReadReq MSHR misses 1406system.cpu1.icache.demand_mshr_misses::cpu1.inst 177818 # number of demand (read+write) MSHR misses 1407system.cpu1.icache.demand_mshr_misses::total 177818 # number of demand (read+write) MSHR misses 1408system.cpu1.icache.overall_mshr_misses::cpu1.inst 177818 # number of overall MSHR misses 1409system.cpu1.icache.overall_mshr_misses::total 177818 # number of overall MSHR misses 1410system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2188079500 # number of ReadReq MSHR miss cycles 1411system.cpu1.icache.ReadReq_mshr_miss_latency::total 2188079500 # number of ReadReq MSHR miss cycles 1412system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2188079500 # number of demand (read+write) MSHR miss cycles 1413system.cpu1.icache.demand_mshr_miss_latency::total 2188079500 # number of demand (read+write) MSHR miss cycles 1414system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2188079500 # number of overall MSHR miss cycles 1415system.cpu1.icache.overall_mshr_miss_latency::total 2188079500 # number of overall MSHR miss cycles 1416system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for ReadReq accesses 1417system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105852 # mshr miss rate for ReadReq accesses 1418system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for demand accesses 1419system.cpu1.icache.demand_mshr_miss_rate::total 0.105852 # mshr miss rate for demand accesses 1420system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105852 # mshr miss rate for overall accesses 1421system.cpu1.icache.overall_mshr_miss_rate::total 0.105852 # mshr miss rate for overall accesses 1422system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average ReadReq mshr miss latency 1423system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12305.163144 # average ReadReq mshr miss latency 1424system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency 1425system.cpu1.icache.demand_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency 1426system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12305.163144 # average overall mshr miss latency 1427system.cpu1.icache.overall_avg_mshr_miss_latency::total 12305.163144 # average overall mshr miss latency 1428system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1429system.cpu1.dcache.replacements 156190 # number of replacements 1430system.cpu1.dcache.tagsinuse 478.738504 # Cycle average of tags in use 1431system.cpu1.dcache.total_refs 2451996 # Total number of references to valid blocks. 1432system.cpu1.dcache.sampled_refs 156506 # Sample count of references to valid blocks. 1433system.cpu1.dcache.avg_refs 15.667105 # Average number of references to valid blocks. 1434system.cpu1.dcache.warmup_cycle 42868987000 # Cycle when the warmup percentage was hit. 1435system.cpu1.dcache.occ_blocks::cpu1.data 478.738504 # Average occupied blocks per requestor 1436system.cpu1.dcache.occ_percent::cpu1.data 0.935036 # Average percentage of cache occupancy 1437system.cpu1.dcache.occ_percent::total 0.935036 # Average percentage of cache occupancy 1438system.cpu1.dcache.ReadReq_hits::cpu1.data 1592507 # number of ReadReq hits 1439system.cpu1.dcache.ReadReq_hits::total 1592507 # number of ReadReq hits 1440system.cpu1.dcache.WriteReq_hits::cpu1.data 821344 # number of WriteReq hits 1441system.cpu1.dcache.WriteReq_hits::total 821344 # number of WriteReq hits 1442system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 23925 # number of LoadLockedReq hits 1443system.cpu1.dcache.LoadLockedReq_hits::total 23925 # number of LoadLockedReq hits 1444system.cpu1.dcache.StoreCondReq_hits::cpu1.data 22430 # number of StoreCondReq hits 1445system.cpu1.dcache.StoreCondReq_hits::total 22430 # number of StoreCondReq hits 1446system.cpu1.dcache.demand_hits::cpu1.data 2413851 # number of demand (read+write) hits 1447system.cpu1.dcache.demand_hits::total 2413851 # number of demand (read+write) hits 1448system.cpu1.dcache.overall_hits::cpu1.data 2413851 # number of overall hits 1449system.cpu1.dcache.overall_hits::total 2413851 # number of overall hits 1450system.cpu1.dcache.ReadReq_misses::cpu1.data 229184 # number of ReadReq misses 1451system.cpu1.dcache.ReadReq_misses::total 229184 # number of ReadReq misses 1452system.cpu1.dcache.WriteReq_misses::cpu1.data 231703 # number of WriteReq misses 1453system.cpu1.dcache.WriteReq_misses::total 231703 # number of WriteReq misses 1454system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 3831 # number of LoadLockedReq misses 1455system.cpu1.dcache.LoadLockedReq_misses::total 3831 # number of LoadLockedReq misses 1456system.cpu1.dcache.StoreCondReq_misses::cpu1.data 1979 # number of StoreCondReq misses 1457system.cpu1.dcache.StoreCondReq_misses::total 1979 # number of StoreCondReq misses 1458system.cpu1.dcache.demand_misses::cpu1.data 460887 # number of demand (read+write) misses 1459system.cpu1.dcache.demand_misses::total 460887 # number of demand (read+write) misses 1460system.cpu1.dcache.overall_misses::cpu1.data 460887 # number of overall misses 1461system.cpu1.dcache.overall_misses::total 460887 # number of overall misses 1462system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3617978500 # number of ReadReq miss cycles 1463system.cpu1.dcache.ReadReq_miss_latency::total 3617978500 # number of ReadReq miss cycles 1464system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7562454737 # number of WriteReq miss cycles 1465system.cpu1.dcache.WriteReq_miss_latency::total 7562454737 # number of WriteReq miss cycles 1466system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50003000 # number of LoadLockedReq miss cycles 1467system.cpu1.dcache.LoadLockedReq_miss_latency::total 50003000 # number of LoadLockedReq miss cycles 1468system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 26428500 # number of StoreCondReq miss cycles 1469system.cpu1.dcache.StoreCondReq_miss_latency::total 26428500 # number of StoreCondReq miss cycles 1470system.cpu1.dcache.demand_miss_latency::cpu1.data 11180433237 # number of demand (read+write) miss cycles 1471system.cpu1.dcache.demand_miss_latency::total 11180433237 # number of demand (read+write) miss cycles 1472system.cpu1.dcache.overall_miss_latency::cpu1.data 11180433237 # number of overall miss cycles 1473system.cpu1.dcache.overall_miss_latency::total 11180433237 # number of overall miss cycles 1474system.cpu1.dcache.ReadReq_accesses::cpu1.data 1821691 # number of ReadReq accesses(hits+misses) 1475system.cpu1.dcache.ReadReq_accesses::total 1821691 # number of ReadReq accesses(hits+misses) 1476system.cpu1.dcache.WriteReq_accesses::cpu1.data 1053047 # number of WriteReq accesses(hits+misses) 1477system.cpu1.dcache.WriteReq_accesses::total 1053047 # number of WriteReq accesses(hits+misses) 1478system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 27756 # number of LoadLockedReq accesses(hits+misses) 1479system.cpu1.dcache.LoadLockedReq_accesses::total 27756 # number of LoadLockedReq accesses(hits+misses) 1480system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 24409 # number of StoreCondReq accesses(hits+misses) 1481system.cpu1.dcache.StoreCondReq_accesses::total 24409 # number of StoreCondReq accesses(hits+misses) 1482system.cpu1.dcache.demand_accesses::cpu1.data 2874738 # number of demand (read+write) accesses 1483system.cpu1.dcache.demand_accesses::total 2874738 # number of demand (read+write) accesses 1484system.cpu1.dcache.overall_accesses::cpu1.data 2874738 # number of overall (read+write) accesses 1485system.cpu1.dcache.overall_accesses::total 2874738 # number of overall (read+write) accesses 1486system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.125808 # miss rate for ReadReq accesses 1487system.cpu1.dcache.ReadReq_miss_rate::total 0.125808 # miss rate for ReadReq accesses 1488system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.220031 # miss rate for WriteReq accesses 1489system.cpu1.dcache.WriteReq_miss_rate::total 0.220031 # miss rate for WriteReq accesses 1490system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.138024 # miss rate for LoadLockedReq accesses 1491system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.138024 # miss rate for LoadLockedReq accesses 1492system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081077 # miss rate for StoreCondReq accesses 1493system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081077 # miss rate for StoreCondReq accesses 1494system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160323 # miss rate for demand accesses 1495system.cpu1.dcache.demand_miss_rate::total 0.160323 # miss rate for demand accesses 1496system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160323 # miss rate for overall accesses 1497system.cpu1.dcache.overall_miss_rate::total 0.160323 # miss rate for overall accesses 1498system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15786.348523 # average ReadReq miss latency 1499system.cpu1.dcache.ReadReq_avg_miss_latency::total 15786.348523 # average ReadReq miss latency 1500system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32638.570657 # average WriteReq miss latency 1501system.cpu1.dcache.WriteReq_avg_miss_latency::total 32638.570657 # average WriteReq miss latency 1502system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13052.205690 # average LoadLockedReq miss latency 1503system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13052.205690 # average LoadLockedReq miss latency 1504system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency 1505system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13354.471956 # average StoreCondReq miss latency 1506system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency 1507system.cpu1.dcache.demand_avg_miss_latency::total 24258.512904 # average overall miss latency 1508system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency 1509system.cpu1.dcache.overall_avg_miss_latency::total 24258.512904 # average overall miss latency 1510system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked 1511system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1512system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked 1513system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1514system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked 1515system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1516system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1517system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1518system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks 1519system.cpu1.dcache.writebacks::total 116478 # number of writebacks 1520system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits 1521system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits 1522system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits 1523system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits 1524system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 879 # number of LoadLockedReq MSHR hits 1525system.cpu1.dcache.LoadLockedReq_mshr_hits::total 879 # number of LoadLockedReq MSHR hits 1526system.cpu1.dcache.demand_mshr_hits::cpu1.data 296787 # number of demand (read+write) MSHR hits 1527system.cpu1.dcache.demand_mshr_hits::total 296787 # number of demand (read+write) MSHR hits 1528system.cpu1.dcache.overall_mshr_hits::cpu1.data 296787 # number of overall MSHR hits 1529system.cpu1.dcache.overall_mshr_hits::total 296787 # number of overall MSHR hits 1530system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 127049 # number of ReadReq MSHR misses 1531system.cpu1.dcache.ReadReq_mshr_misses::total 127049 # number of ReadReq MSHR misses 1532system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37051 # number of WriteReq MSHR misses 1533system.cpu1.dcache.WriteReq_mshr_misses::total 37051 # number of WriteReq MSHR misses 1534system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 2952 # number of LoadLockedReq MSHR misses 1535system.cpu1.dcache.LoadLockedReq_mshr_misses::total 2952 # number of LoadLockedReq MSHR misses 1536system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 1975 # number of StoreCondReq MSHR misses 1537system.cpu1.dcache.StoreCondReq_mshr_misses::total 1975 # number of StoreCondReq MSHR misses 1538system.cpu1.dcache.demand_mshr_misses::cpu1.data 164100 # number of demand (read+write) MSHR misses 1539system.cpu1.dcache.demand_mshr_misses::total 164100 # number of demand (read+write) MSHR misses 1540system.cpu1.dcache.overall_mshr_misses::cpu1.data 164100 # number of overall MSHR misses 1541system.cpu1.dcache.overall_mshr_misses::total 164100 # number of overall MSHR misses 1542system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1572060500 # number of ReadReq MSHR miss cycles 1543system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1572060500 # number of ReadReq MSHR miss cycles 1544system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1129988939 # number of WriteReq MSHR miss cycles 1545system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1129988939 # number of WriteReq MSHR miss cycles 1546system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25904500 # number of LoadLockedReq MSHR miss cycles 1547system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 25904500 # number of LoadLockedReq MSHR miss cycles 1548system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 20495000 # number of StoreCondReq MSHR miss cycles 1549system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 20495000 # number of StoreCondReq MSHR miss cycles 1550system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2702049439 # number of demand (read+write) MSHR miss cycles 1551system.cpu1.dcache.demand_mshr_miss_latency::total 2702049439 # number of demand (read+write) MSHR miss cycles 1552system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2702049439 # number of overall MSHR miss cycles 1553system.cpu1.dcache.overall_mshr_miss_latency::total 2702049439 # number of overall MSHR miss cycles 1554system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 300850500 # number of ReadReq MSHR uncacheable cycles 1555system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 300850500 # number of ReadReq MSHR uncacheable cycles 1556system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 561357500 # number of WriteReq MSHR uncacheable cycles 1557system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 561357500 # number of WriteReq MSHR uncacheable cycles 1558system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 862208000 # number of overall MSHR uncacheable cycles 1559system.cpu1.dcache.overall_mshr_uncacheable_latency::total 862208000 # number of overall MSHR uncacheable cycles 1560system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.069742 # mshr miss rate for ReadReq accesses 1561system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.069742 # mshr miss rate for ReadReq accesses 1562system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for WriteReq accesses 1563system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.035185 # mshr miss rate for WriteReq accesses 1564system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106355 # mshr miss rate for LoadLockedReq accesses 1565system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106355 # mshr miss rate for LoadLockedReq accesses 1566system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080913 # mshr miss rate for StoreCondReq accesses 1567system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080913 # mshr miss rate for StoreCondReq accesses 1568system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for demand accesses 1569system.cpu1.dcache.demand_mshr_miss_rate::total 0.057083 # mshr miss rate for demand accesses 1570system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.057083 # mshr miss rate for overall accesses 1571system.cpu1.dcache.overall_mshr_miss_rate::total 0.057083 # mshr miss rate for overall accesses 1572system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12373.655046 # average ReadReq mshr miss latency 1573system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12373.655046 # average ReadReq mshr miss latency 1574system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30498.203530 # average WriteReq mshr miss latency 1575system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30498.203530 # average WriteReq mshr miss latency 1576system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8775.237127 # average LoadLockedReq mshr miss latency 1577system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8775.237127 # average LoadLockedReq mshr miss latency 1578system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10377.215190 # average StoreCondReq mshr miss latency 1579system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10377.215190 # average StoreCondReq mshr miss latency 1580system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency 1581system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency 1582system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16465.871048 # average overall mshr miss latency 1583system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16465.871048 # average overall mshr miss latency 1584system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1585system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1586system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1587system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1588system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1589system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1590system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1591system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1592system.cpu0.kern.inst.quiesce 4916 # number of quiesce instructions executed 1593system.cpu0.kern.inst.hwrei 189249 # number of hwrei instructions executed 1594system.cpu0.kern.ipl_count::0 67157 40.25% 40.25% # number of times we switched to this ipl 1595system.cpu0.kern.ipl_count::21 237 0.14% 40.40% # number of times we switched to this ipl 1596system.cpu0.kern.ipl_count::22 1923 1.15% 41.55% # number of times we switched to this ipl 1597system.cpu0.kern.ipl_count::30 121 0.07% 41.62% # number of times we switched to this ipl 1598system.cpu0.kern.ipl_count::31 97397 58.38% 100.00% # number of times we switched to this ipl 1599system.cpu0.kern.ipl_count::total 166835 # number of times we switched to this ipl 1600system.cpu0.kern.ipl_good::0 65800 49.19% 49.19% # number of times we switched to this ipl from a different ipl 1601system.cpu0.kern.ipl_good::21 237 0.18% 49.37% # number of times we switched to this ipl from a different ipl 1602system.cpu0.kern.ipl_good::22 1923 1.44% 50.81% # number of times we switched to this ipl from a different ipl 1603system.cpu0.kern.ipl_good::30 121 0.09% 50.90% # number of times we switched to this ipl from a different ipl 1604system.cpu0.kern.ipl_good::31 65679 49.10% 100.00% # number of times we switched to this ipl from a different ipl 1605system.cpu0.kern.ipl_good::total 133760 # number of times we switched to this ipl from a different ipl 1606system.cpu0.kern.ipl_ticks::0 1863324430000 98.10% 98.10% # number of cycles we spent at this ipl 1607system.cpu0.kern.ipl_ticks::21 91299000 0.00% 98.11% # number of cycles we spent at this ipl 1608system.cpu0.kern.ipl_ticks::22 390735500 0.02% 98.13% # number of cycles we spent at this ipl 1609system.cpu0.kern.ipl_ticks::30 47295500 0.00% 98.13% # number of cycles we spent at this ipl 1610system.cpu0.kern.ipl_ticks::31 35546879500 1.87% 100.00% # number of cycles we spent at this ipl 1611system.cpu0.kern.ipl_ticks::total 1899400639500 # number of cycles we spent at this ipl 1612system.cpu0.kern.ipl_used::0 0.979794 # fraction of swpipl calls that actually changed the ipl 1613system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1614system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1615system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1616system.cpu0.kern.ipl_used::31 0.674343 # fraction of swpipl calls that actually changed the ipl 1617system.cpu0.kern.ipl_used::total 0.801750 # fraction of swpipl calls that actually changed the ipl 1618system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed 1619system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed 1620system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed 1621system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed 1622system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed 1623system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed 1624system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed 1625system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed 1626system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed 1627system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed 1628system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed 1629system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed 1630system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed 1631system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed 1632system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed 1633system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed 1634system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed 1635system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed 1636system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed 1637system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed 1638system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed 1639system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed 1640system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed 1641system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed 1642system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed 1643system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed 1644system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed 1645system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed 1646system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed 1647system.cpu0.kern.syscall::total 209 # number of syscalls executed 1648system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1649system.cpu0.kern.callpal::wripir 205 0.12% 0.12% # number of callpals executed 1650system.cpu0.kern.callpal::wrmces 1 0.00% 0.12% # number of callpals executed 1651system.cpu0.kern.callpal::wrfen 1 0.00% 0.12% # number of callpals executed 1652system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.12% # number of callpals executed 1653system.cpu0.kern.callpal::swpctx 3713 2.12% 2.24% # number of callpals executed 1654system.cpu0.kern.callpal::tbi 45 0.03% 2.26% # number of callpals executed 1655system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed 1656system.cpu0.kern.callpal::swpipl 159757 91.11% 93.38% # number of callpals executed 1657system.cpu0.kern.callpal::rdps 6320 3.60% 96.98% # number of callpals executed 1658system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed 1659system.cpu0.kern.callpal::wrusp 2 0.00% 96.98% # number of callpals executed 1660system.cpu0.kern.callpal::rdusp 8 0.00% 96.99% # number of callpals executed 1661system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed 1662system.cpu0.kern.callpal::rti 4796 2.74% 99.73% # number of callpals executed 1663system.cpu0.kern.callpal::callsys 348 0.20% 99.92% # number of callpals executed 1664system.cpu0.kern.callpal::imb 134 0.08% 100.00% # number of callpals executed 1665system.cpu0.kern.callpal::total 175342 # number of callpals executed 1666system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches 1667system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches 1668system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1669system.cpu0.kern.mode_good::kernel 1161 1670system.cpu0.kern.mode_good::user 1162 1671system.cpu0.kern.mode_good::idle 0 1672system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches 1673system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1674system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 1675system.cpu0.kern.mode_switch_good::total 0.278972 # fraction of useful protection mode switches 1676system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode 1677system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode 1678system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1679system.cpu0.kern.swap_context 3714 # number of times the context was actually changed 1680system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1681system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed 1682system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed 1683system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl 1684system.cpu1.kern.ipl_count::22 1921 4.71% 41.54% # number of times we switched to this ipl 1685system.cpu1.kern.ipl_count::30 205 0.50% 42.04% # number of times we switched to this ipl 1686system.cpu1.kern.ipl_count::31 23643 57.96% 100.00% # number of times we switched to this ipl 1687system.cpu1.kern.ipl_count::total 40791 # number of times we switched to this ipl 1688system.cpu1.kern.ipl_good::0 15002 46.99% 46.99% # number of times we switched to this ipl from a different ipl 1689system.cpu1.kern.ipl_good::22 1921 6.02% 53.01% # number of times we switched to this ipl from a different ipl 1690system.cpu1.kern.ipl_good::30 205 0.64% 53.65% # number of times we switched to this ipl from a different ipl 1691system.cpu1.kern.ipl_good::31 14797 46.35% 100.00% # number of times we switched to this ipl from a different ipl 1692system.cpu1.kern.ipl_good::total 31925 # number of times we switched to this ipl from a different ipl 1693system.cpu1.kern.ipl_ticks::0 1870054566000 98.47% 98.47% # number of cycles we spent at this ipl 1694system.cpu1.kern.ipl_ticks::22 345480500 0.02% 98.49% # number of cycles we spent at this ipl 1695system.cpu1.kern.ipl_ticks::30 82493000 0.00% 98.49% # number of cycles we spent at this ipl 1696system.cpu1.kern.ipl_ticks::31 28594480500 1.51% 100.00% # number of cycles we spent at this ipl 1697system.cpu1.kern.ipl_ticks::total 1899077020000 # number of cycles we spent at this ipl 1698system.cpu1.kern.ipl_used::0 0.998669 # fraction of swpipl calls that actually changed the ipl 1699system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1700system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1701system.cpu1.kern.ipl_used::31 0.625851 # fraction of swpipl calls that actually changed the ipl 1702system.cpu1.kern.ipl_used::total 0.782648 # fraction of swpipl calls that actually changed the ipl 1703system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed 1704system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed 1705system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed 1706system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed 1707system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed 1708system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed 1709system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed 1710system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed 1711system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed 1712system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed 1713system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed 1714system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed 1715system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed 1716system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed 1717system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed 1718system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed 1719system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed 1720system.cpu1.kern.syscall::total 117 # number of syscalls executed 1721system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1722system.cpu1.kern.callpal::wripir 121 0.29% 0.29% # number of callpals executed 1723system.cpu1.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed 1724system.cpu1.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed 1725system.cpu1.kern.callpal::swpctx 734 1.74% 2.03% # number of callpals executed 1726system.cpu1.kern.callpal::tbi 9 0.02% 2.05% # number of callpals executed 1727system.cpu1.kern.callpal::wrent 7 0.02% 2.07% # number of callpals executed 1728system.cpu1.kern.callpal::swpipl 35949 85.20% 87.27% # number of callpals executed 1729system.cpu1.kern.callpal::rdps 2433 5.77% 93.03% # number of callpals executed 1730system.cpu1.kern.callpal::wrkgp 1 0.00% 93.03% # number of callpals executed 1731system.cpu1.kern.callpal::wrusp 5 0.01% 93.05% # number of callpals executed 1732system.cpu1.kern.callpal::rdusp 1 0.00% 93.05% # number of callpals executed 1733system.cpu1.kern.callpal::whami 3 0.01% 93.06% # number of callpals executed 1734system.cpu1.kern.callpal::rti 2715 6.43% 99.49% # number of callpals executed 1735system.cpu1.kern.callpal::callsys 167 0.40% 99.89% # number of callpals executed 1736system.cpu1.kern.callpal::imb 47 0.11% 100.00% # number of callpals executed 1737system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1738system.cpu1.kern.callpal::total 42196 # number of callpals executed 1739system.cpu1.kern.mode_switch::kernel 1189 # number of protection mode switches 1740system.cpu1.kern.mode_switch::user 578 # number of protection mode switches 1741system.cpu1.kern.mode_switch::idle 2262 # number of protection mode switches 1742system.cpu1.kern.mode_good::kernel 747 1743system.cpu1.kern.mode_good::user 578 1744system.cpu1.kern.mode_good::idle 169 1745system.cpu1.kern.mode_switch_good::kernel 0.628259 # fraction of useful protection mode switches 1746system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1747system.cpu1.kern.mode_switch_good::idle 0.074713 # fraction of useful protection mode switches 1748system.cpu1.kern.mode_switch_good::total 0.370812 # fraction of useful protection mode switches 1749system.cpu1.kern.mode_ticks::kernel 33800928000 1.78% 1.78% # number of ticks spent at the given mode 1750system.cpu1.kern.mode_ticks::user 913024000 0.05% 1.83% # number of ticks spent at the given mode 1751system.cpu1.kern.mode_ticks::idle 1864011788000 98.17% 100.00% # number of ticks spent at the given mode 1752system.cpu1.kern.swap_context 735 # number of times the context was actually changed 1753 1754---------- End Simulation Statistics ---------- 1755