stats.txt revision 8835:7c68f84d7c4e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.897465 # Number of seconds simulated 4sim_ticks 1897464893500 # Number of ticks simulated 5final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 189830 # Simulator instruction rate (inst/s) 8host_op_rate 189830 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6418636186 # Simulator tick rate (ticks/s) 10host_mem_usage 296280 # Number of bytes of host memory used 11host_seconds 295.62 # Real time elapsed on the host 12sim_insts 56117221 # Number of instructions simulated 13sim_ops 56117221 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30408512 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10470144 # Number of bytes written to this memory 17system.physmem.num_reads 475133 # Number of read requests responded to by this memory 18system.physmem.num_writes 163596 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) 24system.l2c.replacements 397850 # number of replacements 25system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use 26system.l2c.total_refs 2482376 # Total number of references to valid blocks. 27system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. 28system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor 32system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor 33system.l2c.occ_blocks::cpu1.inst 126.484558 # Average occupied blocks per requestor 34system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor 35system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy 36system.l2c.occ_percent::cpu0.inst 0.062074 # Average percentage of cache occupancy 37system.l2c.occ_percent::cpu0.data 0.121117 # Average percentage of cache occupancy 38system.l2c.occ_percent::cpu1.inst 0.001930 # Average percentage of cache occupancy 39system.l2c.occ_percent::cpu1.data 0.001694 # Average percentage of cache occupancy 40system.l2c.occ_percent::total 0.535733 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::cpu0.inst 955732 # number of ReadReq hits 42system.l2c.ReadReq_hits::cpu0.data 764474 # number of ReadReq hits 43system.l2c.ReadReq_hits::cpu1.inst 109195 # number of ReadReq hits 44system.l2c.ReadReq_hits::cpu1.data 38109 # number of ReadReq hits 45system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits 46system.l2c.Writeback_hits::writebacks 827202 # number of Writeback hits 47system.l2c.Writeback_hits::total 827202 # number of Writeback hits 48system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits 49system.l2c.UpgradeReq_hits::cpu1.data 45 # number of UpgradeReq hits 50system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits 51system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits 52system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits 53system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits 54system.l2c.ReadExReq_hits::cpu0.data 168180 # number of ReadExReq hits 55system.l2c.ReadExReq_hits::cpu1.data 11095 # number of ReadExReq hits 56system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits 57system.l2c.demand_hits::cpu0.inst 955732 # number of demand (read+write) hits 58system.l2c.demand_hits::cpu0.data 932654 # number of demand (read+write) hits 59system.l2c.demand_hits::cpu1.inst 109195 # number of demand (read+write) hits 60system.l2c.demand_hits::cpu1.data 49204 # number of demand (read+write) hits 61system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits 62system.l2c.overall_hits::cpu0.inst 955732 # number of overall hits 63system.l2c.overall_hits::cpu0.data 932654 # number of overall hits 64system.l2c.overall_hits::cpu1.inst 109195 # number of overall hits 65system.l2c.overall_hits::cpu1.data 49204 # number of overall hits 66system.l2c.overall_hits::total 2046785 # number of overall hits 67system.l2c.ReadReq_misses::cpu0.inst 15234 # number of ReadReq misses 68system.l2c.ReadReq_misses::cpu0.data 290346 # number of ReadReq misses 69system.l2c.ReadReq_misses::cpu1.inst 1960 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu1.data 2086 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses 72system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::cpu1.data 562 # number of UpgradeReq misses 74system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses 75system.l2c.SCUpgradeReq_misses::cpu0.data 45 # number of SCUpgradeReq misses 76system.l2c.SCUpgradeReq_misses::cpu1.data 84 # number of SCUpgradeReq misses 77system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses 78system.l2c.ReadExReq_misses::cpu0.data 113888 # number of ReadExReq misses 79system.l2c.ReadExReq_misses::cpu1.data 10746 # number of ReadExReq misses 80system.l2c.ReadExReq_misses::total 124634 # number of ReadExReq misses 81system.l2c.demand_misses::cpu0.inst 15234 # number of demand (read+write) misses 82system.l2c.demand_misses::cpu0.data 404234 # number of demand (read+write) misses 83system.l2c.demand_misses::cpu1.inst 1960 # number of demand (read+write) misses 84system.l2c.demand_misses::cpu1.data 12832 # number of demand (read+write) misses 85system.l2c.demand_misses::total 434260 # number of demand (read+write) misses 86system.l2c.overall_misses::cpu0.inst 15234 # number of overall misses 87system.l2c.overall_misses::cpu0.data 404234 # number of overall misses 88system.l2c.overall_misses::cpu1.inst 1960 # number of overall misses 89system.l2c.overall_misses::cpu1.data 12832 # number of overall misses 90system.l2c.overall_misses::total 434260 # number of overall misses 91system.l2c.ReadReq_miss_latency::cpu0.inst 796850500 # number of ReadReq miss cycles 92system.l2c.ReadReq_miss_latency::cpu0.data 15107982000 # number of ReadReq miss cycles 93system.l2c.ReadReq_miss_latency::cpu1.inst 102548000 # number of ReadReq miss cycles 94system.l2c.ReadReq_miss_latency::cpu1.data 110604500 # number of ReadReq miss cycles 95system.l2c.ReadReq_miss_latency::total 16117985000 # number of ReadReq miss cycles 96system.l2c.UpgradeReq_miss_latency::cpu0.data 2465000 # number of UpgradeReq miss cycles 97system.l2c.UpgradeReq_miss_latency::cpu1.data 1619000 # number of UpgradeReq miss cycles 98system.l2c.UpgradeReq_miss_latency::total 4084000 # number of UpgradeReq miss cycles 99system.l2c.SCUpgradeReq_miss_latency::cpu0.data 420000 # number of SCUpgradeReq miss cycles 100system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209500 # number of SCUpgradeReq miss cycles 101system.l2c.SCUpgradeReq_miss_latency::total 629500 # number of SCUpgradeReq miss cycles 102system.l2c.ReadExReq_miss_latency::cpu0.data 5974507500 # number of ReadExReq miss cycles 103system.l2c.ReadExReq_miss_latency::cpu1.data 563694000 # number of ReadExReq miss cycles 104system.l2c.ReadExReq_miss_latency::total 6538201500 # number of ReadExReq miss cycles 105system.l2c.demand_miss_latency::cpu0.inst 796850500 # number of demand (read+write) miss cycles 106system.l2c.demand_miss_latency::cpu0.data 21082489500 # number of demand (read+write) miss cycles 107system.l2c.demand_miss_latency::cpu1.inst 102548000 # number of demand (read+write) miss cycles 108system.l2c.demand_miss_latency::cpu1.data 674298500 # number of demand (read+write) miss cycles 109system.l2c.demand_miss_latency::total 22656186500 # number of demand (read+write) miss cycles 110system.l2c.overall_miss_latency::cpu0.inst 796850500 # number of overall miss cycles 111system.l2c.overall_miss_latency::cpu0.data 21082489500 # number of overall miss cycles 112system.l2c.overall_miss_latency::cpu1.inst 102548000 # number of overall miss cycles 113system.l2c.overall_miss_latency::cpu1.data 674298500 # number of overall miss cycles 114system.l2c.overall_miss_latency::total 22656186500 # number of overall miss cycles 115system.l2c.ReadReq_accesses::cpu0.inst 970966 # number of ReadReq accesses(hits+misses) 116system.l2c.ReadReq_accesses::cpu0.data 1054820 # number of ReadReq accesses(hits+misses) 117system.l2c.ReadReq_accesses::cpu1.inst 111155 # number of ReadReq accesses(hits+misses) 118system.l2c.ReadReq_accesses::cpu1.data 40195 # number of ReadReq accesses(hits+misses) 119system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses) 120system.l2c.Writeback_accesses::writebacks 827202 # number of Writeback accesses(hits+misses) 121system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses) 122system.l2c.UpgradeReq_accesses::cpu0.data 2622 # number of UpgradeReq accesses(hits+misses) 123system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 124system.l2c.UpgradeReq_accesses::total 3229 # number of UpgradeReq accesses(hits+misses) 125system.l2c.SCUpgradeReq_accesses::cpu0.data 74 # number of SCUpgradeReq accesses(hits+misses) 126system.l2c.SCUpgradeReq_accesses::cpu1.data 111 # number of SCUpgradeReq accesses(hits+misses) 127system.l2c.SCUpgradeReq_accesses::total 185 # number of SCUpgradeReq accesses(hits+misses) 128system.l2c.ReadExReq_accesses::cpu0.data 282068 # number of ReadExReq accesses(hits+misses) 129system.l2c.ReadExReq_accesses::cpu1.data 21841 # number of ReadExReq accesses(hits+misses) 130system.l2c.ReadExReq_accesses::total 303909 # number of ReadExReq accesses(hits+misses) 131system.l2c.demand_accesses::cpu0.inst 970966 # number of demand (read+write) accesses 132system.l2c.demand_accesses::cpu0.data 1336888 # number of demand (read+write) accesses 133system.l2c.demand_accesses::cpu1.inst 111155 # number of demand (read+write) accesses 134system.l2c.demand_accesses::cpu1.data 62036 # number of demand (read+write) accesses 135system.l2c.demand_accesses::total 2481045 # number of demand (read+write) accesses 136system.l2c.overall_accesses::cpu0.inst 970966 # number of overall (read+write) accesses 137system.l2c.overall_accesses::cpu0.data 1336888 # number of overall (read+write) accesses 138system.l2c.overall_accesses::cpu1.inst 111155 # number of overall (read+write) accesses 139system.l2c.overall_accesses::cpu1.data 62036 # number of overall (read+write) accesses 140system.l2c.overall_accesses::total 2481045 # number of overall (read+write) accesses 141system.l2c.ReadReq_miss_rate::cpu0.inst 0.015690 # miss rate for ReadReq accesses 142system.l2c.ReadReq_miss_rate::cpu0.data 0.275256 # miss rate for ReadReq accesses 143system.l2c.ReadReq_miss_rate::cpu1.inst 0.017633 # miss rate for ReadReq accesses 144system.l2c.ReadReq_miss_rate::cpu1.data 0.051897 # miss rate for ReadReq accesses 145system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933257 # miss rate for UpgradeReq accesses 146system.l2c.UpgradeReq_miss_rate::cpu1.data 0.925865 # miss rate for UpgradeReq accesses 147system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.608108 # miss rate for SCUpgradeReq accesses 148system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756757 # miss rate for SCUpgradeReq accesses 149system.l2c.ReadExReq_miss_rate::cpu0.data 0.403761 # miss rate for ReadExReq accesses 150system.l2c.ReadExReq_miss_rate::cpu1.data 0.492010 # miss rate for ReadExReq accesses 151system.l2c.demand_miss_rate::cpu0.inst 0.015690 # miss rate for demand accesses 152system.l2c.demand_miss_rate::cpu0.data 0.302369 # miss rate for demand accesses 153system.l2c.demand_miss_rate::cpu1.inst 0.017633 # miss rate for demand accesses 154system.l2c.demand_miss_rate::cpu1.data 0.206848 # miss rate for demand accesses 155system.l2c.overall_miss_rate::cpu0.inst 0.015690 # miss rate for overall accesses 156system.l2c.overall_miss_rate::cpu0.data 0.302369 # miss rate for overall accesses 157system.l2c.overall_miss_rate::cpu1.inst 0.017633 # miss rate for overall accesses 158system.l2c.overall_miss_rate::cpu1.data 0.206848 # miss rate for overall accesses 159system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52307.371669 # average ReadReq miss latency 160system.l2c.ReadReq_avg_miss_latency::cpu0.data 52034.407224 # average ReadReq miss latency 161system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52320.408163 # average ReadReq miss latency 162system.l2c.ReadReq_avg_miss_latency::cpu1.data 53022.291467 # average ReadReq miss latency 163system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1007.355946 # average UpgradeReq miss latency 164system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2880.782918 # average UpgradeReq miss latency 165system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9333.333333 # average SCUpgradeReq miss latency 166system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2494.047619 # average SCUpgradeReq miss latency 167system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52459.499684 # average ReadExReq miss latency 168system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52456.169738 # average ReadExReq miss latency 169system.l2c.demand_avg_miss_latency::cpu0.inst 52307.371669 # average overall miss latency 170system.l2c.demand_avg_miss_latency::cpu0.data 52154.171841 # average overall miss latency 171system.l2c.demand_avg_miss_latency::cpu1.inst 52320.408163 # average overall miss latency 172system.l2c.demand_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency 173system.l2c.overall_avg_miss_latency::cpu0.inst 52307.371669 # average overall miss latency 174system.l2c.overall_avg_miss_latency::cpu0.data 52154.171841 # average overall miss latency 175system.l2c.overall_avg_miss_latency::cpu1.inst 52320.408163 # average overall miss latency 176system.l2c.overall_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency 177system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 180system.l2c.blocked::no_targets 0 # number of cycles access was blocked 181system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 182system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 183system.l2c.fast_writes 0 # number of fast writes performed 184system.l2c.cache_copies 0 # number of cache copies performed 185system.l2c.writebacks::writebacks 122076 # number of writebacks 186system.l2c.writebacks::total 122076 # number of writebacks 187system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 188system.l2c.ReadReq_mshr_hits::cpu1.data 2 # number of ReadReq MSHR hits 189system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 190system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 191system.l2c.demand_mshr_hits::cpu1.data 2 # number of demand (read+write) MSHR hits 192system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 193system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 194system.l2c.overall_mshr_hits::cpu1.data 2 # number of overall MSHR hits 195system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 196system.l2c.ReadReq_mshr_misses::cpu0.inst 15234 # number of ReadReq MSHR misses 197system.l2c.ReadReq_mshr_misses::cpu0.data 290346 # number of ReadReq MSHR misses 198system.l2c.ReadReq_mshr_misses::cpu1.inst 1944 # number of ReadReq MSHR misses 199system.l2c.ReadReq_mshr_misses::cpu1.data 2084 # number of ReadReq MSHR misses 200system.l2c.ReadReq_mshr_misses::total 309608 # number of ReadReq MSHR misses 201system.l2c.UpgradeReq_mshr_misses::cpu0.data 2447 # number of UpgradeReq MSHR misses 202system.l2c.UpgradeReq_mshr_misses::cpu1.data 562 # number of UpgradeReq MSHR misses 203system.l2c.UpgradeReq_mshr_misses::total 3009 # number of UpgradeReq MSHR misses 204system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 45 # number of SCUpgradeReq MSHR misses 205system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 84 # number of SCUpgradeReq MSHR misses 206system.l2c.SCUpgradeReq_mshr_misses::total 129 # number of SCUpgradeReq MSHR misses 207system.l2c.ReadExReq_mshr_misses::cpu0.data 113888 # number of ReadExReq MSHR misses 208system.l2c.ReadExReq_mshr_misses::cpu1.data 10746 # number of ReadExReq MSHR misses 209system.l2c.ReadExReq_mshr_misses::total 124634 # number of ReadExReq MSHR misses 210system.l2c.demand_mshr_misses::cpu0.inst 15234 # number of demand (read+write) MSHR misses 211system.l2c.demand_mshr_misses::cpu0.data 404234 # number of demand (read+write) MSHR misses 212system.l2c.demand_mshr_misses::cpu1.inst 1944 # number of demand (read+write) MSHR misses 213system.l2c.demand_mshr_misses::cpu1.data 12830 # number of demand (read+write) MSHR misses 214system.l2c.demand_mshr_misses::total 434242 # number of demand (read+write) MSHR misses 215system.l2c.overall_mshr_misses::cpu0.inst 15234 # number of overall MSHR misses 216system.l2c.overall_mshr_misses::cpu0.data 404234 # number of overall MSHR misses 217system.l2c.overall_mshr_misses::cpu1.inst 1944 # number of overall MSHR misses 218system.l2c.overall_mshr_misses::cpu1.data 12830 # number of overall MSHR misses 219system.l2c.overall_mshr_misses::total 434242 # number of overall MSHR misses 220system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 610356500 # number of ReadReq MSHR miss cycles 221system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11621105000 # number of ReadReq MSHR miss cycles 222system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 77934000 # number of ReadReq MSHR miss cycles 223system.l2c.ReadReq_mshr_miss_latency::cpu1.data 85027000 # number of ReadReq MSHR miss cycles 224system.l2c.ReadReq_mshr_miss_latency::total 12394422500 # number of ReadReq MSHR miss cycles 225system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97946500 # number of UpgradeReq MSHR miss cycles 226system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22482000 # number of UpgradeReq MSHR miss cycles 227system.l2c.UpgradeReq_mshr_miss_latency::total 120428500 # number of UpgradeReq MSHR miss cycles 228system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1801500 # number of SCUpgradeReq MSHR miss cycles 229system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3360000 # number of SCUpgradeReq MSHR miss cycles 230system.l2c.SCUpgradeReq_mshr_miss_latency::total 5161500 # number of SCUpgradeReq MSHR miss cycles 231system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4590092500 # number of ReadExReq MSHR miss cycles 232system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 432485500 # number of ReadExReq MSHR miss cycles 233system.l2c.ReadExReq_mshr_miss_latency::total 5022578000 # number of ReadExReq MSHR miss cycles 234system.l2c.demand_mshr_miss_latency::cpu0.inst 610356500 # number of demand (read+write) MSHR miss cycles 235system.l2c.demand_mshr_miss_latency::cpu0.data 16211197500 # number of demand (read+write) MSHR miss cycles 236system.l2c.demand_mshr_miss_latency::cpu1.inst 77934000 # number of demand (read+write) MSHR miss cycles 237system.l2c.demand_mshr_miss_latency::cpu1.data 517512500 # number of demand (read+write) MSHR miss cycles 238system.l2c.demand_mshr_miss_latency::total 17417000500 # number of demand (read+write) MSHR miss cycles 239system.l2c.overall_mshr_miss_latency::cpu0.inst 610356500 # number of overall MSHR miss cycles 240system.l2c.overall_mshr_miss_latency::cpu0.data 16211197500 # number of overall MSHR miss cycles 241system.l2c.overall_mshr_miss_latency::cpu1.inst 77934000 # number of overall MSHR miss cycles 242system.l2c.overall_mshr_miss_latency::cpu1.data 517512500 # number of overall MSHR miss cycles 243system.l2c.overall_mshr_miss_latency::total 17417000500 # number of overall MSHR miss cycles 244system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 821008500 # number of ReadReq MSHR uncacheable cycles 245system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17113500 # number of ReadReq MSHR uncacheable cycles 246system.l2c.ReadReq_mshr_uncacheable_latency::total 838122000 # number of ReadReq MSHR uncacheable cycles 247system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1130592498 # number of WriteReq MSHR uncacheable cycles 248system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 289769000 # number of WriteReq MSHR uncacheable cycles 249system.l2c.WriteReq_mshr_uncacheable_latency::total 1420361498 # number of WriteReq MSHR uncacheable cycles 250system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1951600998 # number of overall MSHR uncacheable cycles 251system.l2c.overall_mshr_uncacheable_latency::cpu1.data 306882500 # number of overall MSHR uncacheable cycles 252system.l2c.overall_mshr_uncacheable_latency::total 2258483498 # number of overall MSHR uncacheable cycles 253system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for ReadReq accesses 254system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275256 # mshr miss rate for ReadReq accesses 255system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for ReadReq accesses 256system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051847 # mshr miss rate for ReadReq accesses 257system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933257 # mshr miss rate for UpgradeReq accesses 258system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.925865 # mshr miss rate for UpgradeReq accesses 259system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.608108 # mshr miss rate for SCUpgradeReq accesses 260system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.756757 # mshr miss rate for SCUpgradeReq accesses 261system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.403761 # mshr miss rate for ReadExReq accesses 262system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.492010 # mshr miss rate for ReadExReq accesses 263system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for demand accesses 264system.l2c.demand_mshr_miss_rate::cpu0.data 0.302369 # mshr miss rate for demand accesses 265system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for demand accesses 266system.l2c.demand_mshr_miss_rate::cpu1.data 0.206815 # mshr miss rate for demand accesses 267system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015690 # mshr miss rate for overall accesses 268system.l2c.overall_mshr_miss_rate::cpu0.data 0.302369 # mshr miss rate for overall accesses 269system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017489 # mshr miss rate for overall accesses 270system.l2c.overall_mshr_miss_rate::cpu1.data 0.206815 # mshr miss rate for overall accesses 271system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average ReadReq mshr miss latency 272system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40025.021870 # average ReadReq mshr miss latency 273system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average ReadReq mshr miss latency 274system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40799.904031 # average ReadReq mshr miss latency 275system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40027.176134 # average UpgradeReq mshr miss latency 276system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.558719 # average UpgradeReq mshr miss latency 277system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40033.333333 # average SCUpgradeReq mshr miss latency 278system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency 279system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40303.565784 # average ReadExReq mshr miss latency 280system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40246.184627 # average ReadExReq mshr miss latency 281system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average overall mshr miss latency 282system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.498221 # average overall mshr miss latency 283system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average overall mshr miss latency 284system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40336.126267 # average overall mshr miss latency 285system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.412892 # average overall mshr miss latency 286system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.498221 # average overall mshr miss latency 287system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40089.506173 # average overall mshr miss latency 288system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40336.126267 # average overall mshr miss latency 289system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 290system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 291system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 292system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 293system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 294system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 295system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 296system.iocache.replacements 41697 # number of replacements 297system.iocache.tagsinuse 0.463236 # Cycle average of tags in use 298system.iocache.total_refs 0 # Total number of references to valid blocks. 299system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. 300system.iocache.avg_refs 0 # Average number of references to valid blocks. 301system.iocache.warmup_cycle 1709322783000 # Cycle when the warmup percentage was hit. 302system.iocache.occ_blocks::tsunami.ide 0.463236 # Average occupied blocks per requestor 303system.iocache.occ_percent::tsunami.ide 0.028952 # Average percentage of cache occupancy 304system.iocache.occ_percent::total 0.028952 # Average percentage of cache occupancy 305system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses 306system.iocache.ReadReq_misses::total 177 # number of ReadReq misses 307system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 308system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 309system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses 310system.iocache.demand_misses::total 41729 # number of demand (read+write) misses 311system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses 312system.iocache.overall_misses::total 41729 # number of overall misses 313system.iocache.ReadReq_miss_latency::tsunami.ide 20391998 # number of ReadReq miss cycles 314system.iocache.ReadReq_miss_latency::total 20391998 # number of ReadReq miss cycles 315system.iocache.WriteReq_miss_latency::tsunami.ide 5720293806 # number of WriteReq miss cycles 316system.iocache.WriteReq_miss_latency::total 5720293806 # number of WriteReq miss cycles 317system.iocache.demand_miss_latency::tsunami.ide 5740685804 # number of demand (read+write) miss cycles 318system.iocache.demand_miss_latency::total 5740685804 # number of demand (read+write) miss cycles 319system.iocache.overall_miss_latency::tsunami.ide 5740685804 # number of overall miss cycles 320system.iocache.overall_miss_latency::total 5740685804 # number of overall miss cycles 321system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) 322system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) 323system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 324system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 325system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses 326system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses 327system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses 328system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses 329system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 330system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 331system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 332system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 333system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115209.028249 # average ReadReq miss latency 334system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.907923 # average WriteReq miss latency 335system.iocache.demand_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency 336system.iocache.overall_avg_miss_latency::tsunami.ide 137570.653598 # average overall miss latency 337system.iocache.blocked_cycles::no_mshrs 64638062 # number of cycles access was blocked 338system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 339system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked 340system.iocache.blocked::no_targets 0 # number of cycles access was blocked 341system.iocache.avg_blocked_cycles::no_mshrs 6181.319881 # average number of cycles each access was blocked 342system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 343system.iocache.fast_writes 0 # number of fast writes performed 344system.iocache.cache_copies 0 # number of cache copies performed 345system.iocache.writebacks::writebacks 41520 # number of writebacks 346system.iocache.writebacks::total 41520 # number of writebacks 347system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 348system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses 349system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 350system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 351system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses 352system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses 353system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses 354system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses 355system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11187998 # number of ReadReq MSHR miss cycles 356system.iocache.ReadReq_mshr_miss_latency::total 11187998 # number of ReadReq MSHR miss cycles 357system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559436992 # number of WriteReq MSHR miss cycles 358system.iocache.WriteReq_mshr_miss_latency::total 3559436992 # number of WriteReq MSHR miss cycles 359system.iocache.demand_mshr_miss_latency::tsunami.ide 3570624990 # number of demand (read+write) MSHR miss cycles 360system.iocache.demand_mshr_miss_latency::total 3570624990 # number of demand (read+write) MSHR miss cycles 361system.iocache.overall_mshr_miss_latency::tsunami.ide 3570624990 # number of overall MSHR miss cycles 362system.iocache.overall_mshr_miss_latency::total 3570624990 # number of overall MSHR miss cycles 363system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 364system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 365system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 366system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 367system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63209.028249 # average ReadReq mshr miss latency 368system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.230266 # average WriteReq mshr miss latency 369system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency 370system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.991541 # average overall mshr miss latency 371system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 372system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 373system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 374system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 375system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 376system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 377system.disk0.dma_write_txs 395 # Number of DMA write transactions. 378system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 379system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 380system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 381system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 382system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 383system.disk2.dma_write_txs 1 # Number of DMA write transactions. 384system.cpu0.dtb.fetch_hits 0 # ITB hits 385system.cpu0.dtb.fetch_misses 0 # ITB misses 386system.cpu0.dtb.fetch_acv 0 # ITB acv 387system.cpu0.dtb.fetch_accesses 0 # ITB accesses 388system.cpu0.dtb.read_hits 9525013 # DTB read hits 389system.cpu0.dtb.read_misses 35809 # DTB read misses 390system.cpu0.dtb.read_acv 596 # DTB read access violations 391system.cpu0.dtb.read_accesses 640960 # DTB read accesses 392system.cpu0.dtb.write_hits 6193277 # DTB write hits 393system.cpu0.dtb.write_misses 8191 # DTB write misses 394system.cpu0.dtb.write_acv 352 # DTB write access violations 395system.cpu0.dtb.write_accesses 218947 # DTB write accesses 396system.cpu0.dtb.data_hits 15718290 # DTB hits 397system.cpu0.dtb.data_misses 44000 # DTB misses 398system.cpu0.dtb.data_acv 948 # DTB access violations 399system.cpu0.dtb.data_accesses 859907 # DTB accesses 400system.cpu0.itb.fetch_hits 1059968 # ITB hits 401system.cpu0.itb.fetch_misses 28334 # ITB misses 402system.cpu0.itb.fetch_acv 968 # ITB acv 403system.cpu0.itb.fetch_accesses 1088302 # ITB accesses 404system.cpu0.itb.read_hits 0 # DTB read hits 405system.cpu0.itb.read_misses 0 # DTB read misses 406system.cpu0.itb.read_acv 0 # DTB read access violations 407system.cpu0.itb.read_accesses 0 # DTB read accesses 408system.cpu0.itb.write_hits 0 # DTB write hits 409system.cpu0.itb.write_misses 0 # DTB write misses 410system.cpu0.itb.write_acv 0 # DTB write access violations 411system.cpu0.itb.write_accesses 0 # DTB write accesses 412system.cpu0.itb.data_hits 0 # DTB hits 413system.cpu0.itb.data_misses 0 # DTB misses 414system.cpu0.itb.data_acv 0 # DTB access violations 415system.cpu0.itb.data_accesses 0 # DTB accesses 416system.cpu0.numCycles 112143855 # number of cpu cycles simulated 417system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 418system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 419system.cpu0.BPredUnit.lookups 13691834 # Number of BP lookups 420system.cpu0.BPredUnit.condPredicted 11482212 # Number of conditional branches predicted 421system.cpu0.BPredUnit.condIncorrect 486842 # Number of conditional branches incorrect 422system.cpu0.BPredUnit.BTBLookups 12387016 # Number of BTB lookups 423system.cpu0.BPredUnit.BTBHits 6381871 # Number of BTB hits 424system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 425system.cpu0.BPredUnit.usedRAS 919331 # Number of times the RAS was used to get a target. 426system.cpu0.BPredUnit.RASInCorrect 37475 # Number of incorrect RAS predictions. 427system.cpu0.fetch.icacheStallCycles 28027181 # Number of cycles fetch is stalled on an Icache miss 428system.cpu0.fetch.Insts 69568075 # Number of instructions fetch has processed 429system.cpu0.fetch.Branches 13691834 # Number of branches that fetch encountered 430system.cpu0.fetch.predictedBranches 7301202 # Number of branches that fetch has predicted taken 431system.cpu0.fetch.Cycles 13494473 # Number of cycles fetch has run and was not squashing or blocked 432system.cpu0.fetch.SquashCycles 2151438 # Number of cycles fetch has spent squashing 433system.cpu0.fetch.BlockedCycles 34839073 # Number of cycles fetch has spent blocked 434system.cpu0.fetch.MiscStallCycles 31251 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 435system.cpu0.fetch.PendingTrapStallCycles 192820 # Number of stall cycles due to pending traps 436system.cpu0.fetch.PendingQuiesceStallCycles 330609 # Number of stall cycles due to pending quiesce instructions 437system.cpu0.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR 438system.cpu0.fetch.CacheLines 8536872 # Number of cache lines fetched 439system.cpu0.fetch.IcacheSquashes 297084 # Number of outstanding Icache misses that were squashed 440system.cpu0.fetch.rateDist::samples 78309049 # Number of instructions fetched each cycle (Total) 441system.cpu0.fetch.rateDist::mean 0.888378 # Number of instructions fetched each cycle (Total) 442system.cpu0.fetch.rateDist::stdev 2.203941 # Number of instructions fetched each cycle (Total) 443system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 444system.cpu0.fetch.rateDist::0 64814576 82.77% 82.77% # Number of instructions fetched each cycle (Total) 445system.cpu0.fetch.rateDist::1 945457 1.21% 83.98% # Number of instructions fetched each cycle (Total) 446system.cpu0.fetch.rateDist::2 1900376 2.43% 86.40% # Number of instructions fetched each cycle (Total) 447system.cpu0.fetch.rateDist::3 913364 1.17% 87.57% # Number of instructions fetched each cycle (Total) 448system.cpu0.fetch.rateDist::4 2830968 3.62% 91.18% # Number of instructions fetched each cycle (Total) 449system.cpu0.fetch.rateDist::5 643425 0.82% 92.00% # Number of instructions fetched each cycle (Total) 450system.cpu0.fetch.rateDist::6 763526 0.98% 92.98% # Number of instructions fetched each cycle (Total) 451system.cpu0.fetch.rateDist::7 1019235 1.30% 94.28% # Number of instructions fetched each cycle (Total) 452system.cpu0.fetch.rateDist::8 4478122 5.72% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 454system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 455system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 456system.cpu0.fetch.rateDist::total 78309049 # Number of instructions fetched each cycle (Total) 457system.cpu0.fetch.branchRate 0.122092 # Number of branch fetches per cycle 458system.cpu0.fetch.rate 0.620347 # Number of inst fetches per cycle 459system.cpu0.decode.IdleCycles 29152885 # Number of cycles decode is idle 460system.cpu0.decode.BlockedCycles 34531702 # Number of cycles decode is blocked 461system.cpu0.decode.RunCycles 12346249 # Number of cycles decode is running 462system.cpu0.decode.UnblockCycles 922431 # Number of cycles decode is unblocking 463system.cpu0.decode.SquashCycles 1355781 # Number of cycles decode is squashing 464system.cpu0.decode.BranchResolved 563186 # Number of times decode resolved a branch 465system.cpu0.decode.BranchMispred 37995 # Number of times decode detected a branch misprediction 466system.cpu0.decode.DecodedInsts 68107436 # Number of instructions handled by decode 467system.cpu0.decode.SquashedInsts 115019 # Number of squashed instructions handled by decode 468system.cpu0.rename.SquashCycles 1355781 # Number of cycles rename is squashing 469system.cpu0.rename.IdleCycles 30289459 # Number of cycles rename is idle 470system.cpu0.rename.BlockCycles 12441617 # Number of cycles rename is blocking 471system.cpu0.rename.serializeStallCycles 18623001 # count of cycles rename stalled for serializing inst 472system.cpu0.rename.RunCycles 11519994 # Number of cycles rename is running 473system.cpu0.rename.UnblockCycles 4079195 # Number of cycles rename is unblocking 474system.cpu0.rename.RenamedInsts 64318914 # Number of instructions processed by rename 475system.cpu0.rename.ROBFullEvents 6762 # Number of times rename has blocked due to ROB full 476system.cpu0.rename.IQFullEvents 463310 # Number of times rename has blocked due to IQ full 477system.cpu0.rename.LSQFullEvents 1470134 # Number of times rename has blocked due to LSQ full 478system.cpu0.rename.RenamedOperands 43045469 # Number of destination operands rename has renamed 479system.cpu0.rename.RenameLookups 78042276 # Number of register rename lookups that rename has made 480system.cpu0.rename.int_rename_lookups 77610485 # Number of integer rename lookups 481system.cpu0.rename.fp_rename_lookups 431791 # Number of floating rename lookups 482system.cpu0.rename.CommittedMaps 36467151 # Number of HB maps that are committed 483system.cpu0.rename.UndoneMaps 6578318 # Number of HB maps that are undone due to squashing 484system.cpu0.rename.serializingInsts 1575666 # count of serializing insts renamed 485system.cpu0.rename.tempSerializingInsts 238414 # count of temporary serializing insts renamed 486system.cpu0.rename.skidInsts 11470150 # count of insts added to the skid buffer 487system.cpu0.memDep0.insertedLoads 10031617 # Number of loads inserted to the mem dependence unit. 488system.cpu0.memDep0.insertedStores 6527341 # Number of stores inserted to the mem dependence unit. 489system.cpu0.memDep0.conflictingLoads 1189503 # Number of conflicting loads. 490system.cpu0.memDep0.conflictingStores 776121 # Number of conflicting stores. 491system.cpu0.iq.iqInstsAdded 56398484 # Number of instructions added to the IQ (excludes non-spec) 492system.cpu0.iq.iqNonSpecInstsAdded 2006474 # Number of non-speculative instructions added to the IQ 493system.cpu0.iq.iqInstsIssued 54915556 # Number of instructions issued 494system.cpu0.iq.iqSquashedInstsIssued 111021 # Number of squashed instructions issued 495system.cpu0.iq.iqSquashedInstsExamined 7522313 # Number of squashed instructions iterated over during squash; mainly for profiling 496system.cpu0.iq.iqSquashedOperandsExamined 3811151 # Number of squashed operands that are examined and possibly removed from graph 497system.cpu0.iq.iqSquashedNonSpecRemoved 1368811 # Number of squashed non-spec instructions that were removed 498system.cpu0.iq.issued_per_cycle::samples 78309049 # Number of insts issued each cycle 499system.cpu0.iq.issued_per_cycle::mean 0.701267 # Number of insts issued each cycle 500system.cpu0.iq.issued_per_cycle::stdev 1.347671 # Number of insts issued each cycle 501system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 502system.cpu0.iq.issued_per_cycle::0 54156181 69.16% 69.16% # Number of insts issued each cycle 503system.cpu0.iq.issued_per_cycle::1 10641057 13.59% 82.75% # Number of insts issued each cycle 504system.cpu0.iq.issued_per_cycle::2 5191025 6.63% 89.37% # Number of insts issued each cycle 505system.cpu0.iq.issued_per_cycle::3 3329795 4.25% 93.63% # Number of insts issued each cycle 506system.cpu0.iq.issued_per_cycle::4 2517318 3.21% 96.84% # Number of insts issued each cycle 507system.cpu0.iq.issued_per_cycle::5 1471186 1.88% 98.72% # Number of insts issued each cycle 508system.cpu0.iq.issued_per_cycle::6 638979 0.82% 99.54% # Number of insts issued each cycle 509system.cpu0.iq.issued_per_cycle::7 264076 0.34% 99.87% # Number of insts issued each cycle 510system.cpu0.iq.issued_per_cycle::8 99432 0.13% 100.00% # Number of insts issued each cycle 511system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 513system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 514system.cpu0.iq.issued_per_cycle::total 78309049 # Number of insts issued each cycle 515system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 516system.cpu0.iq.fu_full::IntAlu 63169 8.93% 8.93% # attempts to use FU when none available 517system.cpu0.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available 518system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available 519system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available 520system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available 521system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available 522system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available 523system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available 524system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 525system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available 526system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available 527system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available 528system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available 529system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available 530system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available 531system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available 532system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available 533system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available 534system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available 535system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available 536system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available 537system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available 538system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available 539system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available 540system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available 541system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available 542system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available 543system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available 544system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 545system.cpu0.iq.fu_full::MemRead 344330 48.66% 57.59% # attempts to use FU when none available 546system.cpu0.iq.fu_full::MemWrite 300145 42.41% 100.00% # attempts to use FU when none available 547system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu0.iq.FU_type_0::No_OpClass 3325 0.01% 0.01% # Type of FU issued 550system.cpu0.iq.FU_type_0::IntAlu 37729557 68.70% 68.71% # Type of FU issued 551system.cpu0.iq.FU_type_0::IntMult 60298 0.11% 68.82% # Type of FU issued 552system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued 553system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.85% # Type of FU issued 554system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.85% # Type of FU issued 555system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.85% # Type of FU issued 556system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.85% # Type of FU issued 557system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.85% # Type of FU issued 558system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued 559system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued 560system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued 561system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued 562system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued 563system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued 564system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued 565system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued 566system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued 567system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued 568system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued 569system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued 570system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued 571system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued 572system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued 573system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued 574system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued 575system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued 576system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued 577system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued 578system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued 579system.cpu0.iq.FU_type_0::MemRead 9958587 18.13% 86.99% # Type of FU issued 580system.cpu0.iq.FU_type_0::MemWrite 6269977 11.42% 98.40% # Type of FU issued 581system.cpu0.iq.FU_type_0::IprAccess 876476 1.60% 100.00% # Type of FU issued 582system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 583system.cpu0.iq.FU_type_0::total 54915556 # Type of FU issued 584system.cpu0.iq.rate 0.489688 # Inst issue rate 585system.cpu0.iq.fu_busy_cnt 707644 # FU busy when requested 586system.cpu0.iq.fu_busy_rate 0.012886 # FU busy rate (busy events/executed inst) 587system.cpu0.iq.int_inst_queue_reads 188337006 # Number of integer instruction queue reads 588system.cpu0.iq.int_inst_queue_writes 65642365 # Number of integer instruction queue writes 589system.cpu0.iq.int_inst_queue_wakeup_accesses 53492231 # Number of integer instruction queue wakeup accesses 590system.cpu0.iq.fp_inst_queue_reads 621820 # Number of floating instruction queue reads 591system.cpu0.iq.fp_inst_queue_writes 297359 # Number of floating instruction queue writes 592system.cpu0.iq.fp_inst_queue_wakeup_accesses 294491 # Number of floating instruction queue wakeup accesses 593system.cpu0.iq.int_alu_accesses 55293187 # Number of integer alu accesses 594system.cpu0.iq.fp_alu_accesses 326688 # Number of floating point alu accesses 595system.cpu0.iew.lsq.thread0.forwLoads 545095 # Number of loads that had data forwarded from stores 596system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 597system.cpu0.iew.lsq.thread0.squashedLoads 1437170 # Number of loads squashed 598system.cpu0.iew.lsq.thread0.ignoredResponses 14653 # Number of memory responses ignored because the instruction is squashed 599system.cpu0.iew.lsq.thread0.memOrderViolation 12768 # Number of memory ordering violations 600system.cpu0.iew.lsq.thread0.squashedStores 528040 # Number of stores squashed 601system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 602system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 603system.cpu0.iew.lsq.thread0.rescheduledLoads 18971 # Number of loads that were rescheduled 604system.cpu0.iew.lsq.thread0.cacheBlocked 166861 # Number of times an access to memory failed due to the cache being blocked 605system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 606system.cpu0.iew.iewSquashCycles 1355781 # Number of cycles IEW is squashing 607system.cpu0.iew.iewBlockCycles 8686714 # Number of cycles IEW is blocking 608system.cpu0.iew.iewUnblockCycles 606542 # Number of cycles IEW is unblocking 609system.cpu0.iew.iewDispatchedInsts 61919404 # Number of instructions dispatched to IQ 610system.cpu0.iew.iewDispSquashedInsts 833136 # Number of squashed instructions skipped by dispatch 611system.cpu0.iew.iewDispLoadInsts 10031617 # Number of dispatched load instructions 612system.cpu0.iew.iewDispStoreInsts 6527341 # Number of dispatched store instructions 613system.cpu0.iew.iewDispNonSpecInsts 1771520 # Number of dispatched non-speculative instructions 614system.cpu0.iew.iewIQFullEvents 483474 # Number of times the IQ has become full, causing a stall 615system.cpu0.iew.iewLSQFullEvents 10610 # Number of times the LSQ has become full, causing a stall 616system.cpu0.iew.memOrderViolationEvents 12768 # Number of memory order violations 617system.cpu0.iew.predictedTakenIncorrect 354996 # Number of branches that were predicted taken incorrectly 618system.cpu0.iew.predictedNotTakenIncorrect 356258 # Number of branches that were predicted not taken incorrectly 619system.cpu0.iew.branchMispredicts 711254 # Number of branch mispredicts detected at execute 620system.cpu0.iew.iewExecutedInsts 54276592 # Number of executed instructions 621system.cpu0.iew.iewExecLoadInsts 9587869 # Number of load instructions executed 622system.cpu0.iew.iewExecSquashedInsts 638964 # Number of squashed instructions skipped in execute 623system.cpu0.iew.exec_swp 0 # number of swp insts executed 624system.cpu0.iew.exec_nop 3514446 # number of nop insts executed 625system.cpu0.iew.exec_refs 15803723 # number of memory reference insts executed 626system.cpu0.iew.exec_branches 8658040 # Number of branches executed 627system.cpu0.iew.exec_stores 6215854 # Number of stores executed 628system.cpu0.iew.exec_rate 0.483991 # Inst execution rate 629system.cpu0.iew.wb_sent 53903758 # cumulative count of insts sent to commit 630system.cpu0.iew.wb_count 53786722 # cumulative count of insts written-back 631system.cpu0.iew.wb_producers 26555285 # num instructions producing a value 632system.cpu0.iew.wb_consumers 35742632 # num instructions consuming a value 633system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 634system.cpu0.iew.wb_rate 0.479623 # insts written-back per cycle 635system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back 636system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 637system.cpu0.commit.commitCommittedInsts 53643051 # The number of committed instructions 638system.cpu0.commit.commitCommittedOps 53643051 # The number of committed instructions 639system.cpu0.commit.commitSquashedInsts 8183882 # The number of squashed insts skipped by commit 640system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards 641system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted 642system.cpu0.commit.committed_per_cycle::samples 76953268 # Number of insts commited each cycle 643system.cpu0.commit.committed_per_cycle::mean 0.697086 # Number of insts commited each cycle 644system.cpu0.commit.committed_per_cycle::stdev 1.608248 # Number of insts commited each cycle 645system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 646system.cpu0.commit.committed_per_cycle::0 56721555 73.71% 73.71% # Number of insts commited each cycle 647system.cpu0.commit.committed_per_cycle::1 8492436 11.04% 84.74% # Number of insts commited each cycle 648system.cpu0.commit.committed_per_cycle::2 4533561 5.89% 90.64% # Number of insts commited each cycle 649system.cpu0.commit.committed_per_cycle::3 2497224 3.25% 93.88% # Number of insts commited each cycle 650system.cpu0.commit.committed_per_cycle::4 1462149 1.90% 95.78% # Number of insts commited each cycle 651system.cpu0.commit.committed_per_cycle::5 614089 0.80% 96.58% # Number of insts commited each cycle 652system.cpu0.commit.committed_per_cycle::6 448311 0.58% 97.16% # Number of insts commited each cycle 653system.cpu0.commit.committed_per_cycle::7 488630 0.63% 97.80% # Number of insts commited each cycle 654system.cpu0.commit.committed_per_cycle::8 1695313 2.20% 100.00% # Number of insts commited each cycle 655system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 656system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 657system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 658system.cpu0.commit.committed_per_cycle::total 76953268 # Number of insts commited each cycle 659system.cpu0.commit.committedInsts 53643051 # Number of instructions committed 660system.cpu0.commit.committedOps 53643051 # Number of ops (including micro ops) committed 661system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 662system.cpu0.commit.refs 14593748 # Number of memory references committed 663system.cpu0.commit.loads 8594447 # Number of loads committed 664system.cpu0.commit.membars 217509 # Number of memory barriers committed 665system.cpu0.commit.branches 8090596 # Number of branches committed 666system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. 667system.cpu0.commit.int_insts 49625357 # Number of committed integer instructions. 668system.cpu0.commit.function_calls 704226 # Number of function calls committed. 669system.cpu0.commit.bw_lim_events 1695313 # number cycles where commit BW limit reached 670system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 671system.cpu0.rob.rob_reads 136894487 # The number of ROB reads 672system.cpu0.rob.rob_writes 125011331 # The number of ROB writes 673system.cpu0.timesIdled 1231743 # Number of times that the entire CPU went into an idle state and unscheduled itself 674system.cpu0.idleCycles 33834806 # Total number of cycles that the CPU has spent unscheduled due to idling 675system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 676system.cpu0.committedInsts 50529139 # Number of Instructions Simulated 677system.cpu0.committedOps 50529139 # Number of Ops (including micro ops) Simulated 678system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated 679system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction 680system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads 681system.cpu0.ipc 0.450574 # IPC: Instructions Per Cycle 682system.cpu0.ipc_total 0.450574 # IPC: Total IPC of All Threads 683system.cpu0.int_regfile_reads 71166140 # number of integer regfile reads 684system.cpu0.int_regfile_writes 38904534 # number of integer regfile writes 685system.cpu0.fp_regfile_reads 143931 # number of floating regfile reads 686system.cpu0.fp_regfile_writes 146323 # number of floating regfile writes 687system.cpu0.misc_regfile_reads 1862401 # number of misc regfile reads 688system.cpu0.misc_regfile_writes 887781 # number of misc regfile writes 689system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 690system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 691system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 692system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 693system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 694system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 695system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 696system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 697system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 698system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 699system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 700system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 701system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 702system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 703system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 704system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 705system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 706system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 707system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 708system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 709system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 710system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 711system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 712system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 713system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 714system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 715system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 716system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 717system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 718system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 719system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 720system.cpu0.icache.replacements 970410 # number of replacements 721system.cpu0.icache.tagsinuse 510.008513 # Cycle average of tags in use 722system.cpu0.icache.total_refs 7511566 # Total number of references to valid blocks. 723system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks. 724system.cpu0.icache.avg_refs 7.736529 # Average number of references to valid blocks. 725system.cpu0.icache.warmup_cycle 23358767000 # Cycle when the warmup percentage was hit. 726system.cpu0.icache.occ_blocks::cpu0.inst 510.008513 # Average occupied blocks per requestor 727system.cpu0.icache.occ_percent::cpu0.inst 0.996110 # Average percentage of cache occupancy 728system.cpu0.icache.occ_percent::total 0.996110 # Average percentage of cache occupancy 729system.cpu0.icache.ReadReq_hits::cpu0.inst 7511566 # number of ReadReq hits 730system.cpu0.icache.ReadReq_hits::total 7511566 # number of ReadReq hits 731system.cpu0.icache.demand_hits::cpu0.inst 7511566 # number of demand (read+write) hits 732system.cpu0.icache.demand_hits::total 7511566 # number of demand (read+write) hits 733system.cpu0.icache.overall_hits::cpu0.inst 7511566 # number of overall hits 734system.cpu0.icache.overall_hits::total 7511566 # number of overall hits 735system.cpu0.icache.ReadReq_misses::cpu0.inst 1025306 # number of ReadReq misses 736system.cpu0.icache.ReadReq_misses::total 1025306 # number of ReadReq misses 737system.cpu0.icache.demand_misses::cpu0.inst 1025306 # number of demand (read+write) misses 738system.cpu0.icache.demand_misses::total 1025306 # number of demand (read+write) misses 739system.cpu0.icache.overall_misses::cpu0.inst 1025306 # number of overall misses 740system.cpu0.icache.overall_misses::total 1025306 # number of overall misses 741system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15323045497 # number of ReadReq miss cycles 742system.cpu0.icache.ReadReq_miss_latency::total 15323045497 # number of ReadReq miss cycles 743system.cpu0.icache.demand_miss_latency::cpu0.inst 15323045497 # number of demand (read+write) miss cycles 744system.cpu0.icache.demand_miss_latency::total 15323045497 # number of demand (read+write) miss cycles 745system.cpu0.icache.overall_miss_latency::cpu0.inst 15323045497 # number of overall miss cycles 746system.cpu0.icache.overall_miss_latency::total 15323045497 # number of overall miss cycles 747system.cpu0.icache.ReadReq_accesses::cpu0.inst 8536872 # number of ReadReq accesses(hits+misses) 748system.cpu0.icache.ReadReq_accesses::total 8536872 # number of ReadReq accesses(hits+misses) 749system.cpu0.icache.demand_accesses::cpu0.inst 8536872 # number of demand (read+write) accesses 750system.cpu0.icache.demand_accesses::total 8536872 # number of demand (read+write) accesses 751system.cpu0.icache.overall_accesses::cpu0.inst 8536872 # number of overall (read+write) accesses 752system.cpu0.icache.overall_accesses::total 8536872 # number of overall (read+write) accesses 753system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120103 # miss rate for ReadReq accesses 754system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120103 # miss rate for demand accesses 755system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120103 # miss rate for overall accesses 756system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14944.851095 # average ReadReq miss latency 757system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency 758system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14944.851095 # average overall miss latency 759system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked 760system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 761system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked 762system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 763system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533 # average number of cycles each access was blocked 764system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 765system.cpu0.icache.fast_writes 0 # number of fast writes performed 766system.cpu0.icache.cache_copies 0 # number of cache copies performed 767system.cpu0.icache.writebacks::writebacks 220 # number of writebacks 768system.cpu0.icache.writebacks::total 220 # number of writebacks 769system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54249 # number of ReadReq MSHR hits 770system.cpu0.icache.ReadReq_mshr_hits::total 54249 # number of ReadReq MSHR hits 771system.cpu0.icache.demand_mshr_hits::cpu0.inst 54249 # number of demand (read+write) MSHR hits 772system.cpu0.icache.demand_mshr_hits::total 54249 # number of demand (read+write) MSHR hits 773system.cpu0.icache.overall_mshr_hits::cpu0.inst 54249 # number of overall MSHR hits 774system.cpu0.icache.overall_mshr_hits::total 54249 # number of overall MSHR hits 775system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 971057 # number of ReadReq MSHR misses 776system.cpu0.icache.ReadReq_mshr_misses::total 971057 # number of ReadReq MSHR misses 777system.cpu0.icache.demand_mshr_misses::cpu0.inst 971057 # number of demand (read+write) MSHR misses 778system.cpu0.icache.demand_mshr_misses::total 971057 # number of demand (read+write) MSHR misses 779system.cpu0.icache.overall_mshr_misses::cpu0.inst 971057 # number of overall MSHR misses 780system.cpu0.icache.overall_mshr_misses::total 971057 # number of overall MSHR misses 781system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11617533498 # number of ReadReq MSHR miss cycles 782system.cpu0.icache.ReadReq_mshr_miss_latency::total 11617533498 # number of ReadReq MSHR miss cycles 783system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11617533498 # number of demand (read+write) MSHR miss cycles 784system.cpu0.icache.demand_mshr_miss_latency::total 11617533498 # number of demand (read+write) MSHR miss cycles 785system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11617533498 # number of overall MSHR miss cycles 786system.cpu0.icache.overall_mshr_miss_latency::total 11617533498 # number of overall MSHR miss cycles 787system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for ReadReq accesses 788system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for demand accesses 789system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113749 # mshr miss rate for overall accesses 790system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average ReadReq mshr miss latency 791system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency 792system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11963.801814 # average overall mshr miss latency 793system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 794system.cpu0.dcache.replacements 1340651 # number of replacements 795system.cpu0.dcache.tagsinuse 504.872538 # Cycle average of tags in use 796system.cpu0.dcache.total_refs 11358067 # Total number of references to valid blocks. 797system.cpu0.dcache.sampled_refs 1341162 # Sample count of references to valid blocks. 798system.cpu0.dcache.avg_refs 8.468826 # Average number of references to valid blocks. 799system.cpu0.dcache.warmup_cycle 19222000 # Cycle when the warmup percentage was hit. 800system.cpu0.dcache.occ_blocks::cpu0.data 504.872538 # Average occupied blocks per requestor 801system.cpu0.dcache.occ_percent::cpu0.data 0.986079 # Average percentage of cache occupancy 802system.cpu0.dcache.occ_percent::total 0.986079 # Average percentage of cache occupancy 803system.cpu0.dcache.ReadReq_hits::cpu0.data 6993872 # number of ReadReq hits 804system.cpu0.dcache.ReadReq_hits::total 6993872 # number of ReadReq hits 805system.cpu0.dcache.WriteReq_hits::cpu0.data 3966970 # number of WriteReq hits 806system.cpu0.dcache.WriteReq_hits::total 3966970 # number of WriteReq hits 807system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 182544 # number of LoadLockedReq hits 808system.cpu0.dcache.LoadLockedReq_hits::total 182544 # number of LoadLockedReq hits 809system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208490 # number of StoreCondReq hits 810system.cpu0.dcache.StoreCondReq_hits::total 208490 # number of StoreCondReq hits 811system.cpu0.dcache.demand_hits::cpu0.data 10960842 # number of demand (read+write) hits 812system.cpu0.dcache.demand_hits::total 10960842 # number of demand (read+write) hits 813system.cpu0.dcache.overall_hits::cpu0.data 10960842 # number of overall hits 814system.cpu0.dcache.overall_hits::total 10960842 # number of overall hits 815system.cpu0.dcache.ReadReq_misses::cpu0.data 1697480 # number of ReadReq misses 816system.cpu0.dcache.ReadReq_misses::total 1697480 # number of ReadReq misses 817system.cpu0.dcache.WriteReq_misses::cpu0.data 1808304 # number of WriteReq misses 818system.cpu0.dcache.WriteReq_misses::total 1808304 # number of WriteReq misses 819system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21693 # number of LoadLockedReq misses 820system.cpu0.dcache.LoadLockedReq_misses::total 21693 # number of LoadLockedReq misses 821system.cpu0.dcache.StoreCondReq_misses::cpu0.data 688 # number of StoreCondReq misses 822system.cpu0.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses 823system.cpu0.dcache.demand_misses::cpu0.data 3505784 # number of demand (read+write) misses 824system.cpu0.dcache.demand_misses::total 3505784 # number of demand (read+write) misses 825system.cpu0.dcache.overall_misses::cpu0.data 3505784 # number of overall misses 826system.cpu0.dcache.overall_misses::total 3505784 # number of overall misses 827system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 37053025000 # number of ReadReq miss cycles 828system.cpu0.dcache.ReadReq_miss_latency::total 37053025000 # number of ReadReq miss cycles 829system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55161743853 # number of WriteReq miss cycles 830system.cpu0.dcache.WriteReq_miss_latency::total 55161743853 # number of WriteReq miss cycles 831system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326351000 # number of LoadLockedReq miss cycles 832system.cpu0.dcache.LoadLockedReq_miss_latency::total 326351000 # number of LoadLockedReq miss cycles 833system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6342500 # number of StoreCondReq miss cycles 834system.cpu0.dcache.StoreCondReq_miss_latency::total 6342500 # number of StoreCondReq miss cycles 835system.cpu0.dcache.demand_miss_latency::cpu0.data 92214768853 # number of demand (read+write) miss cycles 836system.cpu0.dcache.demand_miss_latency::total 92214768853 # number of demand (read+write) miss cycles 837system.cpu0.dcache.overall_miss_latency::cpu0.data 92214768853 # number of overall miss cycles 838system.cpu0.dcache.overall_miss_latency::total 92214768853 # number of overall miss cycles 839system.cpu0.dcache.ReadReq_accesses::cpu0.data 8691352 # number of ReadReq accesses(hits+misses) 840system.cpu0.dcache.ReadReq_accesses::total 8691352 # number of ReadReq accesses(hits+misses) 841system.cpu0.dcache.WriteReq_accesses::cpu0.data 5775274 # number of WriteReq accesses(hits+misses) 842system.cpu0.dcache.WriteReq_accesses::total 5775274 # number of WriteReq accesses(hits+misses) 843system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 204237 # number of LoadLockedReq accesses(hits+misses) 844system.cpu0.dcache.LoadLockedReq_accesses::total 204237 # number of LoadLockedReq accesses(hits+misses) 845system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 209178 # number of StoreCondReq accesses(hits+misses) 846system.cpu0.dcache.StoreCondReq_accesses::total 209178 # number of StoreCondReq accesses(hits+misses) 847system.cpu0.dcache.demand_accesses::cpu0.data 14466626 # number of demand (read+write) accesses 848system.cpu0.dcache.demand_accesses::total 14466626 # number of demand (read+write) accesses 849system.cpu0.dcache.overall_accesses::cpu0.data 14466626 # number of overall (read+write) accesses 850system.cpu0.dcache.overall_accesses::total 14466626 # number of overall (read+write) accesses 851system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195307 # miss rate for ReadReq accesses 852system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.313111 # miss rate for WriteReq accesses 853system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106215 # miss rate for LoadLockedReq accesses 854system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003289 # miss rate for StoreCondReq accesses 855system.cpu0.dcache.demand_miss_rate::cpu0.data 0.242336 # miss rate for demand accesses 856system.cpu0.dcache.overall_miss_rate::cpu0.data 0.242336 # miss rate for overall accesses 857system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21828.254236 # average ReadReq miss latency 858system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30504.684972 # average WriteReq miss latency 859system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15044.069516 # average LoadLockedReq miss latency 860system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9218.750000 # average StoreCondReq miss latency 861system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency 862system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26303.608224 # average overall miss latency 863system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked 864system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked 865system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked 866system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked 867system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8997.358713 # average number of cycles each access was blocked 868system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked 869system.cpu0.dcache.fast_writes 0 # number of fast writes performed 870system.cpu0.dcache.cache_copies 0 # number of cache copies performed 871system.cpu0.dcache.writebacks::writebacks 791009 # number of writebacks 872system.cpu0.dcache.writebacks::total 791009 # number of writebacks 873system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 651385 # number of ReadReq MSHR hits 874system.cpu0.dcache.ReadReq_mshr_hits::total 651385 # number of ReadReq MSHR hits 875system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523767 # number of WriteReq MSHR hits 876system.cpu0.dcache.WriteReq_mshr_hits::total 1523767 # number of WriteReq MSHR hits 877system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4864 # number of LoadLockedReq MSHR hits 878system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4864 # number of LoadLockedReq MSHR hits 879system.cpu0.dcache.demand_mshr_hits::cpu0.data 2175152 # number of demand (read+write) MSHR hits 880system.cpu0.dcache.demand_mshr_hits::total 2175152 # number of demand (read+write) MSHR hits 881system.cpu0.dcache.overall_mshr_hits::cpu0.data 2175152 # number of overall MSHR hits 882system.cpu0.dcache.overall_mshr_hits::total 2175152 # number of overall MSHR hits 883system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1046095 # number of ReadReq MSHR misses 884system.cpu0.dcache.ReadReq_mshr_misses::total 1046095 # number of ReadReq MSHR misses 885system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 284537 # number of WriteReq MSHR misses 886system.cpu0.dcache.WriteReq_mshr_misses::total 284537 # number of WriteReq MSHR misses 887system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16829 # number of LoadLockedReq MSHR misses 888system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16829 # number of LoadLockedReq MSHR misses 889system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 688 # number of StoreCondReq MSHR misses 890system.cpu0.dcache.StoreCondReq_mshr_misses::total 688 # number of StoreCondReq MSHR misses 891system.cpu0.dcache.demand_mshr_misses::cpu0.data 1330632 # number of demand (read+write) MSHR misses 892system.cpu0.dcache.demand_mshr_misses::total 1330632 # number of demand (read+write) MSHR misses 893system.cpu0.dcache.overall_mshr_misses::cpu0.data 1330632 # number of overall MSHR misses 894system.cpu0.dcache.overall_mshr_misses::total 1330632 # number of overall MSHR misses 895system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24225951000 # number of ReadReq MSHR miss cycles 896system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24225951000 # number of ReadReq MSHR miss cycles 897system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8293520304 # number of WriteReq MSHR miss cycles 898system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8293520304 # number of WriteReq MSHR miss cycles 899system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195490000 # number of LoadLockedReq MSHR miss cycles 900system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195490000 # number of LoadLockedReq MSHR miss cycles 901system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4269500 # number of StoreCondReq MSHR miss cycles 902system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4269500 # number of StoreCondReq MSHR miss cycles 903system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32519471304 # number of demand (read+write) MSHR miss cycles 904system.cpu0.dcache.demand_mshr_miss_latency::total 32519471304 # number of demand (read+write) MSHR miss cycles 905system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32519471304 # number of overall MSHR miss cycles 906system.cpu0.dcache.overall_mshr_miss_latency::total 32519471304 # number of overall MSHR miss cycles 907system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 916801000 # number of ReadReq MSHR uncacheable cycles 908system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 916801000 # number of ReadReq MSHR uncacheable cycles 909system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1252089998 # number of WriteReq MSHR uncacheable cycles 910system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1252089998 # number of WriteReq MSHR uncacheable cycles 911system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2168890998 # number of overall MSHR uncacheable cycles 912system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2168890998 # number of overall MSHR uncacheable cycles 913system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120360 # mshr miss rate for ReadReq accesses 914system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049268 # mshr miss rate for WriteReq accesses 915system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.082399 # mshr miss rate for LoadLockedReq accesses 916system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003289 # mshr miss rate for StoreCondReq accesses 917system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for demand accesses 918system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091979 # mshr miss rate for overall accesses 919system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23158.461708 # average ReadReq mshr miss latency 920system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29147.423021 # average WriteReq mshr miss latency 921system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11616.257650 # average LoadLockedReq mshr miss latency 922system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6205.668605 # average StoreCondReq mshr miss latency 923system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency 924system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24439.117129 # average overall mshr miss latency 925system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 926system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 927system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 928system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 929system.cpu1.dtb.fetch_hits 0 # ITB hits 930system.cpu1.dtb.fetch_misses 0 # ITB misses 931system.cpu1.dtb.fetch_acv 0 # ITB acv 932system.cpu1.dtb.fetch_accesses 0 # ITB accesses 933system.cpu1.dtb.read_hits 1327892 # DTB read hits 934system.cpu1.dtb.read_misses 10318 # DTB read misses 935system.cpu1.dtb.read_acv 5 # DTB read access violations 936system.cpu1.dtb.read_accesses 331425 # DTB read accesses 937system.cpu1.dtb.write_hits 775217 # DTB write hits 938system.cpu1.dtb.write_misses 3380 # DTB write misses 939system.cpu1.dtb.write_acv 51 # DTB write access violations 940system.cpu1.dtb.write_accesses 128049 # DTB write accesses 941system.cpu1.dtb.data_hits 2103109 # DTB hits 942system.cpu1.dtb.data_misses 13698 # DTB misses 943system.cpu1.dtb.data_acv 56 # DTB access violations 944system.cpu1.dtb.data_accesses 459474 # DTB accesses 945system.cpu1.itb.fetch_hits 367800 # ITB hits 946system.cpu1.itb.fetch_misses 7781 # ITB misses 947system.cpu1.itb.fetch_acv 134 # ITB acv 948system.cpu1.itb.fetch_accesses 375581 # ITB accesses 949system.cpu1.itb.read_hits 0 # DTB read hits 950system.cpu1.itb.read_misses 0 # DTB read misses 951system.cpu1.itb.read_acv 0 # DTB read access violations 952system.cpu1.itb.read_accesses 0 # DTB read accesses 953system.cpu1.itb.write_hits 0 # DTB write hits 954system.cpu1.itb.write_misses 0 # DTB write misses 955system.cpu1.itb.write_acv 0 # DTB write access violations 956system.cpu1.itb.write_accesses 0 # DTB write accesses 957system.cpu1.itb.data_hits 0 # DTB hits 958system.cpu1.itb.data_misses 0 # DTB misses 959system.cpu1.itb.data_acv 0 # DTB access violations 960system.cpu1.itb.data_accesses 0 # DTB accesses 961system.cpu1.numCycles 9964881 # number of cpu cycles simulated 962system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 963system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 964system.cpu1.BPredUnit.lookups 1747552 # Number of BP lookups 965system.cpu1.BPredUnit.condPredicted 1443569 # Number of conditional branches predicted 966system.cpu1.BPredUnit.condIncorrect 66414 # Number of conditional branches incorrect 967system.cpu1.BPredUnit.BTBLookups 1567726 # Number of BTB lookups 968system.cpu1.BPredUnit.BTBHits 697812 # Number of BTB hits 969system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 970system.cpu1.BPredUnit.usedRAS 120159 # Number of times the RAS was used to get a target. 971system.cpu1.BPredUnit.RASInCorrect 5219 # Number of incorrect RAS predictions. 972system.cpu1.fetch.icacheStallCycles 3352807 # Number of cycles fetch is stalled on an Icache miss 973system.cpu1.fetch.Insts 8393265 # Number of instructions fetch has processed 974system.cpu1.fetch.Branches 1747552 # Number of branches that fetch encountered 975system.cpu1.fetch.predictedBranches 817971 # Number of branches that fetch has predicted taken 976system.cpu1.fetch.Cycles 1599998 # Number of cycles fetch has run and was not squashing or blocked 977system.cpu1.fetch.SquashCycles 341231 # Number of cycles fetch has spent squashing 978system.cpu1.fetch.BlockedCycles 3951622 # Number of cycles fetch has spent blocked 979system.cpu1.fetch.MiscStallCycles 24365 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 980system.cpu1.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps 981system.cpu1.fetch.PendingQuiesceStallCycles 48200 # Number of stall cycles due to pending quiesce instructions 982system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR 983system.cpu1.fetch.CacheLines 1053319 # Number of cache lines fetched 984system.cpu1.fetch.IcacheSquashes 37675 # Number of outstanding Icache misses that were squashed 985system.cpu1.fetch.rateDist::samples 9267506 # Number of instructions fetched each cycle (Total) 986system.cpu1.fetch.rateDist::mean 0.905666 # Number of instructions fetched each cycle (Total) 987system.cpu1.fetch.rateDist::stdev 2.249416 # Number of instructions fetched each cycle (Total) 988system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 989system.cpu1.fetch.rateDist::0 7667508 82.74% 82.74% # Number of instructions fetched each cycle (Total) 990system.cpu1.fetch.rateDist::1 116348 1.26% 83.99% # Number of instructions fetched each cycle (Total) 991system.cpu1.fetch.rateDist::2 230890 2.49% 86.48% # Number of instructions fetched each cycle (Total) 992system.cpu1.fetch.rateDist::3 132710 1.43% 87.91% # Number of instructions fetched each cycle (Total) 993system.cpu1.fetch.rateDist::4 250243 2.70% 90.61% # Number of instructions fetched each cycle (Total) 994system.cpu1.fetch.rateDist::5 85158 0.92% 91.53% # Number of instructions fetched each cycle (Total) 995system.cpu1.fetch.rateDist::6 106718 1.15% 92.68% # Number of instructions fetched each cycle (Total) 996system.cpu1.fetch.rateDist::7 73511 0.79% 93.48% # Number of instructions fetched each cycle (Total) 997system.cpu1.fetch.rateDist::8 604420 6.52% 100.00% # Number of instructions fetched each cycle (Total) 998system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 999system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1000system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1001system.cpu1.fetch.rateDist::total 9267506 # Number of instructions fetched each cycle (Total) 1002system.cpu1.fetch.branchRate 0.175371 # Number of branch fetches per cycle 1003system.cpu1.fetch.rate 0.842285 # Number of inst fetches per cycle 1004system.cpu1.decode.IdleCycles 3427974 # Number of cycles decode is idle 1005system.cpu1.decode.BlockedCycles 4057837 # Number of cycles decode is blocked 1006system.cpu1.decode.RunCycles 1486886 # Number of cycles decode is running 1007system.cpu1.decode.UnblockCycles 74257 # Number of cycles decode is unblocking 1008system.cpu1.decode.SquashCycles 220551 # Number of cycles decode is squashing 1009system.cpu1.decode.BranchResolved 74813 # Number of times decode resolved a branch 1010system.cpu1.decode.BranchMispred 4599 # Number of times decode detected a branch misprediction 1011system.cpu1.decode.DecodedInsts 8126768 # Number of instructions handled by decode 1012system.cpu1.decode.SquashedInsts 13850 # Number of squashed instructions handled by decode 1013system.cpu1.rename.SquashCycles 220551 # Number of cycles rename is squashing 1014system.cpu1.rename.IdleCycles 3564378 # Number of cycles rename is idle 1015system.cpu1.rename.BlockCycles 427759 # Number of cycles rename is blocking 1016system.cpu1.rename.serializeStallCycles 3208421 # count of cycles rename stalled for serializing inst 1017system.cpu1.rename.RunCycles 1411256 # Number of cycles rename is running 1018system.cpu1.rename.UnblockCycles 435139 # Number of cycles rename is unblocking 1019system.cpu1.rename.RenamedInsts 7552023 # Number of instructions processed by rename 1020system.cpu1.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full 1021system.cpu1.rename.IQFullEvents 45897 # Number of times rename has blocked due to IQ full 1022system.cpu1.rename.LSQFullEvents 92610 # Number of times rename has blocked due to LSQ full 1023system.cpu1.rename.RenamedOperands 5051424 # Number of destination operands rename has renamed 1024system.cpu1.rename.RenameLookups 9247695 # Number of register rename lookups that rename has made 1025system.cpu1.rename.int_rename_lookups 9194844 # Number of integer rename lookups 1026system.cpu1.rename.fp_rename_lookups 52851 # Number of floating rename lookups 1027system.cpu1.rename.CommittedMaps 4016877 # Number of HB maps that are committed 1028system.cpu1.rename.UndoneMaps 1034547 # Number of HB maps that are undone due to squashing 1029system.cpu1.rename.serializingInsts 305973 # count of serializing insts renamed 1030system.cpu1.rename.tempSerializingInsts 22549 # count of temporary serializing insts renamed 1031system.cpu1.rename.skidInsts 1293822 # count of insts added to the skid buffer 1032system.cpu1.memDep0.insertedLoads 1418447 # Number of loads inserted to the mem dependence unit. 1033system.cpu1.memDep0.insertedStores 841500 # Number of stores inserted to the mem dependence unit. 1034system.cpu1.memDep0.conflictingLoads 143535 # Number of conflicting loads. 1035system.cpu1.memDep0.conflictingStores 89440 # Number of conflicting stores. 1036system.cpu1.iq.iqInstsAdded 6603642 # Number of instructions added to the IQ (excludes non-spec) 1037system.cpu1.iq.iqNonSpecInstsAdded 325438 # Number of non-speculative instructions added to the IQ 1038system.cpu1.iq.iqInstsIssued 6286957 # Number of instructions issued 1039system.cpu1.iq.iqSquashedInstsIssued 22758 # Number of squashed instructions issued 1040system.cpu1.iq.iqSquashedInstsExamined 1275148 # Number of squashed instructions iterated over during squash; mainly for profiling 1041system.cpu1.iq.iqSquashedOperandsExamined 714507 # Number of squashed operands that are examined and possibly removed from graph 1042system.cpu1.iq.iqSquashedNonSpecRemoved 249945 # Number of squashed non-spec instructions that were removed 1043system.cpu1.iq.issued_per_cycle::samples 9267506 # Number of insts issued each cycle 1044system.cpu1.iq.issued_per_cycle::mean 0.678387 # Number of insts issued each cycle 1045system.cpu1.iq.issued_per_cycle::stdev 1.328894 # Number of insts issued each cycle 1046system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1047system.cpu1.iq.issued_per_cycle::0 6496050 70.09% 70.09% # Number of insts issued each cycle 1048system.cpu1.iq.issued_per_cycle::1 1227596 13.25% 83.34% # Number of insts issued each cycle 1049system.cpu1.iq.issued_per_cycle::2 583666 6.30% 89.64% # Number of insts issued each cycle 1050system.cpu1.iq.issued_per_cycle::3 391304 4.22% 93.86% # Number of insts issued each cycle 1051system.cpu1.iq.issued_per_cycle::4 294316 3.18% 97.04% # Number of insts issued each cycle 1052system.cpu1.iq.issued_per_cycle::5 159029 1.72% 98.75% # Number of insts issued each cycle 1053system.cpu1.iq.issued_per_cycle::6 73572 0.79% 99.55% # Number of insts issued each cycle 1054system.cpu1.iq.issued_per_cycle::7 31508 0.34% 99.89% # Number of insts issued each cycle 1055system.cpu1.iq.issued_per_cycle::8 10465 0.11% 100.00% # Number of insts issued each cycle 1056system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1057system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1058system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1059system.cpu1.iq.issued_per_cycle::total 9267506 # Number of insts issued each cycle 1060system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1061system.cpu1.iq.fu_full::IntAlu 2850 1.96% 1.96% # attempts to use FU when none available 1062system.cpu1.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available 1063system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available 1064system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available 1065system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available 1066system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available 1067system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available 1068system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available 1069system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 1070system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available 1071system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available 1072system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available 1073system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available 1074system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available 1075system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available 1076system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available 1077system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available 1078system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available 1079system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available 1080system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available 1081system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available 1082system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available 1083system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available 1084system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available 1085system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available 1086system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available 1087system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available 1088system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available 1089system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 1090system.cpu1.iq.fu_full::MemRead 81883 56.36% 58.33% # attempts to use FU when none available 1091system.cpu1.iq.fu_full::MemWrite 60541 41.67% 100.00% # attempts to use FU when none available 1092system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1093system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1094system.cpu1.iq.FU_type_0::No_OpClass 3977 0.06% 0.06% # Type of FU issued 1095system.cpu1.iq.FU_type_0::IntAlu 3891249 61.89% 61.96% # Type of FU issued 1096system.cpu1.iq.FU_type_0::IntMult 10225 0.16% 62.12% # Type of FU issued 1097system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.12% # Type of FU issued 1098system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.28% # Type of FU issued 1099system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.28% # Type of FU issued 1100system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.28% # Type of FU issued 1101system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.28% # Type of FU issued 1102system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.31% # Type of FU issued 1103system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued 1104system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued 1105system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued 1106system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued 1107system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued 1108system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued 1109system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued 1110system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued 1111system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued 1112system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued 1113system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued 1114system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued 1115system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued 1116system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued 1117system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued 1118system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued 1119system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued 1120system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued 1121system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued 1122system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued 1123system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued 1124system.cpu1.iq.FU_type_0::MemRead 1383111 22.00% 84.31% # Type of FU issued 1125system.cpu1.iq.FU_type_0::MemWrite 794977 12.64% 96.96% # Type of FU issued 1126system.cpu1.iq.FU_type_0::IprAccess 191359 3.04% 100.00% # Type of FU issued 1127system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1128system.cpu1.iq.FU_type_0::total 6286957 # Type of FU issued 1129system.cpu1.iq.rate 0.630911 # Inst issue rate 1130system.cpu1.iq.fu_busy_cnt 145274 # FU busy when requested 1131system.cpu1.iq.fu_busy_rate 0.023107 # FU busy rate (busy events/executed inst) 1132system.cpu1.iq.int_inst_queue_reads 21930562 # Number of integer instruction queue reads 1133system.cpu1.iq.int_inst_queue_writes 8166757 # Number of integer instruction queue writes 1134system.cpu1.iq.int_inst_queue_wakeup_accesses 6084651 # Number of integer instruction queue wakeup accesses 1135system.cpu1.iq.fp_inst_queue_reads 78890 # Number of floating instruction queue reads 1136system.cpu1.iq.fp_inst_queue_writes 39096 # Number of floating instruction queue writes 1137system.cpu1.iq.fp_inst_queue_wakeup_accesses 37806 # Number of floating instruction queue wakeup accesses 1138system.cpu1.iq.int_alu_accesses 6387378 # Number of integer alu accesses 1139system.cpu1.iq.fp_alu_accesses 40876 # Number of floating point alu accesses 1140system.cpu1.iew.lsq.thread0.forwLoads 61877 # Number of loads that had data forwarded from stores 1141system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1142system.cpu1.iew.lsq.thread0.squashedLoads 265041 # Number of loads squashed 1143system.cpu1.iew.lsq.thread0.ignoredResponses 6645 # Number of memory responses ignored because the instruction is squashed 1144system.cpu1.iew.lsq.thread0.memOrderViolation 1728 # Number of memory ordering violations 1145system.cpu1.iew.lsq.thread0.squashedStores 113419 # Number of stores squashed 1146system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1147system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1148system.cpu1.iew.lsq.thread0.rescheduledLoads 368 # Number of loads that were rescheduled 1149system.cpu1.iew.lsq.thread0.cacheBlocked 22536 # Number of times an access to memory failed due to the cache being blocked 1150system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1151system.cpu1.iew.iewSquashCycles 220551 # Number of cycles IEW is squashing 1152system.cpu1.iew.iewBlockCycles 309881 # Number of cycles IEW is blocking 1153system.cpu1.iew.iewUnblockCycles 12131 # Number of cycles IEW is unblocking 1154system.cpu1.iew.iewDispatchedInsts 7193888 # Number of instructions dispatched to IQ 1155system.cpu1.iew.iewDispSquashedInsts 99371 # Number of squashed instructions skipped by dispatch 1156system.cpu1.iew.iewDispLoadInsts 1418447 # Number of dispatched load instructions 1157system.cpu1.iew.iewDispStoreInsts 841500 # Number of dispatched store instructions 1158system.cpu1.iew.iewDispNonSpecInsts 303567 # Number of dispatched non-speculative instructions 1159system.cpu1.iew.iewIQFullEvents 4003 # Number of times the IQ has become full, causing a stall 1160system.cpu1.iew.iewLSQFullEvents 5102 # Number of times the LSQ has become full, causing a stall 1161system.cpu1.iew.memOrderViolationEvents 1728 # Number of memory order violations 1162system.cpu1.iew.predictedTakenIncorrect 48086 # Number of branches that were predicted taken incorrectly 1163system.cpu1.iew.predictedNotTakenIncorrect 60250 # Number of branches that were predicted not taken incorrectly 1164system.cpu1.iew.branchMispredicts 108336 # Number of branch mispredicts detected at execute 1165system.cpu1.iew.iewExecutedInsts 6208556 # Number of executed instructions 1166system.cpu1.iew.iewExecLoadInsts 1341795 # Number of load instructions executed 1167system.cpu1.iew.iewExecSquashedInsts 78401 # Number of squashed instructions skipped in execute 1168system.cpu1.iew.exec_swp 0 # number of swp insts executed 1169system.cpu1.iew.exec_nop 264808 # number of nop insts executed 1170system.cpu1.iew.exec_refs 2123746 # number of memory reference insts executed 1171system.cpu1.iew.exec_branches 906293 # Number of branches executed 1172system.cpu1.iew.exec_stores 781951 # Number of stores executed 1173system.cpu1.iew.exec_rate 0.623044 # Inst execution rate 1174system.cpu1.iew.wb_sent 6150217 # cumulative count of insts sent to commit 1175system.cpu1.iew.wb_count 6122457 # cumulative count of insts written-back 1176system.cpu1.iew.wb_producers 2959215 # num instructions producing a value 1177system.cpu1.iew.wb_consumers 4044738 # num instructions consuming a value 1178system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1179system.cpu1.iew.wb_rate 0.614403 # insts written-back per cycle 1180system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back 1181system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1182system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions 1183system.cpu1.commit.commitCommittedOps 5811574 # The number of committed instructions 1184system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit 1185system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards 1186system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted 1187system.cpu1.commit.committed_per_cycle::samples 9046955 # Number of insts commited each cycle 1188system.cpu1.commit.committed_per_cycle::mean 0.642379 # Number of insts commited each cycle 1189system.cpu1.commit.committed_per_cycle::stdev 1.547455 # Number of insts commited each cycle 1190system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1191system.cpu1.commit.committed_per_cycle::0 6775881 74.90% 74.90% # Number of insts commited each cycle 1192system.cpu1.commit.committed_per_cycle::1 1100597 12.17% 87.06% # Number of insts commited each cycle 1193system.cpu1.commit.committed_per_cycle::2 394396 4.36% 91.42% # Number of insts commited each cycle 1194system.cpu1.commit.committed_per_cycle::3 244103 2.70% 94.12% # Number of insts commited each cycle 1195system.cpu1.commit.committed_per_cycle::4 155347 1.72% 95.84% # Number of insts commited each cycle 1196system.cpu1.commit.committed_per_cycle::5 74536 0.82% 96.66% # Number of insts commited each cycle 1197system.cpu1.commit.committed_per_cycle::6 76677 0.85% 97.51% # Number of insts commited each cycle 1198system.cpu1.commit.committed_per_cycle::7 67598 0.75% 98.26% # Number of insts commited each cycle 1199system.cpu1.commit.committed_per_cycle::8 157820 1.74% 100.00% # Number of insts commited each cycle 1200system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1201system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1202system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1203system.cpu1.commit.committed_per_cycle::total 9046955 # Number of insts commited each cycle 1204system.cpu1.commit.committedInsts 5811574 # Number of instructions committed 1205system.cpu1.commit.committedOps 5811574 # Number of ops (including micro ops) committed 1206system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1207system.cpu1.commit.refs 1881487 # Number of memory references committed 1208system.cpu1.commit.loads 1153406 # Number of loads committed 1209system.cpu1.commit.membars 20496 # Number of memory barriers committed 1210system.cpu1.commit.branches 821024 # Number of branches committed 1211system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. 1212system.cpu1.commit.int_insts 5437311 # Number of committed integer instructions. 1213system.cpu1.commit.function_calls 89377 # Number of function calls committed. 1214system.cpu1.commit.bw_lim_events 157820 # number cycles where commit BW limit reached 1215system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1216system.cpu1.rob.rob_reads 15919643 # The number of ROB reads 1217system.cpu1.rob.rob_writes 14461697 # The number of ROB writes 1218system.cpu1.timesIdled 81901 # Number of times that the entire CPU went into an idle state and unscheduled itself 1219system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling 1220system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1221system.cpu1.committedInsts 5588082 # Number of Instructions Simulated 1222system.cpu1.committedOps 5588082 # Number of Ops (including micro ops) Simulated 1223system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated 1224system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction 1225system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads 1226system.cpu1.ipc 0.560778 # IPC: Instructions Per Cycle 1227system.cpu1.ipc_total 0.560778 # IPC: Total IPC of All Threads 1228system.cpu1.int_regfile_reads 8095217 # number of integer regfile reads 1229system.cpu1.int_regfile_writes 4412873 # number of integer regfile writes 1230system.cpu1.fp_regfile_reads 24584 # number of floating regfile reads 1231system.cpu1.fp_regfile_writes 23091 # number of floating regfile writes 1232system.cpu1.misc_regfile_reads 284668 # number of misc regfile reads 1233system.cpu1.misc_regfile_writes 134791 # number of misc regfile writes 1234system.cpu1.icache.replacements 110606 # number of replacements 1235system.cpu1.icache.tagsinuse 453.435417 # Cycle average of tags in use 1236system.cpu1.icache.total_refs 936898 # Total number of references to valid blocks. 1237system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks. 1238system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks. 1239system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit. 1240system.cpu1.icache.occ_blocks::cpu1.inst 453.435417 # Average occupied blocks per requestor 1241system.cpu1.icache.occ_percent::cpu1.inst 0.885616 # Average percentage of cache occupancy 1242system.cpu1.icache.occ_percent::total 0.885616 # Average percentage of cache occupancy 1243system.cpu1.icache.ReadReq_hits::cpu1.inst 936898 # number of ReadReq hits 1244system.cpu1.icache.ReadReq_hits::total 936898 # number of ReadReq hits 1245system.cpu1.icache.demand_hits::cpu1.inst 936898 # number of demand (read+write) hits 1246system.cpu1.icache.demand_hits::total 936898 # number of demand (read+write) hits 1247system.cpu1.icache.overall_hits::cpu1.inst 936898 # number of overall hits 1248system.cpu1.icache.overall_hits::total 936898 # number of overall hits 1249system.cpu1.icache.ReadReq_misses::cpu1.inst 116421 # number of ReadReq misses 1250system.cpu1.icache.ReadReq_misses::total 116421 # number of ReadReq misses 1251system.cpu1.icache.demand_misses::cpu1.inst 116421 # number of demand (read+write) misses 1252system.cpu1.icache.demand_misses::total 116421 # number of demand (read+write) misses 1253system.cpu1.icache.overall_misses::cpu1.inst 116421 # number of overall misses 1254system.cpu1.icache.overall_misses::total 116421 # number of overall misses 1255system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1750783999 # number of ReadReq miss cycles 1256system.cpu1.icache.ReadReq_miss_latency::total 1750783999 # number of ReadReq miss cycles 1257system.cpu1.icache.demand_miss_latency::cpu1.inst 1750783999 # number of demand (read+write) miss cycles 1258system.cpu1.icache.demand_miss_latency::total 1750783999 # number of demand (read+write) miss cycles 1259system.cpu1.icache.overall_miss_latency::cpu1.inst 1750783999 # number of overall miss cycles 1260system.cpu1.icache.overall_miss_latency::total 1750783999 # number of overall miss cycles 1261system.cpu1.icache.ReadReq_accesses::cpu1.inst 1053319 # number of ReadReq accesses(hits+misses) 1262system.cpu1.icache.ReadReq_accesses::total 1053319 # number of ReadReq accesses(hits+misses) 1263system.cpu1.icache.demand_accesses::cpu1.inst 1053319 # number of demand (read+write) accesses 1264system.cpu1.icache.demand_accesses::total 1053319 # number of demand (read+write) accesses 1265system.cpu1.icache.overall_accesses::cpu1.inst 1053319 # number of overall (read+write) accesses 1266system.cpu1.icache.overall_accesses::total 1053319 # number of overall (read+write) accesses 1267system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.110528 # miss rate for ReadReq accesses 1268system.cpu1.icache.demand_miss_rate::cpu1.inst 0.110528 # miss rate for demand accesses 1269system.cpu1.icache.overall_miss_rate::cpu1.inst 0.110528 # miss rate for overall accesses 1270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15038.386537 # average ReadReq miss latency 1271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency 1272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15038.386537 # average overall miss latency 1273system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked 1274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1275system.cpu1.icache.blocked::no_mshrs 14 # number of cycles access was blocked 1276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1277system.cpu1.icache.avg_blocked_cycles::no_mshrs 6928.500000 # average number of cycles each access was blocked 1278system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1279system.cpu1.icache.fast_writes 0 # number of fast writes performed 1280system.cpu1.icache.cache_copies 0 # number of cache copies performed 1281system.cpu1.icache.writebacks::writebacks 37 # number of writebacks 1282system.cpu1.icache.writebacks::total 37 # number of writebacks 1283system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5236 # number of ReadReq MSHR hits 1284system.cpu1.icache.ReadReq_mshr_hits::total 5236 # number of ReadReq MSHR hits 1285system.cpu1.icache.demand_mshr_hits::cpu1.inst 5236 # number of demand (read+write) MSHR hits 1286system.cpu1.icache.demand_mshr_hits::total 5236 # number of demand (read+write) MSHR hits 1287system.cpu1.icache.overall_mshr_hits::cpu1.inst 5236 # number of overall MSHR hits 1288system.cpu1.icache.overall_mshr_hits::total 5236 # number of overall MSHR hits 1289system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 111185 # number of ReadReq MSHR misses 1290system.cpu1.icache.ReadReq_mshr_misses::total 111185 # number of ReadReq MSHR misses 1291system.cpu1.icache.demand_mshr_misses::cpu1.inst 111185 # number of demand (read+write) MSHR misses 1292system.cpu1.icache.demand_mshr_misses::total 111185 # number of demand (read+write) MSHR misses 1293system.cpu1.icache.overall_mshr_misses::cpu1.inst 111185 # number of overall MSHR misses 1294system.cpu1.icache.overall_mshr_misses::total 111185 # number of overall MSHR misses 1295system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1333353499 # number of ReadReq MSHR miss cycles 1296system.cpu1.icache.ReadReq_mshr_miss_latency::total 1333353499 # number of ReadReq MSHR miss cycles 1297system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1333353499 # number of demand (read+write) MSHR miss cycles 1298system.cpu1.icache.demand_mshr_miss_latency::total 1333353499 # number of demand (read+write) MSHR miss cycles 1299system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1333353499 # number of overall MSHR miss cycles 1300system.cpu1.icache.overall_mshr_miss_latency::total 1333353499 # number of overall MSHR miss cycles 1301system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for ReadReq accesses 1302system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for demand accesses 1303system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105557 # mshr miss rate for overall accesses 1304system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average ReadReq mshr miss latency 1305system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency 1306system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11992.206674 # average overall mshr miss latency 1307system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1308system.cpu1.dcache.replacements 62388 # number of replacements 1309system.cpu1.dcache.tagsinuse 392.324021 # Cycle average of tags in use 1310system.cpu1.dcache.total_refs 1699992 # Total number of references to valid blocks. 1311system.cpu1.dcache.sampled_refs 62715 # Sample count of references to valid blocks. 1312system.cpu1.dcache.avg_refs 27.106625 # Average number of references to valid blocks. 1313system.cpu1.dcache.warmup_cycle 1874614053500 # Cycle when the warmup percentage was hit. 1314system.cpu1.dcache.occ_blocks::cpu1.data 392.324021 # Average occupied blocks per requestor 1315system.cpu1.dcache.occ_percent::cpu1.data 0.766258 # Average percentage of cache occupancy 1316system.cpu1.dcache.occ_percent::total 0.766258 # Average percentage of cache occupancy 1317system.cpu1.dcache.ReadReq_hits::cpu1.data 1127254 # number of ReadReq hits 1318system.cpu1.dcache.ReadReq_hits::total 1127254 # number of ReadReq hits 1319system.cpu1.dcache.WriteReq_hits::cpu1.data 549515 # number of WriteReq hits 1320system.cpu1.dcache.WriteReq_hits::total 549515 # number of WriteReq hits 1321system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16791 # number of LoadLockedReq hits 1322system.cpu1.dcache.LoadLockedReq_hits::total 16791 # number of LoadLockedReq hits 1323system.cpu1.dcache.StoreCondReq_hits::cpu1.data 14923 # number of StoreCondReq hits 1324system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits 1325system.cpu1.dcache.demand_hits::cpu1.data 1676769 # number of demand (read+write) hits 1326system.cpu1.dcache.demand_hits::total 1676769 # number of demand (read+write) hits 1327system.cpu1.dcache.overall_hits::cpu1.data 1676769 # number of overall hits 1328system.cpu1.dcache.overall_hits::total 1676769 # number of overall hits 1329system.cpu1.dcache.ReadReq_misses::cpu1.data 106582 # number of ReadReq misses 1330system.cpu1.dcache.ReadReq_misses::total 106582 # number of ReadReq misses 1331system.cpu1.dcache.WriteReq_misses::cpu1.data 157839 # number of WriteReq misses 1332system.cpu1.dcache.WriteReq_misses::total 157839 # number of WriteReq misses 1333system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1481 # number of LoadLockedReq misses 1334system.cpu1.dcache.LoadLockedReq_misses::total 1481 # number of LoadLockedReq misses 1335system.cpu1.dcache.StoreCondReq_misses::cpu1.data 695 # number of StoreCondReq misses 1336system.cpu1.dcache.StoreCondReq_misses::total 695 # number of StoreCondReq misses 1337system.cpu1.dcache.demand_misses::cpu1.data 264421 # number of demand (read+write) misses 1338system.cpu1.dcache.demand_misses::total 264421 # number of demand (read+write) misses 1339system.cpu1.dcache.overall_misses::cpu1.data 264421 # number of overall misses 1340system.cpu1.dcache.overall_misses::total 264421 # number of overall misses 1341system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1787903500 # number of ReadReq miss cycles 1342system.cpu1.dcache.ReadReq_miss_latency::total 1787903500 # number of ReadReq miss cycles 1343system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5181152780 # number of WriteReq miss cycles 1344system.cpu1.dcache.WriteReq_miss_latency::total 5181152780 # number of WriteReq miss cycles 1345system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19396000 # number of LoadLockedReq miss cycles 1346system.cpu1.dcache.LoadLockedReq_miss_latency::total 19396000 # number of LoadLockedReq miss cycles 1347system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8380000 # number of StoreCondReq miss cycles 1348system.cpu1.dcache.StoreCondReq_miss_latency::total 8380000 # number of StoreCondReq miss cycles 1349system.cpu1.dcache.demand_miss_latency::cpu1.data 6969056280 # number of demand (read+write) miss cycles 1350system.cpu1.dcache.demand_miss_latency::total 6969056280 # number of demand (read+write) miss cycles 1351system.cpu1.dcache.overall_miss_latency::cpu1.data 6969056280 # number of overall miss cycles 1352system.cpu1.dcache.overall_miss_latency::total 6969056280 # number of overall miss cycles 1353system.cpu1.dcache.ReadReq_accesses::cpu1.data 1233836 # number of ReadReq accesses(hits+misses) 1354system.cpu1.dcache.ReadReq_accesses::total 1233836 # number of ReadReq accesses(hits+misses) 1355system.cpu1.dcache.WriteReq_accesses::cpu1.data 707354 # number of WriteReq accesses(hits+misses) 1356system.cpu1.dcache.WriteReq_accesses::total 707354 # number of WriteReq accesses(hits+misses) 1357system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 18272 # number of LoadLockedReq accesses(hits+misses) 1358system.cpu1.dcache.LoadLockedReq_accesses::total 18272 # number of LoadLockedReq accesses(hits+misses) 1359system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15618 # number of StoreCondReq accesses(hits+misses) 1360system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses) 1361system.cpu1.dcache.demand_accesses::cpu1.data 1941190 # number of demand (read+write) accesses 1362system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses 1363system.cpu1.dcache.overall_accesses::cpu1.data 1941190 # number of overall (read+write) accesses 1364system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses 1365system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.086383 # miss rate for ReadReq accesses 1366system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223140 # miss rate for WriteReq accesses 1367system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081053 # miss rate for LoadLockedReq accesses 1368system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044500 # miss rate for StoreCondReq accesses 1369system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136216 # miss rate for demand accesses 1370system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136216 # miss rate for overall accesses 1371system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398 # average ReadReq miss latency 1372system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028 # average WriteReq miss latency 1373system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381 # average LoadLockedReq miss latency 1374system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957 # average StoreCondReq miss latency 1375system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency 1376system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency 1377system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked 1378system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1379system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked 1380system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1381system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558 # average number of cycles each access was blocked 1382system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1383system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1384system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1385system.cpu1.dcache.writebacks::writebacks 35937 # number of writebacks 1386system.cpu1.dcache.writebacks::total 35937 # number of writebacks 1387system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62835 # number of ReadReq MSHR hits 1388system.cpu1.dcache.ReadReq_mshr_hits::total 62835 # number of ReadReq MSHR hits 1389system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 134042 # number of WriteReq MSHR hits 1390system.cpu1.dcache.WriteReq_mshr_hits::total 134042 # number of WriteReq MSHR hits 1391system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 295 # number of LoadLockedReq MSHR hits 1392system.cpu1.dcache.LoadLockedReq_mshr_hits::total 295 # number of LoadLockedReq MSHR hits 1393system.cpu1.dcache.demand_mshr_hits::cpu1.data 196877 # number of demand (read+write) MSHR hits 1394system.cpu1.dcache.demand_mshr_hits::total 196877 # number of demand (read+write) MSHR hits 1395system.cpu1.dcache.overall_mshr_hits::cpu1.data 196877 # number of overall MSHR hits 1396system.cpu1.dcache.overall_mshr_hits::total 196877 # number of overall MSHR hits 1397system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43747 # number of ReadReq MSHR misses 1398system.cpu1.dcache.ReadReq_mshr_misses::total 43747 # number of ReadReq MSHR misses 1399system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23797 # number of WriteReq MSHR misses 1400system.cpu1.dcache.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses 1401system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1186 # number of LoadLockedReq MSHR misses 1402system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1186 # number of LoadLockedReq MSHR misses 1403system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 695 # number of StoreCondReq MSHR misses 1404system.cpu1.dcache.StoreCondReq_mshr_misses::total 695 # number of StoreCondReq MSHR misses 1405system.cpu1.dcache.demand_mshr_misses::cpu1.data 67544 # number of demand (read+write) MSHR misses 1406system.cpu1.dcache.demand_mshr_misses::total 67544 # number of demand (read+write) MSHR misses 1407system.cpu1.dcache.overall_mshr_misses::cpu1.data 67544 # number of overall MSHR misses 1408system.cpu1.dcache.overall_mshr_misses::total 67544 # number of overall MSHR misses 1409system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 555340000 # number of ReadReq MSHR miss cycles 1410system.cpu1.dcache.ReadReq_mshr_miss_latency::total 555340000 # number of ReadReq MSHR miss cycles 1411system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 753314485 # number of WriteReq MSHR miss cycles 1412system.cpu1.dcache.WriteReq_mshr_miss_latency::total 753314485 # number of WriteReq MSHR miss cycles 1413system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 11632000 # number of LoadLockedReq MSHR miss cycles 1414system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 11632000 # number of LoadLockedReq MSHR miss cycles 1415system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6287000 # number of StoreCondReq MSHR miss cycles 1416system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6287000 # number of StoreCondReq MSHR miss cycles 1417system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1308654485 # number of demand (read+write) MSHR miss cycles 1418system.cpu1.dcache.demand_mshr_miss_latency::total 1308654485 # number of demand (read+write) MSHR miss cycles 1419system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1308654485 # number of overall MSHR miss cycles 1420system.cpu1.dcache.overall_mshr_miss_latency::total 1308654485 # number of overall MSHR miss cycles 1421system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19116500 # number of ReadReq MSHR uncacheable cycles 1422system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19116500 # number of ReadReq MSHR uncacheable cycles 1423system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320800500 # number of WriteReq MSHR uncacheable cycles 1424system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 320800500 # number of WriteReq MSHR uncacheable cycles 1425system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 339917000 # number of overall MSHR uncacheable cycles 1426system.cpu1.dcache.overall_mshr_uncacheable_latency::total 339917000 # number of overall MSHR uncacheable cycles 1427system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035456 # mshr miss rate for ReadReq accesses 1428system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033642 # mshr miss rate for WriteReq accesses 1429system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064908 # mshr miss rate for LoadLockedReq accesses 1430system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044500 # mshr miss rate for StoreCondReq accesses 1431system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for demand accesses 1432system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for overall accesses 1433system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184 # average ReadReq mshr miss latency 1434system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352 # average WriteReq mshr miss latency 1435system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9807.757167 # average LoadLockedReq mshr miss latency 1436system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9046.043165 # average StoreCondReq mshr miss latency 1437system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency 1438system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency 1439system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1440system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1441system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1442system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1443system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1444system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed 1445system.cpu0.kern.inst.hwrei 199147 # number of hwrei instructions executed 1446system.cpu0.kern.ipl_count::0 71494 40.63% 40.63% # number of times we switched to this ipl 1447system.cpu0.kern.ipl_count::21 238 0.14% 40.76% # number of times we switched to this ipl 1448system.cpu0.kern.ipl_count::22 1915 1.09% 41.85% # number of times we switched to this ipl 1449system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl 1450system.cpu0.kern.ipl_count::31 102317 58.14% 100.00% # number of times we switched to this ipl 1451system.cpu0.kern.ipl_count::total 175972 # number of times we switched to this ipl 1452system.cpu0.kern.ipl_good::0 70129 49.24% 49.24% # number of times we switched to this ipl from a different ipl 1453system.cpu0.kern.ipl_good::21 238 0.17% 49.41% # number of times we switched to this ipl from a different ipl 1454system.cpu0.kern.ipl_good::22 1915 1.34% 50.76% # number of times we switched to this ipl from a different ipl 1455system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl 1456system.cpu0.kern.ipl_good::31 70122 49.24% 100.00% # number of times we switched to this ipl from a different ipl 1457system.cpu0.kern.ipl_good::total 142412 # number of times we switched to this ipl from a different ipl 1458system.cpu0.kern.ipl_ticks::0 1858860218500 97.97% 97.97% # number of cycles we spent at this ipl 1459system.cpu0.kern.ipl_ticks::21 90821000 0.00% 97.97% # number of cycles we spent at this ipl 1460system.cpu0.kern.ipl_ticks::22 390050500 0.02% 97.99% # number of cycles we spent at this ipl 1461system.cpu0.kern.ipl_ticks::30 4014000 0.00% 97.99% # number of cycles we spent at this ipl 1462system.cpu0.kern.ipl_ticks::31 38119760000 2.01% 100.00% # number of cycles we spent at this ipl 1463system.cpu0.kern.ipl_ticks::total 1897464864000 # number of cycles we spent at this ipl 1464system.cpu0.kern.ipl_used::0 0.980907 # fraction of swpipl calls that actually changed the ipl 1465system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1466system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1467system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1468system.cpu0.kern.ipl_used::31 0.685341 # fraction of swpipl calls that actually changed the ipl 1469system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed 1470system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed 1471system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed 1472system.cpu0.kern.syscall::6 32 14.88% 28.37% # number of syscalls executed 1473system.cpu0.kern.syscall::12 1 0.47% 28.84% # number of syscalls executed 1474system.cpu0.kern.syscall::17 8 3.72% 32.56% # number of syscalls executed 1475system.cpu0.kern.syscall::19 10 4.65% 37.21% # number of syscalls executed 1476system.cpu0.kern.syscall::20 6 2.79% 40.00% # number of syscalls executed 1477system.cpu0.kern.syscall::23 1 0.47% 40.47% # number of syscalls executed 1478system.cpu0.kern.syscall::24 3 1.40% 41.86% # number of syscalls executed 1479system.cpu0.kern.syscall::33 6 2.79% 44.65% # number of syscalls executed 1480system.cpu0.kern.syscall::41 2 0.93% 45.58% # number of syscalls executed 1481system.cpu0.kern.syscall::45 33 15.35% 60.93% # number of syscalls executed 1482system.cpu0.kern.syscall::47 3 1.40% 62.33% # number of syscalls executed 1483system.cpu0.kern.syscall::48 10 4.65% 66.98% # number of syscalls executed 1484system.cpu0.kern.syscall::54 10 4.65% 71.63% # number of syscalls executed 1485system.cpu0.kern.syscall::58 1 0.47% 72.09% # number of syscalls executed 1486system.cpu0.kern.syscall::59 6 2.79% 74.88% # number of syscalls executed 1487system.cpu0.kern.syscall::71 23 10.70% 85.58% # number of syscalls executed 1488system.cpu0.kern.syscall::73 3 1.40% 86.98% # number of syscalls executed 1489system.cpu0.kern.syscall::74 6 2.79% 89.77% # number of syscalls executed 1490system.cpu0.kern.syscall::87 1 0.47% 90.23% # number of syscalls executed 1491system.cpu0.kern.syscall::90 3 1.40% 91.63% # number of syscalls executed 1492system.cpu0.kern.syscall::92 9 4.19% 95.81% # number of syscalls executed 1493system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed 1494system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed 1495system.cpu0.kern.syscall::132 1 0.47% 98.14% # number of syscalls executed 1496system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed 1497system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed 1498system.cpu0.kern.syscall::total 215 # number of syscalls executed 1499system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1500system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed 1501system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 1502system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 1503system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 1504system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed 1505system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed 1506system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed 1507system.cpu0.kern.callpal::swpipl 169050 91.54% 93.71% # number of callpals executed 1508system.cpu0.kern.callpal::rdps 6330 3.43% 97.14% # number of callpals executed 1509system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed 1510system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed 1511system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed 1512system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed 1513system.cpu0.kern.callpal::rti 4761 2.58% 99.73% # number of callpals executed 1514system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed 1515system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed 1516system.cpu0.kern.callpal::total 184665 # number of callpals executed 1517system.cpu0.kern.mode_switch::kernel 7257 # number of protection mode switches 1518system.cpu0.kern.mode_switch::user 1249 # number of protection mode switches 1519system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1520system.cpu0.kern.mode_good::kernel 1248 1521system.cpu0.kern.mode_good::user 1249 1522system.cpu0.kern.mode_good::idle 0 1523system.cpu0.kern.mode_switch_good::kernel 0.171972 # fraction of useful protection mode switches 1524system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1525system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 1526system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches 1527system.cpu0.kern.mode_ticks::kernel 1895601847000 99.90% 99.90% # number of ticks spent at the given mode 1528system.cpu0.kern.mode_ticks::user 1863009000 0.10% 100.00% # number of ticks spent at the given mode 1529system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1530system.cpu0.kern.swap_context 3841 # number of times the context was actually changed 1531system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1532system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed 1533system.cpu1.kern.inst.hwrei 38551 # number of hwrei instructions executed 1534system.cpu1.kern.ipl_count::0 10250 33.36% 33.36% # number of times we switched to this ipl 1535system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl 1536system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl 1537system.cpu1.kern.ipl_count::31 18453 60.05% 100.00% # number of times we switched to this ipl 1538system.cpu1.kern.ipl_count::total 30728 # number of times we switched to this ipl 1539system.cpu1.kern.ipl_good::0 10238 45.71% 45.71% # number of times we switched to this ipl from a different ipl 1540system.cpu1.kern.ipl_good::22 1920 8.57% 54.29% # number of times we switched to this ipl from a different ipl 1541system.cpu1.kern.ipl_good::30 105 0.47% 54.76% # number of times we switched to this ipl from a different ipl 1542system.cpu1.kern.ipl_good::31 10133 45.24% 100.00% # number of times we switched to this ipl from a different ipl 1543system.cpu1.kern.ipl_good::total 22396 # number of times we switched to this ipl from a different ipl 1544system.cpu1.kern.ipl_ticks::0 1871094081500 98.61% 98.61% # number of cycles we spent at this ipl 1545system.cpu1.kern.ipl_ticks::22 343283500 0.02% 98.63% # number of cycles we spent at this ipl 1546system.cpu1.kern.ipl_ticks::30 42013500 0.00% 98.63% # number of cycles we spent at this ipl 1547system.cpu1.kern.ipl_ticks::31 25985147000 1.37% 100.00% # number of cycles we spent at this ipl 1548system.cpu1.kern.ipl_ticks::total 1897464525500 # number of cycles we spent at this ipl 1549system.cpu1.kern.ipl_used::0 0.998829 # fraction of swpipl calls that actually changed the ipl 1550system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1551system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1552system.cpu1.kern.ipl_used::31 0.549125 # fraction of swpipl calls that actually changed the ipl 1553system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed 1554system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed 1555system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed 1556system.cpu1.kern.syscall::15 1 0.90% 21.62% # number of syscalls executed 1557system.cpu1.kern.syscall::17 7 6.31% 27.93% # number of syscalls executed 1558system.cpu1.kern.syscall::23 3 2.70% 30.63% # number of syscalls executed 1559system.cpu1.kern.syscall::24 3 2.70% 33.33% # number of syscalls executed 1560system.cpu1.kern.syscall::33 5 4.50% 37.84% # number of syscalls executed 1561system.cpu1.kern.syscall::45 21 18.92% 56.76% # number of syscalls executed 1562system.cpu1.kern.syscall::47 3 2.70% 59.46% # number of syscalls executed 1563system.cpu1.kern.syscall::59 1 0.90% 60.36% # number of syscalls executed 1564system.cpu1.kern.syscall::71 31 27.93% 88.29% # number of syscalls executed 1565system.cpu1.kern.syscall::74 10 9.01% 97.30% # number of syscalls executed 1566system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed 1567system.cpu1.kern.syscall::total 111 # number of syscalls executed 1568system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1569system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed 1570system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 1571system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 1572system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed 1573system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed 1574system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed 1575system.cpu1.kern.callpal::swpipl 26174 82.49% 83.79% # number of callpals executed 1576system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed 1577system.cpu1.kern.callpal::wrkgp 1 0.00% 91.40% # number of callpals executed 1578system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed 1579system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed 1580system.cpu1.kern.callpal::rti 2528 7.97% 99.39% # number of callpals executed 1581system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed 1582system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed 1583system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1584system.cpu1.kern.callpal::total 31730 # number of callpals executed 1585system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches 1586system.cpu1.kern.mode_switch::user 491 # number of protection mode switches 1587system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches 1588system.cpu1.kern.mode_good::kernel 521 1589system.cpu1.kern.mode_good::user 491 1590system.cpu1.kern.mode_good::idle 30 1591system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches 1592system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1593system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches 1594system.cpu1.kern.mode_switch_good::total 1.614145 # fraction of useful protection mode switches 1595system.cpu1.kern.mode_ticks::kernel 2062444500 0.11% 0.11% # number of ticks spent at the given mode 1596system.cpu1.kern.mode_ticks::user 847773000 0.04% 0.15% # number of ticks spent at the given mode 1597system.cpu1.kern.mode_ticks::idle 1893876331500 99.85% 100.00% # number of ticks spent at the given mode 1598system.cpu1.kern.swap_context 394 # number of times the context was actually changed 1599 1600---------- End Simulation Statistics ---------- 1601