xref: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.897465                       # Number of seconds simulated
sim_ticks                                1897464893500                       # Number of ticks simulated
final_tick                               1897464893500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 100310                       # Simulator instruction rate (inst/s)
host_tick_rate                             3391719918                       # Simulator tick rate (ticks/s)
host_mem_usage                                 326488                       # Number of bytes of host memory used
host_seconds                                   559.44                       # Real time elapsed on the host
sim_insts                                    56117221                       # Number of instructions simulated
system.physmem.bytes_read                    30408512                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                1099328                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                 10470144                       # Number of bytes written to this memory
system.physmem.num_reads                       475133                       # Number of read requests responded to by this memory
system.physmem.num_writes                      163596                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       16025863                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    579367                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                       5517965                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                      21543827                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        397850                       # number of replacements
system.l2c.tagsinuse                     35109.782430                       # Cycle average of tags in use
system.l2c.total_refs                         2482376                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        433566                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          5.725486                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                    9252063000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                 12005.589305                       # Average occupied blocks per context
system.l2c.occ_blocks::1                   237.479904                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 22866.713220                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.183191                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.003624                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.348918                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                    1720206                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     147304                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1867510                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   827202                       # number of Writeback hits
system.l2c.Writeback_hits::total               827202                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                     175                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                      45                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 220                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                    29                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                    27                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                56                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                   168180                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    11095                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               179275                       # number of ReadExReq hits
system.l2c.demand_hits::0                     1888386                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      158399                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2046785                       # number of demand (read+write) hits
system.l2c.overall_hits::0                    1888386                       # number of overall hits
system.l2c.overall_hits::1                     158399                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                2046785                       # number of overall hits
system.l2c.ReadReq_misses::0                   305580                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     4046                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               309626                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  2447                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                   562                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3009                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                  45                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                  84                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             129                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                 113888                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  10746                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             124634                       # number of ReadExReq misses
system.l2c.demand_misses::0                    419468                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     14792                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                434260                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   419468                       # number of overall misses
system.l2c.overall_misses::1                    14792                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               434260                       # number of overall misses
system.l2c.ReadReq_miss_latency           16117985000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency            4084000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency           629500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          6538201500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency            22656186500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency           22656186500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                2025786                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 151350                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2177136                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               827202                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           827202                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                2622                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                 607                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3229                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0                74                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               111                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total           185                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               282068                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                21841                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           303909                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                 2307854                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  173191                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2481045                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                2307854                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 173191                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2481045                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.150845                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.026733                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.933257                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.925865                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.608108                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.756757                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.403761                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.492010                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.181757                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.085409                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.181757                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.085409                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   52745.549447                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   3983683.885319                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  1668.982427                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1  7266.903915                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::0 13988.888889                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1  7494.047619                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 57409.046607                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 608431.183696                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    54011.716031                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1531651.331801                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   54011.716031                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1531651.331801                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          122076                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       18                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                 309608                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses                3009                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses               129                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               124634                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  434242                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 434242                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency      12394422500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     120428500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency      5161500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5022578000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency       17417000500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency      17417000500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency    838122000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency   1420361498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency   2258483498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.152834                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         2.045643                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      1.147597                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      4.957166                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.743243                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.162162                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.441858                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       5.706424                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.188158                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          2.507301                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.188158                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         2.507301                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40032.629971                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.765038                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.627907                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40298.618355                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40108.972647                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40108.972647                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     41697                       # number of replacements
system.iocache.tagsinuse                     0.463236                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              1709322783000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::1                 0.463236                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.028952                       # Average percentage of cache occupancy
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.ReadReq_misses::1                  177                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41729                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41729                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41729                       # number of overall misses
system.iocache.overall_misses::total            41729                       # number of overall misses
system.iocache.ReadReq_miss_latency          20391998                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency       5720293806                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency         5740685804                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency        5740685804                       # number of overall miss cycles
system.iocache.ReadReq_accesses::1                177                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41729                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41729                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41729                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41729                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115209.028249                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137665.907923                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137570.653598                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137570.653598                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      64638062                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6181.319881                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                       41520                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.ReadReq_mshr_misses                177                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses               41729                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses              41729                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.ReadReq_mshr_miss_latency     11187998                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency   3559436992                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency    3570624990                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency   3570624990                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85662.230266                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency 85566.991541                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency 85566.991541                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.read_hits                     9525013                       # DTB read hits
system.cpu0.dtb.read_misses                     35809                       # DTB read misses
system.cpu0.dtb.read_acv                          596                       # DTB read access violations
system.cpu0.dtb.read_accesses                  640960                       # DTB read accesses
system.cpu0.dtb.write_hits                    6193277                       # DTB write hits
system.cpu0.dtb.write_misses                     8191                       # DTB write misses
system.cpu0.dtb.write_acv                         352                       # DTB write access violations
system.cpu0.dtb.write_accesses                 218947                       # DTB write accesses
system.cpu0.dtb.data_hits                    15718290                       # DTB hits
system.cpu0.dtb.data_misses                     44000                       # DTB misses
system.cpu0.dtb.data_acv                          948                       # DTB access violations
system.cpu0.dtb.data_accesses                  859907                       # DTB accesses
system.cpu0.itb.fetch_hits                    1059968                       # ITB hits
system.cpu0.itb.fetch_misses                    28334                       # ITB misses
system.cpu0.itb.fetch_acv                         968                       # ITB acv
system.cpu0.itb.fetch_accesses                1088302                       # ITB accesses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.numCycles                       112143855                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                13691834                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted          11482212                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            486842                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups             12387016                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 6381871                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  919331                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect              37475                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          28027181                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      69568075                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   13691834                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           7301202                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     13494473                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2151438                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles              34839073                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles               31251                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       192820                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       330609                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          117                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  8536872                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               297084                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples          78309049                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.888378                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.203941                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                64814576     82.77%     82.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  945457      1.21%     83.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1900376      2.43%     86.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  913364      1.17%     87.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2830968      3.62%     91.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  643425      0.82%     92.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  763526      0.98%     92.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 1019235      1.30%     94.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4478122      5.72%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            78309049                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.122092                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.620347                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                29152885                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             34531702                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 12346249                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               922431                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1355781                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved              563186                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                37995                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              68107436                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               115019                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1355781                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                30289459                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12441617                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      18623001                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 11519994                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4079195                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              64318914                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 6762                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                463310                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              1470134                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands           43045469                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             78042276                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        77610485                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           431791                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             36467151                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 6578318                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1575666                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        238414                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 11470150                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10031617                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6527341                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1189503                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores          776121                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  56398484                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            2006474                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 54915556                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           111021                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        7522313                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      3811151                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved       1368811                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     78309049                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.701267                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.347671                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           54156181     69.16%     69.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10641057     13.59%     82.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            5191025      6.63%     89.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3329795      4.25%     93.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2517318      3.21%     96.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1471186      1.88%     98.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             638979      0.82%     99.54% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             264076      0.34%     99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              99432      0.13%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       78309049                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  63169      8.93%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                344330     48.66%     57.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               300145     42.41%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             3325      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             37729557     68.70%     68.71% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               60298      0.11%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.82% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15682      0.03%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1654      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.85% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             9958587     18.13%     86.99% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6269977     11.42%     98.40% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            876476      1.60%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              54915556                       # Type of FU issued
system.cpu0.iq.rate                          0.489688                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     707644                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.012886                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         188337006                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         65642365                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     53492231                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             621820                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            297359                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       294491                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              55293187                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 326688                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          545095                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      1437170                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        14653                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        12768                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       528040                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads        18971                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       166861                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1355781                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8686714                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               606542                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           61919404                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           833136                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10031617                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6527341                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts           1771520                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                483474                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                10610                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         12768                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        354996                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       356258                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              711254                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             54276592                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts              9587869                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           638964                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                      3514446                       # number of nop insts executed
system.cpu0.iew.exec_refs                    15803723                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 8658040                       # Number of branches executed
system.cpu0.iew.exec_stores                   6215854                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.483991                       # Inst execution rate
system.cpu0.iew.wb_sent                      53903758                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     53786722                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 26555285                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 35742632                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.479623                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.742958                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      53643051                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts        8183882                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         637663                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           648245                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     76953268                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.697086                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.608248                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     56721555     73.71%     73.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8492436     11.04%     84.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4533561      5.89%     90.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2497224      3.25%     93.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1462149      1.90%     95.78% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       614089      0.80%     96.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       448311      0.58%     97.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       488630      0.63%     97.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1695313      2.20%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     76953268                       # Number of insts commited each cycle
system.cpu0.commit.count                     53643051                       # Number of instructions committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14593748                       # Number of memory references committed
system.cpu0.commit.loads                      8594447                       # Number of loads committed
system.cpu0.commit.membars                     217509                       # Number of memory barriers committed
system.cpu0.commit.branches                   8090596                       # Number of branches committed
system.cpu0.commit.fp_insts                    291990                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 49625357                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              704226                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1695313                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   136894487                       # The number of ROB reads
system.cpu0.rob.rob_writes                  125011331                       # The number of ROB writes
system.cpu0.timesIdled                        1231743                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       33834806                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  3682779567                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   50529139                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             50529139                       # Number of Instructions Simulated
system.cpu0.cpi                              2.219390                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.219390                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.450574                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.450574                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                71166140                       # number of integer regfile reads
system.cpu0.int_regfile_writes               38904534                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   143931                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  146323                       # number of floating regfile writes
system.cpu0.misc_regfile_reads                1862401                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                887781                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.cpu0.icache.replacements                970410                       # number of replacements
system.cpu0.icache.tagsinuse               510.008513                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 7511566                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                970922                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                  7.736529                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23358767000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0           510.008513                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.996110                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::0            7511566                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        7511566                       # number of ReadReq hits
system.cpu0.icache.demand_hits::0             7511566                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         7511566                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::0            7511566                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        7511566                       # number of overall hits
system.cpu0.icache.ReadReq_misses::0          1025306                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1025306                       # number of ReadReq misses
system.cpu0.icache.demand_misses::0           1025306                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1025306                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::0          1025306                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total      1025306                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency   15323045497                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency    15323045497                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency   15323045497                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::0        8536872                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      8536872                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::0         8536872                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      8536872                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::0        8536872                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      8536872                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::0      0.120103                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::0       0.120103                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::0      0.120103                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::0 14944.851095                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::0 14944.851095                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::0 14944.851095                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1297498                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              107                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks                     220                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits            54249                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits             54249                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits            54249                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses         971057                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses          971057                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses         971057                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency  11617533498                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency  11617533498                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency  11617533498                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.113749                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::0     0.113749                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::0     0.113749                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11963.801814                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 11963.801814                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 11963.801814                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements               1340651                       # number of replacements
system.cpu0.dcache.tagsinuse               503.872538                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                11358067                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs               1341162                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                  8.468826                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0           504.872538                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.986079                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::0            6993872                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6993872                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::0           3966970                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3966970                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::0       182544                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       182544                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::0        208490                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       208490                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::0            10960842                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10960842                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::0           10960842                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10960842                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::0          1697480                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1697480                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::0         1808304                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1808304                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::0        21693                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21693                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::0          688                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total          688                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::0           3505784                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3505784                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::0          3505784                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3505784                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency   37053025000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency  55161743853                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency    326351000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency      6342500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency    92214768853                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency   92214768853                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::0        8691352                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8691352                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::0       5775274                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5775274                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::0       204237                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       204237                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::0       209178                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       209178                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::0        14466626                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14466626                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::0       14466626                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14466626                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::0      0.195307                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::0     0.313111                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.106215                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003289                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::0       0.242336                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::0      0.242336                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::0 21828.254236                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::0 30504.684972                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15044.069516                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  9218.750000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::0 26303.608224                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::0 26303.608224                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs    888039305                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       192000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            98700                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              8                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8997.358713                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        24000                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks                  791009                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits           651385                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits         1523767                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits         4864                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits           2175152                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits          2175152                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses        1046095                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses        284537                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses        16829                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses          688                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses         1330632                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses        1330632                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency  24225951000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency   8293520304                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    195490000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency      4269500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency  32519471304                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency  32519471304                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    916801000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1252089998                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency   2168890998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.120360                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049268                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.082399                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.003289                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::0     0.091979                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::0     0.091979                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23158.461708                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29147.423021                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11616.257650                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  6205.668605                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 24439.117129                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 24439.117129                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.read_hits                     1327892                       # DTB read hits
system.cpu1.dtb.read_misses                     10318                       # DTB read misses
system.cpu1.dtb.read_acv                            5                       # DTB read access violations
system.cpu1.dtb.read_accesses                  331425                       # DTB read accesses
system.cpu1.dtb.write_hits                     775217                       # DTB write hits
system.cpu1.dtb.write_misses                     3380                       # DTB write misses
system.cpu1.dtb.write_acv                          51                       # DTB write access violations
system.cpu1.dtb.write_accesses                 128049                       # DTB write accesses
system.cpu1.dtb.data_hits                     2103109                       # DTB hits
system.cpu1.dtb.data_misses                     13698                       # DTB misses
system.cpu1.dtb.data_acv                           56                       # DTB access violations
system.cpu1.dtb.data_accesses                  459474                       # DTB accesses
system.cpu1.itb.fetch_hits                     367800                       # ITB hits
system.cpu1.itb.fetch_misses                     7781                       # ITB misses
system.cpu1.itb.fetch_acv                         134                       # ITB acv
system.cpu1.itb.fetch_accesses                 375581                       # ITB accesses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.numCycles                         9964881                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 1747552                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           1443569                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect             66414                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              1567726                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                  697812                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  120159                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect               5219                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles           3352807                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                       8393265                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    1747552                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches            817971                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      1599998                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                 341231                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles               3951622                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles               24365                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        65426                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles        48200                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  1053319                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes                37675                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples           9267506                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.905666                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.249416                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                 7667508     82.74%     82.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  116348      1.26%     83.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  230890      2.49%     86.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  132710      1.43%     87.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  250243      2.70%     90.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                   85158      0.92%     91.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  106718      1.15%     92.68% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                   73511      0.79%     93.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  604420      6.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total             9267506                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.175371                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.842285                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                 3427974                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles              4057837                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  1486886                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles                74257                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles                220551                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved               74813                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                 4599                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts               8126768                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts                13850                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles                220551                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                 3564378                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                 427759                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles       3208421                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  1411256                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles               435139                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts               7552023                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  104                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 45897                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents                92610                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands            5051424                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups              9247695                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups         9194844                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            52851                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps              4016877                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 1034547                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            305973                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts         22549                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  1293822                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             1418447                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores             841500                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           143535                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores           89440                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                   6603642                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             325438                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                  6286957                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            22758                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        1275148                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined       714507                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        249945                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples      9267506                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.678387                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.328894                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0            6496050     70.09%     70.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            1227596     13.25%     83.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2             583666      6.30%     89.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             391304      4.22%     93.86% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             294316      3.18%     97.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             159029      1.72%     98.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6              73572      0.79%     99.55% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              31508      0.34%     99.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              10465      0.11%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total        9267506                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                   2850      1.96%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                 81883     56.36%     58.33% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                60541     41.67%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass             3977      0.06%      0.06% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              3891249     61.89%     61.96% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               10225      0.16%     62.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              10071      0.16%     62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.28% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1988      0.03%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.31% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             1383111     22.00%     84.31% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite             794977     12.64%     96.96% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            191359      3.04%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total               6286957                       # Type of FU issued
system.cpu1.iq.rate                          0.630911                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                     145274                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.023107                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads          21930562                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes          8166757                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses      6084651                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              78890                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes             39096                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses        37806                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses               6387378                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                  40876                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           61877                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       265041                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         6645                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation         1728                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       113419                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads          368                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        22536                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                220551                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 309881                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                12131                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts            7193888                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            99371                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              1418447                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts              841500                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            303567                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  4003                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 5102                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents          1728                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         48086                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect        60250                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              108336                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts              6208556                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts              1341795                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts            78401                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       264808                       # number of nop insts executed
system.cpu1.iew.exec_refs                     2123746                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                  906293                       # Number of branches executed
system.cpu1.iew.exec_stores                    781951                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.623044                       # Inst execution rate
system.cpu1.iew.wb_sent                       6150217                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                      6122457                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                  2959215                       # num instructions producing a value
system.cpu1.iew.wb_consumers                  4044738                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.614403                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.731621                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts       5811574                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts        1309607                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls          75493                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           100450                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples      9046955                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.642379                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.547455                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0      6775881     74.90%     74.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      1100597     12.17%     87.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2       394396      4.36%     91.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       244103      2.70%     94.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       155347      1.72%     95.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5        74536      0.82%     96.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6        76677      0.85%     97.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7        67598      0.75%     98.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       157820      1.74%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total      9046955                       # Number of insts commited each cycle
system.cpu1.commit.count                      5811574                       # Number of instructions committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                       1881487                       # Number of memory references committed
system.cpu1.commit.loads                      1153406                       # Number of loads committed
system.cpu1.commit.membars                      20496                       # Number of memory barriers committed
system.cpu1.commit.branches                    821024                       # Number of branches committed
system.cpu1.commit.fp_insts                     36401                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                  5437311                       # Number of committed integer instructions.
system.cpu1.commit.function_calls               89377                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events               157820                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                    15919643                       # The number of ROB reads
system.cpu1.rob.rob_writes                   14461697                       # The number of ROB writes
system.cpu1.timesIdled                          81901                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         697375                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  3784961926                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                    5588082                       # Number of Instructions Simulated
system.cpu1.committedInsts_total              5588082                       # Number of Instructions Simulated
system.cpu1.cpi                              1.783238                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.783238                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.560778                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.560778                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                 8095217                       # number of integer regfile reads
system.cpu1.int_regfile_writes                4412873                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    24584                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   23091                       # number of floating regfile writes
system.cpu1.misc_regfile_reads                 284668                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                134791                       # number of misc regfile writes
system.cpu1.icache.replacements                110606                       # number of replacements
system.cpu1.icache.tagsinuse               453.435417                       # Cycle average of tags in use
system.cpu1.icache.total_refs                  936898                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                111117                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                  8.431635                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1874818624000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0           453.435417                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.885616                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::0             936898                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total         936898                       # number of ReadReq hits
system.cpu1.icache.demand_hits::0              936898                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total          936898                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::0             936898                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total         936898                       # number of overall hits
system.cpu1.icache.ReadReq_misses::0           116421                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       116421                       # number of ReadReq misses
system.cpu1.icache.demand_misses::0            116421                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        116421                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::0           116421                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       116421                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency    1750783999                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency     1750783999                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency    1750783999                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::0        1053319                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1053319                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::0         1053319                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1053319                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::0        1053319                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1053319                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::0      0.110528                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::0       0.110528                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::0      0.110528                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::0 15038.386537                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::0 15038.386537                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::0 15038.386537                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs        96999                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs               14                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  6928.500000                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks                      37                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits             5236                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits              5236                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits             5236                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses         111185                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses          111185                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses         111185                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency   1333353499                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency   1333353499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency   1333353499                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.105557                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::0     0.105557                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::0     0.105557                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11992.206674                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11992.206674                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11992.206674                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                 62388                       # number of replacements
system.cpu1.dcache.tagsinuse               392.324021                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 1699992                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                 62715                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 27.106625                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1874614053500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0           392.324021                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.766258                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::0            1127254                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1127254                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::0            549515                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total        549515                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::0        16791                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        16791                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::0         14923                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        14923                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::0             1676769                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         1676769                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::0            1676769                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        1676769                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::0           106582                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       106582                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::0          157839                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       157839                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::0         1481                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         1481                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::0          695                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total          695                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::0            264421                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        264421                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::0           264421                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       264421                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency    1787903500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency   5181152780                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency     19396000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency      8380000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency     6969056280                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency    6969056280                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::0        1233836                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      1233836                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::0        707354                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total       707354                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::0        18272                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        18272                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::0        15618                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        15618                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::0         1941190                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      1941190                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::0        1941190                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      1941190                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::0      0.086383                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::0     0.223140                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.081053                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044500                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::0       0.136216                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::0      0.136216                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::0 16774.910398                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::0 32825.555028                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13096.556381                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12057.553957                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::0 26355.910764                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::0 26355.910764                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     86281997                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             6886                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks                   35937                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits            62835                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits          134042                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits          295                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits            196877                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits           196877                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses          43747                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses         23797                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses         1186                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses          695                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses           67544                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses          67544                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency    555340000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency    753314485                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     11632000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency      6287000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency   1308654485                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency   1308654485                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     19116500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    320800500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency    339917000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035456                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.033642                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.064908                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.044500                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::0     0.034795                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::0     0.034795                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.356184                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31655.859352                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  9807.757167                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9046.043165                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 19374.844324                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 19374.844324                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei                    199147                       # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0                   71494     40.63%     40.63% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    238      0.14%     40.76% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1915      1.09%     41.85% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                      8      0.00%     41.86% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                 102317     58.14%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              175972                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    70129     49.24%     49.24% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     238      0.17%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1915      1.34%     50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                       8      0.01%     50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   70122     49.24%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               142412                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1858860218500     97.97%     97.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               90821000      0.00%     97.97% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              390050500      0.02%     97.99% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30                4014000      0.00%     97.99% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            38119760000      2.01%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1897464864000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.980907                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.685341                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2                         8      3.72%      3.72% # number of syscalls executed
system.cpu0.kern.syscall::3                        18      8.37%     12.09% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.40%     13.49% # number of syscalls executed
system.cpu0.kern.syscall::6                        32     14.88%     28.37% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.47%     28.84% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      3.72%     32.56% # number of syscalls executed
system.cpu0.kern.syscall::19                       10      4.65%     37.21% # number of syscalls executed
system.cpu0.kern.syscall::20                        6      2.79%     40.00% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.47%     40.47% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.40%     41.86% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      2.79%     44.65% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      0.93%     45.58% # number of syscalls executed
system.cpu0.kern.syscall::45                       33     15.35%     60.93% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.40%     62.33% # number of syscalls executed
system.cpu0.kern.syscall::48                       10      4.65%     66.98% # number of syscalls executed
system.cpu0.kern.syscall::54                       10      4.65%     71.63% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.47%     72.09% # number of syscalls executed
system.cpu0.kern.syscall::59                        6      2.79%     74.88% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     10.70%     85.58% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.40%     86.98% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      2.79%     89.77% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.47%     90.23% # number of syscalls executed
system.cpu0.kern.syscall::90                        3      1.40%     91.63% # number of syscalls executed
system.cpu0.kern.syscall::92                        9      4.19%     95.81% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      0.93%     96.74% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      0.93%     97.67% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.47%     98.14% # number of syscalls executed
system.cpu0.kern.syscall::144                       2      0.93%     99.07% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      0.93%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   215                       # number of syscalls executed
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  105      0.06%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3840      2.08%      2.14% # number of callpals executed
system.cpu0.kern.callpal::tbi                      50      0.03%      2.17% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.17% # number of callpals executed
system.cpu0.kern.callpal::swpipl               169050     91.54%     93.71% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6330      3.43%     97.14% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.14% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     97.14% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     9      0.00%     97.15% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     97.15% # number of callpals executed
system.cpu0.kern.callpal::rti                    4761      2.58%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 369      0.20%     99.93% # number of callpals executed
system.cpu0.kern.callpal::imb                     135      0.07%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                184665                       # number of callpals executed
system.cpu0.kern.mode_switch::kernel             7257                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1249                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_good::kernel               1248                      
system.cpu0.kern.mode_good::user                 1249                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch_good::kernel     0.171972                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1895601847000     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1863009000      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3841                       # number of times the context was actually changed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2274                       # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei                     38551                       # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0                   10250     33.36%     33.36% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1920      6.25%     39.61% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    105      0.34%     39.95% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  18453     60.05%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               30728                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    10238     45.71%     45.71% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1920      8.57%     54.29% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     105      0.47%     54.76% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   10133     45.24%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                22396                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1871094081500     98.61%     98.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              343283500      0.02%     98.63% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30               42013500      0.00%     98.63% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            25985147000      1.37%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1897464525500                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.998829                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.549125                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3                        12     10.81%     10.81% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.90%     11.71% # number of syscalls executed
system.cpu1.kern.syscall::6                        10      9.01%     20.72% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.90%     21.62% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      6.31%     27.93% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.70%     30.63% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.70%     33.33% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      4.50%     37.84% # number of syscalls executed
system.cpu1.kern.syscall::45                       21     18.92%     56.76% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.70%     59.46% # number of syscalls executed
system.cpu1.kern.syscall::59                        1      0.90%     60.36% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     27.93%     88.29% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      9.01%     97.30% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.70%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   111                       # number of syscalls executed
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                    8      0.03%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx                  393      1.24%      1.27% # number of callpals executed
system.cpu1.kern.callpal::tbi                       3      0.01%      1.28% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.02%      1.30% # number of callpals executed
system.cpu1.kern.callpal::swpipl                26174     82.49%     83.79% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2413      7.60%     91.40% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.40% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.02%     91.42% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     91.43% # number of callpals executed
system.cpu1.kern.callpal::rti                    2528      7.97%     99.39% # number of callpals executed
system.cpu1.kern.callpal::callsys                 146      0.46%     99.86% # number of callpals executed
system.cpu1.kern.callpal::imb                      45      0.14%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 31730                       # number of callpals executed
system.cpu1.kern.mode_switch::kernel              869                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                491                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2054                       # number of protection mode switches
system.cpu1.kern.mode_good::kernel                521                      
system.cpu1.kern.mode_good::user                  491                      
system.cpu1.kern.mode_good::idle                   30                      
system.cpu1.kern.mode_switch_good::kernel     0.599540                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.014606                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.614145                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        2062444500      0.11%      0.11% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user           847773000      0.04%      0.15% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1893876331500     99.85%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                     394                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------