stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.903124 # Number of seconds simulated 4sim_ticks 1903123778500 # Number of ticks simulated 5final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 103415 # Simulator instruction rate (inst/s) 8host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3505224116 # Simulator tick rate (ticks/s) 10host_mem_usage 322696 # Number of bytes of host memory used 11host_seconds 542.94 # Real time elapsed on the host 12sim_insts 56148221 # Number of instructions simulated 13sim_ops 56148221 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory 26system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory 30system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory 35system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.readReqs 411673 # Number of read requests accepted 57system.physmem.writeReqs 123979 # Number of write requests accepted 58system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue 59system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue 60system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM 61system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue 62system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM 63system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side 64system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side 65system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue 66system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 67system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write 68system.physmem.perBankRdBursts::0 25632 # Per bank write bursts 69system.physmem.perBankRdBursts::1 25720 # Per bank write bursts 70system.physmem.perBankRdBursts::2 26346 # Per bank write bursts 71system.physmem.perBankRdBursts::3 25660 # Per bank write bursts 72system.physmem.perBankRdBursts::4 25672 # Per bank write bursts 73system.physmem.perBankRdBursts::5 25150 # Per bank write bursts 74system.physmem.perBankRdBursts::6 25568 # Per bank write bursts 75system.physmem.perBankRdBursts::7 25491 # Per bank write bursts 76system.physmem.perBankRdBursts::8 25973 # Per bank write bursts 77system.physmem.perBankRdBursts::9 26167 # Per bank write bursts 78system.physmem.perBankRdBursts::10 25812 # Per bank write bursts 79system.physmem.perBankRdBursts::11 25687 # Per bank write bursts 80system.physmem.perBankRdBursts::12 26023 # Per bank write bursts 81system.physmem.perBankRdBursts::13 25844 # Per bank write bursts 82system.physmem.perBankRdBursts::14 25108 # Per bank write bursts 83system.physmem.perBankRdBursts::15 25632 # Per bank write bursts 84system.physmem.perBankWrBursts::0 8431 # Per bank write bursts 85system.physmem.perBankWrBursts::1 7989 # Per bank write bursts 86system.physmem.perBankWrBursts::2 8275 # Per bank write bursts 87system.physmem.perBankWrBursts::3 7382 # Per bank write bursts 88system.physmem.perBankWrBursts::4 7684 # Per bank write bursts 89system.physmem.perBankWrBursts::5 7400 # Per bank write bursts 90system.physmem.perBankWrBursts::6 7193 # Per bank write bursts 91system.physmem.perBankWrBursts::7 7021 # Per bank write bursts 92system.physmem.perBankWrBursts::8 7374 # Per bank write bursts 93system.physmem.perBankWrBursts::9 7755 # Per bank write bursts 94system.physmem.perBankWrBursts::10 7777 # Per bank write bursts 95system.physmem.perBankWrBursts::11 7454 # Per bank write bursts 96system.physmem.perBankWrBursts::12 8052 # Per bank write bursts 97system.physmem.perBankWrBursts::13 8097 # Per bank write bursts 98system.physmem.perBankWrBursts::14 7762 # Per bank write bursts 99system.physmem.perBankWrBursts::15 8306 # Per bank write bursts 100system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 101system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 102system.physmem.totGap 1903119235000 # Total gap between requests 103system.physmem.readPktSize::0 0 # Read request sizes (log2) 104system.physmem.readPktSize::1 0 # Read request sizes (log2) 105system.physmem.readPktSize::2 0 # Read request sizes (log2) 106system.physmem.readPktSize::3 0 # Read request sizes (log2) 107system.physmem.readPktSize::4 0 # Read request sizes (log2) 108system.physmem.readPktSize::5 0 # Read request sizes (log2) 109system.physmem.readPktSize::6 411673 # Read request sizes (log2) 110system.physmem.writePktSize::0 0 # Write request sizes (log2) 111system.physmem.writePktSize::1 0 # Write request sizes (log2) 112system.physmem.writePktSize::2 0 # Write request sizes (log2) 113system.physmem.writePktSize::3 0 # Write request sizes (log2) 114system.physmem.writePktSize::4 0 # Write request sizes (log2) 115system.physmem.writePktSize::5 0 # Write request sizes (log2) 116system.physmem.writePktSize::6 123979 # Write request sizes (log2) 117system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 149system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see 213system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation 227system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads 274system.physmem.totQLat 3887945250 # Total ticks spent queuing 275system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 279system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.14 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing 289system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing 290system.physmem.readRowHits 371100 # Number of row buffer hits during reads 291system.physmem.writeRowHits 99427 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes 294system.physmem.avgGap 3552902.32 # Average gap between requests 295system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined 296system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states 297system.physmem.memoryStateTime::REF 63549460000 # Time in different power states 298system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states 300system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.membus.throughput 18054612 # Throughput (bytes/s) 302system.membus.trans_dist::ReadReq 296849 # Transaction distribution 303system.membus.trans_dist::ReadResp 296569 # Transaction distribution 304system.membus.trans_dist::WriteReq 12351 # Transaction distribution 305system.membus.trans_dist::WriteResp 12351 # Transaction distribution 306system.membus.trans_dist::Writeback 82427 # Transaction distribution 307system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 308system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 309system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution 310system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution 311system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution 312system.membus.trans_dist::ReadExReq 122594 # Transaction distribution 313system.membus.trans_dist::ReadExResp 122459 # Transaction distribution 314system.membus.trans_dist::BadAddressError 280 # Transaction distribution 315system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) 320system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) 321system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 326system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 327system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) 328system.membus.data_through_bus 34349922 # Total data (bytes) 329system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) 330system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) 331system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 332system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) 333system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 334system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) 335system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 336system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) 337system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 338system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) 339system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 340system.cpu_clk_domain.clock 500 # Clock period in ticks 341system.l2c.tags.replacements 345839 # number of replacements 342system.l2c.tags.tagsinuse 65302.356632 # Cycle average of tags in use 343system.l2c.tags.total_refs 2646364 # Total number of references to valid blocks. 344system.l2c.tags.sampled_refs 411006 # Sample count of references to valid blocks. 345system.l2c.tags.avg_refs 6.438748 # Average number of references to valid blocks. 346system.l2c.tags.warmup_cycle 7093732750 # Cycle when the warmup percentage was hit. 347system.l2c.tags.occ_blocks::writebacks 53566.898021 # Average occupied blocks per requestor 348system.l2c.tags.occ_blocks::cpu0.inst 4193.415796 # Average occupied blocks per requestor 349system.l2c.tags.occ_blocks::cpu0.data 5564.276304 # Average occupied blocks per requestor 350system.l2c.tags.occ_blocks::cpu1.inst 1386.450480 # Average occupied blocks per requestor 351system.l2c.tags.occ_blocks::cpu1.data 591.316031 # Average occupied blocks per requestor 352system.l2c.tags.occ_percent::writebacks 0.817366 # Average percentage of cache occupancy 353system.l2c.tags.occ_percent::cpu0.inst 0.063986 # Average percentage of cache occupancy 354system.l2c.tags.occ_percent::cpu0.data 0.084904 # Average percentage of cache occupancy 355system.l2c.tags.occ_percent::cpu1.inst 0.021156 # Average percentage of cache occupancy 356system.l2c.tags.occ_percent::cpu1.data 0.009023 # Average percentage of cache occupancy 357system.l2c.tags.occ_percent::total 0.996435 # Average percentage of cache occupancy 358system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 359system.l2c.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id 360system.l2c.tags.age_task_id_blocks_1024::1 2289 # Occupied blocks per task id 361system.l2c.tags.age_task_id_blocks_1024::2 6029 # Occupied blocks per task id 362system.l2c.tags.age_task_id_blocks_1024::3 6100 # Occupied blocks per task id 363system.l2c.tags.age_task_id_blocks_1024::4 50524 # Occupied blocks per task id 364system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 365system.l2c.tags.tag_accesses 27707761 # Number of tag accesses 366system.l2c.tags.data_accesses 27707761 # Number of data accesses 367system.l2c.ReadReq_hits::cpu0.inst 751132 # number of ReadReq hits 368system.l2c.ReadReq_hits::cpu0.data 546267 # number of ReadReq hits 369system.l2c.ReadReq_hits::cpu1.inst 350558 # number of ReadReq hits 370system.l2c.ReadReq_hits::cpu1.data 278844 # number of ReadReq hits 371system.l2c.ReadReq_hits::total 1926801 # number of ReadReq hits 372system.l2c.Writeback_hits::writebacks 841911 # number of Writeback hits 373system.l2c.Writeback_hits::total 841911 # number of Writeback hits 374system.l2c.UpgradeReq_hits::cpu0.data 128 # number of UpgradeReq hits 375system.l2c.UpgradeReq_hits::cpu1.data 75 # number of UpgradeReq hits 376system.l2c.UpgradeReq_hits::total 203 # number of UpgradeReq hits 377system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits 378system.l2c.SCUpgradeReq_hits::cpu1.data 37 # number of SCUpgradeReq hits 379system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits 380system.l2c.ReadExReq_hits::cpu0.data 140399 # number of ReadExReq hits 381system.l2c.ReadExReq_hits::cpu1.data 48308 # number of ReadExReq hits 382system.l2c.ReadExReq_hits::total 188707 # number of ReadExReq hits 383system.l2c.demand_hits::cpu0.inst 751132 # number of demand (read+write) hits 384system.l2c.demand_hits::cpu0.data 686666 # number of demand (read+write) hits 385system.l2c.demand_hits::cpu1.inst 350558 # number of demand (read+write) hits 386system.l2c.demand_hits::cpu1.data 327152 # number of demand (read+write) hits 387system.l2c.demand_hits::total 2115508 # number of demand (read+write) hits 388system.l2c.overall_hits::cpu0.inst 751132 # number of overall hits 389system.l2c.overall_hits::cpu0.data 686666 # number of overall hits 390system.l2c.overall_hits::cpu1.inst 350558 # number of overall hits 391system.l2c.overall_hits::cpu1.data 327152 # number of overall hits 392system.l2c.overall_hits::total 2115508 # number of overall hits 393system.l2c.ReadReq_misses::cpu0.inst 11641 # number of ReadReq misses 394system.l2c.ReadReq_misses::cpu0.data 272205 # number of ReadReq misses 395system.l2c.ReadReq_misses::cpu1.inst 3725 # number of ReadReq misses 396system.l2c.ReadReq_misses::cpu1.data 1926 # number of ReadReq misses 397system.l2c.ReadReq_misses::total 289497 # number of ReadReq misses 398system.l2c.UpgradeReq_misses::cpu0.data 2575 # number of UpgradeReq misses 399system.l2c.UpgradeReq_misses::cpu1.data 542 # number of UpgradeReq misses 400system.l2c.UpgradeReq_misses::total 3117 # number of UpgradeReq misses 401system.l2c.SCUpgradeReq_misses::cpu0.data 63 # number of SCUpgradeReq misses 402system.l2c.SCUpgradeReq_misses::cpu1.data 103 # number of SCUpgradeReq misses 403system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses 404system.l2c.ReadExReq_misses::cpu0.data 107603 # number of ReadExReq misses 405system.l2c.ReadExReq_misses::cpu1.data 15017 # number of ReadExReq misses 406system.l2c.ReadExReq_misses::total 122620 # number of ReadExReq misses 407system.l2c.demand_misses::cpu0.inst 11641 # number of demand (read+write) misses 408system.l2c.demand_misses::cpu0.data 379808 # number of demand (read+write) misses 409system.l2c.demand_misses::cpu1.inst 3725 # number of demand (read+write) misses 410system.l2c.demand_misses::cpu1.data 16943 # number of demand (read+write) misses 411system.l2c.demand_misses::total 412117 # number of demand (read+write) misses 412system.l2c.overall_misses::cpu0.inst 11641 # number of overall misses 413system.l2c.overall_misses::cpu0.data 379808 # number of overall misses 414system.l2c.overall_misses::cpu1.inst 3725 # number of overall misses 415system.l2c.overall_misses::cpu1.data 16943 # number of overall misses 416system.l2c.overall_misses::total 412117 # number of overall misses 417system.l2c.ReadReq_miss_latency::cpu0.inst 889120500 # number of ReadReq miss cycles 418system.l2c.ReadReq_miss_latency::cpu0.data 17862600250 # number of ReadReq miss cycles 419system.l2c.ReadReq_miss_latency::cpu1.inst 290708250 # number of ReadReq miss cycles 420system.l2c.ReadReq_miss_latency::cpu1.data 148179250 # number of ReadReq miss cycles 421system.l2c.ReadReq_miss_latency::total 19190608250 # number of ReadReq miss cycles 422system.l2c.UpgradeReq_miss_latency::cpu0.data 882962 # number of UpgradeReq miss cycles 423system.l2c.UpgradeReq_miss_latency::cpu1.data 1281445 # number of UpgradeReq miss cycles 424system.l2c.UpgradeReq_miss_latency::total 2164407 # number of UpgradeReq miss cycles 425system.l2c.SCUpgradeReq_miss_latency::cpu0.data 245491 # number of SCUpgradeReq miss cycles 426system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187992 # number of SCUpgradeReq miss cycles 427system.l2c.SCUpgradeReq_miss_latency::total 433483 # number of SCUpgradeReq miss cycles 428system.l2c.ReadExReq_miss_latency::cpu0.data 8878273882 # number of ReadExReq miss cycles 429system.l2c.ReadExReq_miss_latency::cpu1.data 1456523709 # number of ReadExReq miss cycles 430system.l2c.ReadExReq_miss_latency::total 10334797591 # number of ReadExReq miss cycles 431system.l2c.demand_miss_latency::cpu0.inst 889120500 # number of demand (read+write) miss cycles 432system.l2c.demand_miss_latency::cpu0.data 26740874132 # number of demand (read+write) miss cycles 433system.l2c.demand_miss_latency::cpu1.inst 290708250 # number of demand (read+write) miss cycles 434system.l2c.demand_miss_latency::cpu1.data 1604702959 # number of demand (read+write) miss cycles 435system.l2c.demand_miss_latency::total 29525405841 # number of demand (read+write) miss cycles 436system.l2c.overall_miss_latency::cpu0.inst 889120500 # number of overall miss cycles 437system.l2c.overall_miss_latency::cpu0.data 26740874132 # number of overall miss cycles 438system.l2c.overall_miss_latency::cpu1.inst 290708250 # number of overall miss cycles 439system.l2c.overall_miss_latency::cpu1.data 1604702959 # number of overall miss cycles 440system.l2c.overall_miss_latency::total 29525405841 # number of overall miss cycles 441system.l2c.ReadReq_accesses::cpu0.inst 762773 # number of ReadReq accesses(hits+misses) 442system.l2c.ReadReq_accesses::cpu0.data 818472 # number of ReadReq accesses(hits+misses) 443system.l2c.ReadReq_accesses::cpu1.inst 354283 # number of ReadReq accesses(hits+misses) 444system.l2c.ReadReq_accesses::cpu1.data 280770 # number of ReadReq accesses(hits+misses) 445system.l2c.ReadReq_accesses::total 2216298 # number of ReadReq accesses(hits+misses) 446system.l2c.Writeback_accesses::writebacks 841911 # number of Writeback accesses(hits+misses) 447system.l2c.Writeback_accesses::total 841911 # number of Writeback accesses(hits+misses) 448system.l2c.UpgradeReq_accesses::cpu0.data 2703 # number of UpgradeReq accesses(hits+misses) 449system.l2c.UpgradeReq_accesses::cpu1.data 617 # number of UpgradeReq accesses(hits+misses) 450system.l2c.UpgradeReq_accesses::total 3320 # number of UpgradeReq accesses(hits+misses) 451system.l2c.SCUpgradeReq_accesses::cpu0.data 99 # number of SCUpgradeReq accesses(hits+misses) 452system.l2c.SCUpgradeReq_accesses::cpu1.data 140 # number of SCUpgradeReq accesses(hits+misses) 453system.l2c.SCUpgradeReq_accesses::total 239 # number of SCUpgradeReq accesses(hits+misses) 454system.l2c.ReadExReq_accesses::cpu0.data 248002 # number of ReadExReq accesses(hits+misses) 455system.l2c.ReadExReq_accesses::cpu1.data 63325 # number of ReadExReq accesses(hits+misses) 456system.l2c.ReadExReq_accesses::total 311327 # number of ReadExReq accesses(hits+misses) 457system.l2c.demand_accesses::cpu0.inst 762773 # number of demand (read+write) accesses 458system.l2c.demand_accesses::cpu0.data 1066474 # number of demand (read+write) accesses 459system.l2c.demand_accesses::cpu1.inst 354283 # number of demand (read+write) accesses 460system.l2c.demand_accesses::cpu1.data 344095 # number of demand (read+write) accesses 461system.l2c.demand_accesses::total 2527625 # number of demand (read+write) accesses 462system.l2c.overall_accesses::cpu0.inst 762773 # number of overall (read+write) accesses 463system.l2c.overall_accesses::cpu0.data 1066474 # number of overall (read+write) accesses 464system.l2c.overall_accesses::cpu1.inst 354283 # number of overall (read+write) accesses 465system.l2c.overall_accesses::cpu1.data 344095 # number of overall (read+write) accesses 466system.l2c.overall_accesses::total 2527625 # number of overall (read+write) accesses 467system.l2c.ReadReq_miss_rate::cpu0.inst 0.015261 # miss rate for ReadReq accesses 468system.l2c.ReadReq_miss_rate::cpu0.data 0.332577 # miss rate for ReadReq accesses 469system.l2c.ReadReq_miss_rate::cpu1.inst 0.010514 # miss rate for ReadReq accesses 470system.l2c.ReadReq_miss_rate::cpu1.data 0.006860 # miss rate for ReadReq accesses 471system.l2c.ReadReq_miss_rate::total 0.130622 # miss rate for ReadReq accesses 472system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952645 # miss rate for UpgradeReq accesses 473system.l2c.UpgradeReq_miss_rate::cpu1.data 0.878444 # miss rate for UpgradeReq accesses 474system.l2c.UpgradeReq_miss_rate::total 0.938855 # miss rate for UpgradeReq accesses 475system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636364 # miss rate for SCUpgradeReq accesses 476system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735714 # miss rate for SCUpgradeReq accesses 477system.l2c.SCUpgradeReq_miss_rate::total 0.694561 # miss rate for SCUpgradeReq accesses 478system.l2c.ReadExReq_miss_rate::cpu0.data 0.433880 # miss rate for ReadExReq accesses 479system.l2c.ReadExReq_miss_rate::cpu1.data 0.237142 # miss rate for ReadExReq accesses 480system.l2c.ReadExReq_miss_rate::total 0.393862 # miss rate for ReadExReq accesses 481system.l2c.demand_miss_rate::cpu0.inst 0.015261 # miss rate for demand accesses 482system.l2c.demand_miss_rate::cpu0.data 0.356134 # miss rate for demand accesses 483system.l2c.demand_miss_rate::cpu1.inst 0.010514 # miss rate for demand accesses 484system.l2c.demand_miss_rate::cpu1.data 0.049239 # miss rate for demand accesses 485system.l2c.demand_miss_rate::total 0.163045 # miss rate for demand accesses 486system.l2c.overall_miss_rate::cpu0.inst 0.015261 # miss rate for overall accesses 487system.l2c.overall_miss_rate::cpu0.data 0.356134 # miss rate for overall accesses 488system.l2c.overall_miss_rate::cpu1.inst 0.010514 # miss rate for overall accesses 489system.l2c.overall_miss_rate::cpu1.data 0.049239 # miss rate for overall accesses 490system.l2c.overall_miss_rate::total 0.163045 # miss rate for overall accesses 491system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76378.360966 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu0.data 65621.866792 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78042.483221 # average ReadReq miss latency 494system.l2c.ReadReq_avg_miss_latency::cpu1.data 76936.266874 # average ReadReq miss latency 495system.l2c.ReadReq_avg_miss_latency::total 66289.489183 # average ReadReq miss latency 496system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 342.897864 # average UpgradeReq miss latency 497system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2364.289668 # average UpgradeReq miss latency 498system.l2c.UpgradeReq_avg_miss_latency::total 694.387873 # average UpgradeReq miss latency 499system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3896.682540 # average SCUpgradeReq miss latency 500system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1825.165049 # average SCUpgradeReq miss latency 501system.l2c.SCUpgradeReq_avg_miss_latency::total 2611.343373 # average SCUpgradeReq miss latency 502system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82509.538600 # average ReadExReq miss latency 503system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96991.656722 # average ReadExReq miss latency 504system.l2c.ReadExReq_avg_miss_latency::total 84283.131553 # average ReadExReq miss latency 505system.l2c.demand_avg_miss_latency::cpu0.inst 76378.360966 # average overall miss latency 506system.l2c.demand_avg_miss_latency::cpu0.data 70406.295107 # average overall miss latency 507system.l2c.demand_avg_miss_latency::cpu1.inst 78042.483221 # average overall miss latency 508system.l2c.demand_avg_miss_latency::cpu1.data 94711.854984 # average overall miss latency 509system.l2c.demand_avg_miss_latency::total 71643.261115 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu0.inst 76378.360966 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu0.data 70406.295107 # average overall miss latency 512system.l2c.overall_avg_miss_latency::cpu1.inst 78042.483221 # average overall miss latency 513system.l2c.overall_avg_miss_latency::cpu1.data 94711.854984 # average overall miss latency 514system.l2c.overall_avg_miss_latency::total 71643.261115 # average overall miss latency 515system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 518system.l2c.blocked::no_targets 0 # number of cycles access was blocked 519system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.l2c.fast_writes 0 # number of fast writes performed 522system.l2c.cache_copies 0 # number of cache copies performed 523system.l2c.writebacks::writebacks 82427 # number of writebacks 524system.l2c.writebacks::total 82427 # number of writebacks 525system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits 526system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits 527system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits 528system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 529system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits 530system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 531system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 532system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 533system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits 534system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 535system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 536system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 537system.l2c.ReadReq_mshr_misses::cpu0.inst 11628 # number of ReadReq MSHR misses 538system.l2c.ReadReq_mshr_misses::cpu0.data 272204 # number of ReadReq MSHR misses 539system.l2c.ReadReq_mshr_misses::cpu1.inst 3721 # number of ReadReq MSHR misses 540system.l2c.ReadReq_mshr_misses::cpu1.data 1926 # number of ReadReq MSHR misses 541system.l2c.ReadReq_mshr_misses::total 289479 # number of ReadReq MSHR misses 542system.l2c.UpgradeReq_mshr_misses::cpu0.data 2575 # number of UpgradeReq MSHR misses 543system.l2c.UpgradeReq_mshr_misses::cpu1.data 542 # number of UpgradeReq MSHR misses 544system.l2c.UpgradeReq_mshr_misses::total 3117 # number of UpgradeReq MSHR misses 545system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 63 # number of SCUpgradeReq MSHR misses 546system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 103 # number of SCUpgradeReq MSHR misses 547system.l2c.SCUpgradeReq_mshr_misses::total 166 # number of SCUpgradeReq MSHR misses 548system.l2c.ReadExReq_mshr_misses::cpu0.data 107603 # number of ReadExReq MSHR misses 549system.l2c.ReadExReq_mshr_misses::cpu1.data 15017 # number of ReadExReq MSHR misses 550system.l2c.ReadExReq_mshr_misses::total 122620 # number of ReadExReq MSHR misses 551system.l2c.demand_mshr_misses::cpu0.inst 11628 # number of demand (read+write) MSHR misses 552system.l2c.demand_mshr_misses::cpu0.data 379807 # number of demand (read+write) MSHR misses 553system.l2c.demand_mshr_misses::cpu1.inst 3721 # number of demand (read+write) MSHR misses 554system.l2c.demand_mshr_misses::cpu1.data 16943 # number of demand (read+write) MSHR misses 555system.l2c.demand_mshr_misses::total 412099 # number of demand (read+write) MSHR misses 556system.l2c.overall_mshr_misses::cpu0.inst 11628 # number of overall MSHR misses 557system.l2c.overall_mshr_misses::cpu0.data 379807 # number of overall MSHR misses 558system.l2c.overall_mshr_misses::cpu1.inst 3721 # number of overall MSHR misses 559system.l2c.overall_mshr_misses::cpu1.data 16943 # number of overall MSHR misses 560system.l2c.overall_mshr_misses::total 412099 # number of overall MSHR misses 561system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 741621000 # number of ReadReq MSHR miss cycles 562system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14467164750 # number of ReadReq MSHR miss cycles 563system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 243575500 # number of ReadReq MSHR miss cycles 564system.l2c.ReadReq_mshr_miss_latency::cpu1.data 151890250 # number of ReadReq MSHR miss cycles 565system.l2c.ReadReq_mshr_miss_latency::total 15604251500 # number of ReadReq MSHR miss cycles 566system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25805570 # number of UpgradeReq MSHR miss cycles 567system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5431039 # number of UpgradeReq MSHR miss cycles 568system.l2c.UpgradeReq_mshr_miss_latency::total 31236609 # number of UpgradeReq MSHR miss cycles 569system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 646561 # number of SCUpgradeReq MSHR miss cycles 570system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1036098 # number of SCUpgradeReq MSHR miss cycles 571system.l2c.SCUpgradeReq_mshr_miss_latency::total 1682659 # number of SCUpgradeReq MSHR miss cycles 572system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7566064618 # number of ReadExReq MSHR miss cycles 573system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1272103789 # number of ReadExReq MSHR miss cycles 574system.l2c.ReadExReq_mshr_miss_latency::total 8838168407 # number of ReadExReq MSHR miss cycles 575system.l2c.demand_mshr_miss_latency::cpu0.inst 741621000 # number of demand (read+write) MSHR miss cycles 576system.l2c.demand_mshr_miss_latency::cpu0.data 22033229368 # number of demand (read+write) MSHR miss cycles 577system.l2c.demand_mshr_miss_latency::cpu1.inst 243575500 # number of demand (read+write) MSHR miss cycles 578system.l2c.demand_mshr_miss_latency::cpu1.data 1423994039 # number of demand (read+write) MSHR miss cycles 579system.l2c.demand_mshr_miss_latency::total 24442419907 # number of demand (read+write) MSHR miss cycles 580system.l2c.overall_mshr_miss_latency::cpu0.inst 741621000 # number of overall MSHR miss cycles 581system.l2c.overall_mshr_miss_latency::cpu0.data 22033229368 # number of overall MSHR miss cycles 582system.l2c.overall_mshr_miss_latency::cpu1.inst 243575500 # number of overall MSHR miss cycles 583system.l2c.overall_mshr_miss_latency::cpu1.data 1423994039 # number of overall MSHR miss cycles 584system.l2c.overall_mshr_miss_latency::total 24442419907 # number of overall MSHR miss cycles 585system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 930400500 # number of ReadReq MSHR uncacheable cycles 586system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 458814500 # number of ReadReq MSHR uncacheable cycles 587system.l2c.ReadReq_mshr_uncacheable_latency::total 1389215000 # number of ReadReq MSHR uncacheable cycles 588system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1575945000 # number of WriteReq MSHR uncacheable cycles 589system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 887867500 # number of WriteReq MSHR uncacheable cycles 590system.l2c.WriteReq_mshr_uncacheable_latency::total 2463812500 # number of WriteReq MSHR uncacheable cycles 591system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2506345500 # number of overall MSHR uncacheable cycles 592system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1346682000 # number of overall MSHR uncacheable cycles 593system.l2c.overall_mshr_uncacheable_latency::total 3853027500 # number of overall MSHR uncacheable cycles 594system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for ReadReq accesses 595system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.332576 # mshr miss rate for ReadReq accesses 596system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for ReadReq accesses 597system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006860 # mshr miss rate for ReadReq accesses 598system.l2c.ReadReq_mshr_miss_rate::total 0.130614 # mshr miss rate for ReadReq accesses 599system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.952645 # mshr miss rate for UpgradeReq accesses 600system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.878444 # mshr miss rate for UpgradeReq accesses 601system.l2c.UpgradeReq_mshr_miss_rate::total 0.938855 # mshr miss rate for UpgradeReq accesses 602system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636364 # mshr miss rate for SCUpgradeReq accesses 603system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735714 # mshr miss rate for SCUpgradeReq accesses 604system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.694561 # mshr miss rate for SCUpgradeReq accesses 605system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.433880 # mshr miss rate for ReadExReq accesses 606system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237142 # mshr miss rate for ReadExReq accesses 607system.l2c.ReadExReq_mshr_miss_rate::total 0.393862 # mshr miss rate for ReadExReq accesses 608system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for demand accesses 610system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for demand accesses 611system.l2c.demand_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for demand accesses 612system.l2c.demand_mshr_miss_rate::total 0.163038 # mshr miss rate for demand accesses 613system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for overall accesses 614system.l2c.overall_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for overall accesses 615system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for overall accesses 616system.l2c.overall_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for overall accesses 617system.l2c.overall_mshr_miss_rate::total 0.163038 # mshr miss rate for overall accesses 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53148.244515 # average ReadReq mshr miss latency 620system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average ReadReq mshr miss latency 621system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78863.058152 # average ReadReq mshr miss latency 622system.l2c.ReadReq_avg_mshr_miss_latency::total 53904.606206 # average ReadReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.580583 # average UpgradeReq mshr miss latency 624system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.367159 # average UpgradeReq mshr miss latency 625system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.369586 # average UpgradeReq mshr miss latency 626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10262.873016 # average SCUpgradeReq mshr miss latency 627system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10059.203883 # average SCUpgradeReq mshr miss latency 628system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10136.500000 # average SCUpgradeReq mshr miss latency 629system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70314.625224 # average ReadExReq mshr miss latency 630system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84710.913565 # average ReadExReq mshr miss latency 631system.l2c.ReadExReq_avg_mshr_miss_latency::total 72077.706793 # average ReadExReq mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency 635system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency 636system.l2c.demand_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency 637system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency 640system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency 641system.l2c.overall_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency 642system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 643system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 644system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 645system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 646system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 647system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 648system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 649system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 650system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 651system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 652system.iocache.tags.replacements 41695 # number of replacements 653system.iocache.tags.tagsinuse 0.219567 # Cycle average of tags in use 654system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 655system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 656system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 657system.iocache.tags.warmup_cycle 1710336549000 # Cycle when the warmup percentage was hit. 658system.iocache.tags.occ_blocks::tsunami.ide 0.219567 # Average occupied blocks per requestor 659system.iocache.tags.occ_percent::tsunami.ide 0.013723 # Average percentage of cache occupancy 660system.iocache.tags.occ_percent::total 0.013723 # Average percentage of cache occupancy 661system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 662system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 663system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 664system.iocache.tags.tag_accesses 375543 # Number of tag accesses 665system.iocache.tags.data_accesses 375543 # Number of data accesses 666system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 667system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 668system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 669system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 670system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses 671system.iocache.demand_misses::total 175 # number of demand (read+write) misses 672system.iocache.overall_misses::tsunami.ide 175 # number of overall misses 673system.iocache.overall_misses::total 175 # number of overall misses 674system.iocache.ReadReq_miss_latency::tsunami.ide 21364383 # number of ReadReq miss cycles 675system.iocache.ReadReq_miss_latency::total 21364383 # number of ReadReq miss cycles 676system.iocache.demand_miss_latency::tsunami.ide 21364383 # number of demand (read+write) miss cycles 677system.iocache.demand_miss_latency::total 21364383 # number of demand (read+write) miss cycles 678system.iocache.overall_miss_latency::tsunami.ide 21364383 # number of overall miss cycles 679system.iocache.overall_miss_latency::total 21364383 # number of overall miss cycles 680system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 681system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 682system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 683system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 684system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses 685system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses 686system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses 687system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses 688system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 689system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 690system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 691system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 692system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 693system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 694system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency 695system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency 696system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency 697system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency 698system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency 699system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency 700system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.iocache.blocked::no_targets 0 # number of cycles access was blocked 704system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.iocache.fast_writes 41552 # number of fast writes performed 707system.iocache.cache_copies 0 # number of cache copies performed 708system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 709system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 710system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 711system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 712system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses 713system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 714system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses 715system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses 716system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles 717system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles 718system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles 719system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles 720system.iocache.demand_mshr_miss_latency::tsunami.ide 12263383 # number of demand (read+write) MSHR miss cycles 721system.iocache.demand_mshr_miss_latency::total 12263383 # number of demand (read+write) MSHR miss cycles 722system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles 723system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles 724system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 725system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 726system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 727system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 728system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 729system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 730system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 731system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 732system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency 733system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency 734system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency 735system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency 736system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency 737system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency 738system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency 739system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency 740system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 741system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 742system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 743system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 744system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 745system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 746system.disk0.dma_write_txs 395 # Number of DMA write transactions. 747system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 748system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 749system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 750system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 751system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 752system.disk2.dma_write_txs 1 # Number of DMA write transactions. 753system.cpu0.branchPred.lookups 13702956 # Number of BP lookups 754system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted 755system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect 756system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups 757system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits 758system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 759system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage 760system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. 761system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. 762system.cpu0.dtb.fetch_hits 0 # ITB hits 763system.cpu0.dtb.fetch_misses 0 # ITB misses 764system.cpu0.dtb.fetch_acv 0 # ITB acv 765system.cpu0.dtb.fetch_accesses 0 # ITB accesses 766system.cpu0.dtb.read_hits 7950804 # DTB read hits 767system.cpu0.dtb.read_misses 30543 # DTB read misses 768system.cpu0.dtb.read_acv 546 # DTB read access violations 769system.cpu0.dtb.read_accesses 683229 # DTB read accesses 770system.cpu0.dtb.write_hits 5159026 # DTB write hits 771system.cpu0.dtb.write_misses 6845 # DTB write misses 772system.cpu0.dtb.write_acv 353 # DTB write access violations 773system.cpu0.dtb.write_accesses 234573 # DTB write accesses 774system.cpu0.dtb.data_hits 13109830 # DTB hits 775system.cpu0.dtb.data_misses 37388 # DTB misses 776system.cpu0.dtb.data_acv 899 # DTB access violations 777system.cpu0.dtb.data_accesses 917802 # DTB accesses 778system.cpu0.itb.fetch_hits 1312718 # ITB hits 779system.cpu0.itb.fetch_misses 29261 # ITB misses 780system.cpu0.itb.fetch_acv 629 # ITB acv 781system.cpu0.itb.fetch_accesses 1341979 # ITB accesses 782system.cpu0.itb.read_hits 0 # DTB read hits 783system.cpu0.itb.read_misses 0 # DTB read misses 784system.cpu0.itb.read_acv 0 # DTB read access violations 785system.cpu0.itb.read_accesses 0 # DTB read accesses 786system.cpu0.itb.write_hits 0 # DTB write hits 787system.cpu0.itb.write_misses 0 # DTB write misses 788system.cpu0.itb.write_acv 0 # DTB write access violations 789system.cpu0.itb.write_accesses 0 # DTB write accesses 790system.cpu0.itb.data_hits 0 # DTB hits 791system.cpu0.itb.data_misses 0 # DTB misses 792system.cpu0.itb.data_acv 0 # DTB access violations 793system.cpu0.itb.data_accesses 0 # DTB accesses 794system.cpu0.numCycles 99665250 # number of cpu cycles simulated 795system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 796system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 797system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss 798system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed 799system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered 800system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken 801system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked 802system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing 803system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb 804system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 805system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps 806system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions 807system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR 808system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched 809system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed 810system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) 811system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) 812system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) 813system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 814system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) 815system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) 816system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) 817system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) 818system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) 819system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) 820system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) 821system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) 822system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) 823system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 824system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 825system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 826system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) 827system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle 828system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle 829system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle 830system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked 831system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running 832system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking 833system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing 834system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch 835system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction 836system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode 837system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode 838system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing 839system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle 840system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking 841system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst 842system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running 843system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking 844system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename 845system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full 846system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full 847system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full 848system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full 849system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed 850system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made 851system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups 852system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups 853system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed 854system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing 855system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed 856system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed 857system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer 858system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. 859system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. 860system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. 861system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. 862system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) 863system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ 864system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued 865system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued 866system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling 867system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph 868system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed 869system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle 870system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle 871system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle 872system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 873system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle 874system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle 875system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle 876system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle 877system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle 878system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle 879system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle 880system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle 881system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle 882system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 883system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 884system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 885system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle 886system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 887system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available 888system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available 889system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available 890system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available 891system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available 892system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available 893system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available 894system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available 895system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available 896system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available 897system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available 898system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available 899system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available 900system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available 901system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available 902system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available 903system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available 904system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available 905system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available 906system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available 907system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available 908system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available 909system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available 910system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available 911system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available 912system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available 913system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available 914system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available 915system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available 916system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available 917system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available 918system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 919system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 920system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued 921system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued 922system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued 923system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued 924system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued 925system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued 926system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued 927system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued 928system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued 929system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued 930system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued 931system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued 932system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued 933system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued 934system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued 935system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued 936system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued 937system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued 938system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued 939system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued 940system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued 941system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued 942system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued 943system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued 944system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued 945system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued 946system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued 947system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued 948system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued 949system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued 950system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued 951system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued 952system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued 953system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 954system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued 955system.cpu0.iq.rate 0.452554 # Inst issue rate 956system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested 957system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) 958system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads 959system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes 960system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses 961system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads 962system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes 963system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses 964system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses 965system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses 966system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores 967system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 968system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed 969system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed 970system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations 971system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed 972system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 973system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 974system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled 975system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked 976system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 977system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing 978system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking 979system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking 980system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ 981system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch 982system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions 983system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions 984system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions 985system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall 986system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall 987system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations 988system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly 989system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly 990system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute 991system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions 992system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed 993system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute 994system.cpu0.iew.exec_swp 0 # number of swp insts executed 995system.cpu0.iew.exec_nop 2858560 # number of nop insts executed 996system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed 997system.cpu0.iew.exec_branches 7039370 # Number of branches executed 998system.cpu0.iew.exec_stores 5177228 # Number of stores executed 999system.cpu0.iew.exec_rate 0.448278 # Inst execution rate 1000system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit 1001system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back 1002system.cpu0.iew.wb_producers 22691402 # num instructions producing a value 1003system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value 1004system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1005system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle 1006system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back 1007system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1008system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit 1009system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards 1010system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted 1011system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle 1012system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle 1013system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle 1014system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1015system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle 1016system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle 1017system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle 1018system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle 1019system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle 1020system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle 1021system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle 1022system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle 1023system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle 1024system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1025system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1026system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1027system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle 1028system.cpu0.commit.committedInsts 44358216 # Number of instructions committed 1029system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed 1030system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1031system.cpu0.commit.refs 12070511 # Number of memory references committed 1032system.cpu0.commit.loads 7090878 # Number of loads committed 1033system.cpu0.commit.membars 170277 # Number of memory barriers committed 1034system.cpu0.commit.branches 6663650 # Number of branches committed 1035system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. 1036system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. 1037system.cpu0.commit.function_calls 549728 # Number of function calls committed. 1038system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction 1039system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction 1040system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction 1041system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction 1042system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction 1043system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction 1044system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction 1045system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction 1046system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction 1047system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction 1048system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction 1049system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction 1050system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction 1051system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction 1052system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction 1053system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction 1054system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction 1055system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction 1056system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction 1057system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction 1058system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction 1059system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction 1060system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction 1061system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction 1062system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction 1063system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction 1064system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction 1065system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction 1066system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction 1067system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction 1068system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction 1069system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction 1070system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction 1071system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1072system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction 1073system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached 1074system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1075system.cpu0.rob.rob_reads 143064224 # The number of ROB reads 1076system.cpu0.rob.rob_writes 101447849 # The number of ROB writes 1077system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself 1078system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling 1079system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1080system.cpu0.committedInsts 41863465 # Number of Instructions Simulated 1081system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated 1082system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction 1083system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads 1084system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle 1085system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads 1086system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads 1087system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes 1088system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads 1089system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes 1090system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads 1091system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes 1092system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1093system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1094system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1095system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1096system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1097system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1098system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1099system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1100system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1101system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1102system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1103system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1104system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1105system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1106system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1107system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1108system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1109system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1110system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1111system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1112system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1113system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1114system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1115system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1116system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1117system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1118system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1119system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1120system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1121system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1122system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1123system.toL2Bus.throughput 115690704 # Throughput (bytes/s) 1124system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution 1125system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution 1126system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution 1127system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution 1128system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution 1129system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution 1130system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution 1131system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution 1132system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution 1133system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution 1134system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution 1135system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution 1136system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) 1137system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) 1138system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) 1139system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) 1140system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) 1141system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) 1142system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) 1143system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) 1144system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) 1145system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) 1146system.toL2Bus.data_through_bus 215700578 # Total data (bytes) 1147system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) 1148system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) 1149system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1150system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) 1151system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1152system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) 1153system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1154system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) 1155system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1156system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) 1157system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) 1158system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) 1159system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) 1160system.iobus.throughput 1434388 # Throughput (bytes/s) 1161system.iobus.trans_dist::ReadReq 7370 # Transaction distribution 1162system.iobus.trans_dist::ReadResp 7370 # Transaction distribution 1163system.iobus.trans_dist::WriteReq 53903 # Transaction distribution 1164system.iobus.trans_dist::WriteResp 53903 # Transaction distribution 1165system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) 1181system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.data_through_bus 2729818 # Total data (bytes) 1198system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) 1199system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) 1201system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1203system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1205system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1207system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1209system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) 1211system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1213system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1215system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1217system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1219system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1220system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) 1221system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1223system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1224system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) 1225system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1226system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) 1227system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1228system.cpu0.icache.tags.replacements 762211 # number of replacements 1229system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use 1230system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. 1231system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. 1232system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. 1233system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. 1234system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor 1235system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy 1236system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy 1237system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 1238system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 1239system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id 1240system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id 1241system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 1242system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses 1243system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses 1244system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits 1245system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits 1246system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits 1247system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits 1248system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits 1249system.cpu0.icache.overall_hits::total 6309809 # number of overall hits 1250system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses 1251system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses 1252system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses 1253system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses 1254system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses 1255system.cpu0.icache.overall_misses::total 800080 # number of overall misses 1256system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles 1257system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles 1258system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles 1259system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles 1260system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles 1261system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles 1262system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) 1263system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) 1264system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses 1265system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses 1266system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses 1267system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses 1268system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses 1269system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses 1270system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses 1271system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses 1272system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses 1273system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses 1274system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency 1275system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency 1276system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency 1277system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency 1278system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency 1279system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency 1280system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked 1281system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1282system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked 1283system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1284system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked 1285system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1286system.cpu0.icache.fast_writes 0 # number of fast writes performed 1287system.cpu0.icache.cache_copies 0 # number of cache copies performed 1288system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits 1289system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits 1290system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits 1291system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits 1292system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits 1293system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits 1294system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses 1295system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses 1296system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses 1297system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses 1298system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses 1299system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses 1300system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles 1301system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles 1302system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles 1303system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles 1304system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles 1305system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles 1306system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses 1307system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses 1308system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses 1309system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses 1310system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses 1311system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses 1312system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency 1313system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency 1314system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency 1315system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency 1316system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency 1317system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency 1318system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1319system.cpu0.dcache.tags.replacements 1069035 # number of replacements 1320system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use 1321system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. 1322system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. 1323system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. 1324system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. 1325system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor 1326system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy 1327system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy 1328system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1329system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id 1330system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id 1331system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 1332system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1333system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses 1334system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses 1335system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits 1336system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits 1337system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits 1338system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits 1339system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits 1340system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits 1341system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq hits 1342system.cpu0.dcache.StoreCondReq_hits::total 170256 # number of StoreCondReq hits 1343system.cpu0.dcache.demand_hits::cpu0.data 8817417 # number of demand (read+write) hits 1344system.cpu0.dcache.demand_hits::total 8817417 # number of demand (read+write) hits 1345system.cpu0.dcache.overall_hits::cpu0.data 8817417 # number of overall hits 1346system.cpu0.dcache.overall_hits::total 8817417 # number of overall hits 1347system.cpu0.dcache.ReadReq_misses::cpu0.data 1322171 # number of ReadReq misses 1348system.cpu0.dcache.ReadReq_misses::total 1322171 # number of ReadReq misses 1349system.cpu0.dcache.WriteReq_misses::cpu0.data 1644281 # number of WriteReq misses 1350system.cpu0.dcache.WriteReq_misses::total 1644281 # number of WriteReq misses 1351system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16610 # number of LoadLockedReq misses 1352system.cpu0.dcache.LoadLockedReq_misses::total 16610 # number of LoadLockedReq misses 1353system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses 1354system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses 1355system.cpu0.dcache.demand_misses::cpu0.data 2966452 # number of demand (read+write) misses 1356system.cpu0.dcache.demand_misses::total 2966452 # number of demand (read+write) misses 1357system.cpu0.dcache.overall_misses::cpu0.data 2966452 # number of overall misses 1358system.cpu0.dcache.overall_misses::total 2966452 # number of overall misses 1359system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36169344894 # number of ReadReq miss cycles 1360system.cpu0.dcache.ReadReq_miss_latency::total 36169344894 # number of ReadReq miss cycles 1361system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74324803897 # number of WriteReq miss cycles 1362system.cpu0.dcache.WriteReq_miss_latency::total 74324803897 # number of WriteReq miss cycles 1363system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 267182493 # number of LoadLockedReq miss cycles 1364system.cpu0.dcache.LoadLockedReq_miss_latency::total 267182493 # number of LoadLockedReq miss cycles 1365system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles 1366system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles 1367system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles 1368system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles 1369system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles 1370system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles 1371system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) 1372system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) 1373system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) 1374system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) 1375system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) 1376system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) 1377system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) 1378system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) 1379system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses 1380system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses 1381system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses 1382system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses 1383system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses 1384system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq accesses 1385system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342822 # miss rate for WriteReq accesses 1386system.cpu0.dcache.WriteReq_miss_rate::total 0.342822 # miss rate for WriteReq accesses 1387system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101454 # miss rate for LoadLockedReq accesses 1388system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101454 # miss rate for LoadLockedReq accesses 1389system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004479 # miss rate for StoreCondReq accesses 1390system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004479 # miss rate for StoreCondReq accesses 1391system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251738 # miss rate for demand accesses 1392system.cpu0.dcache.demand_miss_rate::total 0.251738 # miss rate for demand accesses 1393system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251738 # miss rate for overall accesses 1394system.cpu0.dcache.overall_miss_rate::total 0.251738 # miss rate for overall accesses 1395system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485 # average ReadReq miss latency 1396system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency 1397system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency 1398system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency 1399system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency 1400system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency 1401system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency 1402system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency 1403system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency 1404system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency 1405system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency 1406system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency 1407system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked 1408system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked 1409system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked 1410system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked 1411system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked 1412system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked 1413system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1414system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1415system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks 1416system.cpu0.dcache.writebacks::total 568073 # number of writebacks 1417system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits 1418system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits 1419system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits 1420system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits 1421system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits 1422system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits 1423system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits 1424system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits 1425system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits 1426system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits 1427system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses 1428system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses 1429system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses 1430system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses 1431system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses 1432system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses 1433system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses 1434system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses 1435system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses 1436system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses 1437system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses 1438system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses 1439system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles 1440system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles 1441system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles 1442system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles 1443system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles 1444system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles 1445system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles 1446system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles 1447system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles 1448system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles 1449system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles 1450system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles 1451system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles 1452system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles 1453system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles 1454system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles 1455system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles 1456system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles 1457system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses 1458system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses 1459system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses 1460system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses 1461system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses 1462system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses 1463system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses 1464system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses 1465system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses 1466system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses 1467system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses 1468system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses 1469system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency 1470system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency 1471system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency 1472system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency 1473system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency 1474system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency 1475system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency 1476system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency 1477system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency 1478system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency 1479system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency 1480system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency 1481system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1482system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1483system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1484system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1485system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1486system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1487system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1488system.cpu1.branchPred.lookups 5770916 # Number of BP lookups 1489system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted 1490system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect 1491system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups 1492system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits 1493system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1494system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage 1495system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. 1496system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. 1497system.cpu1.dtb.fetch_hits 0 # ITB hits 1498system.cpu1.dtb.fetch_misses 0 # ITB misses 1499system.cpu1.dtb.fetch_acv 0 # ITB acv 1500system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1501system.cpu1.dtb.read_hits 3015540 # DTB read hits 1502system.cpu1.dtb.read_misses 12269 # DTB read misses 1503system.cpu1.dtb.read_acv 5 # DTB read access violations 1504system.cpu1.dtb.read_accesses 293761 # DTB read accesses 1505system.cpu1.dtb.write_hits 1836726 # DTB write hits 1506system.cpu1.dtb.write_misses 2353 # DTB write misses 1507system.cpu1.dtb.write_acv 39 # DTB write access violations 1508system.cpu1.dtb.write_accesses 109652 # DTB write accesses 1509system.cpu1.dtb.data_hits 4852266 # DTB hits 1510system.cpu1.dtb.data_misses 14622 # DTB misses 1511system.cpu1.dtb.data_acv 44 # DTB access violations 1512system.cpu1.dtb.data_accesses 403413 # DTB accesses 1513system.cpu1.itb.fetch_hits 632341 # ITB hits 1514system.cpu1.itb.fetch_misses 5352 # ITB misses 1515system.cpu1.itb.fetch_acv 51 # ITB acv 1516system.cpu1.itb.fetch_accesses 637693 # ITB accesses 1517system.cpu1.itb.read_hits 0 # DTB read hits 1518system.cpu1.itb.read_misses 0 # DTB read misses 1519system.cpu1.itb.read_acv 0 # DTB read access violations 1520system.cpu1.itb.read_accesses 0 # DTB read accesses 1521system.cpu1.itb.write_hits 0 # DTB write hits 1522system.cpu1.itb.write_misses 0 # DTB write misses 1523system.cpu1.itb.write_acv 0 # DTB write access violations 1524system.cpu1.itb.write_accesses 0 # DTB write accesses 1525system.cpu1.itb.data_hits 0 # DTB hits 1526system.cpu1.itb.data_misses 0 # DTB misses 1527system.cpu1.itb.data_acv 0 # DTB access violations 1528system.cpu1.itb.data_accesses 0 # DTB accesses 1529system.cpu1.numCycles 26335588 # number of cpu cycles simulated 1530system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1531system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1532system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss 1533system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed 1534system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered 1535system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken 1536system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked 1537system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing 1538system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb 1539system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1540system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps 1541system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions 1542system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR 1543system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched 1544system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed 1545system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) 1546system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) 1547system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) 1548system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1549system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) 1550system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) 1551system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) 1552system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) 1553system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) 1554system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) 1555system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) 1556system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) 1557system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) 1558system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1559system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1560system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1561system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) 1562system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle 1563system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle 1564system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle 1565system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked 1566system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running 1567system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking 1568system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing 1569system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch 1570system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction 1571system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode 1572system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode 1573system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing 1574system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle 1575system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking 1576system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst 1577system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running 1578system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking 1579system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename 1580system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full 1581system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full 1582system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full 1583system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full 1584system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed 1585system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made 1586system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups 1587system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups 1588system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed 1589system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing 1590system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed 1591system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed 1592system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer 1593system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. 1594system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. 1595system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. 1596system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. 1597system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) 1598system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ 1599system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued 1600system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued 1601system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling 1602system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph 1603system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed 1604system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle 1605system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle 1606system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle 1607system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1608system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle 1609system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle 1610system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle 1611system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle 1612system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle 1613system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle 1614system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle 1615system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle 1616system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle 1617system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1618system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1619system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1620system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle 1621system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1622system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available 1623system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available 1624system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available 1625system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available 1626system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available 1627system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available 1628system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available 1629system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available 1630system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available 1631system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available 1632system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available 1633system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available 1634system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available 1635system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available 1636system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available 1637system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available 1638system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available 1639system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available 1640system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available 1641system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available 1642system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available 1643system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available 1644system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available 1645system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available 1646system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available 1647system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available 1648system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available 1649system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available 1650system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available 1651system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available 1652system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available 1653system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1654system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1655system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued 1656system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued 1657system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued 1658system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued 1659system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued 1660system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 1661system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 1662system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 1663system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued 1664system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued 1665system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued 1666system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued 1667system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued 1668system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued 1669system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued 1670system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued 1671system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued 1672system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued 1673system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued 1674system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued 1675system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued 1676system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued 1677system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued 1678system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued 1679system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued 1680system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued 1681system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued 1682system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued 1683system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued 1684system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued 1685system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued 1686system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued 1687system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued 1688system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1689system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued 1690system.cpu1.iq.rate 0.598374 # Inst issue rate 1691system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested 1692system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) 1693system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads 1694system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes 1695system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses 1696system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads 1697system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes 1698system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses 1699system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses 1700system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses 1701system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores 1702system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1703system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed 1704system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed 1705system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations 1706system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed 1707system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1708system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1709system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled 1710system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked 1711system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1712system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing 1713system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking 1714system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking 1715system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ 1716system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch 1717system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions 1718system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions 1719system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions 1720system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall 1721system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall 1722system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations 1723system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly 1724system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly 1725system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute 1726system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions 1727system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed 1728system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute 1729system.cpu1.iew.exec_swp 0 # number of swp insts executed 1730system.cpu1.iew.exec_nop 1012523 # number of nop insts executed 1731system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed 1732system.cpu1.iew.exec_branches 2446532 # Number of branches executed 1733system.cpu1.iew.exec_stores 1845237 # Number of stores executed 1734system.cpu1.iew.exec_rate 0.590834 # Inst execution rate 1735system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit 1736system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back 1737system.cpu1.iew.wb_producers 7566791 # num instructions producing a value 1738system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value 1739system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1740system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle 1741system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back 1742system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1743system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit 1744system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards 1745system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted 1746system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle 1747system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle 1748system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle 1749system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1750system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle 1751system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle 1752system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle 1753system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle 1754system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle 1755system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle 1756system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle 1757system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle 1758system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle 1759system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1760system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1761system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1762system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle 1763system.cpu1.commit.committedInsts 15127070 # Number of instructions committed 1764system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed 1765system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1766system.cpu1.commit.refs 4418203 # Number of memory references committed 1767system.cpu1.commit.loads 2674883 # Number of loads committed 1768system.cpu1.commit.membars 66521 # Number of memory barriers committed 1769system.cpu1.commit.branches 2263870 # Number of branches committed 1770system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. 1771system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. 1772system.cpu1.commit.function_calls 240978 # Number of function calls committed. 1773system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction 1774system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction 1775system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction 1776system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction 1777system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction 1778system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction 1779system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction 1780system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction 1781system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction 1782system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction 1783system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction 1784system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction 1785system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction 1786system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction 1787system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction 1788system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction 1789system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction 1790system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction 1791system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction 1792system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction 1793system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction 1794system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction 1795system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction 1796system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction 1797system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction 1798system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction 1799system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction 1800system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction 1801system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction 1802system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction 1803system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction 1804system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction 1805system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction 1806system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1807system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction 1808system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached 1809system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1810system.cpu1.rob.rob_reads 41251186 # The number of ROB reads 1811system.cpu1.rob.rob_writes 36287802 # The number of ROB writes 1812system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself 1813system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling 1814system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1815system.cpu1.committedInsts 14284756 # Number of Instructions Simulated 1816system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated 1817system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction 1818system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads 1819system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle 1820system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads 1821system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads 1822system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes 1823system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads 1824system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes 1825system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads 1826system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes 1827system.cpu1.icache.tags.replacements 353746 # number of replacements 1828system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use 1829system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. 1830system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. 1831system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. 1832system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. 1833system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor 1834system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy 1835system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy 1836system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1837system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 1839system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1840system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses 1841system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses 1842system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits 1843system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits 1844system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits 1845system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits 1846system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits 1847system.cpu1.icache.overall_hits::total 2153244 # number of overall hits 1848system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses 1849system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses 1850system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses 1851system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses 1852system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses 1853system.cpu1.icache.overall_misses::total 368891 # number of overall misses 1854system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles 1855system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles 1856system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles 1857system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles 1858system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles 1859system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles 1860system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) 1861system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) 1862system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses 1863system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses 1864system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses 1865system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses 1866system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses 1867system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # miss rate for ReadReq accesses 1868system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146261 # miss rate for demand accesses 1869system.cpu1.icache.demand_miss_rate::total 0.146261 # miss rate for demand accesses 1870system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146261 # miss rate for overall accesses 1871system.cpu1.icache.overall_miss_rate::total 0.146261 # miss rate for overall accesses 1872system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044 # average ReadReq miss latency 1873system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044 # average ReadReq miss latency 1874system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency 1875system.cpu1.icache.demand_avg_miss_latency::total 13928.049044 # average overall miss latency 1876system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency 1877system.cpu1.icache.overall_avg_miss_latency::total 13928.049044 # average overall miss latency 1878system.cpu1.icache.blocked_cycles::no_mshrs 1327 # number of cycles access was blocked 1879system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1882system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1884system.cpu1.icache.fast_writes 0 # number of fast writes performed 1885system.cpu1.icache.cache_copies 0 # number of cache copies performed 1886system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14566 # number of ReadReq MSHR hits 1887system.cpu1.icache.ReadReq_mshr_hits::total 14566 # number of ReadReq MSHR hits 1888system.cpu1.icache.demand_mshr_hits::cpu1.inst 14566 # number of demand (read+write) MSHR hits 1889system.cpu1.icache.demand_mshr_hits::total 14566 # number of demand (read+write) MSHR hits 1890system.cpu1.icache.overall_mshr_hits::cpu1.inst 14566 # number of overall MSHR hits 1891system.cpu1.icache.overall_mshr_hits::total 14566 # number of overall MSHR hits 1892system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 354325 # number of ReadReq MSHR misses 1893system.cpu1.icache.ReadReq_mshr_misses::total 354325 # number of ReadReq MSHR misses 1894system.cpu1.icache.demand_mshr_misses::cpu1.inst 354325 # number of demand (read+write) MSHR misses 1895system.cpu1.icache.demand_mshr_misses::total 354325 # number of demand (read+write) MSHR misses 1896system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses 1897system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses 1898system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles 1899system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles 1900system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles 1901system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles 1902system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles 1903system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles 1904system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses 1905system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses 1906system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses 1907system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses 1908system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses 1909system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses 1910system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency 1911system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency 1912system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency 1913system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency 1914system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency 1915system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency 1916system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1917system.cpu1.dcache.tags.replacements 360788 # number of replacements 1918system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use 1919system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks. 1920system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks. 1921system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks. 1922system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit. 1923system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor 1924system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968918 # Average percentage of cache occupancy 1925system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy 1926system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id 1927system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id 1928system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id 1929system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses 1930system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses 1931system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits 1932system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits 1933system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits 1934system.cpu1.dcache.WriteReq_hits::total 1307515 # number of WriteReq hits 1935system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45364 # number of LoadLockedReq hits 1936system.cpu1.dcache.LoadLockedReq_hits::total 45364 # number of LoadLockedReq hits 1937system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48883 # number of StoreCondReq hits 1938system.cpu1.dcache.StoreCondReq_hits::total 48883 # number of StoreCondReq hits 1939system.cpu1.dcache.demand_hits::cpu1.data 3528381 # number of demand (read+write) hits 1940system.cpu1.dcache.demand_hits::total 3528381 # number of demand (read+write) hits 1941system.cpu1.dcache.overall_hits::cpu1.data 3528381 # number of overall hits 1942system.cpu1.dcache.overall_hits::total 3528381 # number of overall hits 1943system.cpu1.dcache.ReadReq_misses::cpu1.data 524895 # number of ReadReq misses 1944system.cpu1.dcache.ReadReq_misses::total 524895 # number of ReadReq misses 1945system.cpu1.dcache.WriteReq_misses::cpu1.data 378889 # number of WriteReq misses 1946system.cpu1.dcache.WriteReq_misses::total 378889 # number of WriteReq misses 1947system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8897 # number of LoadLockedReq misses 1948system.cpu1.dcache.LoadLockedReq_misses::total 8897 # number of LoadLockedReq misses 1949system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses 1950system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses 1951system.cpu1.dcache.demand_misses::cpu1.data 903784 # number of demand (read+write) misses 1952system.cpu1.dcache.demand_misses::total 903784 # number of demand (read+write) misses 1953system.cpu1.dcache.overall_misses::cpu1.data 903784 # number of overall misses 1954system.cpu1.dcache.overall_misses::total 903784 # number of overall misses 1955system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8191623763 # number of ReadReq miss cycles 1956system.cpu1.dcache.ReadReq_miss_latency::total 8191623763 # number of ReadReq miss cycles 1957system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 14087810149 # number of WriteReq miss cycles 1958system.cpu1.dcache.WriteReq_miss_latency::total 14087810149 # number of WriteReq miss cycles 1959system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 135761491 # number of LoadLockedReq miss cycles 1960system.cpu1.dcache.LoadLockedReq_miss_latency::total 135761491 # number of LoadLockedReq miss cycles 1961system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5726098 # number of StoreCondReq miss cycles 1962system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles 1963system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles 1964system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles 1965system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles 1966system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles 1967system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) 1968system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) 1969system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) 1970system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) 1971system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) 1972system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) 1973system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) 1974system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) 1975system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses 1976system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses 1977system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # number of overall (read+write) accesses 1978system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses 1979system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.191166 # miss rate for ReadReq accesses 1980system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses 1981system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224673 # miss rate for WriteReq accesses 1982system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses 1983system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.163967 # miss rate for LoadLockedReq accesses 1984system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses 1985system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses 1986system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses 1987system.cpu1.dcache.demand_miss_rate::cpu1.data 0.203915 # miss rate for demand accesses 1988system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses 1989system.cpu1.dcache.overall_miss_rate::cpu1.data 0.203915 # miss rate for overall accesses 1990system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses 1991system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency 1992system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency 1993system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency 1994system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency 1995system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency 1996system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency 1997system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency 1998system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency 1999system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency 2000system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency 2001system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency 2002system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency 2003system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked 2004system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked 2005system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked 2006system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked 2007system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked 2008system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked 2009system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2010system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2011system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks 2012system.cpu1.dcache.writebacks::total 273838 # number of writebacks 2013system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits 2014system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits 2015system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits 2016system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits 2017system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits 2018system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits 2019system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits 2020system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits 2021system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits 2022system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits 2023system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses 2024system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses 2025system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses 2026system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses 2027system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses 2028system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses 2029system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses 2030system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses 2031system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses 2032system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses 2033system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses 2034system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses 2035system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles 2036system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles 2037system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles 2038system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles 2039system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles 2040system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles 2041system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles 2042system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles 2043system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles 2044system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles 2045system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles 2046system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles 2047system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles 2048system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles 2049system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles 2050system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles 2051system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles 2052system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles 2053system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses 2054system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses 2055system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses 2056system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses 2057system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses 2058system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses 2059system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses 2060system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses 2061system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses 2062system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses 2063system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses 2064system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses 2065system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency 2066system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency 2067system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency 2068system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency 2069system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency 2070system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency 2071system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency 2072system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency 2073system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency 2074system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency 2075system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency 2076system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency 2077system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2078system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2079system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2080system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2081system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2082system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2083system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2084system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2085system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed 2086system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed 2087system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl 2088system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl 2089system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl 2090system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl 2091system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl 2092system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl 2093system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl 2094system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 2095system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl 2096system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl 2097system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl 2098system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl 2099system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl 2100system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl 2101system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl 2102system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl 2103system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl 2104system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl 2105system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl 2106system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2107system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2108system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2109system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl 2110system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl 2111system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed 2112system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed 2113system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed 2114system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed 2115system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed 2116system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed 2117system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed 2118system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed 2119system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed 2120system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed 2121system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed 2122system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed 2123system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed 2124system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed 2125system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed 2126system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed 2127system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed 2128system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed 2129system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed 2130system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed 2131system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed 2132system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed 2133system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed 2134system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed 2135system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed 2136system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed 2137system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed 2138system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed 2139system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed 2140system.cpu0.kern.syscall::total 225 # number of syscalls executed 2141system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2142system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed 2143system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 2144system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 2145system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed 2146system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed 2147system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed 2148system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed 2149system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed 2150system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed 2151system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed 2152system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed 2153system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed 2154system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed 2155system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed 2156system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed 2157system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed 2158system.cpu0.kern.callpal::total 146768 # number of callpals executed 2159system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches 2160system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches 2161system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2162system.cpu0.kern.mode_good::kernel 1341 2163system.cpu0.kern.mode_good::user 1342 2164system.cpu0.kern.mode_good::idle 0 2165system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches 2166system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2167system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2168system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches 2169system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode 2170system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode 2171system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2172system.cpu0.kern.swap_context 2906 # number of times the context was actually changed 2173system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2174system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed 2175system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed 2176system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl 2177system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl 2178system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl 2179system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl 2180system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl 2181system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl 2182system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl 2183system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl 2184system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl 2185system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl 2186system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl 2187system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl 2188system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl 2189system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl 2190system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl 2191system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl 2192system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2193system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2194system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl 2195system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl 2196system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed 2197system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed 2198system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed 2199system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed 2200system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed 2201system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed 2202system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed 2203system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed 2204system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed 2205system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed 2206system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed 2207system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed 2208system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed 2209system.cpu1.kern.syscall::total 101 # number of syscalls executed 2210system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2211system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed 2212system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 2213system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 2214system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed 2215system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed 2216system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed 2217system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed 2218system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed 2219system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed 2220system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed 2221system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed 2222system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed 2223system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed 2224system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 2225system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2226system.cpu1.kern.callpal::total 69486 # number of callpals executed 2227system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches 2228system.cpu1.kern.mode_switch::user 395 # number of protection mode switches 2229system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches 2230system.cpu1.kern.mode_good::kernel 462 2231system.cpu1.kern.mode_good::user 395 2232system.cpu1.kern.mode_good::idle 67 2233system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches 2234system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2235system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches 2236system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches 2237system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode 2238system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode 2239system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode 2240system.cpu1.kern.swap_context 1335 # number of times the context was actually changed 2241 2242---------- End Simulation Statistics ---------- 2243