stats.txt revision 10242:cb4e86c17767
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.906207 # Number of seconds simulated 4sim_ticks 1906207240000 # Number of ticks simulated 5final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 147655 # Simulator instruction rate (inst/s) 8host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5021061637 # Simulator tick rate (ticks/s) 10host_mem_usage 308576 # Number of bytes of host memory used 11host_seconds 379.64 # Real time elapsed on the host 12sim_insts 56056069 # Number of instructions simulated 13sim_ops 56056069 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory 21system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory 29system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 451755 # Number of read requests accepted 54system.physmem.writeReqs 122625 # Number of write requests accepted 55system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 28097 # Per bank write bursts 66system.physmem.perBankRdBursts::1 28602 # Per bank write bursts 67system.physmem.perBankRdBursts::2 29043 # Per bank write bursts 68system.physmem.perBankRdBursts::3 27571 # Per bank write bursts 69system.physmem.perBankRdBursts::4 27384 # Per bank write bursts 70system.physmem.perBankRdBursts::5 27564 # Per bank write bursts 71system.physmem.perBankRdBursts::6 27744 # Per bank write bursts 72system.physmem.perBankRdBursts::7 27694 # Per bank write bursts 73system.physmem.perBankRdBursts::8 27865 # Per bank write bursts 74system.physmem.perBankRdBursts::9 28720 # Per bank write bursts 75system.physmem.perBankRdBursts::10 28531 # Per bank write bursts 76system.physmem.perBankRdBursts::11 28618 # Per bank write bursts 77system.physmem.perBankRdBursts::12 28938 # Per bank write bursts 78system.physmem.perBankRdBursts::13 28977 # Per bank write bursts 79system.physmem.perBankRdBursts::14 28277 # Per bank write bursts 80system.physmem.perBankRdBursts::15 28002 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7839 # Per bank write bursts 82system.physmem.perBankWrBursts::1 8045 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8418 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7040 # Per bank write bursts 85system.physmem.perBankWrBursts::4 6886 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7040 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7326 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7097 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7158 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7908 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7739 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7821 # Per bank write bursts 93system.physmem.perBankWrBursts::12 8331 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8401 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7959 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7587 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 99system.physmem.totGap 1906202745000 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 451755 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 122625 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads 275system.physmem.totQLat 9007685000 # Total ticks spent queuing 276system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM 277system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers 278system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst 279system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 280system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst 281system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s 282system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s 283system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s 284system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s 285system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 286system.physmem.busUtil 0.15 # Data bus utilization in percentage 287system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 288system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 289system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing 290system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing 291system.physmem.readRowHits 408104 # Number of row buffer hits during reads 292system.physmem.writeRowHits 99226 # Number of row buffer hits during writes 293system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads 294system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes 295system.physmem.avgGap 3318713.65 # Average gap between requests 296system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined 297system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states 298system.physmem.memoryStateTime::REF 63652420000 # Time in different power states 299system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states 301system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 302system.membus.throughput 19340215 # Throughput (bytes/s) 303system.membus.trans_dist::ReadReq 296416 # Transaction distribution 304system.membus.trans_dist::ReadResp 296338 # Transaction distribution 305system.membus.trans_dist::WriteReq 12317 # Transaction distribution 306system.membus.trans_dist::WriteResp 12317 # Transaction distribution 307system.membus.trans_dist::Writeback 122625 # Transaction distribution 308system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 309system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution 310system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution 311system.membus.trans_dist::ReadExReq 163308 # Transaction distribution 312system.membus.trans_dist::ReadExResp 163210 # Transaction distribution 313system.membus.trans_dist::BadAddressError 78 # Transaction distribution 314system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) 320system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) 326system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) 327system.membus.data_through_bus 36828250 # Total data (bytes) 328system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) 329system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) 330system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 331system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) 332system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 333system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) 334system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 335system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) 336system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 337system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) 338system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 339system.cpu_clk_domain.clock 500 # Clock period in ticks 340system.l2c.tags.replacements 344852 # number of replacements 341system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use 342system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks. 343system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks. 344system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks. 345system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit. 346system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor 347system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor 348system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor 349system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor 350system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor 351system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy 352system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy 353system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy 354system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy 355system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy 356system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy 357system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id 358system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id 359system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id 360system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id 361system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id 362system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id 363system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id 364system.l2c.tags.tag_accesses 27313168 # Number of tag accesses 365system.l2c.tags.data_accesses 27313168 # Number of data accesses 366system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits 367system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits 368system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits 369system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits 370system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits 371system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits 372system.l2c.Writeback_hits::total 833565 # number of Writeback hits 373system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits 374system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits 375system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits 376system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits 377system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits 378system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits 379system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits 380system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits 381system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits 382system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits 383system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits 384system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits 385system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits 386system.l2c.demand_hits::total 2076901 # number of demand (read+write) hits 387system.l2c.overall_hits::cpu0.inst 979450 # number of overall hits 388system.l2c.overall_hits::cpu0.data 964220 # number of overall hits 389system.l2c.overall_hits::cpu1.inst 94097 # number of overall hits 390system.l2c.overall_hits::cpu1.data 39134 # number of overall hits 391system.l2c.overall_hits::total 2076901 # number of overall hits 392system.l2c.ReadReq_misses::cpu0.inst 14127 # number of ReadReq misses 393system.l2c.ReadReq_misses::cpu0.data 273418 # number of ReadReq misses 394system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses 395system.l2c.ReadReq_misses::cpu1.data 340 # number of ReadReq misses 396system.l2c.ReadReq_misses::total 289058 # number of ReadReq misses 397system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 398system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses 399system.l2c.UpgradeReq_misses::total 2953 # number of UpgradeReq misses 400system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses 401system.l2c.SCUpgradeReq_misses::cpu1.data 76 # number of SCUpgradeReq misses 402system.l2c.SCUpgradeReq_misses::total 110 # number of SCUpgradeReq misses 403system.l2c.ReadExReq_misses::cpu0.data 116199 # number of ReadExReq misses 404system.l2c.ReadExReq_misses::cpu1.data 5616 # number of ReadExReq misses 405system.l2c.ReadExReq_misses::total 121815 # number of ReadExReq misses 406system.l2c.demand_misses::cpu0.inst 14127 # number of demand (read+write) misses 407system.l2c.demand_misses::cpu0.data 389617 # number of demand (read+write) misses 408system.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses 409system.l2c.demand_misses::cpu1.data 5956 # number of demand (read+write) misses 410system.l2c.demand_misses::total 410873 # number of demand (read+write) misses 411system.l2c.overall_misses::cpu0.inst 14127 # number of overall misses 412system.l2c.overall_misses::cpu0.data 389617 # number of overall misses 413system.l2c.overall_misses::cpu1.inst 1173 # number of overall misses 414system.l2c.overall_misses::cpu1.data 5956 # number of overall misses 415system.l2c.overall_misses::total 410873 # number of overall misses 416system.l2c.ReadReq_miss_latency::cpu0.inst 1071252992 # number of ReadReq miss cycles 417system.l2c.ReadReq_miss_latency::cpu0.data 17895085485 # number of ReadReq miss cycles 418system.l2c.ReadReq_miss_latency::cpu1.inst 90289500 # number of ReadReq miss cycles 419system.l2c.ReadReq_miss_latency::cpu1.data 26594999 # number of ReadReq miss cycles 420system.l2c.ReadReq_miss_latency::total 19083222976 # number of ReadReq miss cycles 421system.l2c.UpgradeReq_miss_latency::cpu0.data 1079964 # number of UpgradeReq miss cycles 422system.l2c.UpgradeReq_miss_latency::cpu1.data 402483 # number of UpgradeReq miss cycles 423system.l2c.UpgradeReq_miss_latency::total 1482447 # number of UpgradeReq miss cycles 424system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116495 # number of SCUpgradeReq miss cycles 425system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68997 # number of SCUpgradeReq miss cycles 426system.l2c.SCUpgradeReq_miss_latency::total 185492 # number of SCUpgradeReq miss cycles 427system.l2c.ReadExReq_miss_latency::cpu0.data 9654052371 # number of ReadExReq miss cycles 428system.l2c.ReadExReq_miss_latency::cpu1.data 606648221 # number of ReadExReq miss cycles 429system.l2c.ReadExReq_miss_latency::total 10260700592 # number of ReadExReq miss cycles 430system.l2c.demand_miss_latency::cpu0.inst 1071252992 # number of demand (read+write) miss cycles 431system.l2c.demand_miss_latency::cpu0.data 27549137856 # number of demand (read+write) miss cycles 432system.l2c.demand_miss_latency::cpu1.inst 90289500 # number of demand (read+write) miss cycles 433system.l2c.demand_miss_latency::cpu1.data 633243220 # number of demand (read+write) miss cycles 434system.l2c.demand_miss_latency::total 29343923568 # number of demand (read+write) miss cycles 435system.l2c.overall_miss_latency::cpu0.inst 1071252992 # number of overall miss cycles 436system.l2c.overall_miss_latency::cpu0.data 27549137856 # number of overall miss cycles 437system.l2c.overall_miss_latency::cpu1.inst 90289500 # number of overall miss cycles 438system.l2c.overall_miss_latency::cpu1.data 633243220 # number of overall miss cycles 439system.l2c.overall_miss_latency::total 29343923568 # number of overall miss cycles 440system.l2c.ReadReq_accesses::cpu0.inst 993577 # number of ReadReq accesses(hits+misses) 441system.l2c.ReadReq_accesses::cpu0.data 1061945 # number of ReadReq accesses(hits+misses) 442system.l2c.ReadReq_accesses::cpu1.inst 95270 # number of ReadReq accesses(hits+misses) 443system.l2c.ReadReq_accesses::cpu1.data 31753 # number of ReadReq accesses(hits+misses) 444system.l2c.ReadReq_accesses::total 2182545 # number of ReadReq accesses(hits+misses) 445system.l2c.Writeback_accesses::writebacks 833565 # number of Writeback accesses(hits+misses) 446system.l2c.Writeback_accesses::total 833565 # number of Writeback accesses(hits+misses) 447system.l2c.UpgradeReq_accesses::cpu0.data 2617 # number of UpgradeReq accesses(hits+misses) 448system.l2c.UpgradeReq_accesses::cpu1.data 557 # number of UpgradeReq accesses(hits+misses) 449system.l2c.UpgradeReq_accesses::total 3174 # number of UpgradeReq accesses(hits+misses) 450system.l2c.SCUpgradeReq_accesses::cpu0.data 61 # number of SCUpgradeReq accesses(hits+misses) 451system.l2c.SCUpgradeReq_accesses::cpu1.data 96 # number of SCUpgradeReq accesses(hits+misses) 452system.l2c.SCUpgradeReq_accesses::total 157 # number of SCUpgradeReq accesses(hits+misses) 453system.l2c.ReadExReq_accesses::cpu0.data 291892 # number of ReadExReq accesses(hits+misses) 454system.l2c.ReadExReq_accesses::cpu1.data 13337 # number of ReadExReq accesses(hits+misses) 455system.l2c.ReadExReq_accesses::total 305229 # number of ReadExReq accesses(hits+misses) 456system.l2c.demand_accesses::cpu0.inst 993577 # number of demand (read+write) accesses 457system.l2c.demand_accesses::cpu0.data 1353837 # number of demand (read+write) accesses 458system.l2c.demand_accesses::cpu1.inst 95270 # number of demand (read+write) accesses 459system.l2c.demand_accesses::cpu1.data 45090 # number of demand (read+write) accesses 460system.l2c.demand_accesses::total 2487774 # number of demand (read+write) accesses 461system.l2c.overall_accesses::cpu0.inst 993577 # number of overall (read+write) accesses 462system.l2c.overall_accesses::cpu0.data 1353837 # number of overall (read+write) accesses 463system.l2c.overall_accesses::cpu1.inst 95270 # number of overall (read+write) accesses 464system.l2c.overall_accesses::cpu1.data 45090 # number of overall (read+write) accesses 465system.l2c.overall_accesses::total 2487774 # number of overall (read+write) accesses 466system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses 467system.l2c.ReadReq_miss_rate::cpu0.data 0.257469 # miss rate for ReadReq accesses 468system.l2c.ReadReq_miss_rate::cpu1.inst 0.012312 # miss rate for ReadReq accesses 469system.l2c.ReadReq_miss_rate::cpu1.data 0.010708 # miss rate for ReadReq accesses 470system.l2c.ReadReq_miss_rate::total 0.132441 # miss rate for ReadReq accesses 471system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933130 # miss rate for UpgradeReq accesses 472system.l2c.UpgradeReq_miss_rate::cpu1.data 0.917415 # miss rate for UpgradeReq accesses 473system.l2c.UpgradeReq_miss_rate::total 0.930372 # miss rate for UpgradeReq accesses 474system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.557377 # miss rate for SCUpgradeReq accesses 475system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.791667 # miss rate for SCUpgradeReq accesses 476system.l2c.SCUpgradeReq_miss_rate::total 0.700637 # miss rate for SCUpgradeReq accesses 477system.l2c.ReadExReq_miss_rate::cpu0.data 0.398089 # miss rate for ReadExReq accesses 478system.l2c.ReadExReq_miss_rate::cpu1.data 0.421084 # miss rate for ReadExReq accesses 479system.l2c.ReadExReq_miss_rate::total 0.399094 # miss rate for ReadExReq accesses 480system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses 481system.l2c.demand_miss_rate::cpu0.data 0.287787 # miss rate for demand accesses 482system.l2c.demand_miss_rate::cpu1.inst 0.012312 # miss rate for demand accesses 483system.l2c.demand_miss_rate::cpu1.data 0.132091 # miss rate for demand accesses 484system.l2c.demand_miss_rate::total 0.165157 # miss rate for demand accesses 485system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses 486system.l2c.overall_miss_rate::cpu0.data 0.287787 # miss rate for overall accesses 487system.l2c.overall_miss_rate::cpu1.inst 0.012312 # miss rate for overall accesses 488system.l2c.overall_miss_rate::cpu1.data 0.132091 # miss rate for overall accesses 489system.l2c.overall_miss_rate::total 0.165157 # miss rate for overall accesses 490system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75830.182771 # average ReadReq miss latency 491system.l2c.ReadReq_avg_miss_latency::cpu0.data 65449.551547 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76973.145780 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::cpu1.data 78220.585294 # average ReadReq miss latency 494system.l2c.ReadReq_avg_miss_latency::total 66018.663991 # average ReadReq miss latency 495system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.245700 # average UpgradeReq miss latency 496system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 787.637965 # average UpgradeReq miss latency 497system.l2c.UpgradeReq_avg_miss_latency::total 502.013884 # average UpgradeReq miss latency 498system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3426.323529 # average SCUpgradeReq miss latency 499system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 907.855263 # average SCUpgradeReq miss latency 500system.l2c.SCUpgradeReq_avg_miss_latency::total 1686.290909 # average SCUpgradeReq miss latency 501system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83082.060698 # average ReadExReq miss latency 502system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108021.406873 # average ReadExReq miss latency 503system.l2c.ReadExReq_avg_miss_latency::total 84231.831811 # average ReadExReq miss latency 504system.l2c.demand_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency 505system.l2c.demand_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency 506system.l2c.demand_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency 507system.l2c.demand_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency 508system.l2c.demand_avg_miss_latency::total 71418.476191 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency 512system.l2c.overall_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency 513system.l2c.overall_avg_miss_latency::total 71418.476191 # average overall miss latency 514system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 517system.l2c.blocked::no_targets 0 # number of cycles access was blocked 518system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 519system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 520system.l2c.fast_writes 0 # number of fast writes performed 521system.l2c.cache_copies 0 # number of cache copies performed 522system.l2c.writebacks::writebacks 81105 # number of writebacks 523system.l2c.writebacks::total 81105 # number of writebacks 524system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits 525system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits 526system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 527system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 528system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 529system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 530system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 531system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 532system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 533system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 534system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 535system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 536system.l2c.ReadReq_mshr_misses::cpu0.inst 14118 # number of ReadReq MSHR misses 537system.l2c.ReadReq_mshr_misses::cpu0.data 273418 # number of ReadReq MSHR misses 538system.l2c.ReadReq_mshr_misses::cpu1.inst 1165 # number of ReadReq MSHR misses 539system.l2c.ReadReq_mshr_misses::cpu1.data 339 # number of ReadReq MSHR misses 540system.l2c.ReadReq_mshr_misses::total 289040 # number of ReadReq MSHR misses 541system.l2c.UpgradeReq_mshr_misses::cpu0.data 2442 # number of UpgradeReq MSHR misses 542system.l2c.UpgradeReq_mshr_misses::cpu1.data 511 # number of UpgradeReq MSHR misses 543system.l2c.UpgradeReq_mshr_misses::total 2953 # number of UpgradeReq MSHR misses 544system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 34 # number of SCUpgradeReq MSHR misses 545system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 76 # number of SCUpgradeReq MSHR misses 546system.l2c.SCUpgradeReq_mshr_misses::total 110 # number of SCUpgradeReq MSHR misses 547system.l2c.ReadExReq_mshr_misses::cpu0.data 116199 # number of ReadExReq MSHR misses 548system.l2c.ReadExReq_mshr_misses::cpu1.data 5616 # number of ReadExReq MSHR misses 549system.l2c.ReadExReq_mshr_misses::total 121815 # number of ReadExReq MSHR misses 550system.l2c.demand_mshr_misses::cpu0.inst 14118 # number of demand (read+write) MSHR misses 551system.l2c.demand_mshr_misses::cpu0.data 389617 # number of demand (read+write) MSHR misses 552system.l2c.demand_mshr_misses::cpu1.inst 1165 # number of demand (read+write) MSHR misses 553system.l2c.demand_mshr_misses::cpu1.data 5955 # number of demand (read+write) MSHR misses 554system.l2c.demand_mshr_misses::total 410855 # number of demand (read+write) MSHR misses 555system.l2c.overall_mshr_misses::cpu0.inst 14118 # number of overall MSHR misses 556system.l2c.overall_mshr_misses::cpu0.data 389617 # number of overall MSHR misses 557system.l2c.overall_mshr_misses::cpu1.inst 1165 # number of overall MSHR misses 558system.l2c.overall_mshr_misses::cpu1.data 5955 # number of overall MSHR misses 559system.l2c.overall_mshr_misses::total 410855 # number of overall MSHR misses 560system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 892690758 # number of ReadReq MSHR miss cycles 561system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14487194015 # number of ReadReq MSHR miss cycles 562system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 75058500 # number of ReadReq MSHR miss cycles 563system.l2c.ReadReq_mshr_miss_latency::cpu1.data 22318999 # number of ReadReq MSHR miss cycles 564system.l2c.ReadReq_mshr_miss_latency::total 15477262272 # number of ReadReq MSHR miss cycles 565system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24607428 # number of UpgradeReq MSHR miss cycles 566system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5172008 # number of UpgradeReq MSHR miss cycles 567system.l2c.UpgradeReq_mshr_miss_latency::total 29779436 # number of UpgradeReq MSHR miss cycles 568system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 340034 # number of SCUpgradeReq MSHR miss cycles 569system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 768576 # number of SCUpgradeReq MSHR miss cycles 570system.l2c.SCUpgradeReq_mshr_miss_latency::total 1108610 # number of SCUpgradeReq MSHR miss cycles 571system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8237283129 # number of ReadExReq MSHR miss cycles 572system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 537421779 # number of ReadExReq MSHR miss cycles 573system.l2c.ReadExReq_mshr_miss_latency::total 8774704908 # number of ReadExReq MSHR miss cycles 574system.l2c.demand_mshr_miss_latency::cpu0.inst 892690758 # number of demand (read+write) MSHR miss cycles 575system.l2c.demand_mshr_miss_latency::cpu0.data 22724477144 # number of demand (read+write) MSHR miss cycles 576system.l2c.demand_mshr_miss_latency::cpu1.inst 75058500 # number of demand (read+write) MSHR miss cycles 577system.l2c.demand_mshr_miss_latency::cpu1.data 559740778 # number of demand (read+write) MSHR miss cycles 578system.l2c.demand_mshr_miss_latency::total 24251967180 # number of demand (read+write) MSHR miss cycles 579system.l2c.overall_mshr_miss_latency::cpu0.inst 892690758 # number of overall MSHR miss cycles 580system.l2c.overall_mshr_miss_latency::cpu0.data 22724477144 # number of overall MSHR miss cycles 581system.l2c.overall_mshr_miss_latency::cpu1.inst 75058500 # number of overall MSHR miss cycles 582system.l2c.overall_mshr_miss_latency::cpu1.data 559740778 # number of overall MSHR miss cycles 583system.l2c.overall_mshr_miss_latency::total 24251967180 # number of overall MSHR miss cycles 584system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1368893000 # number of ReadReq MSHR uncacheable cycles 585system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20915000 # number of ReadReq MSHR uncacheable cycles 586system.l2c.ReadReq_mshr_uncacheable_latency::total 1389808000 # number of ReadReq MSHR uncacheable cycles 587system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1950614000 # number of WriteReq MSHR uncacheable cycles 588system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 503814500 # number of WriteReq MSHR uncacheable cycles 589system.l2c.WriteReq_mshr_uncacheable_latency::total 2454428500 # number of WriteReq MSHR uncacheable cycles 590system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3319507000 # number of overall MSHR uncacheable cycles 591system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524729500 # number of overall MSHR uncacheable cycles 592system.l2c.overall_mshr_uncacheable_latency::total 3844236500 # number of overall MSHR uncacheable cycles 593system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for ReadReq accesses 594system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.257469 # mshr miss rate for ReadReq accesses 595system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for ReadReq accesses 596system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010676 # mshr miss rate for ReadReq accesses 597system.l2c.ReadReq_mshr_miss_rate::total 0.132433 # mshr miss rate for ReadReq accesses 598system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933130 # mshr miss rate for UpgradeReq accesses 599system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.917415 # mshr miss rate for UpgradeReq accesses 600system.l2c.UpgradeReq_mshr_miss_rate::total 0.930372 # mshr miss rate for UpgradeReq accesses 601system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.557377 # mshr miss rate for SCUpgradeReq accesses 602system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.791667 # mshr miss rate for SCUpgradeReq accesses 603system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.700637 # mshr miss rate for SCUpgradeReq accesses 604system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.398089 # mshr miss rate for ReadExReq accesses 605system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421084 # mshr miss rate for ReadExReq accesses 606system.l2c.ReadExReq_mshr_miss_rate::total 0.399094 # mshr miss rate for ReadExReq accesses 607system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for demand accesses 608system.l2c.demand_mshr_miss_rate::cpu0.data 0.287787 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for demand accesses 610system.l2c.demand_mshr_miss_rate::cpu1.data 0.132069 # mshr miss rate for demand accesses 611system.l2c.demand_mshr_miss_rate::total 0.165150 # mshr miss rate for demand accesses 612system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for overall accesses 613system.l2c.overall_mshr_miss_rate::cpu0.data 0.287787 # mshr miss rate for overall accesses 614system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for overall accesses 615system.l2c.overall_mshr_miss_rate::cpu1.data 0.132069 # mshr miss rate for overall accesses 616system.l2c.overall_mshr_miss_rate::total 0.165150 # mshr miss rate for overall accesses 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52985.516736 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average ReadReq mshr miss latency 620system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65837.755162 # average ReadReq mshr miss latency 621system.l2c.ReadReq_avg_mshr_miss_latency::total 53547.129366 # average ReadReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10076.751843 # average UpgradeReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10121.346380 # average UpgradeReq mshr miss latency 624system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.468676 # average UpgradeReq mshr miss latency 625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency 626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10112.842105 # average SCUpgradeReq mshr miss latency 627system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.272727 # average SCUpgradeReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70889.449384 # average ReadExReq mshr miss latency 629system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95694.761218 # average ReadExReq mshr miss latency 630system.l2c.ReadExReq_avg_mshr_miss_latency::total 72033.041153 # average ReadExReq mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58325.168419 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93995.092863 # average overall mshr miss latency 635system.l2c.demand_avg_mshr_miss_latency::total 59028.044395 # average overall mshr miss latency 636system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average overall mshr miss latency 637system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58325.168419 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93995.092863 # average overall mshr miss latency 640system.l2c.overall_avg_mshr_miss_latency::total 59028.044395 # average overall mshr miss latency 641system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 642system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 643system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 644system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 645system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 646system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 647system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 648system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 649system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 650system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 651system.iocache.tags.replacements 41700 # number of replacements 652system.iocache.tags.tagsinuse 0.491390 # Cycle average of tags in use 653system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 654system.iocache.tags.sampled_refs 41716 # Sample count of references to valid blocks. 655system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 656system.iocache.tags.warmup_cycle 1711322153000 # Cycle when the warmup percentage was hit. 657system.iocache.tags.occ_blocks::tsunami.ide 0.491390 # Average occupied blocks per requestor 658system.iocache.tags.occ_percent::tsunami.ide 0.030712 # Average percentage of cache occupancy 659system.iocache.tags.occ_percent::total 0.030712 # Average percentage of cache occupancy 660system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 661system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 662system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 663system.iocache.tags.tag_accesses 375588 # Number of tag accesses 664system.iocache.tags.data_accesses 375588 # Number of data accesses 665system.iocache.ReadReq_misses::tsunami.ide 180 # number of ReadReq misses 666system.iocache.ReadReq_misses::total 180 # number of ReadReq misses 667system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 668system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 669system.iocache.demand_misses::tsunami.ide 41732 # number of demand (read+write) misses 670system.iocache.demand_misses::total 41732 # number of demand (read+write) misses 671system.iocache.overall_misses::tsunami.ide 41732 # number of overall misses 672system.iocache.overall_misses::total 41732 # number of overall misses 673system.iocache.ReadReq_miss_latency::tsunami.ide 22063883 # number of ReadReq miss cycles 674system.iocache.ReadReq_miss_latency::total 22063883 # number of ReadReq miss cycles 675system.iocache.WriteReq_miss_latency::tsunami.ide 12446165943 # number of WriteReq miss cycles 676system.iocache.WriteReq_miss_latency::total 12446165943 # number of WriteReq miss cycles 677system.iocache.demand_miss_latency::tsunami.ide 12468229826 # number of demand (read+write) miss cycles 678system.iocache.demand_miss_latency::total 12468229826 # number of demand (read+write) miss cycles 679system.iocache.overall_miss_latency::tsunami.ide 12468229826 # number of overall miss cycles 680system.iocache.overall_miss_latency::total 12468229826 # number of overall miss cycles 681system.iocache.ReadReq_accesses::tsunami.ide 180 # number of ReadReq accesses(hits+misses) 682system.iocache.ReadReq_accesses::total 180 # number of ReadReq accesses(hits+misses) 683system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 684system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 685system.iocache.demand_accesses::tsunami.ide 41732 # number of demand (read+write) accesses 686system.iocache.demand_accesses::total 41732 # number of demand (read+write) accesses 687system.iocache.overall_accesses::tsunami.ide 41732 # number of overall (read+write) accesses 688system.iocache.overall_accesses::total 41732 # number of overall (read+write) accesses 689system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 690system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 691system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 692system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 693system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 694system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 695system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 696system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 697system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency 698system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency 699system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency 700system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency 701system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency 702system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency 703system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency 704system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency 705system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked 706system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 707system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked 708system.iocache.blocked::no_targets 0 # number of cycles access was blocked 709system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked 710system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 711system.iocache.fast_writes 0 # number of fast writes performed 712system.iocache.cache_copies 0 # number of cache copies performed 713system.iocache.writebacks::writebacks 41520 # number of writebacks 714system.iocache.writebacks::total 41520 # number of writebacks 715system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses 716system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses 717system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 718system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 719system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses 720system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses 721system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses 722system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses 723system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles 724system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles 725system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles 726system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles 727system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles 728system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles 729system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles 730system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles 731system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 732system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 733system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 734system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 735system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 736system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 737system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 738system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 739system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency 740system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency 741system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency 742system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency 743system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency 744system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency 745system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency 746system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency 747system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 748system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 749system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 750system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 751system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 752system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 753system.disk0.dma_write_txs 395 # Number of DMA write transactions. 754system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 755system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 756system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 757system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 758system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 759system.disk2.dma_write_txs 1 # Number of DMA write transactions. 760system.cpu0.branchPred.lookups 13535285 # Number of BP lookups 761system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted 762system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect 763system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups 764system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits 765system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 766system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage 767system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. 768system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. 769system.cpu0.dtb.fetch_hits 0 # ITB hits 770system.cpu0.dtb.fetch_misses 0 # ITB misses 771system.cpu0.dtb.fetch_acv 0 # ITB acv 772system.cpu0.dtb.fetch_accesses 0 # ITB accesses 773system.cpu0.dtb.read_hits 9655924 # DTB read hits 774system.cpu0.dtb.read_misses 34371 # DTB read misses 775system.cpu0.dtb.read_acv 569 # DTB read access violations 776system.cpu0.dtb.read_accesses 673777 # DTB read accesses 777system.cpu0.dtb.write_hits 6329246 # DTB write hits 778system.cpu0.dtb.write_misses 8477 # DTB write misses 779system.cpu0.dtb.write_acv 351 # DTB write access violations 780system.cpu0.dtb.write_accesses 236111 # DTB write accesses 781system.cpu0.dtb.data_hits 15985170 # DTB hits 782system.cpu0.dtb.data_misses 42848 # DTB misses 783system.cpu0.dtb.data_acv 920 # DTB access violations 784system.cpu0.dtb.data_accesses 909888 # DTB accesses 785system.cpu0.itb.fetch_hits 1092484 # ITB hits 786system.cpu0.itb.fetch_misses 31809 # ITB misses 787system.cpu0.itb.fetch_acv 996 # ITB acv 788system.cpu0.itb.fetch_accesses 1124293 # ITB accesses 789system.cpu0.itb.read_hits 0 # DTB read hits 790system.cpu0.itb.read_misses 0 # DTB read misses 791system.cpu0.itb.read_acv 0 # DTB read access violations 792system.cpu0.itb.read_accesses 0 # DTB read accesses 793system.cpu0.itb.write_hits 0 # DTB write hits 794system.cpu0.itb.write_misses 0 # DTB write misses 795system.cpu0.itb.write_acv 0 # DTB write access violations 796system.cpu0.itb.write_accesses 0 # DTB write accesses 797system.cpu0.itb.data_hits 0 # DTB hits 798system.cpu0.itb.data_misses 0 # DTB misses 799system.cpu0.itb.data_acv 0 # DTB access violations 800system.cpu0.itb.data_accesses 0 # DTB accesses 801system.cpu0.numCycles 120980731 # number of cpu cycles simulated 802system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 803system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 804system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss 805system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed 806system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered 807system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken 808system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked 809system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing 810system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked 811system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 812system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps 813system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions 814system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR 815system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched 816system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed 817system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) 818system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) 819system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) 820system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 821system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) 822system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) 823system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) 824system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) 825system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) 826system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) 827system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) 828system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) 829system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) 830system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 831system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 832system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 833system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) 834system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle 835system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle 836system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle 837system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked 838system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running 839system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking 840system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing 841system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch 842system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction 843system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode 844system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode 845system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing 846system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle 847system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking 848system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst 849system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running 850system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking 851system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename 852system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full 853system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full 854system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full 855system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full 856system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed 857system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made 858system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups 859system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups 860system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed 861system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing 862system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed 863system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed 864system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer 865system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. 866system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. 867system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. 868system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. 869system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) 870system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ 871system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued 872system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued 873system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling 874system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph 875system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed 876system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle 877system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle 878system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle 879system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 880system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle 881system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle 882system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle 883system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle 884system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle 885system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle 886system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle 887system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle 888system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle 889system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 890system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 891system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 892system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle 893system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 894system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available 895system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available 896system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available 897system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available 898system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available 899system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available 900system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available 901system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available 902system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available 903system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available 904system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available 905system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available 906system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available 907system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available 908system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available 909system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available 910system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available 911system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available 912system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available 913system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available 914system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available 915system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available 916system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available 917system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available 918system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available 919system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available 920system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available 921system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available 922system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available 923system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available 924system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available 925system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 926system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 927system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued 928system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued 929system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued 930system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued 931system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued 932system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued 933system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued 934system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued 935system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued 936system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued 937system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued 938system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued 939system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued 940system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued 941system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued 942system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued 943system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued 944system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued 945system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued 946system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued 947system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued 948system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued 949system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued 950system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued 951system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued 952system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued 953system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued 954system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued 955system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued 956system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued 957system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued 958system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued 959system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued 960system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 961system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued 962system.cpu0.iq.rate 0.455910 # Inst issue rate 963system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested 964system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) 965system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads 966system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes 967system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses 968system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads 969system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes 970system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses 971system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses 972system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses 973system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores 974system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 975system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed 976system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed 977system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations 978system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed 979system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 980system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 981system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled 982system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked 983system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 984system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing 985system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking 986system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking 987system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ 988system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch 989system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions 990system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions 991system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions 992system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall 993system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall 994system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations 995system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly 996system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly 997system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute 998system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions 999system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed 1000system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute 1001system.cpu0.iew.exec_swp 0 # number of swp insts executed 1002system.cpu0.iew.exec_nop 3510502 # number of nop insts executed 1003system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed 1004system.cpu0.iew.exec_branches 8653897 # Number of branches executed 1005system.cpu0.iew.exec_stores 6352232 # Number of stores executed 1006system.cpu0.iew.exec_rate 0.451396 # Inst execution rate 1007system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit 1008system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back 1009system.cpu0.iew.wb_producers 27468175 # num instructions producing a value 1010system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value 1011system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1012system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle 1013system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back 1014system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1015system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit 1016system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards 1017system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted 1018system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle 1019system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle 1020system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle 1021system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1022system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle 1023system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle 1024system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle 1025system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle 1026system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle 1027system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle 1028system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle 1029system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle 1030system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle 1031system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1032system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1033system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1034system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle 1035system.cpu0.commit.committedInsts 54435622 # Number of instructions committed 1036system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed 1037system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1038system.cpu0.commit.refs 14871832 # Number of memory references committed 1039system.cpu0.commit.loads 8745646 # Number of loads committed 1040system.cpu0.commit.membars 219982 # Number of memory barriers committed 1041system.cpu0.commit.branches 8204799 # Number of branches committed 1042system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. 1043system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. 1044system.cpu0.commit.function_calls 712916 # Number of function calls committed. 1045system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction 1046system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction 1047system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction 1048system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction 1049system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction 1050system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction 1051system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction 1052system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction 1053system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction 1054system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction 1055system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction 1056system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction 1057system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction 1058system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction 1059system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction 1060system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction 1061system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction 1062system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction 1063system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction 1064system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction 1065system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction 1066system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction 1067system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction 1068system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction 1069system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction 1070system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction 1071system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction 1072system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction 1073system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction 1074system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction 1075system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction 1076system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction 1077system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction 1078system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1079system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction 1080system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached 1081system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1082system.cpu0.rob.rob_reads 139225703 # The number of ROB reads 1083system.cpu0.rob.rob_writes 125735253 # The number of ROB writes 1084system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself 1085system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling 1086system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1087system.cpu0.committedInsts 51290467 # Number of Instructions Simulated 1088system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated 1089system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction 1090system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads 1091system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle 1092system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads 1093system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads 1094system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes 1095system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads 1096system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes 1097system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads 1098system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes 1099system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1100system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1101system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1102system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1103system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1104system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1105system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1106system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1107system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1108system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1109system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1110system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1111system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1112system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1113system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1114system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1115system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1116system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1117system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1118system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1119system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1120system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1121system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1122system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1123system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1124system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1125system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1126system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1127system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1128system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1129system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1130system.toL2Bus.throughput 111935595 # Throughput (bytes/s) 1131system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution 1132system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution 1133system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution 1134system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution 1135system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution 1136system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution 1137system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution 1138system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution 1139system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution 1140system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution 1141system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution 1142system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) 1143system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) 1144system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) 1145system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) 1146system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) 1147system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) 1148system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) 1149system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) 1150system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) 1151system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) 1152system.toL2Bus.data_through_bus 212628634 # Total data (bytes) 1153system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) 1154system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) 1155system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1156system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) 1157system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1158system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) 1159system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1160system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) 1161system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1162system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) 1163system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1164system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) 1165system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1166system.iobus.throughput 1431950 # Throughput (bytes/s) 1167system.iobus.trans_dist::ReadReq 7376 # Transaction distribution 1168system.iobus.trans_dist::ReadResp 7376 # Transaction distribution 1169system.iobus.trans_dist::WriteReq 53869 # Transaction distribution 1170system.iobus.trans_dist::WriteResp 53869 # Transaction distribution 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) 1187system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.data_through_bus 2729594 # Total data (bytes) 1204system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) 1205system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) 1207system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1209system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1211system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1213system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1215system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) 1217system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1219system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1220system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1221system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1223system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1224system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1225system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1226system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) 1227system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1228system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1229system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1230system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) 1231system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1232system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) 1233system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1234system.cpu0.icache.tags.replacements 993039 # number of replacements 1235system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use 1236system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. 1237system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. 1238system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. 1239system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. 1240system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor 1241system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy 1242system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy 1243system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1244system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 1245system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id 1246system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id 1247system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1248system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses 1249system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses 1250system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits 1251system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits 1252system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits 1253system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits 1254system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits 1255system.cpu0.icache.overall_hits::total 7257459 # number of overall hits 1256system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses 1257system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses 1258system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses 1259system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses 1260system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses 1261system.cpu0.icache.overall_misses::total 1044346 # number of overall misses 1262system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles 1263system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles 1264system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles 1265system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles 1266system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles 1267system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles 1268system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) 1269system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) 1270system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses 1271system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses 1272system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses 1273system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses 1274system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses 1275system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses 1276system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses 1277system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses 1278system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses 1279system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses 1280system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency 1281system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency 1282system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency 1283system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency 1284system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency 1285system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency 1286system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked 1287system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1288system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked 1289system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1290system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked 1291system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1292system.cpu0.icache.fast_writes 0 # number of fast writes performed 1293system.cpu0.icache.cache_copies 0 # number of cache copies performed 1294system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits 1295system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits 1296system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits 1297system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits 1298system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits 1299system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits 1300system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses 1301system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses 1302system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses 1303system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses 1304system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses 1305system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses 1306system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles 1307system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles 1308system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles 1309system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles 1310system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles 1311system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles 1312system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses 1313system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses 1314system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses 1315system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses 1316system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses 1317system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses 1318system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency 1319system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency 1320system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency 1321system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency 1322system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency 1323system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency 1324system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1325system.cpu0.dcache.tags.replacements 1357625 # number of replacements 1326system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use 1327system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. 1328system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. 1329system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. 1330system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. 1331system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor 1332system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy 1333system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy 1334system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1335system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id 1336system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id 1337system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 1338system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1339system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses 1340system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses 1341system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits 1342system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits 1343system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits 1344system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits 1345system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits 1346system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits 1347system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits 1348system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits 1349system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits 1350system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits 1351system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits 1352system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits 1353system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses 1354system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses 1355system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses 1356system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses 1357system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses 1358system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses 1359system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses 1360system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses 1361system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses 1362system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses 1363system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses 1364system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses 1365system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles 1366system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles 1367system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles 1368system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles 1369system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles 1370system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles 1371system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles 1372system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles 1373system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles 1374system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles 1375system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles 1376system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles 1377system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) 1378system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) 1379system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) 1380system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) 1381system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) 1382system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) 1383system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) 1384system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) 1385system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses 1386system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses 1387system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses 1388system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses 1389system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses 1390system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses 1391system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses 1392system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses 1393system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses 1394system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses 1395system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses 1396system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses 1397system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses 1398system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses 1399system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses 1400system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses 1401system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency 1402system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency 1403system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency 1404system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency 1405system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency 1406system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency 1407system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency 1408system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency 1409system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency 1410system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency 1411system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency 1412system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency 1413system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked 1414system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked 1415system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked 1416system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 1417system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked 1418system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked 1419system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1420system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1421system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks 1422system.cpu0.dcache.writebacks::total 808609 # number of writebacks 1423system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits 1424system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits 1425system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits 1426system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits 1427system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits 1428system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits 1429system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits 1430system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits 1431system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits 1432system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits 1433system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses 1434system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses 1435system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses 1436system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses 1437system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses 1438system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses 1439system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses 1440system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses 1441system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses 1442system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses 1443system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses 1444system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses 1445system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles 1446system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles 1447system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles 1448system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles 1449system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles 1450system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles 1451system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles 1452system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles 1453system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles 1454system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles 1455system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles 1456system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles 1457system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles 1458system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles 1459system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles 1460system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles 1461system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles 1462system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles 1463system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses 1464system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses 1465system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses 1466system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses 1467system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses 1468system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses 1469system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses 1470system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses 1471system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses 1472system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses 1473system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses 1474system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses 1475system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency 1476system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency 1477system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency 1478system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency 1479system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency 1480system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency 1481system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency 1482system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency 1483system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency 1484system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency 1485system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency 1486system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency 1487system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1488system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1489system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1490system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1491system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1492system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1493system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1494system.cpu1.branchPred.lookups 1483279 # Number of BP lookups 1495system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted 1496system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect 1497system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups 1498system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits 1499system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1500system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage 1501system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. 1502system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. 1503system.cpu1.dtb.fetch_hits 0 # ITB hits 1504system.cpu1.dtb.fetch_misses 0 # ITB misses 1505system.cpu1.dtb.fetch_acv 0 # ITB acv 1506system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1507system.cpu1.dtb.read_hits 1187167 # DTB read hits 1508system.cpu1.dtb.read_misses 8989 # DTB read misses 1509system.cpu1.dtb.read_acv 6 # DTB read access violations 1510system.cpu1.dtb.read_accesses 276351 # DTB read accesses 1511system.cpu1.dtb.write_hits 628916 # DTB write hits 1512system.cpu1.dtb.write_misses 1890 # DTB write misses 1513system.cpu1.dtb.write_acv 35 # DTB write access violations 1514system.cpu1.dtb.write_accesses 104365 # DTB write accesses 1515system.cpu1.dtb.data_hits 1816083 # DTB hits 1516system.cpu1.dtb.data_misses 10879 # DTB misses 1517system.cpu1.dtb.data_acv 41 # DTB access violations 1518system.cpu1.dtb.data_accesses 380716 # DTB accesses 1519system.cpu1.itb.fetch_hits 316911 # ITB hits 1520system.cpu1.itb.fetch_misses 5517 # ITB misses 1521system.cpu1.itb.fetch_acv 125 # ITB acv 1522system.cpu1.itb.fetch_accesses 322428 # ITB accesses 1523system.cpu1.itb.read_hits 0 # DTB read hits 1524system.cpu1.itb.read_misses 0 # DTB read misses 1525system.cpu1.itb.read_acv 0 # DTB read access violations 1526system.cpu1.itb.read_accesses 0 # DTB read accesses 1527system.cpu1.itb.write_hits 0 # DTB write hits 1528system.cpu1.itb.write_misses 0 # DTB write misses 1529system.cpu1.itb.write_acv 0 # DTB write access violations 1530system.cpu1.itb.write_accesses 0 # DTB write accesses 1531system.cpu1.itb.data_hits 0 # DTB hits 1532system.cpu1.itb.data_misses 0 # DTB misses 1533system.cpu1.itb.data_acv 0 # DTB access violations 1534system.cpu1.itb.data_accesses 0 # DTB accesses 1535system.cpu1.numCycles 8637240 # number of cpu cycles simulated 1536system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1537system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1538system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss 1539system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed 1540system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered 1541system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken 1542system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked 1543system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing 1544system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked 1545system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1546system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps 1547system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions 1548system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR 1549system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched 1550system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed 1551system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) 1552system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) 1553system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) 1554system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1555system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) 1556system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) 1557system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) 1558system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) 1559system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) 1560system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) 1561system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) 1562system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) 1563system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) 1564system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1565system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1566system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1567system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) 1568system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle 1569system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle 1570system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle 1571system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked 1572system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running 1573system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking 1574system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing 1575system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch 1576system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction 1577system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode 1578system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode 1579system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing 1580system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle 1581system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking 1582system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst 1583system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running 1584system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking 1585system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename 1586system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full 1587system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full 1588system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full 1589system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full 1590system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed 1591system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made 1592system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups 1593system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups 1594system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed 1595system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing 1596system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed 1597system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed 1598system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer 1599system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. 1600system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. 1601system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. 1602system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. 1603system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) 1604system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ 1605system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued 1606system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued 1607system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling 1608system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph 1609system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed 1610system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle 1611system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle 1612system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle 1613system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1614system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle 1615system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle 1616system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle 1617system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle 1618system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle 1619system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle 1620system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle 1621system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle 1622system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle 1623system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1624system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1625system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1626system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle 1627system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1628system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available 1629system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available 1630system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available 1631system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available 1632system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available 1633system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available 1634system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available 1635system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available 1636system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available 1637system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available 1638system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available 1639system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available 1640system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available 1641system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available 1642system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available 1643system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available 1644system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available 1645system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available 1646system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available 1647system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available 1648system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available 1649system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available 1650system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available 1651system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available 1652system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available 1653system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available 1654system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available 1655system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available 1656system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available 1657system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available 1658system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available 1659system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1660system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1661system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued 1662system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued 1663system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued 1664system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued 1665system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued 1666system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued 1667system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued 1668system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued 1669system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued 1670system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued 1671system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued 1672system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued 1673system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued 1674system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued 1675system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued 1676system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued 1677system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued 1678system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued 1679system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued 1680system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued 1681system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued 1682system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued 1683system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued 1684system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued 1685system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued 1686system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued 1687system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued 1688system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued 1689system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued 1690system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued 1691system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued 1692system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued 1693system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued 1694system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1695system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued 1696system.cpu1.iq.rate 0.618450 # Inst issue rate 1697system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested 1698system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) 1699system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads 1700system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes 1701system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses 1702system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads 1703system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes 1704system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses 1705system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses 1706system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses 1707system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores 1708system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1709system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed 1710system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed 1711system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations 1712system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed 1713system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1714system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1715system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled 1716system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked 1717system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1718system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing 1719system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking 1720system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking 1721system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ 1722system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch 1723system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions 1724system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions 1725system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions 1726system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall 1727system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall 1728system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations 1729system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly 1730system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly 1731system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute 1732system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions 1733system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed 1734system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute 1735system.cpu1.iew.exec_swp 0 # number of swp insts executed 1736system.cpu1.iew.exec_nop 221139 # number of nop insts executed 1737system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed 1738system.cpu1.iew.exec_branches 762873 # Number of branches executed 1739system.cpu1.iew.exec_stores 633845 # Number of stores executed 1740system.cpu1.iew.exec_rate 0.612230 # Inst execution rate 1741system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit 1742system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back 1743system.cpu1.iew.wb_producers 2532511 # num instructions producing a value 1744system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value 1745system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1746system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle 1747system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back 1748system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1749system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit 1750system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards 1751system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted 1752system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle 1753system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle 1754system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle 1755system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1756system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle 1757system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle 1758system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle 1759system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle 1760system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle 1761system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle 1762system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle 1763system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle 1764system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle 1765system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1766system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1767system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1768system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle 1769system.cpu1.commit.committedInsts 4954074 # Number of instructions committed 1770system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed 1771system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1772system.cpu1.commit.refs 1585273 # Number of memory references committed 1773system.cpu1.commit.loads 996375 # Number of loads committed 1774system.cpu1.commit.membars 16576 # Number of memory barriers committed 1775system.cpu1.commit.branches 700739 # Number of branches committed 1776system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. 1777system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. 1778system.cpu1.commit.function_calls 77324 # Number of function calls committed. 1779system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction 1780system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction 1781system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction 1782system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction 1783system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction 1784system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction 1785system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction 1786system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction 1787system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction 1788system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction 1789system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction 1790system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction 1791system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction 1792system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction 1793system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction 1794system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction 1795system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction 1796system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction 1797system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction 1798system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction 1799system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction 1800system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction 1801system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction 1802system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction 1803system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction 1804system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction 1805system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction 1806system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction 1807system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction 1808system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction 1809system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction 1810system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction 1811system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction 1812system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1813system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction 1814system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached 1815system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1816system.cpu1.rob.rob_reads 13715407 # The number of ROB reads 1817system.cpu1.rob.rob_writes 12215098 # The number of ROB writes 1818system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself 1819system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling 1820system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1821system.cpu1.committedInsts 4765602 # Number of Instructions Simulated 1822system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated 1823system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction 1824system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads 1825system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle 1826system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads 1827system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads 1828system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes 1829system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads 1830system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes 1831system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads 1832system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes 1833system.cpu1.icache.tags.replacements 94727 # number of replacements 1834system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use 1835system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. 1836system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. 1837system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. 1838system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. 1839system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor 1840system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy 1841system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy 1842system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1843system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 1844system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1845system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses 1846system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses 1847system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits 1848system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits 1849system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits 1850system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits 1851system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits 1852system.cpu1.icache.overall_hits::total 794363 # number of overall hits 1853system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses 1854system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses 1855system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses 1856system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses 1857system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses 1858system.cpu1.icache.overall_misses::total 99697 # number of overall misses 1859system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles 1860system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles 1861system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles 1862system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles 1863system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles 1864system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles 1865system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) 1866system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) 1867system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses 1868system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses 1869system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses 1870system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses 1871system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses 1872system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses 1873system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses 1874system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses 1875system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses 1876system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses 1877system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency 1878system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency 1879system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency 1880system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency 1881system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency 1882system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency 1883system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked 1884system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1885system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked 1886system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1887system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked 1888system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1889system.cpu1.icache.fast_writes 0 # number of fast writes performed 1890system.cpu1.icache.cache_copies 0 # number of cache copies performed 1891system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits 1892system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits 1893system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits 1894system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits 1895system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits 1896system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits 1897system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses 1898system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses 1899system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses 1900system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses 1901system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses 1902system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses 1903system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles 1904system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles 1905system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles 1906system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles 1907system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles 1908system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles 1909system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses 1910system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses 1911system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses 1912system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses 1913system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses 1914system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses 1915system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency 1916system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency 1917system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency 1918system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency 1919system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency 1920system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency 1921system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1922system.cpu1.dcache.tags.replacements 45361 # number of replacements 1923system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use 1924system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks. 1925system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks. 1926system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks. 1927system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit. 1928system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor 1929system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy 1930system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy 1931system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id 1932system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 1933system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id 1934system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses 1935system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses 1936system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits 1937system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits 1938system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits 1939system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits 1940system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits 1941system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits 1942system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits 1943system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits 1944system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits 1945system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits 1946system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits 1947system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits 1948system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses 1949system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses 1950system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses 1951system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses 1952system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses 1953system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses 1954system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses 1955system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses 1956system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses 1957system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses 1958system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses 1959system.cpu1.dcache.overall_misses::total 176847 # number of overall misses 1960system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles 1961system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles 1962system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles 1963system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles 1964system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # number of LoadLockedReq miss cycles 1965system.cpu1.dcache.LoadLockedReq_miss_latency::total 13905498 # number of LoadLockedReq miss cycles 1966system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4132075 # number of StoreCondReq miss cycles 1967system.cpu1.dcache.StoreCondReq_miss_latency::total 4132075 # number of StoreCondReq miss cycles 1968system.cpu1.dcache.demand_miss_latency::cpu1.data 6156210526 # number of demand (read+write) miss cycles 1969system.cpu1.dcache.demand_miss_latency::total 6156210526 # number of demand (read+write) miss cycles 1970system.cpu1.dcache.overall_miss_latency::cpu1.data 6156210526 # number of overall miss cycles 1971system.cpu1.dcache.overall_miss_latency::total 6156210526 # number of overall miss cycles 1972system.cpu1.dcache.ReadReq_accesses::cpu1.data 1042294 # number of ReadReq accesses(hits+misses) 1973system.cpu1.dcache.ReadReq_accesses::total 1042294 # number of ReadReq accesses(hits+misses) 1974system.cpu1.dcache.WriteReq_accesses::cpu1.data 572688 # number of WriteReq accesses(hits+misses) 1975system.cpu1.dcache.WriteReq_accesses::total 572688 # number of WriteReq accesses(hits+misses) 1976system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) 1977system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) 1978system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) 1979system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) 1980system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses 1981system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses 1982system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses 1983system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses 1984system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses 1985system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses 1986system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses 1987system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses 1988system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses 1989system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses 1990system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses 1991system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses 1992system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses 1993system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses 1994system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses 1995system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses 1996system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency 1997system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency 1998system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency 1999system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency 2000system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency 2001system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency 2002system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency 2003system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency 2004system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency 2005system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency 2006system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency 2007system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency 2008system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked 2009system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2010system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked 2011system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2012system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked 2013system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2014system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2015system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2016system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks 2017system.cpu1.dcache.writebacks::total 24956 # number of writebacks 2018system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits 2019system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits 2020system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits 2021system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits 2022system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits 2023system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits 2024system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits 2025system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits 2026system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits 2027system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits 2028system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses 2029system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses 2030system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses 2031system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses 2032system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses 2033system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses 2034system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses 2035system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses 2036system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses 2037system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses 2038system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses 2039system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses 2040system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles 2041system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles 2042system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles 2043system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles 2044system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles 2045system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles 2046system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles 2047system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles 2048system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles 2049system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles 2050system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles 2051system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles 2052system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles 2053system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles 2054system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles 2055system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles 2056system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles 2057system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles 2058system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses 2059system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses 2060system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses 2061system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses 2062system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses 2063system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses 2064system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses 2065system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses 2066system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses 2067system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses 2068system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses 2069system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses 2070system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency 2071system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency 2072system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency 2073system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency 2074system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency 2075system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency 2076system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency 2077system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency 2078system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency 2079system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency 2080system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency 2081system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency 2082system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2083system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2084system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2085system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2086system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2087system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2088system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2089system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2090system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed 2091system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed 2092system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl 2093system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl 2094system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl 2095system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl 2096system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl 2097system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl 2098system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl 2099system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl 2100system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl 2101system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl 2102system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl 2103system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl 2104system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl 2105system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl 2106system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl 2107system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl 2108system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl 2109system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl 2110system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl 2111system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2112system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2113system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2114system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl 2115system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl 2116system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 2117system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 2118system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 2119system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 2120system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 2121system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 2122system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 2123system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed 2124system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed 2125system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed 2126system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed 2127system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed 2128system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed 2129system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed 2130system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed 2131system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed 2132system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed 2133system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed 2134system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed 2135system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed 2136system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed 2137system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed 2138system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed 2139system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 2140system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 2141system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 2142system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 2143system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 2144system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 2145system.cpu0.kern.syscall::total 234 # number of syscalls executed 2146system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2147system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed 2148system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed 2149system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed 2150system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed 2151system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed 2152system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed 2153system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed 2154system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed 2155system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed 2156system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed 2157system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed 2158system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed 2159system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed 2160system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed 2161system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed 2162system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed 2163system.cpu0.kern.callpal::total 187581 # number of callpals executed 2164system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches 2165system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches 2166system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2167system.cpu0.kern.mode_good::kernel 1369 2168system.cpu0.kern.mode_good::user 1370 2169system.cpu0.kern.mode_good::idle 0 2170system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches 2171system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2172system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2173system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches 2174system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode 2175system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode 2176system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2177system.cpu0.kern.swap_context 3931 # number of times the context was actually changed 2178system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2179system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed 2180system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed 2181system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl 2182system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl 2183system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl 2184system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl 2185system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl 2186system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl 2187system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl 2188system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl 2189system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl 2190system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl 2191system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl 2192system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl 2193system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl 2194system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl 2195system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl 2196system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl 2197system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2198system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2199system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl 2200system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl 2201system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 2202system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 2203system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 2204system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 2205system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 2206system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 2207system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 2208system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 2209system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 2210system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 2211system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 2212system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 2213system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 2214system.cpu1.kern.syscall::total 92 # number of syscalls executed 2215system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2216system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed 2217system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 2218system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 2219system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed 2220system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed 2221system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed 2222system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed 2223system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed 2224system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed 2225system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed 2226system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed 2227system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed 2228system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed 2229system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed 2230system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2231system.cpu1.kern.callpal::total 28623 # number of callpals executed 2232system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches 2233system.cpu1.kern.mode_switch::user 367 # number of protection mode switches 2234system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches 2235system.cpu1.kern.mode_good::kernel 386 2236system.cpu1.kern.mode_good::user 367 2237system.cpu1.kern.mode_good::idle 19 2238system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches 2239system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2240system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches 2241system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches 2242system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode 2243system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode 2244system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode 2245system.cpu1.kern.swap_context 299 # number of times the context was actually changed 2246 2247---------- End Simulation Statistics ---------- 2248