stats.txt revision 10229:aae7735450a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.905651 # Number of seconds simulated 4sim_ticks 1905651402000 # Number of ticks simulated 5final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 124387 # Simulator instruction rate (inst/s) 8host_op_rate 124387 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4179760275 # Simulator tick rate (ticks/s) 10host_mem_usage 352908 # Number of bytes of host memory used 11host_seconds 455.92 # Real time elapsed on the host 12sim_insts 56710998 # Number of instructions simulated 13sim_ops 56710998 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory 21system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory 29system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 450903 # Number of read requests accepted 54system.physmem.writeReqs 122139 # Number of write requests accepted 55system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 28020 # Per bank write bursts 66system.physmem.perBankRdBursts::1 28240 # Per bank write bursts 67system.physmem.perBankRdBursts::2 28746 # Per bank write bursts 68system.physmem.perBankRdBursts::3 28309 # Per bank write bursts 69system.physmem.perBankRdBursts::4 27973 # Per bank write bursts 70system.physmem.perBankRdBursts::5 28180 # Per bank write bursts 71system.physmem.perBankRdBursts::6 28116 # Per bank write bursts 72system.physmem.perBankRdBursts::7 27456 # Per bank write bursts 73system.physmem.perBankRdBursts::8 27700 # Per bank write bursts 74system.physmem.perBankRdBursts::9 28070 # Per bank write bursts 75system.physmem.perBankRdBursts::10 27744 # Per bank write bursts 76system.physmem.perBankRdBursts::11 28151 # Per bank write bursts 77system.physmem.perBankRdBursts::12 28476 # Per bank write bursts 78system.physmem.perBankRdBursts::13 28764 # Per bank write bursts 79system.physmem.perBankRdBursts::14 28477 # Per bank write bursts 80system.physmem.perBankRdBursts::15 28339 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7807 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7750 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8222 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7743 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7390 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7636 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7609 # Per bank write bursts 88system.physmem.perBankWrBursts::7 6913 # Per bank write bursts 89system.physmem.perBankWrBursts::8 6944 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7275 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7157 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7547 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7916 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8234 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8082 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7890 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 99system.physmem.totGap 1905651381000 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 450903 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 122139 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads 274system.physmem.totQLat 8930594750 # Total ticks spent queuing 275system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 279system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.15 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing 289system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing 290system.physmem.readRowHits 407659 # Number of row buffer hits during reads 291system.physmem.writeRowHits 98604 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes 294system.physmem.avgGap 3325500.37 # Average gap between requests 295system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined 296system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states 297system.physmem.memoryStateTime::REF 63633700000 # Time in different power states 298system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states 300system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.membus.throughput 19303809 # Throughput (bytes/s) 302system.membus.trans_dist::ReadReq 296468 # Transaction distribution 303system.membus.trans_dist::ReadResp 296393 # Transaction distribution 304system.membus.trans_dist::WriteReq 13039 # Transaction distribution 305system.membus.trans_dist::WriteResp 13039 # Transaction distribution 306system.membus.trans_dist::Writeback 122139 # Transaction distribution 307system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution 308system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution 309system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution 310system.membus.trans_dist::ReadExReq 162690 # Transaction distribution 311system.membus.trans_dist::ReadExResp 162297 # Transaction distribution 312system.membus.trans_dist::BadAddressError 75 # Transaction distribution 313system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) 320system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) 326system.membus.data_through_bus 36748378 # Total data (bytes) 327system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) 328system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) 329system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 330system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) 331system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 332system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) 333system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 334system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) 335system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 336system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) 337system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 338system.cpu_clk_domain.clock 500 # Clock period in ticks 339system.l2c.tags.replacements 343977 # number of replacements 340system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use 341system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. 342system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. 343system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. 344system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. 345system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor 346system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor 347system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor 348system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor 349system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor 350system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy 351system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy 352system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy 353system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy 354system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy 355system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy 356system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id 357system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id 358system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id 359system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id 360system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id 361system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id 362system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id 363system.l2c.tags.tag_accesses 27108862 # Number of tag accesses 364system.l2c.tags.data_accesses 27108862 # Number of data accesses 365system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits 366system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits 367system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits 368system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits 369system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits 370system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits 371system.l2c.Writeback_hits::total 822208 # number of Writeback hits 372system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits 373system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits 374system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits 375system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits 376system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 377system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits 378system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits 379system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits 380system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits 381system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits 382system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits 383system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits 384system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits 385system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits 386system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits 387system.l2c.overall_hits::cpu0.data 891053 # number of overall hits 388system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits 389system.l2c.overall_hits::cpu1.data 93491 # number of overall hits 390system.l2c.overall_hits::total 2062288 # number of overall hits 391system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses 392system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses 393system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses 394system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses 395system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses 396system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses 397system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses 398system.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses 399system.l2c.SCUpgradeReq_misses::cpu0.data 406 # number of SCUpgradeReq misses 400system.l2c.SCUpgradeReq_misses::cpu1.data 434 # number of SCUpgradeReq misses 401system.l2c.SCUpgradeReq_misses::total 840 # number of SCUpgradeReq misses 402system.l2c.ReadExReq_misses::cpu0.data 114695 # number of ReadExReq misses 403system.l2c.ReadExReq_misses::cpu1.data 6342 # number of ReadExReq misses 404system.l2c.ReadExReq_misses::total 121037 # number of ReadExReq misses 405system.l2c.demand_misses::cpu0.inst 14035 # number of demand (read+write) misses 406system.l2c.demand_misses::cpu0.data 388087 # number of demand (read+write) misses 407system.l2c.demand_misses::cpu1.inst 1238 # number of demand (read+write) misses 408system.l2c.demand_misses::cpu1.data 6794 # number of demand (read+write) misses 409system.l2c.demand_misses::total 410154 # number of demand (read+write) misses 410system.l2c.overall_misses::cpu0.inst 14035 # number of overall misses 411system.l2c.overall_misses::cpu0.data 388087 # number of overall misses 412system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses 413system.l2c.overall_misses::cpu1.data 6794 # number of overall misses 414system.l2c.overall_misses::total 410154 # number of overall misses 415system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles 416system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles 417system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles 418system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles 419system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles 420system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles 421system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles 422system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles 423system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles 424system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles 425system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles 426system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # number of ReadExReq miss cycles 427system.l2c.ReadExReq_miss_latency::cpu1.data 639497214 # number of ReadExReq miss cycles 428system.l2c.ReadExReq_miss_latency::total 10033444947 # number of ReadExReq miss cycles 429system.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles 430system.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles 431system.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles 432system.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles 433system.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles 434system.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles 435system.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles 436system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles 437system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles 438system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles 439system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) 440system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) 441system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) 442system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) 443system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) 444system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) 445system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) 446system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) 447system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses) 448system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses) 449system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses) 450system.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses) 451system.l2c.SCUpgradeReq_accesses::total 913 # number of SCUpgradeReq accesses(hits+misses) 452system.l2c.ReadExReq_accesses::cpu0.data 269131 # number of ReadExReq accesses(hits+misses) 453system.l2c.ReadExReq_accesses::cpu1.data 31923 # number of ReadExReq accesses(hits+misses) 454system.l2c.ReadExReq_accesses::total 301054 # number of ReadExReq accesses(hits+misses) 455system.l2c.demand_accesses::cpu0.inst 881651 # number of demand (read+write) accesses 456system.l2c.demand_accesses::cpu0.data 1279140 # number of demand (read+write) accesses 457system.l2c.demand_accesses::cpu1.inst 211366 # number of demand (read+write) accesses 458system.l2c.demand_accesses::cpu1.data 100285 # number of demand (read+write) accesses 459system.l2c.demand_accesses::total 2472442 # number of demand (read+write) accesses 460system.l2c.overall_accesses::cpu0.inst 881651 # number of overall (read+write) accesses 461system.l2c.overall_accesses::cpu0.data 1279140 # number of overall (read+write) accesses 462system.l2c.overall_accesses::cpu1.inst 211366 # number of overall (read+write) accesses 463system.l2c.overall_accesses::cpu1.data 100285 # number of overall (read+write) accesses 464system.l2c.overall_accesses::total 2472442 # number of overall (read+write) accesses 465system.l2c.ReadReq_miss_rate::cpu0.inst 0.015919 # miss rate for ReadReq accesses 466system.l2c.ReadReq_miss_rate::cpu0.data 0.270683 # miss rate for ReadReq accesses 467system.l2c.ReadReq_miss_rate::cpu1.inst 0.005857 # miss rate for ReadReq accesses 468system.l2c.ReadReq_miss_rate::cpu1.data 0.006612 # miss rate for ReadReq accesses 469system.l2c.ReadReq_miss_rate::total 0.133148 # miss rate for ReadReq accesses 470system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940535 # miss rate for UpgradeReq accesses 471system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801822 # miss rate for UpgradeReq accesses 472system.l2c.UpgradeReq_miss_rate::total 0.896610 # miss rate for UpgradeReq accesses 473system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.892308 # miss rate for SCUpgradeReq accesses 474system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947598 # miss rate for SCUpgradeReq accesses 475system.l2c.SCUpgradeReq_miss_rate::total 0.920044 # miss rate for SCUpgradeReq accesses 476system.l2c.ReadExReq_miss_rate::cpu0.data 0.426168 # miss rate for ReadExReq accesses 477system.l2c.ReadExReq_miss_rate::cpu1.data 0.198666 # miss rate for ReadExReq accesses 478system.l2c.ReadExReq_miss_rate::total 0.402044 # miss rate for ReadExReq accesses 479system.l2c.demand_miss_rate::cpu0.inst 0.015919 # miss rate for demand accesses 480system.l2c.demand_miss_rate::cpu0.data 0.303397 # miss rate for demand accesses 481system.l2c.demand_miss_rate::cpu1.inst 0.005857 # miss rate for demand accesses 482system.l2c.demand_miss_rate::cpu1.data 0.067747 # miss rate for demand accesses 483system.l2c.demand_miss_rate::total 0.165890 # miss rate for demand accesses 484system.l2c.overall_miss_rate::cpu0.inst 0.015919 # miss rate for overall accesses 485system.l2c.overall_miss_rate::cpu0.data 0.303397 # miss rate for overall accesses 486system.l2c.overall_miss_rate::cpu1.inst 0.005857 # miss rate for overall accesses 487system.l2c.overall_miss_rate::cpu1.data 0.067747 # miss rate for overall accesses 488system.l2c.overall_miss_rate::total 0.165890 # miss rate for overall accesses 489system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76056.590310 # average ReadReq miss latency 490system.l2c.ReadReq_avg_miss_latency::cpu0.data 65406.523369 # average ReadReq miss latency 491system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78241.114701 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu1.data 78223.449115 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::total 65998.519565 # average ReadReq miss latency 494system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 360.818556 # average UpgradeReq miss latency 495system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4325.562500 # average UpgradeReq miss latency 496system.l2c.UpgradeReq_avg_miss_latency::total 1483.577903 # average UpgradeReq miss latency 497system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2395.224138 # average SCUpgradeReq miss latency 498system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 264.965438 # average SCUpgradeReq miss latency 499system.l2c.SCUpgradeReq_avg_miss_latency::total 1294.590476 # average SCUpgradeReq miss latency 500system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81903.724949 # average ReadExReq miss latency 501system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100835.259224 # average ReadExReq miss latency 502system.l2c.ReadExReq_avg_miss_latency::total 82895.684353 # average ReadExReq miss latency 503system.l2c.demand_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency 504system.l2c.demand_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency 505system.l2c.demand_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency 506system.l2c.demand_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency 507system.l2c.demand_avg_miss_latency::total 70984.895742 # average overall miss latency 508system.l2c.overall_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency 512system.l2c.overall_avg_miss_latency::total 70984.895742 # average overall miss latency 513system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 516system.l2c.blocked::no_targets 0 # number of cycles access was blocked 517system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.l2c.fast_writes 0 # number of fast writes performed 520system.l2c.cache_copies 0 # number of cache copies performed 521system.l2c.writebacks::writebacks 80619 # number of writebacks 522system.l2c.writebacks::total 80619 # number of writebacks 523system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits 524system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits 525system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 526system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 527system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 528system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 529system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 530system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 531system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 532system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 533system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 534system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 535system.l2c.ReadReq_mshr_misses::cpu0.inst 14026 # number of ReadReq MSHR misses 536system.l2c.ReadReq_mshr_misses::cpu0.data 273392 # number of ReadReq MSHR misses 537system.l2c.ReadReq_mshr_misses::cpu1.inst 1230 # number of ReadReq MSHR misses 538system.l2c.ReadReq_mshr_misses::cpu1.data 451 # number of ReadReq MSHR misses 539system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses 540system.l2c.UpgradeReq_mshr_misses::cpu0.data 2673 # number of UpgradeReq MSHR misses 541system.l2c.UpgradeReq_mshr_misses::cpu1.data 1056 # number of UpgradeReq MSHR misses 542system.l2c.UpgradeReq_mshr_misses::total 3729 # number of UpgradeReq MSHR misses 543system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 406 # number of SCUpgradeReq MSHR misses 544system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 434 # number of SCUpgradeReq MSHR misses 545system.l2c.SCUpgradeReq_mshr_misses::total 840 # number of SCUpgradeReq MSHR misses 546system.l2c.ReadExReq_mshr_misses::cpu0.data 114695 # number of ReadExReq MSHR misses 547system.l2c.ReadExReq_mshr_misses::cpu1.data 6342 # number of ReadExReq MSHR misses 548system.l2c.ReadExReq_mshr_misses::total 121037 # number of ReadExReq MSHR misses 549system.l2c.demand_mshr_misses::cpu0.inst 14026 # number of demand (read+write) MSHR misses 550system.l2c.demand_mshr_misses::cpu0.data 388087 # number of demand (read+write) MSHR misses 551system.l2c.demand_mshr_misses::cpu1.inst 1230 # number of demand (read+write) MSHR misses 552system.l2c.demand_mshr_misses::cpu1.data 6793 # number of demand (read+write) MSHR misses 553system.l2c.demand_mshr_misses::total 410136 # number of demand (read+write) MSHR misses 554system.l2c.overall_mshr_misses::cpu0.inst 14026 # number of overall MSHR misses 555system.l2c.overall_mshr_misses::cpu0.data 388087 # number of overall MSHR misses 556system.l2c.overall_mshr_misses::cpu1.inst 1230 # number of overall MSHR misses 557system.l2c.overall_mshr_misses::cpu1.data 6793 # number of overall MSHR misses 558system.l2c.overall_mshr_misses::total 410136 # number of overall MSHR misses 559system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 890067005 # number of ReadReq MSHR miss cycles 560system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14473617763 # number of ReadReq MSHR miss cycles 561system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 80840000 # number of ReadReq MSHR miss cycles 562system.l2c.ReadReq_mshr_miss_latency::cpu1.data 29712501 # number of ReadReq MSHR miss cycles 563system.l2c.ReadReq_mshr_miss_latency::total 15474237269 # number of ReadReq MSHR miss cycles 564system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26950129 # number of UpgradeReq MSHR miss cycles 565system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10569046 # number of UpgradeReq MSHR miss cycles 566system.l2c.UpgradeReq_mshr_miss_latency::total 37519175 # number of UpgradeReq MSHR miss cycles 567system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4153902 # number of SCUpgradeReq MSHR miss cycles 568system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4341434 # number of SCUpgradeReq MSHR miss cycles 569system.l2c.SCUpgradeReq_mshr_miss_latency::total 8495336 # number of SCUpgradeReq MSHR miss cycles 570system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7989750261 # number of ReadExReq MSHR miss cycles 571system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 560973786 # number of ReadExReq MSHR miss cycles 572system.l2c.ReadExReq_mshr_miss_latency::total 8550724047 # number of ReadExReq MSHR miss cycles 573system.l2c.demand_mshr_miss_latency::cpu0.inst 890067005 # number of demand (read+write) MSHR miss cycles 574system.l2c.demand_mshr_miss_latency::cpu0.data 22463368024 # number of demand (read+write) MSHR miss cycles 575system.l2c.demand_mshr_miss_latency::cpu1.inst 80840000 # number of demand (read+write) MSHR miss cycles 576system.l2c.demand_mshr_miss_latency::cpu1.data 590686287 # number of demand (read+write) MSHR miss cycles 577system.l2c.demand_mshr_miss_latency::total 24024961316 # number of demand (read+write) MSHR miss cycles 578system.l2c.overall_mshr_miss_latency::cpu0.inst 890067005 # number of overall MSHR miss cycles 579system.l2c.overall_mshr_miss_latency::cpu0.data 22463368024 # number of overall MSHR miss cycles 580system.l2c.overall_mshr_miss_latency::cpu1.inst 80840000 # number of overall MSHR miss cycles 581system.l2c.overall_mshr_miss_latency::cpu1.data 590686287 # number of overall MSHR miss cycles 582system.l2c.overall_mshr_miss_latency::total 24024961316 # number of overall MSHR miss cycles 583system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367392500 # number of ReadReq MSHR uncacheable cycles 584system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22035500 # number of ReadReq MSHR uncacheable cycles 585system.l2c.ReadReq_mshr_uncacheable_latency::total 1389428000 # number of ReadReq MSHR uncacheable cycles 586system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2022747000 # number of WriteReq MSHR uncacheable cycles 587system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 583651500 # number of WriteReq MSHR uncacheable cycles 588system.l2c.WriteReq_mshr_uncacheable_latency::total 2606398500 # number of WriteReq MSHR uncacheable cycles 589system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3390139500 # number of overall MSHR uncacheable cycles 590system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605687000 # number of overall MSHR uncacheable cycles 591system.l2c.overall_mshr_uncacheable_latency::total 3995826500 # number of overall MSHR uncacheable cycles 592system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for ReadReq accesses 593system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270683 # mshr miss rate for ReadReq accesses 594system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for ReadReq accesses 595system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006597 # mshr miss rate for ReadReq accesses 596system.l2c.ReadReq_mshr_miss_rate::total 0.133140 # mshr miss rate for ReadReq accesses 597system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940535 # mshr miss rate for UpgradeReq accesses 598system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801822 # mshr miss rate for UpgradeReq accesses 599system.l2c.UpgradeReq_mshr_miss_rate::total 0.896610 # mshr miss rate for UpgradeReq accesses 600system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.892308 # mshr miss rate for SCUpgradeReq accesses 601system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947598 # mshr miss rate for SCUpgradeReq accesses 602system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.920044 # mshr miss rate for SCUpgradeReq accesses 603system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426168 # mshr miss rate for ReadExReq accesses 604system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198666 # mshr miss rate for ReadExReq accesses 605system.l2c.ReadExReq_mshr_miss_rate::total 0.402044 # mshr miss rate for ReadExReq accesses 606system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for demand accesses 607system.l2c.demand_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for demand accesses 608system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for demand accesses 610system.l2c.demand_mshr_miss_rate::total 0.165883 # mshr miss rate for demand accesses 611system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for overall accesses 612system.l2c.overall_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for overall accesses 613system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for overall accesses 614system.l2c.overall_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for overall accesses 615system.l2c.overall_mshr_miss_rate::total 0.165883 # mshr miss rate for overall accesses 616system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average ReadReq mshr miss latency 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52940.897184 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65881.376940 # average ReadReq mshr miss latency 620system.l2c.ReadReq_avg_mshr_miss_latency::total 53525.737789 # average ReadReq mshr miss latency 621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.352787 # average UpgradeReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.566288 # average UpgradeReq mshr miss latency 623system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.457495 # average UpgradeReq mshr miss latency 624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10231.285714 # average SCUpgradeReq mshr miss latency 625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.304147 # average SCUpgradeReq mshr miss latency 626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10113.495238 # average SCUpgradeReq mshr miss latency 627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69660.841894 # average ReadExReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 88453.766320 # average ReadExReq mshr miss latency 629system.l2c.ReadExReq_avg_mshr_miss_latency::total 70645.538530 # average ReadExReq mshr miss latency 630system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency 634system.l2c.demand_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency 635system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency 636system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency 637system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency 639system.l2c.overall_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency 640system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 641system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 642system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 643system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 644system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 645system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 646system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 647system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 648system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 649system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 650system.iocache.tags.replacements 41695 # number of replacements 651system.iocache.tags.tagsinuse 0.491978 # Cycle average of tags in use 652system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 653system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 654system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 655system.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit. 656system.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor 657system.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy 658system.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy 659system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 660system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 661system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 662system.iocache.tags.tag_accesses 375543 # Number of tag accesses 663system.iocache.tags.data_accesses 375543 # Number of data accesses 664system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 665system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 666system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 667system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 668system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 669system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 670system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 671system.iocache.overall_misses::total 41727 # number of overall misses 672system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles 673system.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles 674system.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles 675system.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles 676system.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles 677system.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles 678system.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles 679system.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles 680system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 681system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 682system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 683system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 684system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 685system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 686system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 687system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 688system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 689system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 690system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 691system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 692system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 693system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 694system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 695system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 696system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency 697system.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency 698system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency 699system.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency 700system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency 701system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency 702system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency 703system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency 704system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked 705system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 706system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked 707system.iocache.blocked::no_targets 0 # number of cycles access was blocked 708system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked 709system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.iocache.fast_writes 0 # number of fast writes performed 711system.iocache.cache_copies 0 # number of cache copies performed 712system.iocache.writebacks::writebacks 41520 # number of writebacks 713system.iocache.writebacks::total 41520 # number of writebacks 714system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 715system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 716system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 717system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 718system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses 719system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses 720system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses 721system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses 722system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles 723system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles 724system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles 725system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles 726system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles 727system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles 728system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles 729system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles 730system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 731system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 732system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 733system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 734system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 735system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 736system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 737system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 738system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency 739system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency 740system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency 741system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency 742system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency 743system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency 744system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency 745system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency 746system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 747system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 748system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 749system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 750system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 751system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 752system.disk0.dma_write_txs 395 # Number of DMA write transactions. 753system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 754system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 755system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 756system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 757system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 758system.disk2.dma_write_txs 1 # Number of DMA write transactions. 759system.cpu0.branchPred.lookups 12477942 # Number of BP lookups 760system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted 761system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect 762system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups 763system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits 764system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 765system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage 766system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. 767system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. 768system.cpu0.dtb.fetch_hits 0 # ITB hits 769system.cpu0.dtb.fetch_misses 0 # ITB misses 770system.cpu0.dtb.fetch_acv 0 # ITB acv 771system.cpu0.dtb.fetch_accesses 0 # ITB accesses 772system.cpu0.dtb.read_hits 8879185 # DTB read hits 773system.cpu0.dtb.read_misses 30734 # DTB read misses 774system.cpu0.dtb.read_acv 556 # DTB read access violations 775system.cpu0.dtb.read_accesses 627584 # DTB read accesses 776system.cpu0.dtb.write_hits 5815647 # DTB write hits 777system.cpu0.dtb.write_misses 8173 # DTB write misses 778system.cpu0.dtb.write_acv 357 # DTB write access violations 779system.cpu0.dtb.write_accesses 210225 # DTB write accesses 780system.cpu0.dtb.data_hits 14694832 # DTB hits 781system.cpu0.dtb.data_misses 38907 # DTB misses 782system.cpu0.dtb.data_acv 913 # DTB access violations 783system.cpu0.dtb.data_accesses 837809 # DTB accesses 784system.cpu0.itb.fetch_hits 998260 # ITB hits 785system.cpu0.itb.fetch_misses 27519 # ITB misses 786system.cpu0.itb.fetch_acv 894 # ITB acv 787system.cpu0.itb.fetch_accesses 1025779 # ITB accesses 788system.cpu0.itb.read_hits 0 # DTB read hits 789system.cpu0.itb.read_misses 0 # DTB read misses 790system.cpu0.itb.read_acv 0 # DTB read access violations 791system.cpu0.itb.read_accesses 0 # DTB read accesses 792system.cpu0.itb.write_hits 0 # DTB write hits 793system.cpu0.itb.write_misses 0 # DTB write misses 794system.cpu0.itb.write_acv 0 # DTB write access violations 795system.cpu0.itb.write_accesses 0 # DTB write accesses 796system.cpu0.itb.data_hits 0 # DTB hits 797system.cpu0.itb.data_misses 0 # DTB misses 798system.cpu0.itb.data_acv 0 # DTB access violations 799system.cpu0.itb.data_accesses 0 # DTB accesses 800system.cpu0.numCycles 116074371 # number of cpu cycles simulated 801system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 802system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 803system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss 804system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed 805system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered 806system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken 807system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked 808system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing 809system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked 810system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 811system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps 812system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions 813system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR 814system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched 815system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed 816system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) 817system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) 818system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) 819system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 820system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) 821system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) 822system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) 823system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) 824system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) 825system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) 826system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) 827system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) 828system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) 829system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 830system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 831system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 832system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) 833system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle 834system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle 835system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle 836system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked 837system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running 838system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking 839system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing 840system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch 841system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction 842system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode 843system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode 844system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing 845system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle 846system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking 847system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst 848system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running 849system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking 850system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename 851system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full 852system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full 853system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full 854system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed 855system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made 856system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups 857system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups 858system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed 859system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing 860system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed 861system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed 862system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer 863system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. 864system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. 865system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. 866system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. 867system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) 868system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ 869system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued 870system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued 871system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling 872system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph 873system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed 874system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle 875system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle 876system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle 877system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 878system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle 879system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle 880system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle 881system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle 882system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle 883system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle 884system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle 885system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle 886system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle 887system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 888system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 889system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 890system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle 891system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 892system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available 893system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available 894system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available 895system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available 896system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available 897system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available 898system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available 899system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available 900system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available 901system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available 902system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available 903system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available 904system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available 905system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available 906system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available 907system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available 908system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available 909system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available 910system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available 911system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available 912system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available 913system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available 914system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available 915system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available 916system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available 917system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available 918system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available 919system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available 920system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available 921system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available 922system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available 923system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 924system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 925system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued 926system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued 927system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued 928system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued 929system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued 930system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued 931system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued 932system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued 933system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued 934system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued 935system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued 936system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued 937system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued 938system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued 939system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued 940system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued 941system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued 942system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued 943system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued 944system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued 945system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued 946system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued 947system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued 948system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued 949system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued 950system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued 951system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued 952system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued 953system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued 954system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued 955system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued 956system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued 957system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued 958system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 959system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued 960system.cpu0.iq.rate 0.443500 # Inst issue rate 961system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested 962system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) 963system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads 964system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes 965system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses 966system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads 967system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes 968system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses 969system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses 970system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses 971system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores 972system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 973system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed 974system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed 975system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations 976system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed 977system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 978system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 979system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled 980system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked 981system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 982system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing 983system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking 984system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking 985system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ 986system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch 987system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions 988system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions 989system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions 990system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall 991system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall 992system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations 993system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly 994system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly 995system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute 996system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions 997system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed 998system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute 999system.cpu0.iew.exec_swp 0 # number of swp insts executed 1000system.cpu0.iew.exec_nop 3229636 # number of nop insts executed 1001system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed 1002system.cpu0.iew.exec_branches 8136394 # Number of branches executed 1003system.cpu0.iew.exec_stores 5837466 # Number of stores executed 1004system.cpu0.iew.exec_rate 0.440174 # Inst execution rate 1005system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit 1006system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back 1007system.cpu0.iew.wb_producers 25278333 # num instructions producing a value 1008system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value 1009system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1010system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle 1011system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back 1012system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1013system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit 1014system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards 1015system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted 1016system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle 1017system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle 1018system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle 1019system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1020system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle 1021system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle 1022system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle 1023system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle 1024system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle 1025system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle 1026system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle 1027system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle 1028system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle 1029system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1030system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1031system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1032system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle 1033system.cpu0.commit.committedInsts 51248256 # Number of instructions committed 1034system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed 1035system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 1036system.cpu0.commit.refs 13810671 # Number of memory references committed 1037system.cpu0.commit.loads 8171492 # Number of loads committed 1038system.cpu0.commit.membars 199624 # Number of memory barriers committed 1039system.cpu0.commit.branches 7741114 # Number of branches committed 1040system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. 1041system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. 1042system.cpu0.commit.function_calls 657479 # Number of function calls committed. 1043system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction 1044system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction 1045system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction 1046system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction 1047system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction 1048system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction 1049system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction 1050system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction 1051system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction 1052system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction 1053system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction 1054system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction 1055system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction 1056system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction 1057system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction 1058system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction 1059system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction 1060system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction 1061system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction 1062system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction 1063system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction 1064system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction 1065system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction 1066system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction 1067system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction 1068system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction 1069system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction 1070system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction 1071system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction 1072system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction 1073system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction 1074system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction 1075system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction 1076system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1077system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction 1078system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached 1079system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 1080system.cpu0.rob.rob_reads 130790454 # The number of ROB reads 1081system.cpu0.rob.rob_writes 116222813 # The number of ROB writes 1082system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself 1083system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling 1084system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1085system.cpu0.committedInsts 48300626 # Number of Instructions Simulated 1086system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated 1087system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction 1088system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads 1089system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle 1090system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads 1091system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads 1092system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes 1093system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads 1094system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes 1095system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads 1096system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes 1097system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1098system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1099system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1100system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1101system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1102system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1103system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1104system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1105system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1106system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1107system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1108system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1109system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1110system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1111system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1112system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1113system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1114system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1115system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1116system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1117system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1118system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1119system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1120system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1121system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1122system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1123system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1124system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1125system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1126system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1127system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1128system.toL2Bus.throughput 111416521 # Throughput (bytes/s) 1129system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution 1130system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution 1131system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution 1132system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution 1133system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution 1134system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution 1135system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution 1136system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution 1137system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution 1138system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution 1139system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution 1140system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) 1141system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) 1142system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) 1143system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) 1144system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) 1145system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) 1146system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) 1147system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) 1148system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) 1149system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) 1150system.toL2Bus.data_through_bus 210926490 # Total data (bytes) 1151system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) 1152system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) 1153system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 1154system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) 1155system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1156system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) 1157system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1158system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) 1159system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1160system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) 1161system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1162system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) 1163system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1164system.iobus.throughput 1435370 # Throughput (bytes/s) 1165system.iobus.trans_dist::ReadReq 7369 # Transaction distribution 1166system.iobus.trans_dist::ReadResp 7369 # Transaction distribution 1167system.iobus.trans_dist::WriteReq 54591 # Transaction distribution 1168system.iobus.trans_dist::WriteResp 54591 # Transaction distribution 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) 1185system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.data_through_bus 2735314 # Total data (bytes) 1202system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) 1203system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 1205system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1207system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1209system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1211system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1213system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) 1215system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1217system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1219system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1220system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1221system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1223system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1224system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) 1225system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1226system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1227system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1228system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) 1229system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1230system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) 1231system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1232system.cpu0.icache.tags.replacements 881127 # number of replacements 1233system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use 1234system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. 1235system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. 1236system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. 1237system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. 1238system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor 1239system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy 1240system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy 1241system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 1242system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 1243system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id 1244system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id 1245system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1246system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 1247system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses 1248system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses 1249system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits 1250system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits 1251system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits 1252system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits 1253system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits 1254system.cpu0.icache.overall_hits::total 6795719 # number of overall hits 1255system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses 1256system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses 1257system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses 1258system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses 1259system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses 1260system.cpu0.icache.overall_misses::total 926821 # number of overall misses 1261system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles 1262system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles 1263system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles 1264system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles 1265system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles 1266system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles 1267system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) 1268system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) 1269system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses 1270system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses 1271system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses 1272system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses 1273system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses 1274system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses 1275system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses 1276system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses 1277system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses 1278system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses 1279system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency 1280system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency 1281system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency 1282system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency 1283system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency 1284system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency 1285system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked 1286system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked 1287system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked 1288system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked 1289system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked 1290system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked 1291system.cpu0.icache.fast_writes 0 # number of fast writes performed 1292system.cpu0.icache.cache_copies 0 # number of cache copies performed 1293system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits 1294system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits 1295system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits 1296system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits 1297system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits 1298system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits 1299system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses 1300system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses 1301system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses 1302system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses 1303system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses 1304system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses 1305system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles 1306system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles 1307system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles 1308system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles 1309system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles 1310system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles 1311system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses 1312system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses 1313system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses 1314system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses 1315system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses 1316system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses 1317system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency 1318system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency 1319system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency 1320system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency 1321system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency 1322system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency 1323system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1324system.cpu0.dcache.tags.replacements 1281204 # number of replacements 1325system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use 1326system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. 1327system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. 1328system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. 1329system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. 1330system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor 1331system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy 1332system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy 1333system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1334system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 1335system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 1336system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 1337system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1338system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses 1339system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses 1340system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits 1341system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits 1342system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits 1343system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits 1344system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits 1345system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits 1346system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits 1347system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits 1348system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits 1349system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits 1350system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits 1351system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits 1352system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses 1353system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses 1354system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses 1355system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses 1356system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses 1357system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses 1358system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses 1359system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses 1360system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses 1361system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses 1362system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses 1363system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses 1364system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles 1365system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles 1366system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles 1367system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles 1368system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles 1369system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles 1370system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles 1371system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles 1372system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles 1373system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles 1374system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles 1375system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles 1376system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) 1377system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) 1378system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) 1379system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) 1380system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) 1381system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) 1382system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) 1383system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) 1384system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses 1385system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses 1386system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses 1387system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses 1388system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses 1389system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses 1390system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses 1391system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses 1392system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses 1393system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses 1394system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses 1395system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses 1396system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses 1397system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses 1398system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses 1399system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses 1400system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency 1401system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency 1402system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency 1403system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency 1404system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency 1405system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency 1406system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency 1407system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency 1408system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency 1409system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency 1410system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency 1411system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency 1412system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked 1413system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked 1414system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked 1415system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 1416system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked 1417system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked 1418system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1419system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1420system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks 1421system.cpu0.dcache.writebacks::total 754427 # number of writebacks 1422system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits 1423system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits 1424system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits 1425system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits 1426system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits 1427system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits 1428system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits 1429system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits 1430system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits 1431system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits 1432system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses 1433system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses 1434system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses 1435system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses 1436system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses 1437system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses 1438system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses 1439system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses 1440system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses 1441system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses 1442system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses 1443system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses 1444system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles 1445system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles 1446system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles 1447system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles 1448system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles 1449system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles 1450system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles 1451system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles 1452system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles 1453system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles 1454system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles 1455system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles 1456system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles 1457system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles 1458system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles 1459system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles 1460system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles 1461system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles 1462system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses 1463system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses 1464system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses 1465system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses 1466system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses 1467system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses 1468system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses 1469system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses 1470system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses 1471system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses 1472system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses 1473system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses 1474system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency 1475system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency 1476system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency 1477system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency 1478system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency 1479system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency 1480system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency 1481system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency 1482system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency 1483system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency 1484system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency 1485system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency 1486system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1487system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1488system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1489system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1490system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1491system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1492system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1493system.cpu1.branchPred.lookups 2485884 # Number of BP lookups 1494system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted 1495system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect 1496system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups 1497system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits 1498system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1499system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage 1500system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. 1501system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. 1502system.cpu1.dtb.fetch_hits 0 # ITB hits 1503system.cpu1.dtb.fetch_misses 0 # ITB misses 1504system.cpu1.dtb.fetch_acv 0 # ITB acv 1505system.cpu1.dtb.fetch_accesses 0 # ITB accesses 1506system.cpu1.dtb.read_hits 1846757 # DTB read hits 1507system.cpu1.dtb.read_misses 10485 # DTB read misses 1508system.cpu1.dtb.read_acv 25 # DTB read access violations 1509system.cpu1.dtb.read_accesses 320297 # DTB read accesses 1510system.cpu1.dtb.write_hits 1188866 # DTB write hits 1511system.cpu1.dtb.write_misses 1998 # DTB write misses 1512system.cpu1.dtb.write_acv 67 # DTB write access violations 1513system.cpu1.dtb.write_accesses 130212 # DTB write accesses 1514system.cpu1.dtb.data_hits 3035623 # DTB hits 1515system.cpu1.dtb.data_misses 12483 # DTB misses 1516system.cpu1.dtb.data_acv 92 # DTB access violations 1517system.cpu1.dtb.data_accesses 450509 # DTB accesses 1518system.cpu1.itb.fetch_hits 420713 # ITB hits 1519system.cpu1.itb.fetch_misses 6600 # ITB misses 1520system.cpu1.itb.fetch_acv 223 # ITB acv 1521system.cpu1.itb.fetch_accesses 427313 # ITB accesses 1522system.cpu1.itb.read_hits 0 # DTB read hits 1523system.cpu1.itb.read_misses 0 # DTB read misses 1524system.cpu1.itb.read_acv 0 # DTB read access violations 1525system.cpu1.itb.read_accesses 0 # DTB read accesses 1526system.cpu1.itb.write_hits 0 # DTB write hits 1527system.cpu1.itb.write_misses 0 # DTB write misses 1528system.cpu1.itb.write_acv 0 # DTB write access violations 1529system.cpu1.itb.write_accesses 0 # DTB write accesses 1530system.cpu1.itb.data_hits 0 # DTB hits 1531system.cpu1.itb.data_misses 0 # DTB misses 1532system.cpu1.itb.data_acv 0 # DTB access violations 1533system.cpu1.itb.data_accesses 0 # DTB accesses 1534system.cpu1.numCycles 14964653 # number of cpu cycles simulated 1535system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1536system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1537system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss 1538system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed 1539system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered 1540system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken 1541system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked 1542system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing 1543system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked 1544system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1545system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps 1546system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions 1547system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR 1548system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched 1549system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed 1550system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) 1551system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) 1552system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) 1553system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1554system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) 1555system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) 1556system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) 1557system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) 1558system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) 1559system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) 1560system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) 1561system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) 1562system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) 1563system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1564system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1565system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1566system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) 1567system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle 1568system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle 1569system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle 1570system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked 1571system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running 1572system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking 1573system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing 1574system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch 1575system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction 1576system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode 1577system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode 1578system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing 1579system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle 1580system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking 1581system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst 1582system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running 1583system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking 1584system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename 1585system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full 1586system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full 1587system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full 1588system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed 1589system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made 1590system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups 1591system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups 1592system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed 1593system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing 1594system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed 1595system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed 1596system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer 1597system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. 1598system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. 1599system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. 1600system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. 1601system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) 1602system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ 1603system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued 1604system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued 1605system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling 1606system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph 1607system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed 1608system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle 1609system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle 1610system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle 1611system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1612system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle 1613system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle 1614system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle 1615system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle 1616system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle 1617system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle 1618system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle 1619system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle 1620system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle 1621system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1622system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1623system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1624system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle 1625system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1626system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available 1627system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available 1628system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available 1629system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available 1630system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available 1631system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available 1632system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available 1633system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available 1634system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available 1635system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available 1636system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available 1637system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available 1638system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available 1639system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available 1640system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available 1641system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available 1642system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available 1643system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available 1644system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available 1645system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available 1646system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available 1647system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available 1648system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available 1649system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available 1650system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available 1651system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available 1652system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available 1653system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available 1654system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available 1655system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available 1656system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available 1657system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1658system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1659system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued 1660system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued 1661system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued 1662system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued 1663system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued 1664system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued 1665system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued 1666system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued 1667system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued 1668system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued 1669system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued 1670system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued 1671system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued 1672system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued 1673system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued 1674system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued 1675system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued 1676system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued 1677system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued 1678system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued 1679system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued 1680system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued 1681system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued 1682system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued 1683system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued 1684system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued 1685system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued 1686system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued 1687system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued 1688system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued 1689system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued 1690system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued 1691system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued 1692system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1693system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued 1694system.cpu1.iq.rate 0.609525 # Inst issue rate 1695system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested 1696system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) 1697system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads 1698system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes 1699system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses 1700system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads 1701system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes 1702system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses 1703system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses 1704system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses 1705system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores 1706system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1707system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed 1708system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed 1709system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations 1710system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed 1711system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1712system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1713system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled 1714system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked 1715system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1716system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing 1717system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking 1718system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking 1719system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ 1720system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch 1721system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions 1722system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions 1723system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions 1724system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall 1725system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall 1726system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations 1727system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly 1728system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly 1729system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute 1730system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions 1731system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed 1732system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute 1733system.cpu1.iew.exec_swp 0 # number of swp insts executed 1734system.cpu1.iew.exec_nop 483081 # number of nop insts executed 1735system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed 1736system.cpu1.iew.exec_branches 1345265 # Number of branches executed 1737system.cpu1.iew.exec_stores 1196645 # Number of stores executed 1738system.cpu1.iew.exec_rate 0.603549 # Inst execution rate 1739system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit 1740system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back 1741system.cpu1.iew.wb_producers 4203498 # num instructions producing a value 1742system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value 1743system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1744system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle 1745system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back 1746system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 1747system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit 1748system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards 1749system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted 1750system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle 1751system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle 1752system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle 1753system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1754system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle 1755system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle 1756system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle 1757system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle 1758system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle 1759system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle 1760system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle 1761system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle 1762system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle 1763system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1764system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1765system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1766system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle 1767system.cpu1.commit.committedInsts 8834118 # Number of instructions committed 1768system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed 1769system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1770system.cpu1.commit.refs 2811640 # Number of memory references committed 1771system.cpu1.commit.loads 1676136 # Number of loads committed 1772system.cpu1.commit.membars 41495 # Number of memory barriers committed 1773system.cpu1.commit.branches 1262292 # Number of branches committed 1774system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. 1775system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. 1776system.cpu1.commit.function_calls 139415 # Number of function calls committed. 1777system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction 1778system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction 1779system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction 1780system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction 1781system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction 1782system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction 1783system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction 1784system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction 1785system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction 1786system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction 1787system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction 1788system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction 1789system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction 1790system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction 1791system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction 1792system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction 1793system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction 1794system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction 1795system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction 1796system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction 1797system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction 1798system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction 1799system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction 1800system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction 1801system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction 1802system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction 1803system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction 1804system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction 1805system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction 1806system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction 1807system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction 1808system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction 1809system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction 1810system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1811system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction 1812system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached 1813system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1814system.cpu1.rob.rob_reads 23736453 # The number of ROB reads 1815system.cpu1.rob.rob_writes 20710450 # The number of ROB writes 1816system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself 1817system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling 1818system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1819system.cpu1.committedInsts 8410372 # Number of Instructions Simulated 1820system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated 1821system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction 1822system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads 1823system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle 1824system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads 1825system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads 1826system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes 1827system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads 1828system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes 1829system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads 1830system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes 1831system.cpu1.icache.tags.replacements 210820 # number of replacements 1832system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use 1833system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. 1834system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. 1835system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. 1836system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. 1837system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor 1838system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy 1839system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy 1840system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1841system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id 1842system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1843system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses 1844system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses 1845system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits 1846system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits 1847system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits 1848system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits 1849system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits 1850system.cpu1.icache.overall_hits::total 1201520 # number of overall hits 1851system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses 1852system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses 1853system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses 1854system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses 1855system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses 1856system.cpu1.icache.overall_misses::total 219211 # number of overall misses 1857system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles 1858system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles 1859system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles 1860system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles 1861system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles 1862system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles 1863system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) 1864system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) 1865system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses 1866system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses 1867system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses 1868system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses 1869system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses 1870system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses 1871system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses 1872system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses 1873system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses 1874system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses 1875system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency 1876system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency 1877system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency 1878system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency 1879system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency 1880system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency 1881system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked 1882system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1883system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked 1884system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1885system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked 1886system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1887system.cpu1.icache.fast_writes 0 # number of fast writes performed 1888system.cpu1.icache.cache_copies 0 # number of cache copies performed 1889system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits 1890system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits 1891system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits 1892system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits 1893system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits 1894system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits 1895system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses 1896system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses 1897system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses 1898system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses 1899system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses 1900system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses 1901system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles 1902system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles 1903system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles 1904system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles 1905system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles 1906system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles 1907system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses 1908system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses 1909system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses 1910system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses 1911system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses 1912system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses 1913system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency 1914system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency 1915system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency 1917system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency 1919system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1920system.cpu1.dcache.tags.replacements 102235 # number of replacements 1921system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use 1922system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. 1923system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. 1924system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. 1925system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. 1926system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor 1927system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy 1928system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy 1929system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id 1930system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id 1931system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id 1932system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses 1933system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses 1934system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits 1935system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits 1936system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits 1937system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits 1938system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits 1939system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits 1940system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits 1941system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits 1942system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits 1943system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits 1944system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits 1945system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits 1946system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses 1947system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses 1948system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses 1949system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses 1950system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses 1951system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses 1952system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses 1953system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses 1954system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses 1955system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses 1956system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses 1957system.cpu1.dcache.overall_misses::total 403088 # number of overall misses 1958system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles 1959system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles 1960system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles 1961system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles 1962system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles 1963system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles 1964system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles 1965system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles 1966system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles 1967system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles 1968system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles 1969system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles 1970system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses) 1971system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses) 1972system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses) 1973system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses) 1974system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses) 1975system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses) 1976system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses) 1977system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses) 1978system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses 1979system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses 1980system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses 1981system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses 1982system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses 1983system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses 1984system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses 1985system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses 1986system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses 1987system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses 1988system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses 1989system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses 1990system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses 1991system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses 1992system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses 1993system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses 1994system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency 1995system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency 1996system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency 1997system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency 1998system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency 1999system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency 2000system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency 2001system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency 2002system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency 2003system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency 2004system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency 2005system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency 2006system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked 2007system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2008system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked 2009system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2010system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked 2011system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2012system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2013system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2014system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks 2015system.cpu1.dcache.writebacks::total 67781 # number of writebacks 2016system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits 2017system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits 2018system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits 2019system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits 2020system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits 2021system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits 2022system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits 2023system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits 2024system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits 2025system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits 2026system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses 2027system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses 2028system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses 2029system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses 2030system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses 2031system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses 2032system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses 2033system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses 2034system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses 2035system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses 2036system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses 2037system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses 2038system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles 2039system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles 2040system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles 2041system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles 2042system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles 2043system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles 2044system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles 2045system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles 2046system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles 2047system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles 2048system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles 2049system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles 2050system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles 2051system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles 2052system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles 2053system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles 2054system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles 2055system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles 2056system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses 2057system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses 2058system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses 2059system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses 2060system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses 2061system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses 2062system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses 2063system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses 2064system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses 2065system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses 2066system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses 2067system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses 2068system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency 2069system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency 2070system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency 2071system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency 2072system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency 2073system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency 2074system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency 2075system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency 2076system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency 2077system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency 2078system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency 2079system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency 2080system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2081system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2082system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2083system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2084system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2085system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2086system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2087system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2088system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed 2089system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed 2090system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl 2091system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl 2092system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl 2093system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl 2094system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl 2095system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl 2096system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl 2097system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl 2098system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl 2099system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl 2100system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl 2101system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl 2102system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl 2103system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl 2104system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl 2105system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl 2106system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl 2107system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl 2108system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl 2109system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2110system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2111system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2112system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl 2113system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl 2114system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed 2115system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed 2116system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed 2117system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed 2118system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed 2119system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed 2120system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed 2121system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed 2122system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed 2123system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed 2124system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed 2125system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed 2126system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed 2127system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed 2128system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed 2129system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed 2130system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed 2131system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed 2132system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed 2133system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed 2134system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed 2135system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed 2136system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed 2137system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed 2138system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed 2139system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed 2140system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed 2141system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed 2142system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed 2143system.cpu0.kern.syscall::total 211 # number of syscalls executed 2144system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2145system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed 2146system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed 2147system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed 2148system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed 2149system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed 2150system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed 2151system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed 2152system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed 2153system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed 2154system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed 2155system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed 2156system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed 2157system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed 2158system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed 2159system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed 2160system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed 2161system.cpu0.kern.callpal::total 169959 # number of callpals executed 2162system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches 2163system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches 2164system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2165system.cpu0.kern.mode_good::kernel 1286 2166system.cpu0.kern.mode_good::user 1287 2167system.cpu0.kern.mode_good::idle 0 2168system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches 2169system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2170system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2171system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches 2172system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode 2173system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode 2174system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2175system.cpu0.kern.swap_context 3530 # number of times the context was actually changed 2176system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2177system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed 2178system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed 2179system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl 2180system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl 2181system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl 2182system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl 2183system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl 2184system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl 2185system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl 2186system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl 2187system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl 2188system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl 2189system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl 2190system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl 2191system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl 2192system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl 2193system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl 2194system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl 2195system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2196system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2197system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl 2198system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl 2199system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed 2200system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed 2201system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed 2202system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed 2203system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed 2204system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed 2205system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed 2206system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed 2207system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed 2208system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed 2209system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed 2210system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed 2211system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed 2212system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed 2213system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed 2214system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed 2215system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed 2216system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed 2217system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed 2218system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed 2219system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed 2220system.cpu1.kern.syscall::total 115 # number of syscalls executed 2221system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2222system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed 2223system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed 2224system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed 2225system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed 2226system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed 2227system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed 2228system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed 2229system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed 2230system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed 2231system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed 2232system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed 2233system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed 2234system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed 2235system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed 2236system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed 2237system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2238system.cpu1.kern.callpal::total 48076 # number of callpals executed 2239system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches 2240system.cpu1.kern.mode_switch::user 460 # number of protection mode switches 2241system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches 2242system.cpu1.kern.mode_good::kernel 662 2243system.cpu1.kern.mode_good::user 460 2244system.cpu1.kern.mode_good::idle 202 2245system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches 2246system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2247system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches 2248system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches 2249system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode 2250system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode 2251system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode 2252system.cpu1.kern.swap_context 1068 # number of times the context was actually changed 2253 2254---------- End Simulation Statistics ---------- 2255