config.ini revision 9924
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14cache_line_size=64 15clk_domain=system.clk_domain 16console=/dist/m5/system/binaries/console 17init_param=0 18kernel=/dist/m5/system/binaries/vmlinux 19load_addr_mask=1099511627775 20mem_mode=timing 21mem_ranges=0:134217727 22memories=system.physmem 23num_work_ids=16 24pal=/dist/m5/system/binaries/ts_osfpal 25readfile=tests/halt.sh 26symbolfile= 27system_rev=1024 28system_type=34 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.bridge] 39type=Bridge 40clk_domain=system.clk_domain 41delay=50000 42ranges=8796093022208:18446744073709551615 43req_size=16 44resp_size=16 45master=system.iobus.slave[0] 46slave=system.membus.master[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51voltage_domain=system.voltage_domain 52 53[system.cpu0] 54type=DerivO3CPU 55children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 56LFSTSize=1024 57LQEntries=32 58LSQCheckLoads=true 59LSQDepCheckShift=4 60SQEntries=32 61SSITSize=1024 62activity=0 63backComSize=5 64branchPred=system.cpu0.branchPred 65cachePorts=200 66checker=Null 67clk_domain=system.cpu_clk_domain 68commitToDecodeDelay=1 69commitToFetchDelay=1 70commitToIEWDelay=1 71commitToRenameDelay=1 72commitWidth=8 73cpu_id=0 74decodeToFetchDelay=1 75decodeToRenameDelay=1 76decodeWidth=8 77dispatchWidth=8 78do_checkpoint_insts=true 79do_quiesce=true 80do_statistics_insts=true 81dtb=system.cpu0.dtb 82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu0.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu0.interrupts 94isa=system.cpu0.isa 95issueToExecuteDelay=1 96issueWidth=8 97itb=system.cpu0.itb 98max_insts_all_threads=0 99max_insts_any_thread=0 100max_loads_all_threads=0 101max_loads_any_thread=0 102needsTSO=false 103numIQEntries=64 104numPhysCCRegs=0 105numPhysFloatRegs=256 106numPhysIntRegs=256 107numROBEntries=192 108numRobs=1 109numThreads=1 110profile=0 111progress_interval=0 112renameToDecodeDelay=1 113renameToFetchDelay=1 114renameToIEWDelay=2 115renameToROBDelay=1 116renameWidth=8 117simpoint_start_insts= 118smtCommitPolicy=RoundRobin 119smtFetchPolicy=SingleThread 120smtIQPolicy=Partitioned 121smtIQThreshold=100 122smtLSQPolicy=Partitioned 123smtLSQThreshold=100 124smtNumFetchingThreads=1 125smtROBPolicy=Partitioned 126smtROBThreshold=100 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu0.tracer 132trapLatency=13 133wbDepth=1 134wbWidth=8 135workload= 136dcache_port=system.cpu0.dcache.cpu_side 137icache_port=system.cpu0.icache.cpu_side 138 139[system.cpu0.branchPred] 140type=BranchPredictor 141BTBEntries=4096 142BTBTagSize=16 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153predType=tournament 154 155[system.cpu0.dcache] 156type=BaseCache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=4 160clk_domain=system.cpu_clk_domain 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169size=32768 170system=system 171tags=system.cpu0.dcache.tags 172tgts_per_mshr=20 173two_queue=false 174write_buffers=8 175cpu_side=system.cpu0.dcache_port 176mem_side=system.toL2Bus.slave[1] 177 178[system.cpu0.dcache.tags] 179type=LRU 180assoc=4 181block_size=64 182clk_domain=system.cpu_clk_domain 183hit_latency=2 184size=32768 185 186[system.cpu0.dtb] 187type=AlphaTLB 188size=64 189 190[system.cpu0.fuPool] 191type=FUPool 192children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 193FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 194 195[system.cpu0.fuPool.FUList0] 196type=FUDesc 197children=opList 198count=6 199opList=system.cpu0.fuPool.FUList0.opList 200 201[system.cpu0.fuPool.FUList0.opList] 202type=OpDesc 203issueLat=1 204opClass=IntAlu 205opLat=1 206 207[system.cpu0.fuPool.FUList1] 208type=FUDesc 209children=opList0 opList1 210count=2 211opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 212 213[system.cpu0.fuPool.FUList1.opList0] 214type=OpDesc 215issueLat=1 216opClass=IntMult 217opLat=3 218 219[system.cpu0.fuPool.FUList1.opList1] 220type=OpDesc 221issueLat=19 222opClass=IntDiv 223opLat=20 224 225[system.cpu0.fuPool.FUList2] 226type=FUDesc 227children=opList0 opList1 opList2 228count=4 229opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 230 231[system.cpu0.fuPool.FUList2.opList0] 232type=OpDesc 233issueLat=1 234opClass=FloatAdd 235opLat=2 236 237[system.cpu0.fuPool.FUList2.opList1] 238type=OpDesc 239issueLat=1 240opClass=FloatCmp 241opLat=2 242 243[system.cpu0.fuPool.FUList2.opList2] 244type=OpDesc 245issueLat=1 246opClass=FloatCvt 247opLat=2 248 249[system.cpu0.fuPool.FUList3] 250type=FUDesc 251children=opList0 opList1 opList2 252count=2 253opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 254 255[system.cpu0.fuPool.FUList3.opList0] 256type=OpDesc 257issueLat=1 258opClass=FloatMult 259opLat=4 260 261[system.cpu0.fuPool.FUList3.opList1] 262type=OpDesc 263issueLat=12 264opClass=FloatDiv 265opLat=12 266 267[system.cpu0.fuPool.FUList3.opList2] 268type=OpDesc 269issueLat=24 270opClass=FloatSqrt 271opLat=24 272 273[system.cpu0.fuPool.FUList4] 274type=FUDesc 275children=opList 276count=0 277opList=system.cpu0.fuPool.FUList4.opList 278 279[system.cpu0.fuPool.FUList4.opList] 280type=OpDesc 281issueLat=1 282opClass=MemRead 283opLat=1 284 285[system.cpu0.fuPool.FUList5] 286type=FUDesc 287children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 288count=4 289opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 290 291[system.cpu0.fuPool.FUList5.opList00] 292type=OpDesc 293issueLat=1 294opClass=SimdAdd 295opLat=1 296 297[system.cpu0.fuPool.FUList5.opList01] 298type=OpDesc 299issueLat=1 300opClass=SimdAddAcc 301opLat=1 302 303[system.cpu0.fuPool.FUList5.opList02] 304type=OpDesc 305issueLat=1 306opClass=SimdAlu 307opLat=1 308 309[system.cpu0.fuPool.FUList5.opList03] 310type=OpDesc 311issueLat=1 312opClass=SimdCmp 313opLat=1 314 315[system.cpu0.fuPool.FUList5.opList04] 316type=OpDesc 317issueLat=1 318opClass=SimdCvt 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList05] 322type=OpDesc 323issueLat=1 324opClass=SimdMisc 325opLat=1 326 327[system.cpu0.fuPool.FUList5.opList06] 328type=OpDesc 329issueLat=1 330opClass=SimdMult 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList07] 334type=OpDesc 335issueLat=1 336opClass=SimdMultAcc 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList08] 340type=OpDesc 341issueLat=1 342opClass=SimdShift 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList09] 346type=OpDesc 347issueLat=1 348opClass=SimdShiftAcc 349opLat=1 350 351[system.cpu0.fuPool.FUList5.opList10] 352type=OpDesc 353issueLat=1 354opClass=SimdSqrt 355opLat=1 356 357[system.cpu0.fuPool.FUList5.opList11] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatAdd 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList12] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatAlu 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList13] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatCmp 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList14] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatCvt 379opLat=1 380 381[system.cpu0.fuPool.FUList5.opList15] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatDiv 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList16] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatMisc 391opLat=1 392 393[system.cpu0.fuPool.FUList5.opList17] 394type=OpDesc 395issueLat=1 396opClass=SimdFloatMult 397opLat=1 398 399[system.cpu0.fuPool.FUList5.opList18] 400type=OpDesc 401issueLat=1 402opClass=SimdFloatMultAcc 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList19] 406type=OpDesc 407issueLat=1 408opClass=SimdFloatSqrt 409opLat=1 410 411[system.cpu0.fuPool.FUList6] 412type=FUDesc 413children=opList 414count=0 415opList=system.cpu0.fuPool.FUList6.opList 416 417[system.cpu0.fuPool.FUList6.opList] 418type=OpDesc 419issueLat=1 420opClass=MemWrite 421opLat=1 422 423[system.cpu0.fuPool.FUList7] 424type=FUDesc 425children=opList0 opList1 426count=4 427opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 428 429[system.cpu0.fuPool.FUList7.opList0] 430type=OpDesc 431issueLat=1 432opClass=MemRead 433opLat=1 434 435[system.cpu0.fuPool.FUList7.opList1] 436type=OpDesc 437issueLat=1 438opClass=MemWrite 439opLat=1 440 441[system.cpu0.fuPool.FUList8] 442type=FUDesc 443children=opList 444count=1 445opList=system.cpu0.fuPool.FUList8.opList 446 447[system.cpu0.fuPool.FUList8.opList] 448type=OpDesc 449issueLat=3 450opClass=IprAccess 451opLat=3 452 453[system.cpu0.icache] 454type=BaseCache 455children=tags 456addr_ranges=0:18446744073709551615 457assoc=1 458clk_domain=system.cpu_clk_domain 459forward_snoops=true 460hit_latency=2 461is_top_level=true 462max_miss_count=0 463mshrs=4 464prefetch_on_access=false 465prefetcher=Null 466response_latency=2 467size=32768 468system=system 469tags=system.cpu0.icache.tags 470tgts_per_mshr=20 471two_queue=false 472write_buffers=8 473cpu_side=system.cpu0.icache_port 474mem_side=system.toL2Bus.slave[0] 475 476[system.cpu0.icache.tags] 477type=LRU 478assoc=1 479block_size=64 480clk_domain=system.cpu_clk_domain 481hit_latency=2 482size=32768 483 484[system.cpu0.interrupts] 485type=AlphaInterrupts 486 487[system.cpu0.isa] 488type=AlphaISA 489 490[system.cpu0.itb] 491type=AlphaTLB 492size=48 493 494[system.cpu0.tracer] 495type=ExeTracer 496 497[system.cpu1] 498type=DerivO3CPU 499children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 500LFSTSize=1024 501LQEntries=32 502LSQCheckLoads=true 503LSQDepCheckShift=4 504SQEntries=32 505SSITSize=1024 506activity=0 507backComSize=5 508branchPred=system.cpu1.branchPred 509cachePorts=200 510checker=Null 511clk_domain=system.cpu_clk_domain 512commitToDecodeDelay=1 513commitToFetchDelay=1 514commitToIEWDelay=1 515commitToRenameDelay=1 516commitWidth=8 517cpu_id=1 518decodeToFetchDelay=1 519decodeToRenameDelay=1 520decodeWidth=8 521dispatchWidth=8 522do_checkpoint_insts=true 523do_quiesce=true 524do_statistics_insts=true 525dtb=system.cpu1.dtb 526fetchToDecodeDelay=1 527fetchTrapLatency=1 528fetchWidth=8 529forwardComSize=5 530fuPool=system.cpu1.fuPool 531function_trace=false 532function_trace_start=0 533iewToCommitDelay=1 534iewToDecodeDelay=1 535iewToFetchDelay=1 536iewToRenameDelay=1 537interrupts=system.cpu1.interrupts 538isa=system.cpu1.isa 539issueToExecuteDelay=1 540issueWidth=8 541itb=system.cpu1.itb 542max_insts_all_threads=0 543max_insts_any_thread=0 544max_loads_all_threads=0 545max_loads_any_thread=0 546needsTSO=false 547numIQEntries=64 548numPhysCCRegs=0 549numPhysFloatRegs=256 550numPhysIntRegs=256 551numROBEntries=192 552numRobs=1 553numThreads=1 554profile=0 555progress_interval=0 556renameToDecodeDelay=1 557renameToFetchDelay=1 558renameToIEWDelay=2 559renameToROBDelay=1 560renameWidth=8 561simpoint_start_insts= 562smtCommitPolicy=RoundRobin 563smtFetchPolicy=SingleThread 564smtIQPolicy=Partitioned 565smtIQThreshold=100 566smtLSQPolicy=Partitioned 567smtLSQThreshold=100 568smtNumFetchingThreads=1 569smtROBPolicy=Partitioned 570smtROBThreshold=100 571squashWidth=8 572store_set_clear_period=250000 573switched_out=false 574system=system 575tracer=system.cpu1.tracer 576trapLatency=13 577wbDepth=1 578wbWidth=8 579workload= 580dcache_port=system.cpu1.dcache.cpu_side 581icache_port=system.cpu1.icache.cpu_side 582 583[system.cpu1.branchPred] 584type=BranchPredictor 585BTBEntries=4096 586BTBTagSize=16 587RASSize=16 588choiceCtrBits=2 589choicePredictorSize=8192 590globalCtrBits=2 591globalPredictorSize=8192 592instShiftAmt=2 593localCtrBits=2 594localHistoryTableSize=2048 595localPredictorSize=2048 596numThreads=1 597predType=tournament 598 599[system.cpu1.dcache] 600type=BaseCache 601children=tags 602addr_ranges=0:18446744073709551615 603assoc=4 604clk_domain=system.cpu_clk_domain 605forward_snoops=true 606hit_latency=2 607is_top_level=true 608max_miss_count=0 609mshrs=4 610prefetch_on_access=false 611prefetcher=Null 612response_latency=2 613size=32768 614system=system 615tags=system.cpu1.dcache.tags 616tgts_per_mshr=20 617two_queue=false 618write_buffers=8 619cpu_side=system.cpu1.dcache_port 620mem_side=system.toL2Bus.slave[3] 621 622[system.cpu1.dcache.tags] 623type=LRU 624assoc=4 625block_size=64 626clk_domain=system.cpu_clk_domain 627hit_latency=2 628size=32768 629 630[system.cpu1.dtb] 631type=AlphaTLB 632size=64 633 634[system.cpu1.fuPool] 635type=FUPool 636children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 637FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 638 639[system.cpu1.fuPool.FUList0] 640type=FUDesc 641children=opList 642count=6 643opList=system.cpu1.fuPool.FUList0.opList 644 645[system.cpu1.fuPool.FUList0.opList] 646type=OpDesc 647issueLat=1 648opClass=IntAlu 649opLat=1 650 651[system.cpu1.fuPool.FUList1] 652type=FUDesc 653children=opList0 opList1 654count=2 655opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 656 657[system.cpu1.fuPool.FUList1.opList0] 658type=OpDesc 659issueLat=1 660opClass=IntMult 661opLat=3 662 663[system.cpu1.fuPool.FUList1.opList1] 664type=OpDesc 665issueLat=19 666opClass=IntDiv 667opLat=20 668 669[system.cpu1.fuPool.FUList2] 670type=FUDesc 671children=opList0 opList1 opList2 672count=4 673opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 674 675[system.cpu1.fuPool.FUList2.opList0] 676type=OpDesc 677issueLat=1 678opClass=FloatAdd 679opLat=2 680 681[system.cpu1.fuPool.FUList2.opList1] 682type=OpDesc 683issueLat=1 684opClass=FloatCmp 685opLat=2 686 687[system.cpu1.fuPool.FUList2.opList2] 688type=OpDesc 689issueLat=1 690opClass=FloatCvt 691opLat=2 692 693[system.cpu1.fuPool.FUList3] 694type=FUDesc 695children=opList0 opList1 opList2 696count=2 697opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 698 699[system.cpu1.fuPool.FUList3.opList0] 700type=OpDesc 701issueLat=1 702opClass=FloatMult 703opLat=4 704 705[system.cpu1.fuPool.FUList3.opList1] 706type=OpDesc 707issueLat=12 708opClass=FloatDiv 709opLat=12 710 711[system.cpu1.fuPool.FUList3.opList2] 712type=OpDesc 713issueLat=24 714opClass=FloatSqrt 715opLat=24 716 717[system.cpu1.fuPool.FUList4] 718type=FUDesc 719children=opList 720count=0 721opList=system.cpu1.fuPool.FUList4.opList 722 723[system.cpu1.fuPool.FUList4.opList] 724type=OpDesc 725issueLat=1 726opClass=MemRead 727opLat=1 728 729[system.cpu1.fuPool.FUList5] 730type=FUDesc 731children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 732count=4 733opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 734 735[system.cpu1.fuPool.FUList5.opList00] 736type=OpDesc 737issueLat=1 738opClass=SimdAdd 739opLat=1 740 741[system.cpu1.fuPool.FUList5.opList01] 742type=OpDesc 743issueLat=1 744opClass=SimdAddAcc 745opLat=1 746 747[system.cpu1.fuPool.FUList5.opList02] 748type=OpDesc 749issueLat=1 750opClass=SimdAlu 751opLat=1 752 753[system.cpu1.fuPool.FUList5.opList03] 754type=OpDesc 755issueLat=1 756opClass=SimdCmp 757opLat=1 758 759[system.cpu1.fuPool.FUList5.opList04] 760type=OpDesc 761issueLat=1 762opClass=SimdCvt 763opLat=1 764 765[system.cpu1.fuPool.FUList5.opList05] 766type=OpDesc 767issueLat=1 768opClass=SimdMisc 769opLat=1 770 771[system.cpu1.fuPool.FUList5.opList06] 772type=OpDesc 773issueLat=1 774opClass=SimdMult 775opLat=1 776 777[system.cpu1.fuPool.FUList5.opList07] 778type=OpDesc 779issueLat=1 780opClass=SimdMultAcc 781opLat=1 782 783[system.cpu1.fuPool.FUList5.opList08] 784type=OpDesc 785issueLat=1 786opClass=SimdShift 787opLat=1 788 789[system.cpu1.fuPool.FUList5.opList09] 790type=OpDesc 791issueLat=1 792opClass=SimdShiftAcc 793opLat=1 794 795[system.cpu1.fuPool.FUList5.opList10] 796type=OpDesc 797issueLat=1 798opClass=SimdSqrt 799opLat=1 800 801[system.cpu1.fuPool.FUList5.opList11] 802type=OpDesc 803issueLat=1 804opClass=SimdFloatAdd 805opLat=1 806 807[system.cpu1.fuPool.FUList5.opList12] 808type=OpDesc 809issueLat=1 810opClass=SimdFloatAlu 811opLat=1 812 813[system.cpu1.fuPool.FUList5.opList13] 814type=OpDesc 815issueLat=1 816opClass=SimdFloatCmp 817opLat=1 818 819[system.cpu1.fuPool.FUList5.opList14] 820type=OpDesc 821issueLat=1 822opClass=SimdFloatCvt 823opLat=1 824 825[system.cpu1.fuPool.FUList5.opList15] 826type=OpDesc 827issueLat=1 828opClass=SimdFloatDiv 829opLat=1 830 831[system.cpu1.fuPool.FUList5.opList16] 832type=OpDesc 833issueLat=1 834opClass=SimdFloatMisc 835opLat=1 836 837[system.cpu1.fuPool.FUList5.opList17] 838type=OpDesc 839issueLat=1 840opClass=SimdFloatMult 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList18] 844type=OpDesc 845issueLat=1 846opClass=SimdFloatMultAcc 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList19] 850type=OpDesc 851issueLat=1 852opClass=SimdFloatSqrt 853opLat=1 854 855[system.cpu1.fuPool.FUList6] 856type=FUDesc 857children=opList 858count=0 859opList=system.cpu1.fuPool.FUList6.opList 860 861[system.cpu1.fuPool.FUList6.opList] 862type=OpDesc 863issueLat=1 864opClass=MemWrite 865opLat=1 866 867[system.cpu1.fuPool.FUList7] 868type=FUDesc 869children=opList0 opList1 870count=4 871opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 872 873[system.cpu1.fuPool.FUList7.opList0] 874type=OpDesc 875issueLat=1 876opClass=MemRead 877opLat=1 878 879[system.cpu1.fuPool.FUList7.opList1] 880type=OpDesc 881issueLat=1 882opClass=MemWrite 883opLat=1 884 885[system.cpu1.fuPool.FUList8] 886type=FUDesc 887children=opList 888count=1 889opList=system.cpu1.fuPool.FUList8.opList 890 891[system.cpu1.fuPool.FUList8.opList] 892type=OpDesc 893issueLat=3 894opClass=IprAccess 895opLat=3 896 897[system.cpu1.icache] 898type=BaseCache 899children=tags 900addr_ranges=0:18446744073709551615 901assoc=1 902clk_domain=system.cpu_clk_domain 903forward_snoops=true 904hit_latency=2 905is_top_level=true 906max_miss_count=0 907mshrs=4 908prefetch_on_access=false 909prefetcher=Null 910response_latency=2 911size=32768 912system=system 913tags=system.cpu1.icache.tags 914tgts_per_mshr=20 915two_queue=false 916write_buffers=8 917cpu_side=system.cpu1.icache_port 918mem_side=system.toL2Bus.slave[2] 919 920[system.cpu1.icache.tags] 921type=LRU 922assoc=1 923block_size=64 924clk_domain=system.cpu_clk_domain 925hit_latency=2 926size=32768 927 928[system.cpu1.interrupts] 929type=AlphaInterrupts 930 931[system.cpu1.isa] 932type=AlphaISA 933 934[system.cpu1.itb] 935type=AlphaTLB 936size=48 937 938[system.cpu1.tracer] 939type=ExeTracer 940 941[system.cpu_clk_domain] 942type=SrcClockDomain 943clock=500 944voltage_domain=system.voltage_domain 945 946[system.disk0] 947type=IdeDisk 948children=image 949delay=1000000 950driveID=master 951image=system.disk0.image 952 953[system.disk0.image] 954type=CowDiskImage 955children=child 956child=system.disk0.image.child 957image_file= 958read_only=false 959table_size=65536 960 961[system.disk0.image.child] 962type=RawDiskImage 963image_file=/dist/m5/system/disks/linux-latest.img 964read_only=true 965 966[system.disk2] 967type=IdeDisk 968children=image 969delay=1000000 970driveID=master 971image=system.disk2.image 972 973[system.disk2.image] 974type=CowDiskImage 975children=child 976child=system.disk2.image.child 977image_file= 978read_only=false 979table_size=65536 980 981[system.disk2.image.child] 982type=RawDiskImage 983image_file=/dist/m5/system/disks/linux-bigswap2.img 984read_only=true 985 986[system.intrctrl] 987type=IntrControl 988sys=system 989 990[system.iobus] 991type=NoncoherentBus 992clk_domain=system.clk_domain 993header_cycles=1 994use_default_range=true 995width=8 996default=system.tsunami.pciconfig.pio 997master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 998slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 999 1000[system.iocache] 1001type=BaseCache 1002children=tags 1003addr_ranges=0:134217727 1004assoc=8 1005clk_domain=system.clk_domain 1006forward_snoops=false 1007hit_latency=50 1008is_top_level=true 1009max_miss_count=0 1010mshrs=20 1011prefetch_on_access=false 1012prefetcher=Null 1013response_latency=50 1014size=1024 1015system=system 1016tags=system.iocache.tags 1017tgts_per_mshr=12 1018two_queue=false 1019write_buffers=8 1020cpu_side=system.iobus.master[29] 1021mem_side=system.membus.slave[2] 1022 1023[system.iocache.tags] 1024type=LRU 1025assoc=8 1026block_size=64 1027clk_domain=system.clk_domain 1028hit_latency=50 1029size=1024 1030 1031[system.l2c] 1032type=BaseCache 1033children=tags 1034addr_ranges=0:18446744073709551615 1035assoc=8 1036clk_domain=system.cpu_clk_domain 1037forward_snoops=true 1038hit_latency=20 1039is_top_level=false 1040max_miss_count=0 1041mshrs=20 1042prefetch_on_access=false 1043prefetcher=Null 1044response_latency=20 1045size=4194304 1046system=system 1047tags=system.l2c.tags 1048tgts_per_mshr=12 1049two_queue=false 1050write_buffers=8 1051cpu_side=system.toL2Bus.master[0] 1052mem_side=system.membus.slave[1] 1053 1054[system.l2c.tags] 1055type=LRU 1056assoc=8 1057block_size=64 1058clk_domain=system.cpu_clk_domain 1059hit_latency=20 1060size=4194304 1061 1062[system.membus] 1063type=CoherentBus 1064children=badaddr_responder 1065clk_domain=system.clk_domain 1066header_cycles=1 1067system=system 1068use_default_range=false 1069width=8 1070default=system.membus.badaddr_responder.pio 1071master=system.bridge.slave system.physmem.port 1072slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1073 1074[system.membus.badaddr_responder] 1075type=IsaFake 1076clk_domain=system.clk_domain 1077fake_mem=false 1078pio_addr=0 1079pio_latency=100000 1080pio_size=8 1081ret_bad_addr=true 1082ret_data16=65535 1083ret_data32=4294967295 1084ret_data64=18446744073709551615 1085ret_data8=255 1086system=system 1087update_data=false 1088warn_access= 1089pio=system.membus.default 1090 1091[system.physmem] 1092type=SimpleDRAM 1093activation_limit=4 1094addr_mapping=RaBaChCo 1095banks_per_rank=8 1096burst_length=8 1097channels=1 1098clk_domain=system.clk_domain 1099conf_table_reported=true 1100device_bus_width=8 1101device_rowbuffer_size=1024 1102devices_per_rank=8 1103in_addr_map=true 1104mem_sched_policy=frfcfs 1105null=false 1106page_policy=open 1107range=0:134217727 1108ranks_per_channel=2 1109read_buffer_size=32 1110static_backend_latency=10000 1111static_frontend_latency=10000 1112tBURST=5000 1113tCL=13750 1114tRCD=13750 1115tREFI=7800000 1116tRFC=300000 1117tRP=13750 1118tWTR=7500 1119tXAW=40000 1120write_buffer_size=32 1121write_thresh_perc=70 1122port=system.membus.master[1] 1123 1124[system.simple_disk] 1125type=SimpleDisk 1126children=disk 1127disk=system.simple_disk.disk 1128system=system 1129 1130[system.simple_disk.disk] 1131type=RawDiskImage 1132image_file=/dist/m5/system/disks/linux-latest.img 1133read_only=true 1134 1135[system.terminal] 1136type=Terminal 1137intr_control=system.intrctrl 1138number=0 1139output=true 1140port=3456 1141 1142[system.toL2Bus] 1143type=CoherentBus 1144clk_domain=system.cpu_clk_domain 1145header_cycles=1 1146system=system 1147use_default_range=false 1148width=8 1149master=system.l2c.cpu_side 1150slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1151 1152[system.tsunami] 1153type=Tsunami 1154children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1155intrctrl=system.intrctrl 1156system=system 1157 1158[system.tsunami.backdoor] 1159type=AlphaBackdoor 1160clk_domain=system.clk_domain 1161cpu=system.cpu0 1162disk=system.simple_disk 1163pio_addr=8804682956800 1164pio_latency=100000 1165platform=system.tsunami 1166system=system 1167terminal=system.terminal 1168pio=system.iobus.master[24] 1169 1170[system.tsunami.cchip] 1171type=TsunamiCChip 1172clk_domain=system.clk_domain 1173pio_addr=8803072344064 1174pio_latency=100000 1175system=system 1176tsunami=system.tsunami 1177pio=system.iobus.master[0] 1178 1179[system.tsunami.ethernet] 1180type=NSGigE 1181BAR0=1 1182BAR0LegacyIO=false 1183BAR0Size=256 1184BAR1=0 1185BAR1LegacyIO=false 1186BAR1Size=4096 1187BAR2=0 1188BAR2LegacyIO=false 1189BAR2Size=0 1190BAR3=0 1191BAR3LegacyIO=false 1192BAR3Size=0 1193BAR4=0 1194BAR4LegacyIO=false 1195BAR4Size=0 1196BAR5=0 1197BAR5LegacyIO=false 1198BAR5Size=0 1199BIST=0 1200CacheLineSize=0 1201CardbusCIS=0 1202ClassCode=2 1203Command=0 1204DeviceID=34 1205ExpansionROM=0 1206HeaderType=0 1207InterruptLine=30 1208InterruptPin=1 1209LatencyTimer=0 1210MaximumLatency=52 1211MinimumGrant=176 1212ProgIF=0 1213Revision=0 1214Status=656 1215SubClassCode=0 1216SubsystemID=0 1217SubsystemVendorID=0 1218VendorID=4107 1219clk_domain=system.clk_domain 1220config_latency=20000 1221dma_data_free=false 1222dma_desc_free=false 1223dma_no_allocate=true 1224dma_read_delay=0 1225dma_read_factor=0 1226dma_write_delay=0 1227dma_write_factor=0 1228hardware_address=00:90:00:00:00:01 1229intr_delay=10000000 1230pci_bus=0 1231pci_dev=1 1232pci_func=0 1233pio_latency=30000 1234platform=system.tsunami 1235rss=false 1236rx_delay=1000000 1237rx_fifo_size=524288 1238rx_filter=true 1239rx_thread=false 1240system=system 1241tx_delay=1000000 1242tx_fifo_size=524288 1243tx_thread=false 1244config=system.iobus.master[28] 1245dma=system.iobus.slave[2] 1246pio=system.iobus.master[27] 1247 1248[system.tsunami.fake_OROM] 1249type=IsaFake 1250clk_domain=system.clk_domain 1251fake_mem=false 1252pio_addr=8796093677568 1253pio_latency=100000 1254pio_size=393216 1255ret_bad_addr=false 1256ret_data16=65535 1257ret_data32=4294967295 1258ret_data64=18446744073709551615 1259ret_data8=255 1260system=system 1261update_data=false 1262warn_access= 1263pio=system.iobus.master[8] 1264 1265[system.tsunami.fake_ata0] 1266type=IsaFake 1267clk_domain=system.clk_domain 1268fake_mem=false 1269pio_addr=8804615848432 1270pio_latency=100000 1271pio_size=8 1272ret_bad_addr=false 1273ret_data16=65535 1274ret_data32=4294967295 1275ret_data64=18446744073709551615 1276ret_data8=255 1277system=system 1278update_data=false 1279warn_access= 1280pio=system.iobus.master[19] 1281 1282[system.tsunami.fake_ata1] 1283type=IsaFake 1284clk_domain=system.clk_domain 1285fake_mem=false 1286pio_addr=8804615848304 1287pio_latency=100000 1288pio_size=8 1289ret_bad_addr=false 1290ret_data16=65535 1291ret_data32=4294967295 1292ret_data64=18446744073709551615 1293ret_data8=255 1294system=system 1295update_data=false 1296warn_access= 1297pio=system.iobus.master[20] 1298 1299[system.tsunami.fake_pnp_addr] 1300type=IsaFake 1301clk_domain=system.clk_domain 1302fake_mem=false 1303pio_addr=8804615848569 1304pio_latency=100000 1305pio_size=8 1306ret_bad_addr=false 1307ret_data16=65535 1308ret_data32=4294967295 1309ret_data64=18446744073709551615 1310ret_data8=255 1311system=system 1312update_data=false 1313warn_access= 1314pio=system.iobus.master[9] 1315 1316[system.tsunami.fake_pnp_read0] 1317type=IsaFake 1318clk_domain=system.clk_domain 1319fake_mem=false 1320pio_addr=8804615848451 1321pio_latency=100000 1322pio_size=8 1323ret_bad_addr=false 1324ret_data16=65535 1325ret_data32=4294967295 1326ret_data64=18446744073709551615 1327ret_data8=255 1328system=system 1329update_data=false 1330warn_access= 1331pio=system.iobus.master[11] 1332 1333[system.tsunami.fake_pnp_read1] 1334type=IsaFake 1335clk_domain=system.clk_domain 1336fake_mem=false 1337pio_addr=8804615848515 1338pio_latency=100000 1339pio_size=8 1340ret_bad_addr=false 1341ret_data16=65535 1342ret_data32=4294967295 1343ret_data64=18446744073709551615 1344ret_data8=255 1345system=system 1346update_data=false 1347warn_access= 1348pio=system.iobus.master[12] 1349 1350[system.tsunami.fake_pnp_read2] 1351type=IsaFake 1352clk_domain=system.clk_domain 1353fake_mem=false 1354pio_addr=8804615848579 1355pio_latency=100000 1356pio_size=8 1357ret_bad_addr=false 1358ret_data16=65535 1359ret_data32=4294967295 1360ret_data64=18446744073709551615 1361ret_data8=255 1362system=system 1363update_data=false 1364warn_access= 1365pio=system.iobus.master[13] 1366 1367[system.tsunami.fake_pnp_read3] 1368type=IsaFake 1369clk_domain=system.clk_domain 1370fake_mem=false 1371pio_addr=8804615848643 1372pio_latency=100000 1373pio_size=8 1374ret_bad_addr=false 1375ret_data16=65535 1376ret_data32=4294967295 1377ret_data64=18446744073709551615 1378ret_data8=255 1379system=system 1380update_data=false 1381warn_access= 1382pio=system.iobus.master[14] 1383 1384[system.tsunami.fake_pnp_read4] 1385type=IsaFake 1386clk_domain=system.clk_domain 1387fake_mem=false 1388pio_addr=8804615848707 1389pio_latency=100000 1390pio_size=8 1391ret_bad_addr=false 1392ret_data16=65535 1393ret_data32=4294967295 1394ret_data64=18446744073709551615 1395ret_data8=255 1396system=system 1397update_data=false 1398warn_access= 1399pio=system.iobus.master[15] 1400 1401[system.tsunami.fake_pnp_read5] 1402type=IsaFake 1403clk_domain=system.clk_domain 1404fake_mem=false 1405pio_addr=8804615848771 1406pio_latency=100000 1407pio_size=8 1408ret_bad_addr=false 1409ret_data16=65535 1410ret_data32=4294967295 1411ret_data64=18446744073709551615 1412ret_data8=255 1413system=system 1414update_data=false 1415warn_access= 1416pio=system.iobus.master[16] 1417 1418[system.tsunami.fake_pnp_read6] 1419type=IsaFake 1420clk_domain=system.clk_domain 1421fake_mem=false 1422pio_addr=8804615848835 1423pio_latency=100000 1424pio_size=8 1425ret_bad_addr=false 1426ret_data16=65535 1427ret_data32=4294967295 1428ret_data64=18446744073709551615 1429ret_data8=255 1430system=system 1431update_data=false 1432warn_access= 1433pio=system.iobus.master[17] 1434 1435[system.tsunami.fake_pnp_read7] 1436type=IsaFake 1437clk_domain=system.clk_domain 1438fake_mem=false 1439pio_addr=8804615848899 1440pio_latency=100000 1441pio_size=8 1442ret_bad_addr=false 1443ret_data16=65535 1444ret_data32=4294967295 1445ret_data64=18446744073709551615 1446ret_data8=255 1447system=system 1448update_data=false 1449warn_access= 1450pio=system.iobus.master[18] 1451 1452[system.tsunami.fake_pnp_write] 1453type=IsaFake 1454clk_domain=system.clk_domain 1455fake_mem=false 1456pio_addr=8804615850617 1457pio_latency=100000 1458pio_size=8 1459ret_bad_addr=false 1460ret_data16=65535 1461ret_data32=4294967295 1462ret_data64=18446744073709551615 1463ret_data8=255 1464system=system 1465update_data=false 1466warn_access= 1467pio=system.iobus.master[10] 1468 1469[system.tsunami.fake_ppc] 1470type=IsaFake 1471clk_domain=system.clk_domain 1472fake_mem=false 1473pio_addr=8804615848891 1474pio_latency=100000 1475pio_size=8 1476ret_bad_addr=false 1477ret_data16=65535 1478ret_data32=4294967295 1479ret_data64=18446744073709551615 1480ret_data8=255 1481system=system 1482update_data=false 1483warn_access= 1484pio=system.iobus.master[7] 1485 1486[system.tsunami.fake_sm_chip] 1487type=IsaFake 1488clk_domain=system.clk_domain 1489fake_mem=false 1490pio_addr=8804615848816 1491pio_latency=100000 1492pio_size=8 1493ret_bad_addr=false 1494ret_data16=65535 1495ret_data32=4294967295 1496ret_data64=18446744073709551615 1497ret_data8=255 1498system=system 1499update_data=false 1500warn_access= 1501pio=system.iobus.master[2] 1502 1503[system.tsunami.fake_uart1] 1504type=IsaFake 1505clk_domain=system.clk_domain 1506fake_mem=false 1507pio_addr=8804615848696 1508pio_latency=100000 1509pio_size=8 1510ret_bad_addr=false 1511ret_data16=65535 1512ret_data32=4294967295 1513ret_data64=18446744073709551615 1514ret_data8=255 1515system=system 1516update_data=false 1517warn_access= 1518pio=system.iobus.master[3] 1519 1520[system.tsunami.fake_uart2] 1521type=IsaFake 1522clk_domain=system.clk_domain 1523fake_mem=false 1524pio_addr=8804615848936 1525pio_latency=100000 1526pio_size=8 1527ret_bad_addr=false 1528ret_data16=65535 1529ret_data32=4294967295 1530ret_data64=18446744073709551615 1531ret_data8=255 1532system=system 1533update_data=false 1534warn_access= 1535pio=system.iobus.master[4] 1536 1537[system.tsunami.fake_uart3] 1538type=IsaFake 1539clk_domain=system.clk_domain 1540fake_mem=false 1541pio_addr=8804615848680 1542pio_latency=100000 1543pio_size=8 1544ret_bad_addr=false 1545ret_data16=65535 1546ret_data32=4294967295 1547ret_data64=18446744073709551615 1548ret_data8=255 1549system=system 1550update_data=false 1551warn_access= 1552pio=system.iobus.master[5] 1553 1554[system.tsunami.fake_uart4] 1555type=IsaFake 1556clk_domain=system.clk_domain 1557fake_mem=false 1558pio_addr=8804615848944 1559pio_latency=100000 1560pio_size=8 1561ret_bad_addr=false 1562ret_data16=65535 1563ret_data32=4294967295 1564ret_data64=18446744073709551615 1565ret_data8=255 1566system=system 1567update_data=false 1568warn_access= 1569pio=system.iobus.master[6] 1570 1571[system.tsunami.fb] 1572type=BadDevice 1573clk_domain=system.clk_domain 1574devicename=FrameBuffer 1575pio_addr=8804615848912 1576pio_latency=100000 1577system=system 1578pio=system.iobus.master[21] 1579 1580[system.tsunami.ide] 1581type=IdeController 1582BAR0=1 1583BAR0LegacyIO=false 1584BAR0Size=8 1585BAR1=1 1586BAR1LegacyIO=false 1587BAR1Size=4 1588BAR2=1 1589BAR2LegacyIO=false 1590BAR2Size=8 1591BAR3=1 1592BAR3LegacyIO=false 1593BAR3Size=4 1594BAR4=1 1595BAR4LegacyIO=false 1596BAR4Size=16 1597BAR5=1 1598BAR5LegacyIO=false 1599BAR5Size=0 1600BIST=0 1601CacheLineSize=0 1602CardbusCIS=0 1603ClassCode=1 1604Command=0 1605DeviceID=28945 1606ExpansionROM=0 1607HeaderType=0 1608InterruptLine=31 1609InterruptPin=1 1610LatencyTimer=0 1611MaximumLatency=0 1612MinimumGrant=0 1613ProgIF=133 1614Revision=0 1615Status=640 1616SubClassCode=1 1617SubsystemID=0 1618SubsystemVendorID=0 1619VendorID=32902 1620clk_domain=system.clk_domain 1621config_latency=20000 1622ctrl_offset=0 1623disks=system.disk0 system.disk2 1624io_shift=0 1625pci_bus=0 1626pci_dev=0 1627pci_func=0 1628pio_latency=30000 1629platform=system.tsunami 1630system=system 1631config=system.iobus.master[26] 1632dma=system.iobus.slave[1] 1633pio=system.iobus.master[25] 1634 1635[system.tsunami.io] 1636type=TsunamiIO 1637clk_domain=system.clk_domain 1638frequency=976562500 1639pio_addr=8804615847936 1640pio_latency=100000 1641system=system 1642time=Thu Jan 1 00:00:00 2009 1643tsunami=system.tsunami 1644year_is_bcd=false 1645pio=system.iobus.master[22] 1646 1647[system.tsunami.pchip] 1648type=TsunamiPChip 1649clk_domain=system.clk_domain 1650pio_addr=8802535473152 1651pio_latency=100000 1652system=system 1653tsunami=system.tsunami 1654pio=system.iobus.master[1] 1655 1656[system.tsunami.pciconfig] 1657type=PciConfigAll 1658bus=0 1659clk_domain=system.clk_domain 1660pio_addr=0 1661pio_latency=30000 1662platform=system.tsunami 1663size=16777216 1664system=system 1665pio=system.iobus.default 1666 1667[system.tsunami.uart] 1668type=Uart8250 1669clk_domain=system.clk_domain 1670pio_addr=8804615848952 1671pio_latency=100000 1672platform=system.tsunami 1673system=system 1674terminal=system.terminal 1675pio=system.iobus.master[23] 1676 1677[system.voltage_domain] 1678type=VoltageDomain 1679voltage=1.000000 1680 1681