config.ini revision 9885
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14cache_line_size=64 15clk_domain=system.clk_domain 16console=/dist/m5/system/binaries/console 17init_param=0 18kernel=/dist/m5/system/binaries/vmlinux 19load_addr_mask=1099511627775 20mem_mode=timing 21mem_ranges=0:134217727 22memories=system.physmem 23num_work_ids=16 24pal=/dist/m5/system/binaries/ts_osfpal 25readfile=tests/halt.sh 26symbolfile= 27system_rev=1024 28system_type=34 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.bridge] 39type=Bridge 40clk_domain=system.clk_domain 41delay=50000 42ranges=8796093022208:18446744073709551615 43req_size=16 44resp_size=16 45master=system.iobus.slave[0] 46slave=system.membus.master[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51voltage_domain=system.voltage_domain 52 53[system.cpu0] 54type=DerivO3CPU 55children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 56LFSTSize=1024 57LQEntries=32 58LSQCheckLoads=true 59LSQDepCheckShift=4 60SQEntries=32 61SSITSize=1024 62activity=0 63backComSize=5 64branchPred=system.cpu0.branchPred 65cachePorts=200 66checker=Null 67clk_domain=system.cpu_clk_domain 68commitToDecodeDelay=1 69commitToFetchDelay=1 70commitToIEWDelay=1 71commitToRenameDelay=1 72commitWidth=8 73cpu_id=0 74decodeToFetchDelay=1 75decodeToRenameDelay=1 76decodeWidth=8 77dispatchWidth=8 78do_checkpoint_insts=true 79do_quiesce=true 80do_statistics_insts=true 81dtb=system.cpu0.dtb 82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu0.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu0.interrupts 94isa=system.cpu0.isa 95issueToExecuteDelay=1 96issueWidth=8 97itb=system.cpu0.itb 98max_insts_all_threads=0 99max_insts_any_thread=0 100max_loads_all_threads=0 101max_loads_any_thread=0 102needsTSO=false 103numIQEntries=64 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu0.tracer 131trapLatency=13 132wbDepth=1 133wbWidth=8 134workload= 135dcache_port=system.cpu0.dcache.cpu_side 136icache_port=system.cpu0.icache.cpu_side 137 138[system.cpu0.branchPred] 139type=BranchPredictor 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=tournament 153 154[system.cpu0.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=4 159clk_domain=system.cpu_clk_domain 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168size=32768 169system=system 170tags=system.cpu0.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu0.dcache_port 175mem_side=system.toL2Bus.slave[1] 176 177[system.cpu0.dcache.tags] 178type=LRU 179assoc=4 180block_size=64 181clk_domain=system.cpu_clk_domain 182hit_latency=2 183size=32768 184 185[system.cpu0.dtb] 186type=AlphaTLB 187size=64 188 189[system.cpu0.fuPool] 190type=FUPool 191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 192FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 193 194[system.cpu0.fuPool.FUList0] 195type=FUDesc 196children=opList 197count=6 198opList=system.cpu0.fuPool.FUList0.opList 199 200[system.cpu0.fuPool.FUList0.opList] 201type=OpDesc 202issueLat=1 203opClass=IntAlu 204opLat=1 205 206[system.cpu0.fuPool.FUList1] 207type=FUDesc 208children=opList0 opList1 209count=2 210opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 211 212[system.cpu0.fuPool.FUList1.opList0] 213type=OpDesc 214issueLat=1 215opClass=IntMult 216opLat=3 217 218[system.cpu0.fuPool.FUList1.opList1] 219type=OpDesc 220issueLat=19 221opClass=IntDiv 222opLat=20 223 224[system.cpu0.fuPool.FUList2] 225type=FUDesc 226children=opList0 opList1 opList2 227count=4 228opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 229 230[system.cpu0.fuPool.FUList2.opList0] 231type=OpDesc 232issueLat=1 233opClass=FloatAdd 234opLat=2 235 236[system.cpu0.fuPool.FUList2.opList1] 237type=OpDesc 238issueLat=1 239opClass=FloatCmp 240opLat=2 241 242[system.cpu0.fuPool.FUList2.opList2] 243type=OpDesc 244issueLat=1 245opClass=FloatCvt 246opLat=2 247 248[system.cpu0.fuPool.FUList3] 249type=FUDesc 250children=opList0 opList1 opList2 251count=2 252opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 253 254[system.cpu0.fuPool.FUList3.opList0] 255type=OpDesc 256issueLat=1 257opClass=FloatMult 258opLat=4 259 260[system.cpu0.fuPool.FUList3.opList1] 261type=OpDesc 262issueLat=12 263opClass=FloatDiv 264opLat=12 265 266[system.cpu0.fuPool.FUList3.opList2] 267type=OpDesc 268issueLat=24 269opClass=FloatSqrt 270opLat=24 271 272[system.cpu0.fuPool.FUList4] 273type=FUDesc 274children=opList 275count=0 276opList=system.cpu0.fuPool.FUList4.opList 277 278[system.cpu0.fuPool.FUList4.opList] 279type=OpDesc 280issueLat=1 281opClass=MemRead 282opLat=1 283 284[system.cpu0.fuPool.FUList5] 285type=FUDesc 286children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 287count=4 288opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 289 290[system.cpu0.fuPool.FUList5.opList00] 291type=OpDesc 292issueLat=1 293opClass=SimdAdd 294opLat=1 295 296[system.cpu0.fuPool.FUList5.opList01] 297type=OpDesc 298issueLat=1 299opClass=SimdAddAcc 300opLat=1 301 302[system.cpu0.fuPool.FUList5.opList02] 303type=OpDesc 304issueLat=1 305opClass=SimdAlu 306opLat=1 307 308[system.cpu0.fuPool.FUList5.opList03] 309type=OpDesc 310issueLat=1 311opClass=SimdCmp 312opLat=1 313 314[system.cpu0.fuPool.FUList5.opList04] 315type=OpDesc 316issueLat=1 317opClass=SimdCvt 318opLat=1 319 320[system.cpu0.fuPool.FUList5.opList05] 321type=OpDesc 322issueLat=1 323opClass=SimdMisc 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList06] 327type=OpDesc 328issueLat=1 329opClass=SimdMult 330opLat=1 331 332[system.cpu0.fuPool.FUList5.opList07] 333type=OpDesc 334issueLat=1 335opClass=SimdMultAcc 336opLat=1 337 338[system.cpu0.fuPool.FUList5.opList08] 339type=OpDesc 340issueLat=1 341opClass=SimdShift 342opLat=1 343 344[system.cpu0.fuPool.FUList5.opList09] 345type=OpDesc 346issueLat=1 347opClass=SimdShiftAcc 348opLat=1 349 350[system.cpu0.fuPool.FUList5.opList10] 351type=OpDesc 352issueLat=1 353opClass=SimdSqrt 354opLat=1 355 356[system.cpu0.fuPool.FUList5.opList11] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatAdd 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList12] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatAlu 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList13] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatCmp 372opLat=1 373 374[system.cpu0.fuPool.FUList5.opList14] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatCvt 378opLat=1 379 380[system.cpu0.fuPool.FUList5.opList15] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatDiv 384opLat=1 385 386[system.cpu0.fuPool.FUList5.opList16] 387type=OpDesc 388issueLat=1 389opClass=SimdFloatMisc 390opLat=1 391 392[system.cpu0.fuPool.FUList5.opList17] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatMult 396opLat=1 397 398[system.cpu0.fuPool.FUList5.opList18] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatMultAcc 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList19] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatSqrt 408opLat=1 409 410[system.cpu0.fuPool.FUList6] 411type=FUDesc 412children=opList 413count=0 414opList=system.cpu0.fuPool.FUList6.opList 415 416[system.cpu0.fuPool.FUList6.opList] 417type=OpDesc 418issueLat=1 419opClass=MemWrite 420opLat=1 421 422[system.cpu0.fuPool.FUList7] 423type=FUDesc 424children=opList0 opList1 425count=4 426opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 427 428[system.cpu0.fuPool.FUList7.opList0] 429type=OpDesc 430issueLat=1 431opClass=MemRead 432opLat=1 433 434[system.cpu0.fuPool.FUList7.opList1] 435type=OpDesc 436issueLat=1 437opClass=MemWrite 438opLat=1 439 440[system.cpu0.fuPool.FUList8] 441type=FUDesc 442children=opList 443count=1 444opList=system.cpu0.fuPool.FUList8.opList 445 446[system.cpu0.fuPool.FUList8.opList] 447type=OpDesc 448issueLat=3 449opClass=IprAccess 450opLat=3 451 452[system.cpu0.icache] 453type=BaseCache 454children=tags 455addr_ranges=0:18446744073709551615 456assoc=1 457clk_domain=system.cpu_clk_domain 458forward_snoops=true 459hit_latency=2 460is_top_level=true 461max_miss_count=0 462mshrs=4 463prefetch_on_access=false 464prefetcher=Null 465response_latency=2 466size=32768 467system=system 468tags=system.cpu0.icache.tags 469tgts_per_mshr=20 470two_queue=false 471write_buffers=8 472cpu_side=system.cpu0.icache_port 473mem_side=system.toL2Bus.slave[0] 474 475[system.cpu0.icache.tags] 476type=LRU 477assoc=1 478block_size=64 479clk_domain=system.cpu_clk_domain 480hit_latency=2 481size=32768 482 483[system.cpu0.interrupts] 484type=AlphaInterrupts 485 486[system.cpu0.isa] 487type=AlphaISA 488 489[system.cpu0.itb] 490type=AlphaTLB 491size=48 492 493[system.cpu0.tracer] 494type=ExeTracer 495 496[system.cpu1] 497type=DerivO3CPU 498children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 499LFSTSize=1024 500LQEntries=32 501LSQCheckLoads=true 502LSQDepCheckShift=4 503SQEntries=32 504SSITSize=1024 505activity=0 506backComSize=5 507branchPred=system.cpu1.branchPred 508cachePorts=200 509checker=Null 510clk_domain=system.cpu_clk_domain 511commitToDecodeDelay=1 512commitToFetchDelay=1 513commitToIEWDelay=1 514commitToRenameDelay=1 515commitWidth=8 516cpu_id=1 517decodeToFetchDelay=1 518decodeToRenameDelay=1 519decodeWidth=8 520dispatchWidth=8 521do_checkpoint_insts=true 522do_quiesce=true 523do_statistics_insts=true 524dtb=system.cpu1.dtb 525fetchToDecodeDelay=1 526fetchTrapLatency=1 527fetchWidth=8 528forwardComSize=5 529fuPool=system.cpu1.fuPool 530function_trace=false 531function_trace_start=0 532iewToCommitDelay=1 533iewToDecodeDelay=1 534iewToFetchDelay=1 535iewToRenameDelay=1 536interrupts=system.cpu1.interrupts 537isa=system.cpu1.isa 538issueToExecuteDelay=1 539issueWidth=8 540itb=system.cpu1.itb 541max_insts_all_threads=0 542max_insts_any_thread=0 543max_loads_all_threads=0 544max_loads_any_thread=0 545needsTSO=false 546numIQEntries=64 547numPhysFloatRegs=256 548numPhysIntRegs=256 549numROBEntries=192 550numRobs=1 551numThreads=1 552profile=0 553progress_interval=0 554renameToDecodeDelay=1 555renameToFetchDelay=1 556renameToIEWDelay=2 557renameToROBDelay=1 558renameWidth=8 559simpoint_start_insts= 560smtCommitPolicy=RoundRobin 561smtFetchPolicy=SingleThread 562smtIQPolicy=Partitioned 563smtIQThreshold=100 564smtLSQPolicy=Partitioned 565smtLSQThreshold=100 566smtNumFetchingThreads=1 567smtROBPolicy=Partitioned 568smtROBThreshold=100 569squashWidth=8 570store_set_clear_period=250000 571switched_out=false 572system=system 573tracer=system.cpu1.tracer 574trapLatency=13 575wbDepth=1 576wbWidth=8 577workload= 578dcache_port=system.cpu1.dcache.cpu_side 579icache_port=system.cpu1.icache.cpu_side 580 581[system.cpu1.branchPred] 582type=BranchPredictor 583BTBEntries=4096 584BTBTagSize=16 585RASSize=16 586choiceCtrBits=2 587choicePredictorSize=8192 588globalCtrBits=2 589globalPredictorSize=8192 590instShiftAmt=2 591localCtrBits=2 592localHistoryTableSize=2048 593localPredictorSize=2048 594numThreads=1 595predType=tournament 596 597[system.cpu1.dcache] 598type=BaseCache 599children=tags 600addr_ranges=0:18446744073709551615 601assoc=4 602clk_domain=system.cpu_clk_domain 603forward_snoops=true 604hit_latency=2 605is_top_level=true 606max_miss_count=0 607mshrs=4 608prefetch_on_access=false 609prefetcher=Null 610response_latency=2 611size=32768 612system=system 613tags=system.cpu1.dcache.tags 614tgts_per_mshr=20 615two_queue=false 616write_buffers=8 617cpu_side=system.cpu1.dcache_port 618mem_side=system.toL2Bus.slave[3] 619 620[system.cpu1.dcache.tags] 621type=LRU 622assoc=4 623block_size=64 624clk_domain=system.cpu_clk_domain 625hit_latency=2 626size=32768 627 628[system.cpu1.dtb] 629type=AlphaTLB 630size=64 631 632[system.cpu1.fuPool] 633type=FUPool 634children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 635FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 636 637[system.cpu1.fuPool.FUList0] 638type=FUDesc 639children=opList 640count=6 641opList=system.cpu1.fuPool.FUList0.opList 642 643[system.cpu1.fuPool.FUList0.opList] 644type=OpDesc 645issueLat=1 646opClass=IntAlu 647opLat=1 648 649[system.cpu1.fuPool.FUList1] 650type=FUDesc 651children=opList0 opList1 652count=2 653opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 654 655[system.cpu1.fuPool.FUList1.opList0] 656type=OpDesc 657issueLat=1 658opClass=IntMult 659opLat=3 660 661[system.cpu1.fuPool.FUList1.opList1] 662type=OpDesc 663issueLat=19 664opClass=IntDiv 665opLat=20 666 667[system.cpu1.fuPool.FUList2] 668type=FUDesc 669children=opList0 opList1 opList2 670count=4 671opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 672 673[system.cpu1.fuPool.FUList2.opList0] 674type=OpDesc 675issueLat=1 676opClass=FloatAdd 677opLat=2 678 679[system.cpu1.fuPool.FUList2.opList1] 680type=OpDesc 681issueLat=1 682opClass=FloatCmp 683opLat=2 684 685[system.cpu1.fuPool.FUList2.opList2] 686type=OpDesc 687issueLat=1 688opClass=FloatCvt 689opLat=2 690 691[system.cpu1.fuPool.FUList3] 692type=FUDesc 693children=opList0 opList1 opList2 694count=2 695opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 696 697[system.cpu1.fuPool.FUList3.opList0] 698type=OpDesc 699issueLat=1 700opClass=FloatMult 701opLat=4 702 703[system.cpu1.fuPool.FUList3.opList1] 704type=OpDesc 705issueLat=12 706opClass=FloatDiv 707opLat=12 708 709[system.cpu1.fuPool.FUList3.opList2] 710type=OpDesc 711issueLat=24 712opClass=FloatSqrt 713opLat=24 714 715[system.cpu1.fuPool.FUList4] 716type=FUDesc 717children=opList 718count=0 719opList=system.cpu1.fuPool.FUList4.opList 720 721[system.cpu1.fuPool.FUList4.opList] 722type=OpDesc 723issueLat=1 724opClass=MemRead 725opLat=1 726 727[system.cpu1.fuPool.FUList5] 728type=FUDesc 729children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 730count=4 731opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 732 733[system.cpu1.fuPool.FUList5.opList00] 734type=OpDesc 735issueLat=1 736opClass=SimdAdd 737opLat=1 738 739[system.cpu1.fuPool.FUList5.opList01] 740type=OpDesc 741issueLat=1 742opClass=SimdAddAcc 743opLat=1 744 745[system.cpu1.fuPool.FUList5.opList02] 746type=OpDesc 747issueLat=1 748opClass=SimdAlu 749opLat=1 750 751[system.cpu1.fuPool.FUList5.opList03] 752type=OpDesc 753issueLat=1 754opClass=SimdCmp 755opLat=1 756 757[system.cpu1.fuPool.FUList5.opList04] 758type=OpDesc 759issueLat=1 760opClass=SimdCvt 761opLat=1 762 763[system.cpu1.fuPool.FUList5.opList05] 764type=OpDesc 765issueLat=1 766opClass=SimdMisc 767opLat=1 768 769[system.cpu1.fuPool.FUList5.opList06] 770type=OpDesc 771issueLat=1 772opClass=SimdMult 773opLat=1 774 775[system.cpu1.fuPool.FUList5.opList07] 776type=OpDesc 777issueLat=1 778opClass=SimdMultAcc 779opLat=1 780 781[system.cpu1.fuPool.FUList5.opList08] 782type=OpDesc 783issueLat=1 784opClass=SimdShift 785opLat=1 786 787[system.cpu1.fuPool.FUList5.opList09] 788type=OpDesc 789issueLat=1 790opClass=SimdShiftAcc 791opLat=1 792 793[system.cpu1.fuPool.FUList5.opList10] 794type=OpDesc 795issueLat=1 796opClass=SimdSqrt 797opLat=1 798 799[system.cpu1.fuPool.FUList5.opList11] 800type=OpDesc 801issueLat=1 802opClass=SimdFloatAdd 803opLat=1 804 805[system.cpu1.fuPool.FUList5.opList12] 806type=OpDesc 807issueLat=1 808opClass=SimdFloatAlu 809opLat=1 810 811[system.cpu1.fuPool.FUList5.opList13] 812type=OpDesc 813issueLat=1 814opClass=SimdFloatCmp 815opLat=1 816 817[system.cpu1.fuPool.FUList5.opList14] 818type=OpDesc 819issueLat=1 820opClass=SimdFloatCvt 821opLat=1 822 823[system.cpu1.fuPool.FUList5.opList15] 824type=OpDesc 825issueLat=1 826opClass=SimdFloatDiv 827opLat=1 828 829[system.cpu1.fuPool.FUList5.opList16] 830type=OpDesc 831issueLat=1 832opClass=SimdFloatMisc 833opLat=1 834 835[system.cpu1.fuPool.FUList5.opList17] 836type=OpDesc 837issueLat=1 838opClass=SimdFloatMult 839opLat=1 840 841[system.cpu1.fuPool.FUList5.opList18] 842type=OpDesc 843issueLat=1 844opClass=SimdFloatMultAcc 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList19] 848type=OpDesc 849issueLat=1 850opClass=SimdFloatSqrt 851opLat=1 852 853[system.cpu1.fuPool.FUList6] 854type=FUDesc 855children=opList 856count=0 857opList=system.cpu1.fuPool.FUList6.opList 858 859[system.cpu1.fuPool.FUList6.opList] 860type=OpDesc 861issueLat=1 862opClass=MemWrite 863opLat=1 864 865[system.cpu1.fuPool.FUList7] 866type=FUDesc 867children=opList0 opList1 868count=4 869opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 870 871[system.cpu1.fuPool.FUList7.opList0] 872type=OpDesc 873issueLat=1 874opClass=MemRead 875opLat=1 876 877[system.cpu1.fuPool.FUList7.opList1] 878type=OpDesc 879issueLat=1 880opClass=MemWrite 881opLat=1 882 883[system.cpu1.fuPool.FUList8] 884type=FUDesc 885children=opList 886count=1 887opList=system.cpu1.fuPool.FUList8.opList 888 889[system.cpu1.fuPool.FUList8.opList] 890type=OpDesc 891issueLat=3 892opClass=IprAccess 893opLat=3 894 895[system.cpu1.icache] 896type=BaseCache 897children=tags 898addr_ranges=0:18446744073709551615 899assoc=1 900clk_domain=system.cpu_clk_domain 901forward_snoops=true 902hit_latency=2 903is_top_level=true 904max_miss_count=0 905mshrs=4 906prefetch_on_access=false 907prefetcher=Null 908response_latency=2 909size=32768 910system=system 911tags=system.cpu1.icache.tags 912tgts_per_mshr=20 913two_queue=false 914write_buffers=8 915cpu_side=system.cpu1.icache_port 916mem_side=system.toL2Bus.slave[2] 917 918[system.cpu1.icache.tags] 919type=LRU 920assoc=1 921block_size=64 922clk_domain=system.cpu_clk_domain 923hit_latency=2 924size=32768 925 926[system.cpu1.interrupts] 927type=AlphaInterrupts 928 929[system.cpu1.isa] 930type=AlphaISA 931 932[system.cpu1.itb] 933type=AlphaTLB 934size=48 935 936[system.cpu1.tracer] 937type=ExeTracer 938 939[system.cpu_clk_domain] 940type=SrcClockDomain 941clock=500 942voltage_domain=system.voltage_domain 943 944[system.disk0] 945type=IdeDisk 946children=image 947delay=1000000 948driveID=master 949image=system.disk0.image 950 951[system.disk0.image] 952type=CowDiskImage 953children=child 954child=system.disk0.image.child 955image_file= 956read_only=false 957table_size=65536 958 959[system.disk0.image.child] 960type=RawDiskImage 961image_file=/dist/m5/system/disks/linux-latest.img 962read_only=true 963 964[system.disk2] 965type=IdeDisk 966children=image 967delay=1000000 968driveID=master 969image=system.disk2.image 970 971[system.disk2.image] 972type=CowDiskImage 973children=child 974child=system.disk2.image.child 975image_file= 976read_only=false 977table_size=65536 978 979[system.disk2.image.child] 980type=RawDiskImage 981image_file=/dist/m5/system/disks/linux-bigswap2.img 982read_only=true 983 984[system.intrctrl] 985type=IntrControl 986sys=system 987 988[system.iobus] 989type=NoncoherentBus 990clk_domain=system.clk_domain 991header_cycles=1 992use_default_range=true 993width=8 994default=system.tsunami.pciconfig.pio 995master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 996slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 997 998[system.iocache] 999type=BaseCache 1000children=tags 1001addr_ranges=0:134217727 1002assoc=8 1003clk_domain=system.clk_domain 1004forward_snoops=false 1005hit_latency=50 1006is_top_level=true 1007max_miss_count=0 1008mshrs=20 1009prefetch_on_access=false 1010prefetcher=Null 1011response_latency=50 1012size=1024 1013system=system 1014tags=system.iocache.tags 1015tgts_per_mshr=12 1016two_queue=false 1017write_buffers=8 1018cpu_side=system.iobus.master[29] 1019mem_side=system.membus.slave[2] 1020 1021[system.iocache.tags] 1022type=LRU 1023assoc=8 1024block_size=64 1025clk_domain=system.clk_domain 1026hit_latency=50 1027size=1024 1028 1029[system.l2c] 1030type=BaseCache 1031children=tags 1032addr_ranges=0:18446744073709551615 1033assoc=8 1034clk_domain=system.cpu_clk_domain 1035forward_snoops=true 1036hit_latency=20 1037is_top_level=false 1038max_miss_count=0 1039mshrs=20 1040prefetch_on_access=false 1041prefetcher=Null 1042response_latency=20 1043size=4194304 1044system=system 1045tags=system.l2c.tags 1046tgts_per_mshr=12 1047two_queue=false 1048write_buffers=8 1049cpu_side=system.toL2Bus.master[0] 1050mem_side=system.membus.slave[1] 1051 1052[system.l2c.tags] 1053type=LRU 1054assoc=8 1055block_size=64 1056clk_domain=system.cpu_clk_domain 1057hit_latency=20 1058size=4194304 1059 1060[system.membus] 1061type=CoherentBus 1062children=badaddr_responder 1063clk_domain=system.clk_domain 1064header_cycles=1 1065system=system 1066use_default_range=false 1067width=8 1068default=system.membus.badaddr_responder.pio 1069master=system.bridge.slave system.physmem.port 1070slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1071 1072[system.membus.badaddr_responder] 1073type=IsaFake 1074clk_domain=system.clk_domain 1075fake_mem=false 1076pio_addr=0 1077pio_latency=100000 1078pio_size=8 1079ret_bad_addr=true 1080ret_data16=65535 1081ret_data32=4294967295 1082ret_data64=18446744073709551615 1083ret_data8=255 1084system=system 1085update_data=false 1086warn_access= 1087pio=system.membus.default 1088 1089[system.physmem] 1090type=SimpleDRAM 1091activation_limit=4 1092addr_mapping=RaBaChCo 1093banks_per_rank=8 1094burst_length=8 1095channels=1 1096clk_domain=system.clk_domain 1097conf_table_reported=true 1098device_bus_width=8 1099device_rowbuffer_size=1024 1100devices_per_rank=8 1101in_addr_map=true 1102mem_sched_policy=frfcfs 1103null=false 1104page_policy=open 1105range=0:134217727 1106ranks_per_channel=2 1107read_buffer_size=32 1108static_backend_latency=10000 1109static_frontend_latency=10000 1110tBURST=5000 1111tCL=13750 1112tRCD=13750 1113tREFI=7800000 1114tRFC=300000 1115tRP=13750 1116tWTR=7500 1117tXAW=40000 1118write_buffer_size=32 1119write_thresh_perc=70 1120port=system.membus.master[1] 1121 1122[system.simple_disk] 1123type=SimpleDisk 1124children=disk 1125disk=system.simple_disk.disk 1126system=system 1127 1128[system.simple_disk.disk] 1129type=RawDiskImage 1130image_file=/dist/m5/system/disks/linux-latest.img 1131read_only=true 1132 1133[system.terminal] 1134type=Terminal 1135intr_control=system.intrctrl 1136number=0 1137output=true 1138port=3456 1139 1140[system.toL2Bus] 1141type=CoherentBus 1142clk_domain=system.cpu_clk_domain 1143header_cycles=1 1144system=system 1145use_default_range=false 1146width=8 1147master=system.l2c.cpu_side 1148slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1149 1150[system.tsunami] 1151type=Tsunami 1152children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1153intrctrl=system.intrctrl 1154system=system 1155 1156[system.tsunami.backdoor] 1157type=AlphaBackdoor 1158clk_domain=system.clk_domain 1159cpu=system.cpu0 1160disk=system.simple_disk 1161pio_addr=8804682956800 1162pio_latency=100000 1163platform=system.tsunami 1164system=system 1165terminal=system.terminal 1166pio=system.iobus.master[24] 1167 1168[system.tsunami.cchip] 1169type=TsunamiCChip 1170clk_domain=system.clk_domain 1171pio_addr=8803072344064 1172pio_latency=100000 1173system=system 1174tsunami=system.tsunami 1175pio=system.iobus.master[0] 1176 1177[system.tsunami.ethernet] 1178type=NSGigE 1179BAR0=1 1180BAR0LegacyIO=false 1181BAR0Size=256 1182BAR1=0 1183BAR1LegacyIO=false 1184BAR1Size=4096 1185BAR2=0 1186BAR2LegacyIO=false 1187BAR2Size=0 1188BAR3=0 1189BAR3LegacyIO=false 1190BAR3Size=0 1191BAR4=0 1192BAR4LegacyIO=false 1193BAR4Size=0 1194BAR5=0 1195BAR5LegacyIO=false 1196BAR5Size=0 1197BIST=0 1198CacheLineSize=0 1199CardbusCIS=0 1200ClassCode=2 1201Command=0 1202DeviceID=34 1203ExpansionROM=0 1204HeaderType=0 1205InterruptLine=30 1206InterruptPin=1 1207LatencyTimer=0 1208MaximumLatency=52 1209MinimumGrant=176 1210ProgIF=0 1211Revision=0 1212Status=656 1213SubClassCode=0 1214SubsystemID=0 1215SubsystemVendorID=0 1216VendorID=4107 1217clk_domain=system.clk_domain 1218config_latency=20000 1219dma_data_free=false 1220dma_desc_free=false 1221dma_no_allocate=true 1222dma_read_delay=0 1223dma_read_factor=0 1224dma_write_delay=0 1225dma_write_factor=0 1226hardware_address=00:90:00:00:00:01 1227intr_delay=10000000 1228pci_bus=0 1229pci_dev=1 1230pci_func=0 1231pio_latency=30000 1232platform=system.tsunami 1233rss=false 1234rx_delay=1000000 1235rx_fifo_size=524288 1236rx_filter=true 1237rx_thread=false 1238system=system 1239tx_delay=1000000 1240tx_fifo_size=524288 1241tx_thread=false 1242config=system.iobus.master[28] 1243dma=system.iobus.slave[2] 1244pio=system.iobus.master[27] 1245 1246[system.tsunami.fake_OROM] 1247type=IsaFake 1248clk_domain=system.clk_domain 1249fake_mem=false 1250pio_addr=8796093677568 1251pio_latency=100000 1252pio_size=393216 1253ret_bad_addr=false 1254ret_data16=65535 1255ret_data32=4294967295 1256ret_data64=18446744073709551615 1257ret_data8=255 1258system=system 1259update_data=false 1260warn_access= 1261pio=system.iobus.master[8] 1262 1263[system.tsunami.fake_ata0] 1264type=IsaFake 1265clk_domain=system.clk_domain 1266fake_mem=false 1267pio_addr=8804615848432 1268pio_latency=100000 1269pio_size=8 1270ret_bad_addr=false 1271ret_data16=65535 1272ret_data32=4294967295 1273ret_data64=18446744073709551615 1274ret_data8=255 1275system=system 1276update_data=false 1277warn_access= 1278pio=system.iobus.master[19] 1279 1280[system.tsunami.fake_ata1] 1281type=IsaFake 1282clk_domain=system.clk_domain 1283fake_mem=false 1284pio_addr=8804615848304 1285pio_latency=100000 1286pio_size=8 1287ret_bad_addr=false 1288ret_data16=65535 1289ret_data32=4294967295 1290ret_data64=18446744073709551615 1291ret_data8=255 1292system=system 1293update_data=false 1294warn_access= 1295pio=system.iobus.master[20] 1296 1297[system.tsunami.fake_pnp_addr] 1298type=IsaFake 1299clk_domain=system.clk_domain 1300fake_mem=false 1301pio_addr=8804615848569 1302pio_latency=100000 1303pio_size=8 1304ret_bad_addr=false 1305ret_data16=65535 1306ret_data32=4294967295 1307ret_data64=18446744073709551615 1308ret_data8=255 1309system=system 1310update_data=false 1311warn_access= 1312pio=system.iobus.master[9] 1313 1314[system.tsunami.fake_pnp_read0] 1315type=IsaFake 1316clk_domain=system.clk_domain 1317fake_mem=false 1318pio_addr=8804615848451 1319pio_latency=100000 1320pio_size=8 1321ret_bad_addr=false 1322ret_data16=65535 1323ret_data32=4294967295 1324ret_data64=18446744073709551615 1325ret_data8=255 1326system=system 1327update_data=false 1328warn_access= 1329pio=system.iobus.master[11] 1330 1331[system.tsunami.fake_pnp_read1] 1332type=IsaFake 1333clk_domain=system.clk_domain 1334fake_mem=false 1335pio_addr=8804615848515 1336pio_latency=100000 1337pio_size=8 1338ret_bad_addr=false 1339ret_data16=65535 1340ret_data32=4294967295 1341ret_data64=18446744073709551615 1342ret_data8=255 1343system=system 1344update_data=false 1345warn_access= 1346pio=system.iobus.master[12] 1347 1348[system.tsunami.fake_pnp_read2] 1349type=IsaFake 1350clk_domain=system.clk_domain 1351fake_mem=false 1352pio_addr=8804615848579 1353pio_latency=100000 1354pio_size=8 1355ret_bad_addr=false 1356ret_data16=65535 1357ret_data32=4294967295 1358ret_data64=18446744073709551615 1359ret_data8=255 1360system=system 1361update_data=false 1362warn_access= 1363pio=system.iobus.master[13] 1364 1365[system.tsunami.fake_pnp_read3] 1366type=IsaFake 1367clk_domain=system.clk_domain 1368fake_mem=false 1369pio_addr=8804615848643 1370pio_latency=100000 1371pio_size=8 1372ret_bad_addr=false 1373ret_data16=65535 1374ret_data32=4294967295 1375ret_data64=18446744073709551615 1376ret_data8=255 1377system=system 1378update_data=false 1379warn_access= 1380pio=system.iobus.master[14] 1381 1382[system.tsunami.fake_pnp_read4] 1383type=IsaFake 1384clk_domain=system.clk_domain 1385fake_mem=false 1386pio_addr=8804615848707 1387pio_latency=100000 1388pio_size=8 1389ret_bad_addr=false 1390ret_data16=65535 1391ret_data32=4294967295 1392ret_data64=18446744073709551615 1393ret_data8=255 1394system=system 1395update_data=false 1396warn_access= 1397pio=system.iobus.master[15] 1398 1399[system.tsunami.fake_pnp_read5] 1400type=IsaFake 1401clk_domain=system.clk_domain 1402fake_mem=false 1403pio_addr=8804615848771 1404pio_latency=100000 1405pio_size=8 1406ret_bad_addr=false 1407ret_data16=65535 1408ret_data32=4294967295 1409ret_data64=18446744073709551615 1410ret_data8=255 1411system=system 1412update_data=false 1413warn_access= 1414pio=system.iobus.master[16] 1415 1416[system.tsunami.fake_pnp_read6] 1417type=IsaFake 1418clk_domain=system.clk_domain 1419fake_mem=false 1420pio_addr=8804615848835 1421pio_latency=100000 1422pio_size=8 1423ret_bad_addr=false 1424ret_data16=65535 1425ret_data32=4294967295 1426ret_data64=18446744073709551615 1427ret_data8=255 1428system=system 1429update_data=false 1430warn_access= 1431pio=system.iobus.master[17] 1432 1433[system.tsunami.fake_pnp_read7] 1434type=IsaFake 1435clk_domain=system.clk_domain 1436fake_mem=false 1437pio_addr=8804615848899 1438pio_latency=100000 1439pio_size=8 1440ret_bad_addr=false 1441ret_data16=65535 1442ret_data32=4294967295 1443ret_data64=18446744073709551615 1444ret_data8=255 1445system=system 1446update_data=false 1447warn_access= 1448pio=system.iobus.master[18] 1449 1450[system.tsunami.fake_pnp_write] 1451type=IsaFake 1452clk_domain=system.clk_domain 1453fake_mem=false 1454pio_addr=8804615850617 1455pio_latency=100000 1456pio_size=8 1457ret_bad_addr=false 1458ret_data16=65535 1459ret_data32=4294967295 1460ret_data64=18446744073709551615 1461ret_data8=255 1462system=system 1463update_data=false 1464warn_access= 1465pio=system.iobus.master[10] 1466 1467[system.tsunami.fake_ppc] 1468type=IsaFake 1469clk_domain=system.clk_domain 1470fake_mem=false 1471pio_addr=8804615848891 1472pio_latency=100000 1473pio_size=8 1474ret_bad_addr=false 1475ret_data16=65535 1476ret_data32=4294967295 1477ret_data64=18446744073709551615 1478ret_data8=255 1479system=system 1480update_data=false 1481warn_access= 1482pio=system.iobus.master[7] 1483 1484[system.tsunami.fake_sm_chip] 1485type=IsaFake 1486clk_domain=system.clk_domain 1487fake_mem=false 1488pio_addr=8804615848816 1489pio_latency=100000 1490pio_size=8 1491ret_bad_addr=false 1492ret_data16=65535 1493ret_data32=4294967295 1494ret_data64=18446744073709551615 1495ret_data8=255 1496system=system 1497update_data=false 1498warn_access= 1499pio=system.iobus.master[2] 1500 1501[system.tsunami.fake_uart1] 1502type=IsaFake 1503clk_domain=system.clk_domain 1504fake_mem=false 1505pio_addr=8804615848696 1506pio_latency=100000 1507pio_size=8 1508ret_bad_addr=false 1509ret_data16=65535 1510ret_data32=4294967295 1511ret_data64=18446744073709551615 1512ret_data8=255 1513system=system 1514update_data=false 1515warn_access= 1516pio=system.iobus.master[3] 1517 1518[system.tsunami.fake_uart2] 1519type=IsaFake 1520clk_domain=system.clk_domain 1521fake_mem=false 1522pio_addr=8804615848936 1523pio_latency=100000 1524pio_size=8 1525ret_bad_addr=false 1526ret_data16=65535 1527ret_data32=4294967295 1528ret_data64=18446744073709551615 1529ret_data8=255 1530system=system 1531update_data=false 1532warn_access= 1533pio=system.iobus.master[4] 1534 1535[system.tsunami.fake_uart3] 1536type=IsaFake 1537clk_domain=system.clk_domain 1538fake_mem=false 1539pio_addr=8804615848680 1540pio_latency=100000 1541pio_size=8 1542ret_bad_addr=false 1543ret_data16=65535 1544ret_data32=4294967295 1545ret_data64=18446744073709551615 1546ret_data8=255 1547system=system 1548update_data=false 1549warn_access= 1550pio=system.iobus.master[5] 1551 1552[system.tsunami.fake_uart4] 1553type=IsaFake 1554clk_domain=system.clk_domain 1555fake_mem=false 1556pio_addr=8804615848944 1557pio_latency=100000 1558pio_size=8 1559ret_bad_addr=false 1560ret_data16=65535 1561ret_data32=4294967295 1562ret_data64=18446744073709551615 1563ret_data8=255 1564system=system 1565update_data=false 1566warn_access= 1567pio=system.iobus.master[6] 1568 1569[system.tsunami.fb] 1570type=BadDevice 1571clk_domain=system.clk_domain 1572devicename=FrameBuffer 1573pio_addr=8804615848912 1574pio_latency=100000 1575system=system 1576pio=system.iobus.master[21] 1577 1578[system.tsunami.ide] 1579type=IdeController 1580BAR0=1 1581BAR0LegacyIO=false 1582BAR0Size=8 1583BAR1=1 1584BAR1LegacyIO=false 1585BAR1Size=4 1586BAR2=1 1587BAR2LegacyIO=false 1588BAR2Size=8 1589BAR3=1 1590BAR3LegacyIO=false 1591BAR3Size=4 1592BAR4=1 1593BAR4LegacyIO=false 1594BAR4Size=16 1595BAR5=1 1596BAR5LegacyIO=false 1597BAR5Size=0 1598BIST=0 1599CacheLineSize=0 1600CardbusCIS=0 1601ClassCode=1 1602Command=0 1603DeviceID=28945 1604ExpansionROM=0 1605HeaderType=0 1606InterruptLine=31 1607InterruptPin=1 1608LatencyTimer=0 1609MaximumLatency=0 1610MinimumGrant=0 1611ProgIF=133 1612Revision=0 1613Status=640 1614SubClassCode=1 1615SubsystemID=0 1616SubsystemVendorID=0 1617VendorID=32902 1618clk_domain=system.clk_domain 1619config_latency=20000 1620ctrl_offset=0 1621disks=system.disk0 system.disk2 1622io_shift=0 1623pci_bus=0 1624pci_dev=0 1625pci_func=0 1626pio_latency=30000 1627platform=system.tsunami 1628system=system 1629config=system.iobus.master[26] 1630dma=system.iobus.slave[1] 1631pio=system.iobus.master[25] 1632 1633[system.tsunami.io] 1634type=TsunamiIO 1635clk_domain=system.clk_domain 1636frequency=976562500 1637pio_addr=8804615847936 1638pio_latency=100000 1639system=system 1640time=Thu Jan 1 00:00:00 2009 1641tsunami=system.tsunami 1642year_is_bcd=false 1643pio=system.iobus.master[22] 1644 1645[system.tsunami.pchip] 1646type=TsunamiPChip 1647clk_domain=system.clk_domain 1648pio_addr=8802535473152 1649pio_latency=100000 1650system=system 1651tsunami=system.tsunami 1652pio=system.iobus.master[1] 1653 1654[system.tsunami.pciconfig] 1655type=PciConfigAll 1656bus=0 1657clk_domain=system.clk_domain 1658pio_addr=0 1659pio_latency=30000 1660platform=system.tsunami 1661size=16777216 1662system=system 1663pio=system.iobus.default 1664 1665[system.tsunami.uart] 1666type=Uart8250 1667clk_domain=system.clk_domain 1668pio_addr=8804615848952 1669pio_latency=100000 1670platform=system.tsunami 1671system=system 1672terminal=system.terminal 1673pio=system.iobus.master[23] 1674 1675[system.voltage_domain] 1676type=VoltageDomain 1677voltage=1.000000 1678 1679