config.ini revision 9661:18755c467503
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000 15console=/dist/m5/system/binaries/console 16init_param=0 17kernel=/dist/m5/system/binaries/vmlinux 18load_addr_mask=1099511627775 19mem_mode=timing 20mem_ranges=0:134217727 21memories=system.physmem 22num_work_ids=16 23pal=/dist/m5/system/binaries/ts_osfpal 24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu0] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu0.branchPred 59cachePorts=200 60checker=Null 61clock=500 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu0.dtb 76fetchToDecodeDelay=1 77fetchTrapLatency=1 78fetchWidth=8 79forwardComSize=5 80fuPool=system.cpu0.fuPool 81function_trace=false 82function_trace_start=0 83iewToCommitDelay=1 84iewToDecodeDelay=1 85iewToFetchDelay=1 86iewToRenameDelay=1 87interrupts=system.cpu0.interrupts 88isa=system.cpu0.isa 89issueToExecuteDelay=1 90issueWidth=8 91itb=system.cpu0.itb 92max_insts_all_threads=0 93max_insts_any_thread=0 94max_loads_all_threads=0 95max_loads_any_thread=0 96needsTSO=false 97numIQEntries=64 98numPhysFloatRegs=256 99numPhysIntRegs=256 100numROBEntries=192 101numRobs=1 102numThreads=1 103profile=0 104progress_interval=0 105renameToDecodeDelay=1 106renameToFetchDelay=1 107renameToIEWDelay=2 108renameToROBDelay=1 109renameWidth=8 110simpoint_start_insts= 111smtCommitPolicy=RoundRobin 112smtFetchPolicy=SingleThread 113smtIQPolicy=Partitioned 114smtIQThreshold=100 115smtLSQPolicy=Partitioned 116smtLSQThreshold=100 117smtNumFetchingThreads=1 118smtROBPolicy=Partitioned 119smtROBThreshold=100 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu0.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 128workload= 129dcache_port=system.cpu0.dcache.cpu_side 130icache_port=system.cpu0.icache.cpu_side 131 132[system.cpu0.branchPred] 133type=BranchPredictor 134BTBEntries=4096 135BTBTagSize=16 136RASSize=16 137choiceCtrBits=2 138choicePredictorSize=8192 139globalCtrBits=2 140globalHistoryBits=13 141globalPredictorSize=8192 142instShiftAmt=2 143localCtrBits=2 144localHistoryBits=11 145localHistoryTableSize=2048 146localPredictorSize=2048 147numThreads=1 148predType=tournament 149 150[system.cpu0.dcache] 151type=BaseCache 152addr_ranges=0:18446744073709551615 153assoc=4 154block_size=64 155clock=500 156forward_snoops=true 157hit_latency=2 158is_top_level=true 159max_miss_count=0 160mshrs=4 161prefetch_on_access=false 162prefetcher=Null 163response_latency=2 164size=32768 165system=system 166tgts_per_mshr=20 167two_queue=false 168write_buffers=8 169cpu_side=system.cpu0.dcache_port 170mem_side=system.toL2Bus.slave[1] 171 172[system.cpu0.dtb] 173type=AlphaTLB 174size=64 175 176[system.cpu0.fuPool] 177type=FUPool 178children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 179FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 180 181[system.cpu0.fuPool.FUList0] 182type=FUDesc 183children=opList 184count=6 185opList=system.cpu0.fuPool.FUList0.opList 186 187[system.cpu0.fuPool.FUList0.opList] 188type=OpDesc 189issueLat=1 190opClass=IntAlu 191opLat=1 192 193[system.cpu0.fuPool.FUList1] 194type=FUDesc 195children=opList0 opList1 196count=2 197opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 198 199[system.cpu0.fuPool.FUList1.opList0] 200type=OpDesc 201issueLat=1 202opClass=IntMult 203opLat=3 204 205[system.cpu0.fuPool.FUList1.opList1] 206type=OpDesc 207issueLat=19 208opClass=IntDiv 209opLat=20 210 211[system.cpu0.fuPool.FUList2] 212type=FUDesc 213children=opList0 opList1 opList2 214count=4 215opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 216 217[system.cpu0.fuPool.FUList2.opList0] 218type=OpDesc 219issueLat=1 220opClass=FloatAdd 221opLat=2 222 223[system.cpu0.fuPool.FUList2.opList1] 224type=OpDesc 225issueLat=1 226opClass=FloatCmp 227opLat=2 228 229[system.cpu0.fuPool.FUList2.opList2] 230type=OpDesc 231issueLat=1 232opClass=FloatCvt 233opLat=2 234 235[system.cpu0.fuPool.FUList3] 236type=FUDesc 237children=opList0 opList1 opList2 238count=2 239opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 240 241[system.cpu0.fuPool.FUList3.opList0] 242type=OpDesc 243issueLat=1 244opClass=FloatMult 245opLat=4 246 247[system.cpu0.fuPool.FUList3.opList1] 248type=OpDesc 249issueLat=12 250opClass=FloatDiv 251opLat=12 252 253[system.cpu0.fuPool.FUList3.opList2] 254type=OpDesc 255issueLat=24 256opClass=FloatSqrt 257opLat=24 258 259[system.cpu0.fuPool.FUList4] 260type=FUDesc 261children=opList 262count=0 263opList=system.cpu0.fuPool.FUList4.opList 264 265[system.cpu0.fuPool.FUList4.opList] 266type=OpDesc 267issueLat=1 268opClass=MemRead 269opLat=1 270 271[system.cpu0.fuPool.FUList5] 272type=FUDesc 273children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 274count=4 275opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 276 277[system.cpu0.fuPool.FUList5.opList00] 278type=OpDesc 279issueLat=1 280opClass=SimdAdd 281opLat=1 282 283[system.cpu0.fuPool.FUList5.opList01] 284type=OpDesc 285issueLat=1 286opClass=SimdAddAcc 287opLat=1 288 289[system.cpu0.fuPool.FUList5.opList02] 290type=OpDesc 291issueLat=1 292opClass=SimdAlu 293opLat=1 294 295[system.cpu0.fuPool.FUList5.opList03] 296type=OpDesc 297issueLat=1 298opClass=SimdCmp 299opLat=1 300 301[system.cpu0.fuPool.FUList5.opList04] 302type=OpDesc 303issueLat=1 304opClass=SimdCvt 305opLat=1 306 307[system.cpu0.fuPool.FUList5.opList05] 308type=OpDesc 309issueLat=1 310opClass=SimdMisc 311opLat=1 312 313[system.cpu0.fuPool.FUList5.opList06] 314type=OpDesc 315issueLat=1 316opClass=SimdMult 317opLat=1 318 319[system.cpu0.fuPool.FUList5.opList07] 320type=OpDesc 321issueLat=1 322opClass=SimdMultAcc 323opLat=1 324 325[system.cpu0.fuPool.FUList5.opList08] 326type=OpDesc 327issueLat=1 328opClass=SimdShift 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList09] 332type=OpDesc 333issueLat=1 334opClass=SimdShiftAcc 335opLat=1 336 337[system.cpu0.fuPool.FUList5.opList10] 338type=OpDesc 339issueLat=1 340opClass=SimdSqrt 341opLat=1 342 343[system.cpu0.fuPool.FUList5.opList11] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatAdd 347opLat=1 348 349[system.cpu0.fuPool.FUList5.opList12] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatAlu 353opLat=1 354 355[system.cpu0.fuPool.FUList5.opList13] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatCmp 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList14] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatCvt 365opLat=1 366 367[system.cpu0.fuPool.FUList5.opList15] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatDiv 371opLat=1 372 373[system.cpu0.fuPool.FUList5.opList16] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMisc 377opLat=1 378 379[system.cpu0.fuPool.FUList5.opList17] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatMult 383opLat=1 384 385[system.cpu0.fuPool.FUList5.opList18] 386type=OpDesc 387issueLat=1 388opClass=SimdFloatMultAcc 389opLat=1 390 391[system.cpu0.fuPool.FUList5.opList19] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatSqrt 395opLat=1 396 397[system.cpu0.fuPool.FUList6] 398type=FUDesc 399children=opList 400count=0 401opList=system.cpu0.fuPool.FUList6.opList 402 403[system.cpu0.fuPool.FUList6.opList] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu0.fuPool.FUList7] 410type=FUDesc 411children=opList0 opList1 412count=4 413opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 414 415[system.cpu0.fuPool.FUList7.opList0] 416type=OpDesc 417issueLat=1 418opClass=MemRead 419opLat=1 420 421[system.cpu0.fuPool.FUList7.opList1] 422type=OpDesc 423issueLat=1 424opClass=MemWrite 425opLat=1 426 427[system.cpu0.fuPool.FUList8] 428type=FUDesc 429children=opList 430count=1 431opList=system.cpu0.fuPool.FUList8.opList 432 433[system.cpu0.fuPool.FUList8.opList] 434type=OpDesc 435issueLat=3 436opClass=IprAccess 437opLat=3 438 439[system.cpu0.icache] 440type=BaseCache 441addr_ranges=0:18446744073709551615 442assoc=1 443block_size=64 444clock=500 445forward_snoops=true 446hit_latency=2 447is_top_level=true 448max_miss_count=0 449mshrs=4 450prefetch_on_access=false 451prefetcher=Null 452response_latency=2 453size=32768 454system=system 455tgts_per_mshr=20 456two_queue=false 457write_buffers=8 458cpu_side=system.cpu0.icache_port 459mem_side=system.toL2Bus.slave[0] 460 461[system.cpu0.interrupts] 462type=AlphaInterrupts 463 464[system.cpu0.isa] 465type=AlphaISA 466 467[system.cpu0.itb] 468type=AlphaTLB 469size=48 470 471[system.cpu0.tracer] 472type=ExeTracer 473 474[system.cpu1] 475type=DerivO3CPU 476children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 477LFSTSize=1024 478LQEntries=32 479LSQCheckLoads=true 480LSQDepCheckShift=4 481SQEntries=32 482SSITSize=1024 483activity=0 484backComSize=5 485branchPred=system.cpu1.branchPred 486cachePorts=200 487checker=Null 488clock=500 489commitToDecodeDelay=1 490commitToFetchDelay=1 491commitToIEWDelay=1 492commitToRenameDelay=1 493commitWidth=8 494cpu_id=1 495decodeToFetchDelay=1 496decodeToRenameDelay=1 497decodeWidth=8 498dispatchWidth=8 499do_checkpoint_insts=true 500do_quiesce=true 501do_statistics_insts=true 502dtb=system.cpu1.dtb 503fetchToDecodeDelay=1 504fetchTrapLatency=1 505fetchWidth=8 506forwardComSize=5 507fuPool=system.cpu1.fuPool 508function_trace=false 509function_trace_start=0 510iewToCommitDelay=1 511iewToDecodeDelay=1 512iewToFetchDelay=1 513iewToRenameDelay=1 514interrupts=system.cpu1.interrupts 515isa=system.cpu1.isa 516issueToExecuteDelay=1 517issueWidth=8 518itb=system.cpu1.itb 519max_insts_all_threads=0 520max_insts_any_thread=0 521max_loads_all_threads=0 522max_loads_any_thread=0 523needsTSO=false 524numIQEntries=64 525numPhysFloatRegs=256 526numPhysIntRegs=256 527numROBEntries=192 528numRobs=1 529numThreads=1 530profile=0 531progress_interval=0 532renameToDecodeDelay=1 533renameToFetchDelay=1 534renameToIEWDelay=2 535renameToROBDelay=1 536renameWidth=8 537simpoint_start_insts= 538smtCommitPolicy=RoundRobin 539smtFetchPolicy=SingleThread 540smtIQPolicy=Partitioned 541smtIQThreshold=100 542smtLSQPolicy=Partitioned 543smtLSQThreshold=100 544smtNumFetchingThreads=1 545smtROBPolicy=Partitioned 546smtROBThreshold=100 547squashWidth=8 548store_set_clear_period=250000 549switched_out=false 550system=system 551tracer=system.cpu1.tracer 552trapLatency=13 553wbDepth=1 554wbWidth=8 555workload= 556dcache_port=system.cpu1.dcache.cpu_side 557icache_port=system.cpu1.icache.cpu_side 558 559[system.cpu1.branchPred] 560type=BranchPredictor 561BTBEntries=4096 562BTBTagSize=16 563RASSize=16 564choiceCtrBits=2 565choicePredictorSize=8192 566globalCtrBits=2 567globalHistoryBits=13 568globalPredictorSize=8192 569instShiftAmt=2 570localCtrBits=2 571localHistoryBits=11 572localHistoryTableSize=2048 573localPredictorSize=2048 574numThreads=1 575predType=tournament 576 577[system.cpu1.dcache] 578type=BaseCache 579addr_ranges=0:18446744073709551615 580assoc=4 581block_size=64 582clock=500 583forward_snoops=true 584hit_latency=2 585is_top_level=true 586max_miss_count=0 587mshrs=4 588prefetch_on_access=false 589prefetcher=Null 590response_latency=2 591size=32768 592system=system 593tgts_per_mshr=20 594two_queue=false 595write_buffers=8 596cpu_side=system.cpu1.dcache_port 597mem_side=system.toL2Bus.slave[3] 598 599[system.cpu1.dtb] 600type=AlphaTLB 601size=64 602 603[system.cpu1.fuPool] 604type=FUPool 605children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 606FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 607 608[system.cpu1.fuPool.FUList0] 609type=FUDesc 610children=opList 611count=6 612opList=system.cpu1.fuPool.FUList0.opList 613 614[system.cpu1.fuPool.FUList0.opList] 615type=OpDesc 616issueLat=1 617opClass=IntAlu 618opLat=1 619 620[system.cpu1.fuPool.FUList1] 621type=FUDesc 622children=opList0 opList1 623count=2 624opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 625 626[system.cpu1.fuPool.FUList1.opList0] 627type=OpDesc 628issueLat=1 629opClass=IntMult 630opLat=3 631 632[system.cpu1.fuPool.FUList1.opList1] 633type=OpDesc 634issueLat=19 635opClass=IntDiv 636opLat=20 637 638[system.cpu1.fuPool.FUList2] 639type=FUDesc 640children=opList0 opList1 opList2 641count=4 642opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 643 644[system.cpu1.fuPool.FUList2.opList0] 645type=OpDesc 646issueLat=1 647opClass=FloatAdd 648opLat=2 649 650[system.cpu1.fuPool.FUList2.opList1] 651type=OpDesc 652issueLat=1 653opClass=FloatCmp 654opLat=2 655 656[system.cpu1.fuPool.FUList2.opList2] 657type=OpDesc 658issueLat=1 659opClass=FloatCvt 660opLat=2 661 662[system.cpu1.fuPool.FUList3] 663type=FUDesc 664children=opList0 opList1 opList2 665count=2 666opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 667 668[system.cpu1.fuPool.FUList3.opList0] 669type=OpDesc 670issueLat=1 671opClass=FloatMult 672opLat=4 673 674[system.cpu1.fuPool.FUList3.opList1] 675type=OpDesc 676issueLat=12 677opClass=FloatDiv 678opLat=12 679 680[system.cpu1.fuPool.FUList3.opList2] 681type=OpDesc 682issueLat=24 683opClass=FloatSqrt 684opLat=24 685 686[system.cpu1.fuPool.FUList4] 687type=FUDesc 688children=opList 689count=0 690opList=system.cpu1.fuPool.FUList4.opList 691 692[system.cpu1.fuPool.FUList4.opList] 693type=OpDesc 694issueLat=1 695opClass=MemRead 696opLat=1 697 698[system.cpu1.fuPool.FUList5] 699type=FUDesc 700children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 701count=4 702opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 703 704[system.cpu1.fuPool.FUList5.opList00] 705type=OpDesc 706issueLat=1 707opClass=SimdAdd 708opLat=1 709 710[system.cpu1.fuPool.FUList5.opList01] 711type=OpDesc 712issueLat=1 713opClass=SimdAddAcc 714opLat=1 715 716[system.cpu1.fuPool.FUList5.opList02] 717type=OpDesc 718issueLat=1 719opClass=SimdAlu 720opLat=1 721 722[system.cpu1.fuPool.FUList5.opList03] 723type=OpDesc 724issueLat=1 725opClass=SimdCmp 726opLat=1 727 728[system.cpu1.fuPool.FUList5.opList04] 729type=OpDesc 730issueLat=1 731opClass=SimdCvt 732opLat=1 733 734[system.cpu1.fuPool.FUList5.opList05] 735type=OpDesc 736issueLat=1 737opClass=SimdMisc 738opLat=1 739 740[system.cpu1.fuPool.FUList5.opList06] 741type=OpDesc 742issueLat=1 743opClass=SimdMult 744opLat=1 745 746[system.cpu1.fuPool.FUList5.opList07] 747type=OpDesc 748issueLat=1 749opClass=SimdMultAcc 750opLat=1 751 752[system.cpu1.fuPool.FUList5.opList08] 753type=OpDesc 754issueLat=1 755opClass=SimdShift 756opLat=1 757 758[system.cpu1.fuPool.FUList5.opList09] 759type=OpDesc 760issueLat=1 761opClass=SimdShiftAcc 762opLat=1 763 764[system.cpu1.fuPool.FUList5.opList10] 765type=OpDesc 766issueLat=1 767opClass=SimdSqrt 768opLat=1 769 770[system.cpu1.fuPool.FUList5.opList11] 771type=OpDesc 772issueLat=1 773opClass=SimdFloatAdd 774opLat=1 775 776[system.cpu1.fuPool.FUList5.opList12] 777type=OpDesc 778issueLat=1 779opClass=SimdFloatAlu 780opLat=1 781 782[system.cpu1.fuPool.FUList5.opList13] 783type=OpDesc 784issueLat=1 785opClass=SimdFloatCmp 786opLat=1 787 788[system.cpu1.fuPool.FUList5.opList14] 789type=OpDesc 790issueLat=1 791opClass=SimdFloatCvt 792opLat=1 793 794[system.cpu1.fuPool.FUList5.opList15] 795type=OpDesc 796issueLat=1 797opClass=SimdFloatDiv 798opLat=1 799 800[system.cpu1.fuPool.FUList5.opList16] 801type=OpDesc 802issueLat=1 803opClass=SimdFloatMisc 804opLat=1 805 806[system.cpu1.fuPool.FUList5.opList17] 807type=OpDesc 808issueLat=1 809opClass=SimdFloatMult 810opLat=1 811 812[system.cpu1.fuPool.FUList5.opList18] 813type=OpDesc 814issueLat=1 815opClass=SimdFloatMultAcc 816opLat=1 817 818[system.cpu1.fuPool.FUList5.opList19] 819type=OpDesc 820issueLat=1 821opClass=SimdFloatSqrt 822opLat=1 823 824[system.cpu1.fuPool.FUList6] 825type=FUDesc 826children=opList 827count=0 828opList=system.cpu1.fuPool.FUList6.opList 829 830[system.cpu1.fuPool.FUList6.opList] 831type=OpDesc 832issueLat=1 833opClass=MemWrite 834opLat=1 835 836[system.cpu1.fuPool.FUList7] 837type=FUDesc 838children=opList0 opList1 839count=4 840opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 841 842[system.cpu1.fuPool.FUList7.opList0] 843type=OpDesc 844issueLat=1 845opClass=MemRead 846opLat=1 847 848[system.cpu1.fuPool.FUList7.opList1] 849type=OpDesc 850issueLat=1 851opClass=MemWrite 852opLat=1 853 854[system.cpu1.fuPool.FUList8] 855type=FUDesc 856children=opList 857count=1 858opList=system.cpu1.fuPool.FUList8.opList 859 860[system.cpu1.fuPool.FUList8.opList] 861type=OpDesc 862issueLat=3 863opClass=IprAccess 864opLat=3 865 866[system.cpu1.icache] 867type=BaseCache 868addr_ranges=0:18446744073709551615 869assoc=1 870block_size=64 871clock=500 872forward_snoops=true 873hit_latency=2 874is_top_level=true 875max_miss_count=0 876mshrs=4 877prefetch_on_access=false 878prefetcher=Null 879response_latency=2 880size=32768 881system=system 882tgts_per_mshr=20 883two_queue=false 884write_buffers=8 885cpu_side=system.cpu1.icache_port 886mem_side=system.toL2Bus.slave[2] 887 888[system.cpu1.interrupts] 889type=AlphaInterrupts 890 891[system.cpu1.isa] 892type=AlphaISA 893 894[system.cpu1.itb] 895type=AlphaTLB 896size=48 897 898[system.cpu1.tracer] 899type=ExeTracer 900 901[system.disk0] 902type=IdeDisk 903children=image 904delay=1000000 905driveID=master 906image=system.disk0.image 907 908[system.disk0.image] 909type=CowDiskImage 910children=child 911child=system.disk0.image.child 912image_file= 913read_only=false 914table_size=65536 915 916[system.disk0.image.child] 917type=RawDiskImage 918image_file=/dist/m5/system/disks/linux-latest.img 919read_only=true 920 921[system.disk2] 922type=IdeDisk 923children=image 924delay=1000000 925driveID=master 926image=system.disk2.image 927 928[system.disk2.image] 929type=CowDiskImage 930children=child 931child=system.disk2.image.child 932image_file= 933read_only=false 934table_size=65536 935 936[system.disk2.image.child] 937type=RawDiskImage 938image_file=/dist/m5/system/disks/linux-bigswap2.img 939read_only=true 940 941[system.intrctrl] 942type=IntrControl 943sys=system 944 945[system.iobus] 946type=NoncoherentBus 947block_size=64 948clock=1000 949header_cycles=1 950use_default_range=true 951width=8 952default=system.tsunami.pciconfig.pio 953master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 954slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 955 956[system.iocache] 957type=BaseCache 958addr_ranges=0:134217727 959assoc=8 960block_size=64 961clock=1000 962forward_snoops=false 963hit_latency=50 964is_top_level=true 965max_miss_count=0 966mshrs=20 967prefetch_on_access=false 968prefetcher=Null 969response_latency=50 970size=1024 971system=system 972tgts_per_mshr=12 973two_queue=false 974write_buffers=8 975cpu_side=system.iobus.master[29] 976mem_side=system.membus.slave[2] 977 978[system.l2c] 979type=BaseCache 980addr_ranges=0:18446744073709551615 981assoc=8 982block_size=64 983clock=500 984forward_snoops=true 985hit_latency=20 986is_top_level=false 987max_miss_count=0 988mshrs=20 989prefetch_on_access=false 990prefetcher=Null 991response_latency=20 992size=4194304 993system=system 994tgts_per_mshr=12 995two_queue=false 996write_buffers=8 997cpu_side=system.toL2Bus.master[0] 998mem_side=system.membus.slave[1] 999 1000[system.membus] 1001type=CoherentBus 1002children=badaddr_responder 1003block_size=64 1004clock=1000 1005header_cycles=1 1006system=system 1007use_default_range=false 1008width=8 1009default=system.membus.badaddr_responder.pio 1010master=system.bridge.slave system.physmem.port 1011slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1012 1013[system.membus.badaddr_responder] 1014type=IsaFake 1015clock=1000 1016fake_mem=false 1017pio_addr=0 1018pio_latency=100000 1019pio_size=8 1020ret_bad_addr=true 1021ret_data16=65535 1022ret_data32=4294967295 1023ret_data64=18446744073709551615 1024ret_data8=255 1025system=system 1026update_data=false 1027warn_access= 1028pio=system.membus.default 1029 1030[system.physmem] 1031type=SimpleDRAM 1032activation_limit=4 1033addr_mapping=openmap 1034banks_per_rank=8 1035channels=1 1036clock=1000 1037conf_table_reported=false 1038in_addr_map=true 1039lines_per_rowbuffer=32 1040mem_sched_policy=frfcfs 1041null=false 1042page_policy=open 1043range=0:134217727 1044ranks_per_channel=2 1045read_buffer_size=32 1046tBURST=5000 1047tCL=13750 1048tRCD=13750 1049tREFI=7800000 1050tRFC=300000 1051tRP=13750 1052tWTR=7500 1053tXAW=40000 1054write_buffer_size=32 1055write_thresh_perc=70 1056zero=false 1057port=system.membus.master[1] 1058 1059[system.simple_disk] 1060type=SimpleDisk 1061children=disk 1062disk=system.simple_disk.disk 1063system=system 1064 1065[system.simple_disk.disk] 1066type=RawDiskImage 1067image_file=/dist/m5/system/disks/linux-latest.img 1068read_only=true 1069 1070[system.terminal] 1071type=Terminal 1072intr_control=system.intrctrl 1073number=0 1074output=true 1075port=3456 1076 1077[system.toL2Bus] 1078type=CoherentBus 1079block_size=64 1080clock=500 1081header_cycles=1 1082system=system 1083use_default_range=false 1084width=8 1085master=system.l2c.cpu_side 1086slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1087 1088[system.tsunami] 1089type=Tsunami 1090children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1091intrctrl=system.intrctrl 1092system=system 1093 1094[system.tsunami.backdoor] 1095type=AlphaBackdoor 1096clock=1000 1097cpu=system.cpu0 1098disk=system.simple_disk 1099pio_addr=8804682956800 1100pio_latency=100000 1101platform=system.tsunami 1102system=system 1103terminal=system.terminal 1104pio=system.iobus.master[24] 1105 1106[system.tsunami.cchip] 1107type=TsunamiCChip 1108clock=1000 1109pio_addr=8803072344064 1110pio_latency=100000 1111system=system 1112tsunami=system.tsunami 1113pio=system.iobus.master[0] 1114 1115[system.tsunami.ethernet] 1116type=NSGigE 1117BAR0=1 1118BAR0LegacyIO=false 1119BAR0Size=256 1120BAR1=0 1121BAR1LegacyIO=false 1122BAR1Size=4096 1123BAR2=0 1124BAR2LegacyIO=false 1125BAR2Size=0 1126BAR3=0 1127BAR3LegacyIO=false 1128BAR3Size=0 1129BAR4=0 1130BAR4LegacyIO=false 1131BAR4Size=0 1132BAR5=0 1133BAR5LegacyIO=false 1134BAR5Size=0 1135BIST=0 1136CacheLineSize=0 1137CardbusCIS=0 1138ClassCode=2 1139Command=0 1140DeviceID=34 1141ExpansionROM=0 1142HeaderType=0 1143InterruptLine=30 1144InterruptPin=1 1145LatencyTimer=0 1146MaximumLatency=52 1147MinimumGrant=176 1148ProgIF=0 1149Revision=0 1150Status=656 1151SubClassCode=0 1152SubsystemID=0 1153SubsystemVendorID=0 1154VendorID=4107 1155clock=2000 1156config_latency=20000 1157dma_data_free=false 1158dma_desc_free=false 1159dma_no_allocate=true 1160dma_read_delay=0 1161dma_read_factor=0 1162dma_write_delay=0 1163dma_write_factor=0 1164hardware_address=00:90:00:00:00:01 1165intr_delay=10000000 1166pci_bus=0 1167pci_dev=1 1168pci_func=0 1169pio_latency=30000 1170platform=system.tsunami 1171rss=false 1172rx_delay=1000000 1173rx_fifo_size=524288 1174rx_filter=true 1175rx_thread=false 1176system=system 1177tx_delay=1000000 1178tx_fifo_size=524288 1179tx_thread=false 1180config=system.iobus.master[28] 1181dma=system.iobus.slave[2] 1182pio=system.iobus.master[27] 1183 1184[system.tsunami.fake_OROM] 1185type=IsaFake 1186clock=1000 1187fake_mem=false 1188pio_addr=8796093677568 1189pio_latency=100000 1190pio_size=393216 1191ret_bad_addr=false 1192ret_data16=65535 1193ret_data32=4294967295 1194ret_data64=18446744073709551615 1195ret_data8=255 1196system=system 1197update_data=false 1198warn_access= 1199pio=system.iobus.master[8] 1200 1201[system.tsunami.fake_ata0] 1202type=IsaFake 1203clock=1000 1204fake_mem=false 1205pio_addr=8804615848432 1206pio_latency=100000 1207pio_size=8 1208ret_bad_addr=false 1209ret_data16=65535 1210ret_data32=4294967295 1211ret_data64=18446744073709551615 1212ret_data8=255 1213system=system 1214update_data=false 1215warn_access= 1216pio=system.iobus.master[19] 1217 1218[system.tsunami.fake_ata1] 1219type=IsaFake 1220clock=1000 1221fake_mem=false 1222pio_addr=8804615848304 1223pio_latency=100000 1224pio_size=8 1225ret_bad_addr=false 1226ret_data16=65535 1227ret_data32=4294967295 1228ret_data64=18446744073709551615 1229ret_data8=255 1230system=system 1231update_data=false 1232warn_access= 1233pio=system.iobus.master[20] 1234 1235[system.tsunami.fake_pnp_addr] 1236type=IsaFake 1237clock=1000 1238fake_mem=false 1239pio_addr=8804615848569 1240pio_latency=100000 1241pio_size=8 1242ret_bad_addr=false 1243ret_data16=65535 1244ret_data32=4294967295 1245ret_data64=18446744073709551615 1246ret_data8=255 1247system=system 1248update_data=false 1249warn_access= 1250pio=system.iobus.master[9] 1251 1252[system.tsunami.fake_pnp_read0] 1253type=IsaFake 1254clock=1000 1255fake_mem=false 1256pio_addr=8804615848451 1257pio_latency=100000 1258pio_size=8 1259ret_bad_addr=false 1260ret_data16=65535 1261ret_data32=4294967295 1262ret_data64=18446744073709551615 1263ret_data8=255 1264system=system 1265update_data=false 1266warn_access= 1267pio=system.iobus.master[11] 1268 1269[system.tsunami.fake_pnp_read1] 1270type=IsaFake 1271clock=1000 1272fake_mem=false 1273pio_addr=8804615848515 1274pio_latency=100000 1275pio_size=8 1276ret_bad_addr=false 1277ret_data16=65535 1278ret_data32=4294967295 1279ret_data64=18446744073709551615 1280ret_data8=255 1281system=system 1282update_data=false 1283warn_access= 1284pio=system.iobus.master[12] 1285 1286[system.tsunami.fake_pnp_read2] 1287type=IsaFake 1288clock=1000 1289fake_mem=false 1290pio_addr=8804615848579 1291pio_latency=100000 1292pio_size=8 1293ret_bad_addr=false 1294ret_data16=65535 1295ret_data32=4294967295 1296ret_data64=18446744073709551615 1297ret_data8=255 1298system=system 1299update_data=false 1300warn_access= 1301pio=system.iobus.master[13] 1302 1303[system.tsunami.fake_pnp_read3] 1304type=IsaFake 1305clock=1000 1306fake_mem=false 1307pio_addr=8804615848643 1308pio_latency=100000 1309pio_size=8 1310ret_bad_addr=false 1311ret_data16=65535 1312ret_data32=4294967295 1313ret_data64=18446744073709551615 1314ret_data8=255 1315system=system 1316update_data=false 1317warn_access= 1318pio=system.iobus.master[14] 1319 1320[system.tsunami.fake_pnp_read4] 1321type=IsaFake 1322clock=1000 1323fake_mem=false 1324pio_addr=8804615848707 1325pio_latency=100000 1326pio_size=8 1327ret_bad_addr=false 1328ret_data16=65535 1329ret_data32=4294967295 1330ret_data64=18446744073709551615 1331ret_data8=255 1332system=system 1333update_data=false 1334warn_access= 1335pio=system.iobus.master[15] 1336 1337[system.tsunami.fake_pnp_read5] 1338type=IsaFake 1339clock=1000 1340fake_mem=false 1341pio_addr=8804615848771 1342pio_latency=100000 1343pio_size=8 1344ret_bad_addr=false 1345ret_data16=65535 1346ret_data32=4294967295 1347ret_data64=18446744073709551615 1348ret_data8=255 1349system=system 1350update_data=false 1351warn_access= 1352pio=system.iobus.master[16] 1353 1354[system.tsunami.fake_pnp_read6] 1355type=IsaFake 1356clock=1000 1357fake_mem=false 1358pio_addr=8804615848835 1359pio_latency=100000 1360pio_size=8 1361ret_bad_addr=false 1362ret_data16=65535 1363ret_data32=4294967295 1364ret_data64=18446744073709551615 1365ret_data8=255 1366system=system 1367update_data=false 1368warn_access= 1369pio=system.iobus.master[17] 1370 1371[system.tsunami.fake_pnp_read7] 1372type=IsaFake 1373clock=1000 1374fake_mem=false 1375pio_addr=8804615848899 1376pio_latency=100000 1377pio_size=8 1378ret_bad_addr=false 1379ret_data16=65535 1380ret_data32=4294967295 1381ret_data64=18446744073709551615 1382ret_data8=255 1383system=system 1384update_data=false 1385warn_access= 1386pio=system.iobus.master[18] 1387 1388[system.tsunami.fake_pnp_write] 1389type=IsaFake 1390clock=1000 1391fake_mem=false 1392pio_addr=8804615850617 1393pio_latency=100000 1394pio_size=8 1395ret_bad_addr=false 1396ret_data16=65535 1397ret_data32=4294967295 1398ret_data64=18446744073709551615 1399ret_data8=255 1400system=system 1401update_data=false 1402warn_access= 1403pio=system.iobus.master[10] 1404 1405[system.tsunami.fake_ppc] 1406type=IsaFake 1407clock=1000 1408fake_mem=false 1409pio_addr=8804615848891 1410pio_latency=100000 1411pio_size=8 1412ret_bad_addr=false 1413ret_data16=65535 1414ret_data32=4294967295 1415ret_data64=18446744073709551615 1416ret_data8=255 1417system=system 1418update_data=false 1419warn_access= 1420pio=system.iobus.master[7] 1421 1422[system.tsunami.fake_sm_chip] 1423type=IsaFake 1424clock=1000 1425fake_mem=false 1426pio_addr=8804615848816 1427pio_latency=100000 1428pio_size=8 1429ret_bad_addr=false 1430ret_data16=65535 1431ret_data32=4294967295 1432ret_data64=18446744073709551615 1433ret_data8=255 1434system=system 1435update_data=false 1436warn_access= 1437pio=system.iobus.master[2] 1438 1439[system.tsunami.fake_uart1] 1440type=IsaFake 1441clock=1000 1442fake_mem=false 1443pio_addr=8804615848696 1444pio_latency=100000 1445pio_size=8 1446ret_bad_addr=false 1447ret_data16=65535 1448ret_data32=4294967295 1449ret_data64=18446744073709551615 1450ret_data8=255 1451system=system 1452update_data=false 1453warn_access= 1454pio=system.iobus.master[3] 1455 1456[system.tsunami.fake_uart2] 1457type=IsaFake 1458clock=1000 1459fake_mem=false 1460pio_addr=8804615848936 1461pio_latency=100000 1462pio_size=8 1463ret_bad_addr=false 1464ret_data16=65535 1465ret_data32=4294967295 1466ret_data64=18446744073709551615 1467ret_data8=255 1468system=system 1469update_data=false 1470warn_access= 1471pio=system.iobus.master[4] 1472 1473[system.tsunami.fake_uart3] 1474type=IsaFake 1475clock=1000 1476fake_mem=false 1477pio_addr=8804615848680 1478pio_latency=100000 1479pio_size=8 1480ret_bad_addr=false 1481ret_data16=65535 1482ret_data32=4294967295 1483ret_data64=18446744073709551615 1484ret_data8=255 1485system=system 1486update_data=false 1487warn_access= 1488pio=system.iobus.master[5] 1489 1490[system.tsunami.fake_uart4] 1491type=IsaFake 1492clock=1000 1493fake_mem=false 1494pio_addr=8804615848944 1495pio_latency=100000 1496pio_size=8 1497ret_bad_addr=false 1498ret_data16=65535 1499ret_data32=4294967295 1500ret_data64=18446744073709551615 1501ret_data8=255 1502system=system 1503update_data=false 1504warn_access= 1505pio=system.iobus.master[6] 1506 1507[system.tsunami.fb] 1508type=BadDevice 1509clock=1000 1510devicename=FrameBuffer 1511pio_addr=8804615848912 1512pio_latency=100000 1513system=system 1514pio=system.iobus.master[21] 1515 1516[system.tsunami.ide] 1517type=IdeController 1518BAR0=1 1519BAR0LegacyIO=false 1520BAR0Size=8 1521BAR1=1 1522BAR1LegacyIO=false 1523BAR1Size=4 1524BAR2=1 1525BAR2LegacyIO=false 1526BAR2Size=8 1527BAR3=1 1528BAR3LegacyIO=false 1529BAR3Size=4 1530BAR4=1 1531BAR4LegacyIO=false 1532BAR4Size=16 1533BAR5=1 1534BAR5LegacyIO=false 1535BAR5Size=0 1536BIST=0 1537CacheLineSize=0 1538CardbusCIS=0 1539ClassCode=1 1540Command=0 1541DeviceID=28945 1542ExpansionROM=0 1543HeaderType=0 1544InterruptLine=31 1545InterruptPin=1 1546LatencyTimer=0 1547MaximumLatency=0 1548MinimumGrant=0 1549ProgIF=133 1550Revision=0 1551Status=640 1552SubClassCode=1 1553SubsystemID=0 1554SubsystemVendorID=0 1555VendorID=32902 1556clock=1000 1557config_latency=20000 1558ctrl_offset=0 1559disks=system.disk0 system.disk2 1560io_shift=0 1561pci_bus=0 1562pci_dev=0 1563pci_func=0 1564pio_latency=30000 1565platform=system.tsunami 1566system=system 1567config=system.iobus.master[26] 1568dma=system.iobus.slave[1] 1569pio=system.iobus.master[25] 1570 1571[system.tsunami.io] 1572type=TsunamiIO 1573clock=1000 1574frequency=976562500 1575pio_addr=8804615847936 1576pio_latency=100000 1577system=system 1578time=Thu Jan 1 00:00:00 2009 1579tsunami=system.tsunami 1580year_is_bcd=false 1581pio=system.iobus.master[22] 1582 1583[system.tsunami.pchip] 1584type=TsunamiPChip 1585clock=1000 1586pio_addr=8802535473152 1587pio_latency=100000 1588system=system 1589tsunami=system.tsunami 1590pio=system.iobus.master[1] 1591 1592[system.tsunami.pciconfig] 1593type=PciConfigAll 1594bus=0 1595clock=1000 1596pio_latency=30000 1597platform=system.tsunami 1598size=16777216 1599system=system 1600pio=system.iobus.default 1601 1602[system.tsunami.uart] 1603type=Uart8250 1604clock=1000 1605pio_addr=8804615848952 1606pio_latency=100000 1607platform=system.tsunami 1608system=system 1609terminal=system.terminal 1610pio=system.iobus.master[23] 1611 1612