config.ini revision 11570
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain 18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing 28mem_ranges=0:134217727 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh 39symbolfile= 40system_rev=1024 41system_type=34 42thermal_components= 43thermal_model=Null 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null 63ranges=8796093022208:18446744073709551615 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 72domain_id=-1 73eventq_index=0 74init_perf_level=0 75voltage_domain=system.voltage_domain 76 77[system.cpu0] 78type=DerivO3CPU 79children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 80LFSTSize=1024 81LQEntries=32 82LSQCheckLoads=true 83LSQDepCheckShift=4 84SQEntries=32 85SSITSize=1024 86activity=0 87backComSize=5 88branchPred=system.cpu0.branchPred 89cachePorts=200 90checker=Null 91clk_domain=system.cpu_clk_domain 92commitToDecodeDelay=1 93commitToFetchDelay=1 94commitToIEWDelay=1 95commitToRenameDelay=1 96commitWidth=8 97cpu_id=0 98decodeToFetchDelay=1 99decodeToRenameDelay=1 100decodeWidth=8 101default_p_state=UNDEFINED 102dispatchWidth=8 103do_checkpoint_insts=true 104do_quiesce=true 105do_statistics_insts=true 106dtb=system.cpu0.dtb 107eventq_index=0 108fetchBufferSize=64 109fetchQueueSize=32 110fetchToDecodeDelay=1 111fetchTrapLatency=1 112fetchWidth=8 113forwardComSize=5 114fuPool=system.cpu0.fuPool 115function_trace=false 116function_trace_start=0 117iewToCommitDelay=1 118iewToDecodeDelay=1 119iewToFetchDelay=1 120iewToRenameDelay=1 121interrupts=system.cpu0.interrupts 122isa=system.cpu0.isa 123issueToExecuteDelay=1 124issueWidth=8 125itb=system.cpu0.itb 126max_insts_all_threads=0 127max_insts_any_thread=0 128max_loads_all_threads=0 129max_loads_any_thread=0 130needsTSO=false 131numIQEntries=64 132numPhysCCRegs=0 133numPhysFloatRegs=256 134numPhysIntRegs=256 135numROBEntries=192 136numRobs=1 137numThreads=1 138p_state_clk_gate_bins=20 139p_state_clk_gate_max=1000000000000 140p_state_clk_gate_min=1000 141power_model=Null 142profile=0 143progress_interval=0 144renameToDecodeDelay=1 145renameToFetchDelay=1 146renameToIEWDelay=2 147renameToROBDelay=1 148renameWidth=8 149simpoint_start_insts= 150smtCommitPolicy=RoundRobin 151smtFetchPolicy=SingleThread 152smtIQPolicy=Partitioned 153smtIQThreshold=100 154smtLSQPolicy=Partitioned 155smtLSQThreshold=100 156smtNumFetchingThreads=1 157smtROBPolicy=Partitioned 158smtROBThreshold=100 159socket_id=0 160squashWidth=8 161store_set_clear_period=250000 162switched_out=false 163system=system 164tracer=system.cpu0.tracer 165trapLatency=13 166wbWidth=8 167workload= 168dcache_port=system.cpu0.dcache.cpu_side 169icache_port=system.cpu0.icache.cpu_side 170 171[system.cpu0.branchPred] 172type=TournamentBP 173BTBEntries=4096 174BTBTagSize=16 175RASSize=16 176choiceCtrBits=2 177choicePredictorSize=8192 178eventq_index=0 179globalCtrBits=2 180globalPredictorSize=8192 181indirectHashGHR=true 182indirectHashTargets=true 183indirectPathLength=3 184indirectSets=256 185indirectTagSize=16 186indirectWays=2 187instShiftAmt=2 188localCtrBits=2 189localHistoryTableSize=2048 190localPredictorSize=2048 191numThreads=1 192useIndirect=true 193 194[system.cpu0.dcache] 195type=Cache 196children=tags 197addr_ranges=0:18446744073709551615 198assoc=4 199clk_domain=system.cpu_clk_domain 200clusivity=mostly_incl 201default_p_state=UNDEFINED 202demand_mshr_reserve=1 203eventq_index=0 204hit_latency=2 205is_read_only=false 206max_miss_count=0 207mshrs=4 208p_state_clk_gate_bins=20 209p_state_clk_gate_max=1000000000000 210p_state_clk_gate_min=1000 211power_model=Null 212prefetch_on_access=false 213prefetcher=Null 214response_latency=2 215sequential_access=false 216size=32768 217system=system 218tags=system.cpu0.dcache.tags 219tgts_per_mshr=20 220write_buffers=8 221writeback_clean=false 222cpu_side=system.cpu0.dcache_port 223mem_side=system.toL2Bus.slave[1] 224 225[system.cpu0.dcache.tags] 226type=LRU 227assoc=4 228block_size=64 229clk_domain=system.cpu_clk_domain 230default_p_state=UNDEFINED 231eventq_index=0 232hit_latency=2 233p_state_clk_gate_bins=20 234p_state_clk_gate_max=1000000000000 235p_state_clk_gate_min=1000 236power_model=Null 237sequential_access=false 238size=32768 239 240[system.cpu0.dtb] 241type=AlphaTLB 242eventq_index=0 243size=64 244 245[system.cpu0.fuPool] 246type=FUPool 247children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 248FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 249eventq_index=0 250 251[system.cpu0.fuPool.FUList0] 252type=FUDesc 253children=opList 254count=6 255eventq_index=0 256opList=system.cpu0.fuPool.FUList0.opList 257 258[system.cpu0.fuPool.FUList0.opList] 259type=OpDesc 260eventq_index=0 261opClass=IntAlu 262opLat=1 263pipelined=true 264 265[system.cpu0.fuPool.FUList1] 266type=FUDesc 267children=opList0 opList1 268count=2 269eventq_index=0 270opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 271 272[system.cpu0.fuPool.FUList1.opList0] 273type=OpDesc 274eventq_index=0 275opClass=IntMult 276opLat=3 277pipelined=true 278 279[system.cpu0.fuPool.FUList1.opList1] 280type=OpDesc 281eventq_index=0 282opClass=IntDiv 283opLat=20 284pipelined=false 285 286[system.cpu0.fuPool.FUList2] 287type=FUDesc 288children=opList0 opList1 opList2 289count=4 290eventq_index=0 291opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 292 293[system.cpu0.fuPool.FUList2.opList0] 294type=OpDesc 295eventq_index=0 296opClass=FloatAdd 297opLat=2 298pipelined=true 299 300[system.cpu0.fuPool.FUList2.opList1] 301type=OpDesc 302eventq_index=0 303opClass=FloatCmp 304opLat=2 305pipelined=true 306 307[system.cpu0.fuPool.FUList2.opList2] 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu0.fuPool.FUList3] 315type=FUDesc 316children=opList0 opList1 opList2 317count=2 318eventq_index=0 319opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 320 321[system.cpu0.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu0.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0 331opClass=FloatDiv 332opLat=12 333pipelined=false 334 335[system.cpu0.fuPool.FUList3.opList2] 336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu0.fuPool.FUList4] 343type=FUDesc 344children=opList 345count=0 346eventq_index=0 347opList=system.cpu0.fuPool.FUList4.opList 348 349[system.cpu0.fuPool.FUList4.opList] 350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355 356[system.cpu0.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 362 363[system.cpu0.fuPool.FUList5.opList00] 364type=OpDesc 365eventq_index=0 366opClass=SimdAdd 367opLat=1 368pipelined=true 369 370[system.cpu0.fuPool.FUList5.opList01] 371type=OpDesc 372eventq_index=0 373opClass=SimdAddAcc 374opLat=1 375pipelined=true 376 377[system.cpu0.fuPool.FUList5.opList02] 378type=OpDesc 379eventq_index=0 380opClass=SimdAlu 381opLat=1 382pipelined=true 383 384[system.cpu0.fuPool.FUList5.opList03] 385type=OpDesc 386eventq_index=0 387opClass=SimdCmp 388opLat=1 389pipelined=true 390 391[system.cpu0.fuPool.FUList5.opList04] 392type=OpDesc 393eventq_index=0 394opClass=SimdCvt 395opLat=1 396pipelined=true 397 398[system.cpu0.fuPool.FUList5.opList05] 399type=OpDesc 400eventq_index=0 401opClass=SimdMisc 402opLat=1 403pipelined=true 404 405[system.cpu0.fuPool.FUList5.opList06] 406type=OpDesc 407eventq_index=0 408opClass=SimdMult 409opLat=1 410pipelined=true 411 412[system.cpu0.fuPool.FUList5.opList07] 413type=OpDesc 414eventq_index=0 415opClass=SimdMultAcc 416opLat=1 417pipelined=true 418 419[system.cpu0.fuPool.FUList5.opList08] 420type=OpDesc 421eventq_index=0 422opClass=SimdShift 423opLat=1 424pipelined=true 425 426[system.cpu0.fuPool.FUList5.opList09] 427type=OpDesc 428eventq_index=0 429opClass=SimdShiftAcc 430opLat=1 431pipelined=true 432 433[system.cpu0.fuPool.FUList5.opList10] 434type=OpDesc 435eventq_index=0 436opClass=SimdSqrt 437opLat=1 438pipelined=true 439 440[system.cpu0.fuPool.FUList5.opList11] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatAdd 444opLat=1 445pipelined=true 446 447[system.cpu0.fuPool.FUList5.opList12] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatAlu 451opLat=1 452pipelined=true 453 454[system.cpu0.fuPool.FUList5.opList13] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatCmp 458opLat=1 459pipelined=true 460 461[system.cpu0.fuPool.FUList5.opList14] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatCvt 465opLat=1 466pipelined=true 467 468[system.cpu0.fuPool.FUList5.opList15] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatDiv 472opLat=1 473pipelined=true 474 475[system.cpu0.fuPool.FUList5.opList16] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatMisc 479opLat=1 480pipelined=true 481 482[system.cpu0.fuPool.FUList5.opList17] 483type=OpDesc 484eventq_index=0 485opClass=SimdFloatMult 486opLat=1 487pipelined=true 488 489[system.cpu0.fuPool.FUList5.opList18] 490type=OpDesc 491eventq_index=0 492opClass=SimdFloatMultAcc 493opLat=1 494pipelined=true 495 496[system.cpu0.fuPool.FUList5.opList19] 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu0.fuPool.FUList6] 504type=FUDesc 505children=opList 506count=0 507eventq_index=0 508opList=system.cpu0.fuPool.FUList6.opList 509 510[system.cpu0.fuPool.FUList6.opList] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 517[system.cpu0.fuPool.FUList7] 518type=FUDesc 519children=opList0 opList1 520count=4 521eventq_index=0 522opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 523 524[system.cpu0.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu0.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537 538[system.cpu0.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu0.fuPool.FUList8.opList 544 545[system.cpu0.fuPool.FUList8.opList] 546type=OpDesc 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu0.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615 556assoc=1 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 562hit_latency=2 563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=32768 575system=system 576tags=system.cpu0.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu0.icache_port 581mem_side=system.toL2Bus.slave[0] 582 583[system.cpu0.icache.tags] 584type=LRU 585assoc=1 586block_size=64 587clk_domain=system.cpu_clk_domain 588default_p_state=UNDEFINED 589eventq_index=0 590hit_latency=2 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=32768 597 598[system.cpu0.interrupts] 599type=AlphaInterrupts 600eventq_index=0 601 602[system.cpu0.isa] 603type=AlphaISA 604eventq_index=0 605system=system 606 607[system.cpu0.itb] 608type=AlphaTLB 609eventq_index=0 610size=48 611 612[system.cpu0.tracer] 613type=ExeTracer 614eventq_index=0 615 616[system.cpu1] 617type=DerivO3CPU 618children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 619LFSTSize=1024 620LQEntries=32 621LSQCheckLoads=true 622LSQDepCheckShift=4 623SQEntries=32 624SSITSize=1024 625activity=0 626backComSize=5 627branchPred=system.cpu1.branchPred 628cachePorts=200 629checker=Null 630clk_domain=system.cpu_clk_domain 631commitToDecodeDelay=1 632commitToFetchDelay=1 633commitToIEWDelay=1 634commitToRenameDelay=1 635commitWidth=8 636cpu_id=1 637decodeToFetchDelay=1 638decodeToRenameDelay=1 639decodeWidth=8 640default_p_state=UNDEFINED 641dispatchWidth=8 642do_checkpoint_insts=true 643do_quiesce=true 644do_statistics_insts=true 645dtb=system.cpu1.dtb 646eventq_index=0 647fetchBufferSize=64 648fetchQueueSize=32 649fetchToDecodeDelay=1 650fetchTrapLatency=1 651fetchWidth=8 652forwardComSize=5 653fuPool=system.cpu1.fuPool 654function_trace=false 655function_trace_start=0 656iewToCommitDelay=1 657iewToDecodeDelay=1 658iewToFetchDelay=1 659iewToRenameDelay=1 660interrupts=system.cpu1.interrupts 661isa=system.cpu1.isa 662issueToExecuteDelay=1 663issueWidth=8 664itb=system.cpu1.itb 665max_insts_all_threads=0 666max_insts_any_thread=0 667max_loads_all_threads=0 668max_loads_any_thread=0 669needsTSO=false 670numIQEntries=64 671numPhysCCRegs=0 672numPhysFloatRegs=256 673numPhysIntRegs=256 674numROBEntries=192 675numRobs=1 676numThreads=1 677p_state_clk_gate_bins=20 678p_state_clk_gate_max=1000000000000 679p_state_clk_gate_min=1000 680power_model=Null 681profile=0 682progress_interval=0 683renameToDecodeDelay=1 684renameToFetchDelay=1 685renameToIEWDelay=2 686renameToROBDelay=1 687renameWidth=8 688simpoint_start_insts= 689smtCommitPolicy=RoundRobin 690smtFetchPolicy=SingleThread 691smtIQPolicy=Partitioned 692smtIQThreshold=100 693smtLSQPolicy=Partitioned 694smtLSQThreshold=100 695smtNumFetchingThreads=1 696smtROBPolicy=Partitioned 697smtROBThreshold=100 698socket_id=0 699squashWidth=8 700store_set_clear_period=250000 701switched_out=false 702system=system 703tracer=system.cpu1.tracer 704trapLatency=13 705wbWidth=8 706workload= 707dcache_port=system.cpu1.dcache.cpu_side 708icache_port=system.cpu1.icache.cpu_side 709 710[system.cpu1.branchPred] 711type=TournamentBP 712BTBEntries=4096 713BTBTagSize=16 714RASSize=16 715choiceCtrBits=2 716choicePredictorSize=8192 717eventq_index=0 718globalCtrBits=2 719globalPredictorSize=8192 720indirectHashGHR=true 721indirectHashTargets=true 722indirectPathLength=3 723indirectSets=256 724indirectTagSize=16 725indirectWays=2 726instShiftAmt=2 727localCtrBits=2 728localHistoryTableSize=2048 729localPredictorSize=2048 730numThreads=1 731useIndirect=true 732 733[system.cpu1.dcache] 734type=Cache 735children=tags 736addr_ranges=0:18446744073709551615 737assoc=4 738clk_domain=system.cpu_clk_domain 739clusivity=mostly_incl 740default_p_state=UNDEFINED 741demand_mshr_reserve=1 742eventq_index=0 743hit_latency=2 744is_read_only=false 745max_miss_count=0 746mshrs=4 747p_state_clk_gate_bins=20 748p_state_clk_gate_max=1000000000000 749p_state_clk_gate_min=1000 750power_model=Null 751prefetch_on_access=false 752prefetcher=Null 753response_latency=2 754sequential_access=false 755size=32768 756system=system 757tags=system.cpu1.dcache.tags 758tgts_per_mshr=20 759write_buffers=8 760writeback_clean=false 761cpu_side=system.cpu1.dcache_port 762mem_side=system.toL2Bus.slave[3] 763 764[system.cpu1.dcache.tags] 765type=LRU 766assoc=4 767block_size=64 768clk_domain=system.cpu_clk_domain 769default_p_state=UNDEFINED 770eventq_index=0 771hit_latency=2 772p_state_clk_gate_bins=20 773p_state_clk_gate_max=1000000000000 774p_state_clk_gate_min=1000 775power_model=Null 776sequential_access=false 777size=32768 778 779[system.cpu1.dtb] 780type=AlphaTLB 781eventq_index=0 782size=64 783 784[system.cpu1.fuPool] 785type=FUPool 786children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 787FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 788eventq_index=0 789 790[system.cpu1.fuPool.FUList0] 791type=FUDesc 792children=opList 793count=6 794eventq_index=0 795opList=system.cpu1.fuPool.FUList0.opList 796 797[system.cpu1.fuPool.FUList0.opList] 798type=OpDesc 799eventq_index=0 800opClass=IntAlu 801opLat=1 802pipelined=true 803 804[system.cpu1.fuPool.FUList1] 805type=FUDesc 806children=opList0 opList1 807count=2 808eventq_index=0 809opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 810 811[system.cpu1.fuPool.FUList1.opList0] 812type=OpDesc 813eventq_index=0 814opClass=IntMult 815opLat=3 816pipelined=true 817 818[system.cpu1.fuPool.FUList1.opList1] 819type=OpDesc 820eventq_index=0 821opClass=IntDiv 822opLat=20 823pipelined=false 824 825[system.cpu1.fuPool.FUList2] 826type=FUDesc 827children=opList0 opList1 opList2 828count=4 829eventq_index=0 830opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 831 832[system.cpu1.fuPool.FUList2.opList0] 833type=OpDesc 834eventq_index=0 835opClass=FloatAdd 836opLat=2 837pipelined=true 838 839[system.cpu1.fuPool.FUList2.opList1] 840type=OpDesc 841eventq_index=0 842opClass=FloatCmp 843opLat=2 844pipelined=true 845 846[system.cpu1.fuPool.FUList2.opList2] 847type=OpDesc 848eventq_index=0 849opClass=FloatCvt 850opLat=2 851pipelined=true 852 853[system.cpu1.fuPool.FUList3] 854type=FUDesc 855children=opList0 opList1 opList2 856count=2 857eventq_index=0 858opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 859 860[system.cpu1.fuPool.FUList3.opList0] 861type=OpDesc 862eventq_index=0 863opClass=FloatMult 864opLat=4 865pipelined=true 866 867[system.cpu1.fuPool.FUList3.opList1] 868type=OpDesc 869eventq_index=0 870opClass=FloatDiv 871opLat=12 872pipelined=false 873 874[system.cpu1.fuPool.FUList3.opList2] 875type=OpDesc 876eventq_index=0 877opClass=FloatSqrt 878opLat=24 879pipelined=false 880 881[system.cpu1.fuPool.FUList4] 882type=FUDesc 883children=opList 884count=0 885eventq_index=0 886opList=system.cpu1.fuPool.FUList4.opList 887 888[system.cpu1.fuPool.FUList4.opList] 889type=OpDesc 890eventq_index=0 891opClass=MemRead 892opLat=1 893pipelined=true 894 895[system.cpu1.fuPool.FUList5] 896type=FUDesc 897children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 898count=4 899eventq_index=0 900opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 901 902[system.cpu1.fuPool.FUList5.opList00] 903type=OpDesc 904eventq_index=0 905opClass=SimdAdd 906opLat=1 907pipelined=true 908 909[system.cpu1.fuPool.FUList5.opList01] 910type=OpDesc 911eventq_index=0 912opClass=SimdAddAcc 913opLat=1 914pipelined=true 915 916[system.cpu1.fuPool.FUList5.opList02] 917type=OpDesc 918eventq_index=0 919opClass=SimdAlu 920opLat=1 921pipelined=true 922 923[system.cpu1.fuPool.FUList5.opList03] 924type=OpDesc 925eventq_index=0 926opClass=SimdCmp 927opLat=1 928pipelined=true 929 930[system.cpu1.fuPool.FUList5.opList04] 931type=OpDesc 932eventq_index=0 933opClass=SimdCvt 934opLat=1 935pipelined=true 936 937[system.cpu1.fuPool.FUList5.opList05] 938type=OpDesc 939eventq_index=0 940opClass=SimdMisc 941opLat=1 942pipelined=true 943 944[system.cpu1.fuPool.FUList5.opList06] 945type=OpDesc 946eventq_index=0 947opClass=SimdMult 948opLat=1 949pipelined=true 950 951[system.cpu1.fuPool.FUList5.opList07] 952type=OpDesc 953eventq_index=0 954opClass=SimdMultAcc 955opLat=1 956pipelined=true 957 958[system.cpu1.fuPool.FUList5.opList08] 959type=OpDesc 960eventq_index=0 961opClass=SimdShift 962opLat=1 963pipelined=true 964 965[system.cpu1.fuPool.FUList5.opList09] 966type=OpDesc 967eventq_index=0 968opClass=SimdShiftAcc 969opLat=1 970pipelined=true 971 972[system.cpu1.fuPool.FUList5.opList10] 973type=OpDesc 974eventq_index=0 975opClass=SimdSqrt 976opLat=1 977pipelined=true 978 979[system.cpu1.fuPool.FUList5.opList11] 980type=OpDesc 981eventq_index=0 982opClass=SimdFloatAdd 983opLat=1 984pipelined=true 985 986[system.cpu1.fuPool.FUList5.opList12] 987type=OpDesc 988eventq_index=0 989opClass=SimdFloatAlu 990opLat=1 991pipelined=true 992 993[system.cpu1.fuPool.FUList5.opList13] 994type=OpDesc 995eventq_index=0 996opClass=SimdFloatCmp 997opLat=1 998pipelined=true 999 1000[system.cpu1.fuPool.FUList5.opList14] 1001type=OpDesc 1002eventq_index=0 1003opClass=SimdFloatCvt 1004opLat=1 1005pipelined=true 1006 1007[system.cpu1.fuPool.FUList5.opList15] 1008type=OpDesc 1009eventq_index=0 1010opClass=SimdFloatDiv 1011opLat=1 1012pipelined=true 1013 1014[system.cpu1.fuPool.FUList5.opList16] 1015type=OpDesc 1016eventq_index=0 1017opClass=SimdFloatMisc 1018opLat=1 1019pipelined=true 1020 1021[system.cpu1.fuPool.FUList5.opList17] 1022type=OpDesc 1023eventq_index=0 1024opClass=SimdFloatMult 1025opLat=1 1026pipelined=true 1027 1028[system.cpu1.fuPool.FUList5.opList18] 1029type=OpDesc 1030eventq_index=0 1031opClass=SimdFloatMultAcc 1032opLat=1 1033pipelined=true 1034 1035[system.cpu1.fuPool.FUList5.opList19] 1036type=OpDesc 1037eventq_index=0 1038opClass=SimdFloatSqrt 1039opLat=1 1040pipelined=true 1041 1042[system.cpu1.fuPool.FUList6] 1043type=FUDesc 1044children=opList 1045count=0 1046eventq_index=0 1047opList=system.cpu1.fuPool.FUList6.opList 1048 1049[system.cpu1.fuPool.FUList6.opList] 1050type=OpDesc 1051eventq_index=0 1052opClass=MemWrite 1053opLat=1 1054pipelined=true 1055 1056[system.cpu1.fuPool.FUList7] 1057type=FUDesc 1058children=opList0 opList1 1059count=4 1060eventq_index=0 1061opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 1062 1063[system.cpu1.fuPool.FUList7.opList0] 1064type=OpDesc 1065eventq_index=0 1066opClass=MemRead 1067opLat=1 1068pipelined=true 1069 1070[system.cpu1.fuPool.FUList7.opList1] 1071type=OpDesc 1072eventq_index=0 1073opClass=MemWrite 1074opLat=1 1075pipelined=true 1076 1077[system.cpu1.fuPool.FUList8] 1078type=FUDesc 1079children=opList 1080count=1 1081eventq_index=0 1082opList=system.cpu1.fuPool.FUList8.opList 1083 1084[system.cpu1.fuPool.FUList8.opList] 1085type=OpDesc 1086eventq_index=0 1087opClass=IprAccess 1088opLat=3 1089pipelined=false 1090 1091[system.cpu1.icache] 1092type=Cache 1093children=tags 1094addr_ranges=0:18446744073709551615 1095assoc=1 1096clk_domain=system.cpu_clk_domain 1097clusivity=mostly_incl 1098default_p_state=UNDEFINED 1099demand_mshr_reserve=1 1100eventq_index=0 1101hit_latency=2 1102is_read_only=true 1103max_miss_count=0 1104mshrs=4 1105p_state_clk_gate_bins=20 1106p_state_clk_gate_max=1000000000000 1107p_state_clk_gate_min=1000 1108power_model=Null 1109prefetch_on_access=false 1110prefetcher=Null 1111response_latency=2 1112sequential_access=false 1113size=32768 1114system=system 1115tags=system.cpu1.icache.tags 1116tgts_per_mshr=20 1117write_buffers=8 1118writeback_clean=true 1119cpu_side=system.cpu1.icache_port 1120mem_side=system.toL2Bus.slave[2] 1121 1122[system.cpu1.icache.tags] 1123type=LRU 1124assoc=1 1125block_size=64 1126clk_domain=system.cpu_clk_domain 1127default_p_state=UNDEFINED 1128eventq_index=0 1129hit_latency=2 1130p_state_clk_gate_bins=20 1131p_state_clk_gate_max=1000000000000 1132p_state_clk_gate_min=1000 1133power_model=Null 1134sequential_access=false 1135size=32768 1136 1137[system.cpu1.interrupts] 1138type=AlphaInterrupts 1139eventq_index=0 1140 1141[system.cpu1.isa] 1142type=AlphaISA 1143eventq_index=0 1144system=system 1145 1146[system.cpu1.itb] 1147type=AlphaTLB 1148eventq_index=0 1149size=48 1150 1151[system.cpu1.tracer] 1152type=ExeTracer 1153eventq_index=0 1154 1155[system.cpu_clk_domain] 1156type=SrcClockDomain 1157clock=500 1158domain_id=-1 1159eventq_index=0 1160init_perf_level=0 1161voltage_domain=system.voltage_domain 1162 1163[system.disk0] 1164type=IdeDisk 1165children=image 1166delay=1000000 1167driveID=master 1168eventq_index=0 1169image=system.disk0.image 1170 1171[system.disk0.image] 1172type=CowDiskImage 1173children=child 1174child=system.disk0.image.child 1175eventq_index=0 1176image_file= 1177read_only=false 1178table_size=65536 1179 1180[system.disk0.image.child] 1181type=RawDiskImage 1182eventq_index=0 1183image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img 1184read_only=true 1185 1186[system.disk2] 1187type=IdeDisk 1188children=image 1189delay=1000000 1190driveID=master 1191eventq_index=0 1192image=system.disk2.image 1193 1194[system.disk2.image] 1195type=CowDiskImage 1196children=child 1197child=system.disk2.image.child 1198eventq_index=0 1199image_file= 1200read_only=false 1201table_size=65536 1202 1203[system.disk2.image.child] 1204type=RawDiskImage 1205eventq_index=0 1206image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img 1207read_only=true 1208 1209[system.dvfs_handler] 1210type=DVFSHandler 1211domains= 1212enable=false 1213eventq_index=0 1214sys_clk_domain=system.clk_domain 1215transition_latency=100000000 1216 1217[system.intrctrl] 1218type=IntrControl 1219eventq_index=0 1220sys=system 1221 1222[system.iobus] 1223type=NoncoherentXBar 1224clk_domain=system.clk_domain 1225default_p_state=UNDEFINED 1226eventq_index=0 1227forward_latency=1 1228frontend_latency=2 1229p_state_clk_gate_bins=20 1230p_state_clk_gate_max=1000000000000 1231p_state_clk_gate_min=1000 1232power_model=Null 1233response_latency=2 1234use_default_range=false 1235width=16 1236master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 1237slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 1238 1239[system.iocache] 1240type=Cache 1241children=tags 1242addr_ranges=0:134217727 1243assoc=8 1244clk_domain=system.clk_domain 1245clusivity=mostly_incl 1246default_p_state=UNDEFINED 1247demand_mshr_reserve=1 1248eventq_index=0 1249hit_latency=50 1250is_read_only=false 1251max_miss_count=0 1252mshrs=20 1253p_state_clk_gate_bins=20 1254p_state_clk_gate_max=1000000000000 1255p_state_clk_gate_min=1000 1256power_model=Null 1257prefetch_on_access=false 1258prefetcher=Null 1259response_latency=50 1260sequential_access=false 1261size=1024 1262system=system 1263tags=system.iocache.tags 1264tgts_per_mshr=12 1265write_buffers=8 1266writeback_clean=false 1267cpu_side=system.iobus.master[27] 1268mem_side=system.membus.slave[2] 1269 1270[system.iocache.tags] 1271type=LRU 1272assoc=8 1273block_size=64 1274clk_domain=system.clk_domain 1275default_p_state=UNDEFINED 1276eventq_index=0 1277hit_latency=50 1278p_state_clk_gate_bins=20 1279p_state_clk_gate_max=1000000000000 1280p_state_clk_gate_min=1000 1281power_model=Null 1282sequential_access=false 1283size=1024 1284 1285[system.l2c] 1286type=Cache 1287children=tags 1288addr_ranges=0:18446744073709551615 1289assoc=8 1290clk_domain=system.cpu_clk_domain 1291clusivity=mostly_incl 1292default_p_state=UNDEFINED 1293demand_mshr_reserve=1 1294eventq_index=0 1295hit_latency=20 1296is_read_only=false 1297max_miss_count=0 1298mshrs=20 1299p_state_clk_gate_bins=20 1300p_state_clk_gate_max=1000000000000 1301p_state_clk_gate_min=1000 1302power_model=Null 1303prefetch_on_access=false 1304prefetcher=Null 1305response_latency=20 1306sequential_access=false 1307size=4194304 1308system=system 1309tags=system.l2c.tags 1310tgts_per_mshr=12 1311write_buffers=8 1312writeback_clean=false 1313cpu_side=system.toL2Bus.master[0] 1314mem_side=system.membus.slave[1] 1315 1316[system.l2c.tags] 1317type=LRU 1318assoc=8 1319block_size=64 1320clk_domain=system.cpu_clk_domain 1321default_p_state=UNDEFINED 1322eventq_index=0 1323hit_latency=20 1324p_state_clk_gate_bins=20 1325p_state_clk_gate_max=1000000000000 1326p_state_clk_gate_min=1000 1327power_model=Null 1328sequential_access=false 1329size=4194304 1330 1331[system.membus] 1332type=CoherentXBar 1333children=badaddr_responder snoop_filter 1334clk_domain=system.clk_domain 1335default_p_state=UNDEFINED 1336eventq_index=0 1337forward_latency=4 1338frontend_latency=3 1339p_state_clk_gate_bins=20 1340p_state_clk_gate_max=1000000000000 1341p_state_clk_gate_min=1000 1342point_of_coherency=true 1343power_model=Null 1344response_latency=2 1345snoop_filter=system.membus.snoop_filter 1346snoop_response_latency=4 1347system=system 1348use_default_range=false 1349width=16 1350default=system.membus.badaddr_responder.pio 1351master=system.bridge.slave system.physmem.port 1352slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1353 1354[system.membus.badaddr_responder] 1355type=IsaFake 1356clk_domain=system.clk_domain 1357default_p_state=UNDEFINED 1358eventq_index=0 1359fake_mem=false 1360p_state_clk_gate_bins=20 1361p_state_clk_gate_max=1000000000000 1362p_state_clk_gate_min=1000 1363pio_addr=0 1364pio_latency=100000 1365pio_size=8 1366power_model=Null 1367ret_bad_addr=true 1368ret_data16=65535 1369ret_data32=4294967295 1370ret_data64=18446744073709551615 1371ret_data8=255 1372system=system 1373update_data=false 1374warn_access= 1375pio=system.membus.default 1376 1377[system.membus.snoop_filter] 1378type=SnoopFilter 1379eventq_index=0 1380lookup_latency=1 1381max_capacity=8388608 1382system=system 1383 1384[system.physmem] 1385type=DRAMCtrl 1386IDD0=0.075000 1387IDD02=0.000000 1388IDD2N=0.050000 1389IDD2N2=0.000000 1390IDD2P0=0.000000 1391IDD2P02=0.000000 1392IDD2P1=0.000000 1393IDD2P12=0.000000 1394IDD3N=0.057000 1395IDD3N2=0.000000 1396IDD3P0=0.000000 1397IDD3P02=0.000000 1398IDD3P1=0.000000 1399IDD3P12=0.000000 1400IDD4R=0.187000 1401IDD4R2=0.000000 1402IDD4W=0.165000 1403IDD4W2=0.000000 1404IDD5=0.220000 1405IDD52=0.000000 1406IDD6=0.000000 1407IDD62=0.000000 1408VDD=1.500000 1409VDD2=0.000000 1410activation_limit=4 1411addr_mapping=RoRaBaCoCh 1412bank_groups_per_rank=0 1413banks_per_rank=8 1414burst_length=8 1415channels=1 1416clk_domain=system.clk_domain 1417conf_table_reported=true 1418default_p_state=UNDEFINED 1419device_bus_width=8 1420device_rowbuffer_size=1024 1421device_size=536870912 1422devices_per_rank=8 1423dll=true 1424eventq_index=0 1425in_addr_map=true 1426max_accesses_per_row=16 1427mem_sched_policy=frfcfs 1428min_writes_per_switch=16 1429null=false 1430p_state_clk_gate_bins=20 1431p_state_clk_gate_max=1000000000000 1432p_state_clk_gate_min=1000 1433page_policy=open_adaptive 1434power_model=Null 1435range=0:134217727 1436ranks_per_channel=2 1437read_buffer_size=32 1438static_backend_latency=10000 1439static_frontend_latency=10000 1440tBURST=5000 1441tCCD_L=0 1442tCK=1250 1443tCL=13750 1444tCS=2500 1445tRAS=35000 1446tRCD=13750 1447tREFI=7800000 1448tRFC=260000 1449tRP=13750 1450tRRD=6000 1451tRRD_L=0 1452tRTP=7500 1453tRTW=2500 1454tWR=15000 1455tWTR=7500 1456tXAW=30000 1457tXP=0 1458tXPDLL=0 1459tXS=0 1460tXSDLL=0 1461write_buffer_size=64 1462write_high_thresh_perc=85 1463write_low_thresh_perc=50 1464port=system.membus.master[1] 1465 1466[system.simple_disk] 1467type=SimpleDisk 1468children=disk 1469disk=system.simple_disk.disk 1470eventq_index=0 1471system=system 1472 1473[system.simple_disk.disk] 1474type=RawDiskImage 1475eventq_index=0 1476image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img 1477read_only=true 1478 1479[system.terminal] 1480type=Terminal 1481eventq_index=0 1482intr_control=system.intrctrl 1483number=0 1484output=true 1485port=3456 1486 1487[system.toL2Bus] 1488type=CoherentXBar 1489children=snoop_filter 1490clk_domain=system.cpu_clk_domain 1491default_p_state=UNDEFINED 1492eventq_index=0 1493forward_latency=0 1494frontend_latency=1 1495p_state_clk_gate_bins=20 1496p_state_clk_gate_max=1000000000000 1497p_state_clk_gate_min=1000 1498point_of_coherency=false 1499power_model=Null 1500response_latency=1 1501snoop_filter=system.toL2Bus.snoop_filter 1502snoop_response_latency=1 1503system=system 1504use_default_range=false 1505width=32 1506master=system.l2c.cpu_side 1507slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1508 1509[system.toL2Bus.snoop_filter] 1510type=SnoopFilter 1511eventq_index=0 1512lookup_latency=0 1513max_capacity=8388608 1514system=system 1515 1516[system.tsunami] 1517type=Tsunami 1518children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart 1519eventq_index=0 1520intrctrl=system.intrctrl 1521system=system 1522 1523[system.tsunami.backdoor] 1524type=AlphaBackdoor 1525clk_domain=system.clk_domain 1526cpu=system.cpu0 1527default_p_state=UNDEFINED 1528disk=system.simple_disk 1529eventq_index=0 1530p_state_clk_gate_bins=20 1531p_state_clk_gate_max=1000000000000 1532p_state_clk_gate_min=1000 1533pio_addr=8804682956800 1534pio_latency=100000 1535platform=system.tsunami 1536power_model=Null 1537system=system 1538terminal=system.terminal 1539pio=system.iobus.master[24] 1540 1541[system.tsunami.cchip] 1542type=TsunamiCChip 1543clk_domain=system.clk_domain 1544default_p_state=UNDEFINED 1545eventq_index=0 1546p_state_clk_gate_bins=20 1547p_state_clk_gate_max=1000000000000 1548p_state_clk_gate_min=1000 1549pio_addr=8803072344064 1550pio_latency=100000 1551power_model=Null 1552system=system 1553tsunami=system.tsunami 1554pio=system.iobus.master[0] 1555 1556[system.tsunami.ethernet] 1557type=NSGigE 1558BAR0=1 1559BAR0LegacyIO=false 1560BAR0Size=256 1561BAR1=0 1562BAR1LegacyIO=false 1563BAR1Size=4096 1564BAR2=0 1565BAR2LegacyIO=false 1566BAR2Size=0 1567BAR3=0 1568BAR3LegacyIO=false 1569BAR3Size=0 1570BAR4=0 1571BAR4LegacyIO=false 1572BAR4Size=0 1573BAR5=0 1574BAR5LegacyIO=false 1575BAR5Size=0 1576BIST=0 1577CacheLineSize=0 1578CapabilityPtr=0 1579CardbusCIS=0 1580ClassCode=2 1581Command=0 1582DeviceID=34 1583ExpansionROM=0 1584HeaderType=0 1585InterruptLine=30 1586InterruptPin=1 1587LatencyTimer=0 1588LegacyIOBase=0 1589MSICAPBaseOffset=0 1590MSICAPCapId=0 1591MSICAPMaskBits=0 1592MSICAPMsgAddr=0 1593MSICAPMsgCtrl=0 1594MSICAPMsgData=0 1595MSICAPMsgUpperAddr=0 1596MSICAPNextCapability=0 1597MSICAPPendingBits=0 1598MSIXCAPBaseOffset=0 1599MSIXCAPCapId=0 1600MSIXCAPNextCapability=0 1601MSIXMsgCtrl=0 1602MSIXPbaOffset=0 1603MSIXTableOffset=0 1604MaximumLatency=52 1605MinimumGrant=176 1606PMCAPBaseOffset=0 1607PMCAPCapId=0 1608PMCAPCapabilities=0 1609PMCAPCtrlStatus=0 1610PMCAPNextCapability=0 1611PXCAPBaseOffset=0 1612PXCAPCapId=0 1613PXCAPCapabilities=0 1614PXCAPDevCap2=0 1615PXCAPDevCapabilities=0 1616PXCAPDevCtrl=0 1617PXCAPDevCtrl2=0 1618PXCAPDevStatus=0 1619PXCAPLinkCap=0 1620PXCAPLinkCtrl=0 1621PXCAPLinkStatus=0 1622PXCAPNextCapability=0 1623ProgIF=0 1624Revision=0 1625Status=656 1626SubClassCode=0 1627SubsystemID=0 1628SubsystemVendorID=0 1629VendorID=4107 1630clk_domain=system.clk_domain 1631config_latency=20000 1632default_p_state=UNDEFINED 1633dma_data_free=false 1634dma_desc_free=false 1635dma_no_allocate=true 1636dma_read_delay=0 1637dma_read_factor=0 1638dma_write_delay=0 1639dma_write_factor=0 1640eventq_index=0 1641hardware_address=00:90:00:00:00:01 1642host=system.tsunami.pchip 1643intr_delay=10000000 1644p_state_clk_gate_bins=20 1645p_state_clk_gate_max=1000000000000 1646p_state_clk_gate_min=1000 1647pci_bus=0 1648pci_dev=1 1649pci_func=0 1650pio_latency=30000 1651power_model=Null 1652rss=false 1653rx_delay=1000000 1654rx_fifo_size=524288 1655rx_filter=true 1656rx_thread=false 1657system=system 1658tx_delay=1000000 1659tx_fifo_size=524288 1660tx_thread=false 1661dma=system.iobus.slave[2] 1662pio=system.iobus.master[26] 1663 1664[system.tsunami.fake_OROM] 1665type=IsaFake 1666clk_domain=system.clk_domain 1667default_p_state=UNDEFINED 1668eventq_index=0 1669fake_mem=false 1670p_state_clk_gate_bins=20 1671p_state_clk_gate_max=1000000000000 1672p_state_clk_gate_min=1000 1673pio_addr=8796093677568 1674pio_latency=100000 1675pio_size=393216 1676power_model=Null 1677ret_bad_addr=false 1678ret_data16=65535 1679ret_data32=4294967295 1680ret_data64=18446744073709551615 1681ret_data8=255 1682system=system 1683update_data=false 1684warn_access= 1685pio=system.iobus.master[8] 1686 1687[system.tsunami.fake_ata0] 1688type=IsaFake 1689clk_domain=system.clk_domain 1690default_p_state=UNDEFINED 1691eventq_index=0 1692fake_mem=false 1693p_state_clk_gate_bins=20 1694p_state_clk_gate_max=1000000000000 1695p_state_clk_gate_min=1000 1696pio_addr=8804615848432 1697pio_latency=100000 1698pio_size=8 1699power_model=Null 1700ret_bad_addr=false 1701ret_data16=65535 1702ret_data32=4294967295 1703ret_data64=18446744073709551615 1704ret_data8=255 1705system=system 1706update_data=false 1707warn_access= 1708pio=system.iobus.master[19] 1709 1710[system.tsunami.fake_ata1] 1711type=IsaFake 1712clk_domain=system.clk_domain 1713default_p_state=UNDEFINED 1714eventq_index=0 1715fake_mem=false 1716p_state_clk_gate_bins=20 1717p_state_clk_gate_max=1000000000000 1718p_state_clk_gate_min=1000 1719pio_addr=8804615848304 1720pio_latency=100000 1721pio_size=8 1722power_model=Null 1723ret_bad_addr=false 1724ret_data16=65535 1725ret_data32=4294967295 1726ret_data64=18446744073709551615 1727ret_data8=255 1728system=system 1729update_data=false 1730warn_access= 1731pio=system.iobus.master[20] 1732 1733[system.tsunami.fake_pnp_addr] 1734type=IsaFake 1735clk_domain=system.clk_domain 1736default_p_state=UNDEFINED 1737eventq_index=0 1738fake_mem=false 1739p_state_clk_gate_bins=20 1740p_state_clk_gate_max=1000000000000 1741p_state_clk_gate_min=1000 1742pio_addr=8804615848569 1743pio_latency=100000 1744pio_size=8 1745power_model=Null 1746ret_bad_addr=false 1747ret_data16=65535 1748ret_data32=4294967295 1749ret_data64=18446744073709551615 1750ret_data8=255 1751system=system 1752update_data=false 1753warn_access= 1754pio=system.iobus.master[9] 1755 1756[system.tsunami.fake_pnp_read0] 1757type=IsaFake 1758clk_domain=system.clk_domain 1759default_p_state=UNDEFINED 1760eventq_index=0 1761fake_mem=false 1762p_state_clk_gate_bins=20 1763p_state_clk_gate_max=1000000000000 1764p_state_clk_gate_min=1000 1765pio_addr=8804615848451 1766pio_latency=100000 1767pio_size=8 1768power_model=Null 1769ret_bad_addr=false 1770ret_data16=65535 1771ret_data32=4294967295 1772ret_data64=18446744073709551615 1773ret_data8=255 1774system=system 1775update_data=false 1776warn_access= 1777pio=system.iobus.master[11] 1778 1779[system.tsunami.fake_pnp_read1] 1780type=IsaFake 1781clk_domain=system.clk_domain 1782default_p_state=UNDEFINED 1783eventq_index=0 1784fake_mem=false 1785p_state_clk_gate_bins=20 1786p_state_clk_gate_max=1000000000000 1787p_state_clk_gate_min=1000 1788pio_addr=8804615848515 1789pio_latency=100000 1790pio_size=8 1791power_model=Null 1792ret_bad_addr=false 1793ret_data16=65535 1794ret_data32=4294967295 1795ret_data64=18446744073709551615 1796ret_data8=255 1797system=system 1798update_data=false 1799warn_access= 1800pio=system.iobus.master[12] 1801 1802[system.tsunami.fake_pnp_read2] 1803type=IsaFake 1804clk_domain=system.clk_domain 1805default_p_state=UNDEFINED 1806eventq_index=0 1807fake_mem=false 1808p_state_clk_gate_bins=20 1809p_state_clk_gate_max=1000000000000 1810p_state_clk_gate_min=1000 1811pio_addr=8804615848579 1812pio_latency=100000 1813pio_size=8 1814power_model=Null 1815ret_bad_addr=false 1816ret_data16=65535 1817ret_data32=4294967295 1818ret_data64=18446744073709551615 1819ret_data8=255 1820system=system 1821update_data=false 1822warn_access= 1823pio=system.iobus.master[13] 1824 1825[system.tsunami.fake_pnp_read3] 1826type=IsaFake 1827clk_domain=system.clk_domain 1828default_p_state=UNDEFINED 1829eventq_index=0 1830fake_mem=false 1831p_state_clk_gate_bins=20 1832p_state_clk_gate_max=1000000000000 1833p_state_clk_gate_min=1000 1834pio_addr=8804615848643 1835pio_latency=100000 1836pio_size=8 1837power_model=Null 1838ret_bad_addr=false 1839ret_data16=65535 1840ret_data32=4294967295 1841ret_data64=18446744073709551615 1842ret_data8=255 1843system=system 1844update_data=false 1845warn_access= 1846pio=system.iobus.master[14] 1847 1848[system.tsunami.fake_pnp_read4] 1849type=IsaFake 1850clk_domain=system.clk_domain 1851default_p_state=UNDEFINED 1852eventq_index=0 1853fake_mem=false 1854p_state_clk_gate_bins=20 1855p_state_clk_gate_max=1000000000000 1856p_state_clk_gate_min=1000 1857pio_addr=8804615848707 1858pio_latency=100000 1859pio_size=8 1860power_model=Null 1861ret_bad_addr=false 1862ret_data16=65535 1863ret_data32=4294967295 1864ret_data64=18446744073709551615 1865ret_data8=255 1866system=system 1867update_data=false 1868warn_access= 1869pio=system.iobus.master[15] 1870 1871[system.tsunami.fake_pnp_read5] 1872type=IsaFake 1873clk_domain=system.clk_domain 1874default_p_state=UNDEFINED 1875eventq_index=0 1876fake_mem=false 1877p_state_clk_gate_bins=20 1878p_state_clk_gate_max=1000000000000 1879p_state_clk_gate_min=1000 1880pio_addr=8804615848771 1881pio_latency=100000 1882pio_size=8 1883power_model=Null 1884ret_bad_addr=false 1885ret_data16=65535 1886ret_data32=4294967295 1887ret_data64=18446744073709551615 1888ret_data8=255 1889system=system 1890update_data=false 1891warn_access= 1892pio=system.iobus.master[16] 1893 1894[system.tsunami.fake_pnp_read6] 1895type=IsaFake 1896clk_domain=system.clk_domain 1897default_p_state=UNDEFINED 1898eventq_index=0 1899fake_mem=false 1900p_state_clk_gate_bins=20 1901p_state_clk_gate_max=1000000000000 1902p_state_clk_gate_min=1000 1903pio_addr=8804615848835 1904pio_latency=100000 1905pio_size=8 1906power_model=Null 1907ret_bad_addr=false 1908ret_data16=65535 1909ret_data32=4294967295 1910ret_data64=18446744073709551615 1911ret_data8=255 1912system=system 1913update_data=false 1914warn_access= 1915pio=system.iobus.master[17] 1916 1917[system.tsunami.fake_pnp_read7] 1918type=IsaFake 1919clk_domain=system.clk_domain 1920default_p_state=UNDEFINED 1921eventq_index=0 1922fake_mem=false 1923p_state_clk_gate_bins=20 1924p_state_clk_gate_max=1000000000000 1925p_state_clk_gate_min=1000 1926pio_addr=8804615848899 1927pio_latency=100000 1928pio_size=8 1929power_model=Null 1930ret_bad_addr=false 1931ret_data16=65535 1932ret_data32=4294967295 1933ret_data64=18446744073709551615 1934ret_data8=255 1935system=system 1936update_data=false 1937warn_access= 1938pio=system.iobus.master[18] 1939 1940[system.tsunami.fake_pnp_write] 1941type=IsaFake 1942clk_domain=system.clk_domain 1943default_p_state=UNDEFINED 1944eventq_index=0 1945fake_mem=false 1946p_state_clk_gate_bins=20 1947p_state_clk_gate_max=1000000000000 1948p_state_clk_gate_min=1000 1949pio_addr=8804615850617 1950pio_latency=100000 1951pio_size=8 1952power_model=Null 1953ret_bad_addr=false 1954ret_data16=65535 1955ret_data32=4294967295 1956ret_data64=18446744073709551615 1957ret_data8=255 1958system=system 1959update_data=false 1960warn_access= 1961pio=system.iobus.master[10] 1962 1963[system.tsunami.fake_ppc] 1964type=IsaFake 1965clk_domain=system.clk_domain 1966default_p_state=UNDEFINED 1967eventq_index=0 1968fake_mem=false 1969p_state_clk_gate_bins=20 1970p_state_clk_gate_max=1000000000000 1971p_state_clk_gate_min=1000 1972pio_addr=8804615848891 1973pio_latency=100000 1974pio_size=8 1975power_model=Null 1976ret_bad_addr=false 1977ret_data16=65535 1978ret_data32=4294967295 1979ret_data64=18446744073709551615 1980ret_data8=255 1981system=system 1982update_data=false 1983warn_access= 1984pio=system.iobus.master[7] 1985 1986[system.tsunami.fake_sm_chip] 1987type=IsaFake 1988clk_domain=system.clk_domain 1989default_p_state=UNDEFINED 1990eventq_index=0 1991fake_mem=false 1992p_state_clk_gate_bins=20 1993p_state_clk_gate_max=1000000000000 1994p_state_clk_gate_min=1000 1995pio_addr=8804615848816 1996pio_latency=100000 1997pio_size=8 1998power_model=Null 1999ret_bad_addr=false 2000ret_data16=65535 2001ret_data32=4294967295 2002ret_data64=18446744073709551615 2003ret_data8=255 2004system=system 2005update_data=false 2006warn_access= 2007pio=system.iobus.master[2] 2008 2009[system.tsunami.fake_uart1] 2010type=IsaFake 2011clk_domain=system.clk_domain 2012default_p_state=UNDEFINED 2013eventq_index=0 2014fake_mem=false 2015p_state_clk_gate_bins=20 2016p_state_clk_gate_max=1000000000000 2017p_state_clk_gate_min=1000 2018pio_addr=8804615848696 2019pio_latency=100000 2020pio_size=8 2021power_model=Null 2022ret_bad_addr=false 2023ret_data16=65535 2024ret_data32=4294967295 2025ret_data64=18446744073709551615 2026ret_data8=255 2027system=system 2028update_data=false 2029warn_access= 2030pio=system.iobus.master[3] 2031 2032[system.tsunami.fake_uart2] 2033type=IsaFake 2034clk_domain=system.clk_domain 2035default_p_state=UNDEFINED 2036eventq_index=0 2037fake_mem=false 2038p_state_clk_gate_bins=20 2039p_state_clk_gate_max=1000000000000 2040p_state_clk_gate_min=1000 2041pio_addr=8804615848936 2042pio_latency=100000 2043pio_size=8 2044power_model=Null 2045ret_bad_addr=false 2046ret_data16=65535 2047ret_data32=4294967295 2048ret_data64=18446744073709551615 2049ret_data8=255 2050system=system 2051update_data=false 2052warn_access= 2053pio=system.iobus.master[4] 2054 2055[system.tsunami.fake_uart3] 2056type=IsaFake 2057clk_domain=system.clk_domain 2058default_p_state=UNDEFINED 2059eventq_index=0 2060fake_mem=false 2061p_state_clk_gate_bins=20 2062p_state_clk_gate_max=1000000000000 2063p_state_clk_gate_min=1000 2064pio_addr=8804615848680 2065pio_latency=100000 2066pio_size=8 2067power_model=Null 2068ret_bad_addr=false 2069ret_data16=65535 2070ret_data32=4294967295 2071ret_data64=18446744073709551615 2072ret_data8=255 2073system=system 2074update_data=false 2075warn_access= 2076pio=system.iobus.master[5] 2077 2078[system.tsunami.fake_uart4] 2079type=IsaFake 2080clk_domain=system.clk_domain 2081default_p_state=UNDEFINED 2082eventq_index=0 2083fake_mem=false 2084p_state_clk_gate_bins=20 2085p_state_clk_gate_max=1000000000000 2086p_state_clk_gate_min=1000 2087pio_addr=8804615848944 2088pio_latency=100000 2089pio_size=8 2090power_model=Null 2091ret_bad_addr=false 2092ret_data16=65535 2093ret_data32=4294967295 2094ret_data64=18446744073709551615 2095ret_data8=255 2096system=system 2097update_data=false 2098warn_access= 2099pio=system.iobus.master[6] 2100 2101[system.tsunami.fb] 2102type=BadDevice 2103clk_domain=system.clk_domain 2104default_p_state=UNDEFINED 2105devicename=FrameBuffer 2106eventq_index=0 2107p_state_clk_gate_bins=20 2108p_state_clk_gate_max=1000000000000 2109p_state_clk_gate_min=1000 2110pio_addr=8804615848912 2111pio_latency=100000 2112power_model=Null 2113system=system 2114pio=system.iobus.master[21] 2115 2116[system.tsunami.ide] 2117type=IdeController 2118BAR0=1 2119BAR0LegacyIO=false 2120BAR0Size=8 2121BAR1=1 2122BAR1LegacyIO=false 2123BAR1Size=4 2124BAR2=1 2125BAR2LegacyIO=false 2126BAR2Size=8 2127BAR3=1 2128BAR3LegacyIO=false 2129BAR3Size=4 2130BAR4=1 2131BAR4LegacyIO=false 2132BAR4Size=16 2133BAR5=1 2134BAR5LegacyIO=false 2135BAR5Size=0 2136BIST=0 2137CacheLineSize=0 2138CapabilityPtr=0 2139CardbusCIS=0 2140ClassCode=1 2141Command=0 2142DeviceID=28945 2143ExpansionROM=0 2144HeaderType=0 2145InterruptLine=31 2146InterruptPin=1 2147LatencyTimer=0 2148LegacyIOBase=0 2149MSICAPBaseOffset=0 2150MSICAPCapId=0 2151MSICAPMaskBits=0 2152MSICAPMsgAddr=0 2153MSICAPMsgCtrl=0 2154MSICAPMsgData=0 2155MSICAPMsgUpperAddr=0 2156MSICAPNextCapability=0 2157MSICAPPendingBits=0 2158MSIXCAPBaseOffset=0 2159MSIXCAPCapId=0 2160MSIXCAPNextCapability=0 2161MSIXMsgCtrl=0 2162MSIXPbaOffset=0 2163MSIXTableOffset=0 2164MaximumLatency=0 2165MinimumGrant=0 2166PMCAPBaseOffset=0 2167PMCAPCapId=0 2168PMCAPCapabilities=0 2169PMCAPCtrlStatus=0 2170PMCAPNextCapability=0 2171PXCAPBaseOffset=0 2172PXCAPCapId=0 2173PXCAPCapabilities=0 2174PXCAPDevCap2=0 2175PXCAPDevCapabilities=0 2176PXCAPDevCtrl=0 2177PXCAPDevCtrl2=0 2178PXCAPDevStatus=0 2179PXCAPLinkCap=0 2180PXCAPLinkCtrl=0 2181PXCAPLinkStatus=0 2182PXCAPNextCapability=0 2183ProgIF=133 2184Revision=0 2185Status=640 2186SubClassCode=1 2187SubsystemID=0 2188SubsystemVendorID=0 2189VendorID=32902 2190clk_domain=system.clk_domain 2191config_latency=20000 2192ctrl_offset=0 2193default_p_state=UNDEFINED 2194disks=system.disk0 system.disk2 2195eventq_index=0 2196host=system.tsunami.pchip 2197io_shift=0 2198p_state_clk_gate_bins=20 2199p_state_clk_gate_max=1000000000000 2200p_state_clk_gate_min=1000 2201pci_bus=0 2202pci_dev=0 2203pci_func=0 2204pio_latency=30000 2205power_model=Null 2206system=system 2207dma=system.iobus.slave[1] 2208pio=system.iobus.master[25] 2209 2210[system.tsunami.io] 2211type=TsunamiIO 2212clk_domain=system.clk_domain 2213default_p_state=UNDEFINED 2214eventq_index=0 2215frequency=976562500 2216p_state_clk_gate_bins=20 2217p_state_clk_gate_max=1000000000000 2218p_state_clk_gate_min=1000 2219pio_addr=8804615847936 2220pio_latency=100000 2221power_model=Null 2222system=system 2223time=Thu Jan 1 00:00:00 2009 2224tsunami=system.tsunami 2225year_is_bcd=false 2226pio=system.iobus.master[22] 2227 2228[system.tsunami.pchip] 2229type=TsunamiPChip 2230clk_domain=system.clk_domain 2231conf_base=8804649402368 2232conf_device_bits=8 2233conf_size=16777216 2234default_p_state=UNDEFINED 2235eventq_index=0 2236p_state_clk_gate_bins=20 2237p_state_clk_gate_max=1000000000000 2238p_state_clk_gate_min=1000 2239pci_dma_base=0 2240pci_mem_base=8796093022208 2241pci_pio_base=8804615847936 2242pio_addr=8802535473152 2243pio_latency=100000 2244platform=system.tsunami 2245power_model=Null 2246system=system 2247tsunami=system.tsunami 2248pio=system.iobus.master[1] 2249 2250[system.tsunami.uart] 2251type=Uart8250 2252clk_domain=system.clk_domain 2253default_p_state=UNDEFINED 2254eventq_index=0 2255p_state_clk_gate_bins=20 2256p_state_clk_gate_max=1000000000000 2257p_state_clk_gate_min=1000 2258pio_addr=8804615848952 2259pio_latency=100000 2260platform=system.tsunami 2261power_model=Null 2262system=system 2263terminal=system.terminal 2264pio=system.iobus.master[23] 2265 2266[system.voltage_domain] 2267type=VoltageDomain 2268eventq_index=0 2269voltage=1.000000 2270 2271