config.ini revision 10798
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain 18console=/home/stever/m5/m5_system_2.0b3/binaries/console 19eventq_index=0 20init_param=0 21kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem 28mmap_using_noreserve=false 29num_work_ids=16 30pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal 31readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh 32symbolfile= 33system_rev=1024 34system_type=34 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 48eventq_index=0 49ranges=8796093022208:18446744073709551615 50req_size=16 51resp_size=16 52master=system.iobus.slave[0] 53slave=system.membus.master[0] 54 55[system.clk_domain] 56type=SrcClockDomain 57clock=1000 58domain_id=-1 59eventq_index=0 60init_perf_level=0 61voltage_domain=system.voltage_domain 62 63[system.cpu0] 64type=DerivO3CPU 65children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 66LFSTSize=1024 67LQEntries=32 68LSQCheckLoads=true 69LSQDepCheckShift=4 70SQEntries=32 71SSITSize=1024 72activity=0 73backComSize=5 74branchPred=system.cpu0.branchPred 75cachePorts=200 76checker=Null 77clk_domain=system.cpu_clk_domain 78commitToDecodeDelay=1 79commitToFetchDelay=1 80commitToIEWDelay=1 81commitToRenameDelay=1 82commitWidth=8 83cpu_id=0 84decodeToFetchDelay=1 85decodeToRenameDelay=1 86decodeWidth=8 87dispatchWidth=8 88do_checkpoint_insts=true 89do_quiesce=true 90do_statistics_insts=true 91dtb=system.cpu0.dtb 92eventq_index=0 93fetchBufferSize=64 94fetchQueueSize=32 95fetchToDecodeDelay=1 96fetchTrapLatency=1 97fetchWidth=8 98forwardComSize=5 99fuPool=system.cpu0.fuPool 100function_trace=false 101function_trace_start=0 102iewToCommitDelay=1 103iewToDecodeDelay=1 104iewToFetchDelay=1 105iewToRenameDelay=1 106interrupts=system.cpu0.interrupts 107isa=system.cpu0.isa 108issueToExecuteDelay=1 109issueWidth=8 110itb=system.cpu0.itb 111max_insts_all_threads=0 112max_insts_any_thread=0 113max_loads_all_threads=0 114max_loads_any_thread=0 115needsTSO=false 116numIQEntries=64 117numPhysCCRegs=0 118numPhysFloatRegs=256 119numPhysIntRegs=256 120numROBEntries=192 121numRobs=1 122numThreads=1 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=2 128renameToROBDelay=1 129renameWidth=8 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144system=system 145tracer=system.cpu0.tracer 146trapLatency=13 147wbWidth=8 148workload= 149dcache_port=system.cpu0.dcache.cpu_side 150icache_port=system.cpu0.icache.cpu_side 151 152[system.cpu0.branchPred] 153type=TournamentBP 154BTBEntries=4096 155BTBTagSize=16 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162instShiftAmt=2 163localCtrBits=2 164localHistoryTableSize=2048 165localPredictorSize=2048 166numThreads=1 167 168[system.cpu0.dcache] 169type=BaseCache 170children=tags 171addr_ranges=0:18446744073709551615 172assoc=4 173clk_domain=system.cpu_clk_domain 174demand_mshr_reserve=1 175eventq_index=0 176forward_snoops=true 177hit_latency=2 178is_top_level=true 179max_miss_count=0 180mshrs=4 181prefetch_on_access=false 182prefetcher=Null 183response_latency=2 184sequential_access=false 185size=32768 186system=system 187tags=system.cpu0.dcache.tags 188tgts_per_mshr=20 189two_queue=false 190write_buffers=8 191cpu_side=system.cpu0.dcache_port 192mem_side=system.toL2Bus.slave[1] 193 194[system.cpu0.dcache.tags] 195type=LRU 196assoc=4 197block_size=64 198clk_domain=system.cpu_clk_domain 199eventq_index=0 200hit_latency=2 201sequential_access=false 202size=32768 203 204[system.cpu0.dtb] 205type=AlphaTLB 206eventq_index=0 207size=64 208 209[system.cpu0.fuPool] 210type=FUPool 211children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 212FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 213eventq_index=0 214 215[system.cpu0.fuPool.FUList0] 216type=FUDesc 217children=opList 218count=6 219eventq_index=0 220opList=system.cpu0.fuPool.FUList0.opList 221 222[system.cpu0.fuPool.FUList0.opList] 223type=OpDesc 224eventq_index=0 225issueLat=1 226opClass=IntAlu 227opLat=1 228 229[system.cpu0.fuPool.FUList1] 230type=FUDesc 231children=opList0 opList1 232count=2 233eventq_index=0 234opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 235 236[system.cpu0.fuPool.FUList1.opList0] 237type=OpDesc 238eventq_index=0 239issueLat=1 240opClass=IntMult 241opLat=3 242 243[system.cpu0.fuPool.FUList1.opList1] 244type=OpDesc 245eventq_index=0 246issueLat=19 247opClass=IntDiv 248opLat=20 249 250[system.cpu0.fuPool.FUList2] 251type=FUDesc 252children=opList0 opList1 opList2 253count=4 254eventq_index=0 255opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 256 257[system.cpu0.fuPool.FUList2.opList0] 258type=OpDesc 259eventq_index=0 260issueLat=1 261opClass=FloatAdd 262opLat=2 263 264[system.cpu0.fuPool.FUList2.opList1] 265type=OpDesc 266eventq_index=0 267issueLat=1 268opClass=FloatCmp 269opLat=2 270 271[system.cpu0.fuPool.FUList2.opList2] 272type=OpDesc 273eventq_index=0 274issueLat=1 275opClass=FloatCvt 276opLat=2 277 278[system.cpu0.fuPool.FUList3] 279type=FUDesc 280children=opList0 opList1 opList2 281count=2 282eventq_index=0 283opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 284 285[system.cpu0.fuPool.FUList3.opList0] 286type=OpDesc 287eventq_index=0 288issueLat=1 289opClass=FloatMult 290opLat=4 291 292[system.cpu0.fuPool.FUList3.opList1] 293type=OpDesc 294eventq_index=0 295issueLat=12 296opClass=FloatDiv 297opLat=12 298 299[system.cpu0.fuPool.FUList3.opList2] 300type=OpDesc 301eventq_index=0 302issueLat=24 303opClass=FloatSqrt 304opLat=24 305 306[system.cpu0.fuPool.FUList4] 307type=FUDesc 308children=opList 309count=0 310eventq_index=0 311opList=system.cpu0.fuPool.FUList4.opList 312 313[system.cpu0.fuPool.FUList4.opList] 314type=OpDesc 315eventq_index=0 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu0.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 324eventq_index=0 325opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 326 327[system.cpu0.fuPool.FUList5.opList00] 328type=OpDesc 329eventq_index=0 330issueLat=1 331opClass=SimdAdd 332opLat=1 333 334[system.cpu0.fuPool.FUList5.opList01] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=SimdAddAcc 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList02] 342type=OpDesc 343eventq_index=0 344issueLat=1 345opClass=SimdAlu 346opLat=1 347 348[system.cpu0.fuPool.FUList5.opList03] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdCmp 353opLat=1 354 355[system.cpu0.fuPool.FUList5.opList04] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdCvt 360opLat=1 361 362[system.cpu0.fuPool.FUList5.opList05] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdMisc 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList06] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdMult 374opLat=1 375 376[system.cpu0.fuPool.FUList5.opList07] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdMultAcc 381opLat=1 382 383[system.cpu0.fuPool.FUList5.opList08] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdShift 388opLat=1 389 390[system.cpu0.fuPool.FUList5.opList09] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdShiftAcc 395opLat=1 396 397[system.cpu0.fuPool.FUList5.opList10] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdSqrt 402opLat=1 403 404[system.cpu0.fuPool.FUList5.opList11] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdFloatAdd 409opLat=1 410 411[system.cpu0.fuPool.FUList5.opList12] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdFloatAlu 416opLat=1 417 418[system.cpu0.fuPool.FUList5.opList13] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdFloatCmp 423opLat=1 424 425[system.cpu0.fuPool.FUList5.opList14] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatCvt 430opLat=1 431 432[system.cpu0.fuPool.FUList5.opList15] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatDiv 437opLat=1 438 439[system.cpu0.fuPool.FUList5.opList16] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatMisc 444opLat=1 445 446[system.cpu0.fuPool.FUList5.opList17] 447type=OpDesc 448eventq_index=0 449issueLat=1 450opClass=SimdFloatMult 451opLat=1 452 453[system.cpu0.fuPool.FUList5.opList18] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=SimdFloatMultAcc 458opLat=1 459 460[system.cpu0.fuPool.FUList5.opList19] 461type=OpDesc 462eventq_index=0 463issueLat=1 464opClass=SimdFloatSqrt 465opLat=1 466 467[system.cpu0.fuPool.FUList6] 468type=FUDesc 469children=opList 470count=0 471eventq_index=0 472opList=system.cpu0.fuPool.FUList6.opList 473 474[system.cpu0.fuPool.FUList6.opList] 475type=OpDesc 476eventq_index=0 477issueLat=1 478opClass=MemWrite 479opLat=1 480 481[system.cpu0.fuPool.FUList7] 482type=FUDesc 483children=opList0 opList1 484count=4 485eventq_index=0 486opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 487 488[system.cpu0.fuPool.FUList7.opList0] 489type=OpDesc 490eventq_index=0 491issueLat=1 492opClass=MemRead 493opLat=1 494 495[system.cpu0.fuPool.FUList7.opList1] 496type=OpDesc 497eventq_index=0 498issueLat=1 499opClass=MemWrite 500opLat=1 501 502[system.cpu0.fuPool.FUList8] 503type=FUDesc 504children=opList 505count=1 506eventq_index=0 507opList=system.cpu0.fuPool.FUList8.opList 508 509[system.cpu0.fuPool.FUList8.opList] 510type=OpDesc 511eventq_index=0 512issueLat=3 513opClass=IprAccess 514opLat=3 515 516[system.cpu0.icache] 517type=BaseCache 518children=tags 519addr_ranges=0:18446744073709551615 520assoc=1 521clk_domain=system.cpu_clk_domain 522demand_mshr_reserve=1 523eventq_index=0 524forward_snoops=true 525hit_latency=2 526is_top_level=true 527max_miss_count=0 528mshrs=4 529prefetch_on_access=false 530prefetcher=Null 531response_latency=2 532sequential_access=false 533size=32768 534system=system 535tags=system.cpu0.icache.tags 536tgts_per_mshr=20 537two_queue=false 538write_buffers=8 539cpu_side=system.cpu0.icache_port 540mem_side=system.toL2Bus.slave[0] 541 542[system.cpu0.icache.tags] 543type=LRU 544assoc=1 545block_size=64 546clk_domain=system.cpu_clk_domain 547eventq_index=0 548hit_latency=2 549sequential_access=false 550size=32768 551 552[system.cpu0.interrupts] 553type=AlphaInterrupts 554eventq_index=0 555 556[system.cpu0.isa] 557type=AlphaISA 558eventq_index=0 559system=system 560 561[system.cpu0.itb] 562type=AlphaTLB 563eventq_index=0 564size=48 565 566[system.cpu0.tracer] 567type=ExeTracer 568eventq_index=0 569 570[system.cpu1] 571type=DerivO3CPU 572children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 573LFSTSize=1024 574LQEntries=32 575LSQCheckLoads=true 576LSQDepCheckShift=4 577SQEntries=32 578SSITSize=1024 579activity=0 580backComSize=5 581branchPred=system.cpu1.branchPred 582cachePorts=200 583checker=Null 584clk_domain=system.cpu_clk_domain 585commitToDecodeDelay=1 586commitToFetchDelay=1 587commitToIEWDelay=1 588commitToRenameDelay=1 589commitWidth=8 590cpu_id=1 591decodeToFetchDelay=1 592decodeToRenameDelay=1 593decodeWidth=8 594dispatchWidth=8 595do_checkpoint_insts=true 596do_quiesce=true 597do_statistics_insts=true 598dtb=system.cpu1.dtb 599eventq_index=0 600fetchBufferSize=64 601fetchQueueSize=32 602fetchToDecodeDelay=1 603fetchTrapLatency=1 604fetchWidth=8 605forwardComSize=5 606fuPool=system.cpu1.fuPool 607function_trace=false 608function_trace_start=0 609iewToCommitDelay=1 610iewToDecodeDelay=1 611iewToFetchDelay=1 612iewToRenameDelay=1 613interrupts=system.cpu1.interrupts 614isa=system.cpu1.isa 615issueToExecuteDelay=1 616issueWidth=8 617itb=system.cpu1.itb 618max_insts_all_threads=0 619max_insts_any_thread=0 620max_loads_all_threads=0 621max_loads_any_thread=0 622needsTSO=false 623numIQEntries=64 624numPhysCCRegs=0 625numPhysFloatRegs=256 626numPhysIntRegs=256 627numROBEntries=192 628numRobs=1 629numThreads=1 630profile=0 631progress_interval=0 632renameToDecodeDelay=1 633renameToFetchDelay=1 634renameToIEWDelay=2 635renameToROBDelay=1 636renameWidth=8 637simpoint_start_insts= 638smtCommitPolicy=RoundRobin 639smtFetchPolicy=SingleThread 640smtIQPolicy=Partitioned 641smtIQThreshold=100 642smtLSQPolicy=Partitioned 643smtLSQThreshold=100 644smtNumFetchingThreads=1 645smtROBPolicy=Partitioned 646smtROBThreshold=100 647socket_id=0 648squashWidth=8 649store_set_clear_period=250000 650switched_out=false 651system=system 652tracer=system.cpu1.tracer 653trapLatency=13 654wbWidth=8 655workload= 656dcache_port=system.cpu1.dcache.cpu_side 657icache_port=system.cpu1.icache.cpu_side 658 659[system.cpu1.branchPred] 660type=TournamentBP 661BTBEntries=4096 662BTBTagSize=16 663RASSize=16 664choiceCtrBits=2 665choicePredictorSize=8192 666eventq_index=0 667globalCtrBits=2 668globalPredictorSize=8192 669instShiftAmt=2 670localCtrBits=2 671localHistoryTableSize=2048 672localPredictorSize=2048 673numThreads=1 674 675[system.cpu1.dcache] 676type=BaseCache 677children=tags 678addr_ranges=0:18446744073709551615 679assoc=4 680clk_domain=system.cpu_clk_domain 681demand_mshr_reserve=1 682eventq_index=0 683forward_snoops=true 684hit_latency=2 685is_top_level=true 686max_miss_count=0 687mshrs=4 688prefetch_on_access=false 689prefetcher=Null 690response_latency=2 691sequential_access=false 692size=32768 693system=system 694tags=system.cpu1.dcache.tags 695tgts_per_mshr=20 696two_queue=false 697write_buffers=8 698cpu_side=system.cpu1.dcache_port 699mem_side=system.toL2Bus.slave[3] 700 701[system.cpu1.dcache.tags] 702type=LRU 703assoc=4 704block_size=64 705clk_domain=system.cpu_clk_domain 706eventq_index=0 707hit_latency=2 708sequential_access=false 709size=32768 710 711[system.cpu1.dtb] 712type=AlphaTLB 713eventq_index=0 714size=64 715 716[system.cpu1.fuPool] 717type=FUPool 718children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 719FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 720eventq_index=0 721 722[system.cpu1.fuPool.FUList0] 723type=FUDesc 724children=opList 725count=6 726eventq_index=0 727opList=system.cpu1.fuPool.FUList0.opList 728 729[system.cpu1.fuPool.FUList0.opList] 730type=OpDesc 731eventq_index=0 732issueLat=1 733opClass=IntAlu 734opLat=1 735 736[system.cpu1.fuPool.FUList1] 737type=FUDesc 738children=opList0 opList1 739count=2 740eventq_index=0 741opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 742 743[system.cpu1.fuPool.FUList1.opList0] 744type=OpDesc 745eventq_index=0 746issueLat=1 747opClass=IntMult 748opLat=3 749 750[system.cpu1.fuPool.FUList1.opList1] 751type=OpDesc 752eventq_index=0 753issueLat=19 754opClass=IntDiv 755opLat=20 756 757[system.cpu1.fuPool.FUList2] 758type=FUDesc 759children=opList0 opList1 opList2 760count=4 761eventq_index=0 762opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 763 764[system.cpu1.fuPool.FUList2.opList0] 765type=OpDesc 766eventq_index=0 767issueLat=1 768opClass=FloatAdd 769opLat=2 770 771[system.cpu1.fuPool.FUList2.opList1] 772type=OpDesc 773eventq_index=0 774issueLat=1 775opClass=FloatCmp 776opLat=2 777 778[system.cpu1.fuPool.FUList2.opList2] 779type=OpDesc 780eventq_index=0 781issueLat=1 782opClass=FloatCvt 783opLat=2 784 785[system.cpu1.fuPool.FUList3] 786type=FUDesc 787children=opList0 opList1 opList2 788count=2 789eventq_index=0 790opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 791 792[system.cpu1.fuPool.FUList3.opList0] 793type=OpDesc 794eventq_index=0 795issueLat=1 796opClass=FloatMult 797opLat=4 798 799[system.cpu1.fuPool.FUList3.opList1] 800type=OpDesc 801eventq_index=0 802issueLat=12 803opClass=FloatDiv 804opLat=12 805 806[system.cpu1.fuPool.FUList3.opList2] 807type=OpDesc 808eventq_index=0 809issueLat=24 810opClass=FloatSqrt 811opLat=24 812 813[system.cpu1.fuPool.FUList4] 814type=FUDesc 815children=opList 816count=0 817eventq_index=0 818opList=system.cpu1.fuPool.FUList4.opList 819 820[system.cpu1.fuPool.FUList4.opList] 821type=OpDesc 822eventq_index=0 823issueLat=1 824opClass=MemRead 825opLat=1 826 827[system.cpu1.fuPool.FUList5] 828type=FUDesc 829children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 830count=4 831eventq_index=0 832opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 833 834[system.cpu1.fuPool.FUList5.opList00] 835type=OpDesc 836eventq_index=0 837issueLat=1 838opClass=SimdAdd 839opLat=1 840 841[system.cpu1.fuPool.FUList5.opList01] 842type=OpDesc 843eventq_index=0 844issueLat=1 845opClass=SimdAddAcc 846opLat=1 847 848[system.cpu1.fuPool.FUList5.opList02] 849type=OpDesc 850eventq_index=0 851issueLat=1 852opClass=SimdAlu 853opLat=1 854 855[system.cpu1.fuPool.FUList5.opList03] 856type=OpDesc 857eventq_index=0 858issueLat=1 859opClass=SimdCmp 860opLat=1 861 862[system.cpu1.fuPool.FUList5.opList04] 863type=OpDesc 864eventq_index=0 865issueLat=1 866opClass=SimdCvt 867opLat=1 868 869[system.cpu1.fuPool.FUList5.opList05] 870type=OpDesc 871eventq_index=0 872issueLat=1 873opClass=SimdMisc 874opLat=1 875 876[system.cpu1.fuPool.FUList5.opList06] 877type=OpDesc 878eventq_index=0 879issueLat=1 880opClass=SimdMult 881opLat=1 882 883[system.cpu1.fuPool.FUList5.opList07] 884type=OpDesc 885eventq_index=0 886issueLat=1 887opClass=SimdMultAcc 888opLat=1 889 890[system.cpu1.fuPool.FUList5.opList08] 891type=OpDesc 892eventq_index=0 893issueLat=1 894opClass=SimdShift 895opLat=1 896 897[system.cpu1.fuPool.FUList5.opList09] 898type=OpDesc 899eventq_index=0 900issueLat=1 901opClass=SimdShiftAcc 902opLat=1 903 904[system.cpu1.fuPool.FUList5.opList10] 905type=OpDesc 906eventq_index=0 907issueLat=1 908opClass=SimdSqrt 909opLat=1 910 911[system.cpu1.fuPool.FUList5.opList11] 912type=OpDesc 913eventq_index=0 914issueLat=1 915opClass=SimdFloatAdd 916opLat=1 917 918[system.cpu1.fuPool.FUList5.opList12] 919type=OpDesc 920eventq_index=0 921issueLat=1 922opClass=SimdFloatAlu 923opLat=1 924 925[system.cpu1.fuPool.FUList5.opList13] 926type=OpDesc 927eventq_index=0 928issueLat=1 929opClass=SimdFloatCmp 930opLat=1 931 932[system.cpu1.fuPool.FUList5.opList14] 933type=OpDesc 934eventq_index=0 935issueLat=1 936opClass=SimdFloatCvt 937opLat=1 938 939[system.cpu1.fuPool.FUList5.opList15] 940type=OpDesc 941eventq_index=0 942issueLat=1 943opClass=SimdFloatDiv 944opLat=1 945 946[system.cpu1.fuPool.FUList5.opList16] 947type=OpDesc 948eventq_index=0 949issueLat=1 950opClass=SimdFloatMisc 951opLat=1 952 953[system.cpu1.fuPool.FUList5.opList17] 954type=OpDesc 955eventq_index=0 956issueLat=1 957opClass=SimdFloatMult 958opLat=1 959 960[system.cpu1.fuPool.FUList5.opList18] 961type=OpDesc 962eventq_index=0 963issueLat=1 964opClass=SimdFloatMultAcc 965opLat=1 966 967[system.cpu1.fuPool.FUList5.opList19] 968type=OpDesc 969eventq_index=0 970issueLat=1 971opClass=SimdFloatSqrt 972opLat=1 973 974[system.cpu1.fuPool.FUList6] 975type=FUDesc 976children=opList 977count=0 978eventq_index=0 979opList=system.cpu1.fuPool.FUList6.opList 980 981[system.cpu1.fuPool.FUList6.opList] 982type=OpDesc 983eventq_index=0 984issueLat=1 985opClass=MemWrite 986opLat=1 987 988[system.cpu1.fuPool.FUList7] 989type=FUDesc 990children=opList0 opList1 991count=4 992eventq_index=0 993opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 994 995[system.cpu1.fuPool.FUList7.opList0] 996type=OpDesc 997eventq_index=0 998issueLat=1 999opClass=MemRead 1000opLat=1 1001 1002[system.cpu1.fuPool.FUList7.opList1] 1003type=OpDesc 1004eventq_index=0 1005issueLat=1 1006opClass=MemWrite 1007opLat=1 1008 1009[system.cpu1.fuPool.FUList8] 1010type=FUDesc 1011children=opList 1012count=1 1013eventq_index=0 1014opList=system.cpu1.fuPool.FUList8.opList 1015 1016[system.cpu1.fuPool.FUList8.opList] 1017type=OpDesc 1018eventq_index=0 1019issueLat=3 1020opClass=IprAccess 1021opLat=3 1022 1023[system.cpu1.icache] 1024type=BaseCache 1025children=tags 1026addr_ranges=0:18446744073709551615 1027assoc=1 1028clk_domain=system.cpu_clk_domain 1029demand_mshr_reserve=1 1030eventq_index=0 1031forward_snoops=true 1032hit_latency=2 1033is_top_level=true 1034max_miss_count=0 1035mshrs=4 1036prefetch_on_access=false 1037prefetcher=Null 1038response_latency=2 1039sequential_access=false 1040size=32768 1041system=system 1042tags=system.cpu1.icache.tags 1043tgts_per_mshr=20 1044two_queue=false 1045write_buffers=8 1046cpu_side=system.cpu1.icache_port 1047mem_side=system.toL2Bus.slave[2] 1048 1049[system.cpu1.icache.tags] 1050type=LRU 1051assoc=1 1052block_size=64 1053clk_domain=system.cpu_clk_domain 1054eventq_index=0 1055hit_latency=2 1056sequential_access=false 1057size=32768 1058 1059[system.cpu1.interrupts] 1060type=AlphaInterrupts 1061eventq_index=0 1062 1063[system.cpu1.isa] 1064type=AlphaISA 1065eventq_index=0 1066system=system 1067 1068[system.cpu1.itb] 1069type=AlphaTLB 1070eventq_index=0 1071size=48 1072 1073[system.cpu1.tracer] 1074type=ExeTracer 1075eventq_index=0 1076 1077[system.cpu_clk_domain] 1078type=SrcClockDomain 1079clock=500 1080domain_id=-1 1081eventq_index=0 1082init_perf_level=0 1083voltage_domain=system.voltage_domain 1084 1085[system.disk0] 1086type=IdeDisk 1087children=image 1088delay=1000000 1089driveID=master 1090eventq_index=0 1091image=system.disk0.image 1092 1093[system.disk0.image] 1094type=CowDiskImage 1095children=child 1096child=system.disk0.image.child 1097eventq_index=0 1098image_file= 1099read_only=false 1100table_size=65536 1101 1102[system.disk0.image.child] 1103type=RawDiskImage 1104eventq_index=0 1105image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img 1106read_only=true 1107 1108[system.disk2] 1109type=IdeDisk 1110children=image 1111delay=1000000 1112driveID=master 1113eventq_index=0 1114image=system.disk2.image 1115 1116[system.disk2.image] 1117type=CowDiskImage 1118children=child 1119child=system.disk2.image.child 1120eventq_index=0 1121image_file= 1122read_only=false 1123table_size=65536 1124 1125[system.disk2.image.child] 1126type=RawDiskImage 1127eventq_index=0 1128image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img 1129read_only=true 1130 1131[system.dvfs_handler] 1132type=DVFSHandler 1133domains= 1134enable=false 1135eventq_index=0 1136sys_clk_domain=system.clk_domain 1137transition_latency=100000000 1138 1139[system.intrctrl] 1140type=IntrControl 1141eventq_index=0 1142sys=system 1143 1144[system.iobus] 1145type=NoncoherentXBar 1146clk_domain=system.clk_domain 1147eventq_index=0 1148forward_latency=1 1149frontend_latency=2 1150response_latency=2 1151use_default_range=true 1152width=16 1153default=system.tsunami.pciconfig.pio 1154master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 1155slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 1156 1157[system.iocache] 1158type=BaseCache 1159children=tags 1160addr_ranges=0:134217727 1161assoc=8 1162clk_domain=system.clk_domain 1163demand_mshr_reserve=1 1164eventq_index=0 1165forward_snoops=false 1166hit_latency=50 1167is_top_level=true 1168max_miss_count=0 1169mshrs=20 1170prefetch_on_access=false 1171prefetcher=Null 1172response_latency=50 1173sequential_access=false 1174size=1024 1175system=system 1176tags=system.iocache.tags 1177tgts_per_mshr=12 1178two_queue=false 1179write_buffers=8 1180cpu_side=system.iobus.master[29] 1181mem_side=system.membus.slave[2] 1182 1183[system.iocache.tags] 1184type=LRU 1185assoc=8 1186block_size=64 1187clk_domain=system.clk_domain 1188eventq_index=0 1189hit_latency=50 1190sequential_access=false 1191size=1024 1192 1193[system.l2c] 1194type=BaseCache 1195children=tags 1196addr_ranges=0:18446744073709551615 1197assoc=8 1198clk_domain=system.cpu_clk_domain 1199demand_mshr_reserve=1 1200eventq_index=0 1201forward_snoops=true 1202hit_latency=20 1203is_top_level=false 1204max_miss_count=0 1205mshrs=20 1206prefetch_on_access=false 1207prefetcher=Null 1208response_latency=20 1209sequential_access=false 1210size=4194304 1211system=system 1212tags=system.l2c.tags 1213tgts_per_mshr=12 1214two_queue=false 1215write_buffers=8 1216cpu_side=system.toL2Bus.master[0] 1217mem_side=system.membus.slave[1] 1218 1219[system.l2c.tags] 1220type=LRU 1221assoc=8 1222block_size=64 1223clk_domain=system.cpu_clk_domain 1224eventq_index=0 1225hit_latency=20 1226sequential_access=false 1227size=4194304 1228 1229[system.membus] 1230type=CoherentXBar 1231children=badaddr_responder 1232clk_domain=system.clk_domain 1233eventq_index=0 1234forward_latency=4 1235frontend_latency=3 1236response_latency=2 1237snoop_filter=Null 1238snoop_response_latency=4 1239system=system 1240use_default_range=false 1241width=16 1242default=system.membus.badaddr_responder.pio 1243master=system.bridge.slave system.physmem.port 1244slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1245 1246[system.membus.badaddr_responder] 1247type=IsaFake 1248clk_domain=system.clk_domain 1249eventq_index=0 1250fake_mem=false 1251pio_addr=0 1252pio_latency=100000 1253pio_size=8 1254ret_bad_addr=true 1255ret_data16=65535 1256ret_data32=4294967295 1257ret_data64=18446744073709551615 1258ret_data8=255 1259system=system 1260update_data=false 1261warn_access= 1262pio=system.membus.default 1263 1264[system.physmem] 1265type=DRAMCtrl 1266IDD0=0.075000 1267IDD02=0.000000 1268IDD2N=0.050000 1269IDD2N2=0.000000 1270IDD2P0=0.000000 1271IDD2P02=0.000000 1272IDD2P1=0.000000 1273IDD2P12=0.000000 1274IDD3N=0.057000 1275IDD3N2=0.000000 1276IDD3P0=0.000000 1277IDD3P02=0.000000 1278IDD3P1=0.000000 1279IDD3P12=0.000000 1280IDD4R=0.187000 1281IDD4R2=0.000000 1282IDD4W=0.165000 1283IDD4W2=0.000000 1284IDD5=0.220000 1285IDD52=0.000000 1286IDD6=0.000000 1287IDD62=0.000000 1288VDD=1.500000 1289VDD2=0.000000 1290activation_limit=4 1291addr_mapping=RoRaBaCoCh 1292bank_groups_per_rank=0 1293banks_per_rank=8 1294burst_length=8 1295channels=1 1296clk_domain=system.clk_domain 1297conf_table_reported=true 1298device_bus_width=8 1299device_rowbuffer_size=1024 1300device_size=536870912 1301devices_per_rank=8 1302dll=true 1303eventq_index=0 1304in_addr_map=true 1305max_accesses_per_row=16 1306mem_sched_policy=frfcfs 1307min_writes_per_switch=16 1308null=false 1309page_policy=open_adaptive 1310range=0:134217727 1311ranks_per_channel=2 1312read_buffer_size=32 1313static_backend_latency=10000 1314static_frontend_latency=10000 1315tBURST=5000 1316tCCD_L=0 1317tCK=1250 1318tCL=13750 1319tCS=2500 1320tRAS=35000 1321tRCD=13750 1322tREFI=7800000 1323tRFC=260000 1324tRP=13750 1325tRRD=6000 1326tRRD_L=0 1327tRTP=7500 1328tRTW=2500 1329tWR=15000 1330tWTR=7500 1331tXAW=30000 1332tXP=0 1333tXPDLL=0 1334tXS=0 1335tXSDLL=0 1336write_buffer_size=64 1337write_high_thresh_perc=85 1338write_low_thresh_perc=50 1339port=system.membus.master[1] 1340 1341[system.simple_disk] 1342type=SimpleDisk 1343children=disk 1344disk=system.simple_disk.disk 1345eventq_index=0 1346system=system 1347 1348[system.simple_disk.disk] 1349type=RawDiskImage 1350eventq_index=0 1351image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img 1352read_only=true 1353 1354[system.terminal] 1355type=Terminal 1356eventq_index=0 1357intr_control=system.intrctrl 1358number=0 1359output=true 1360port=3456 1361 1362[system.toL2Bus] 1363type=CoherentXBar 1364clk_domain=system.cpu_clk_domain 1365eventq_index=0 1366forward_latency=0 1367frontend_latency=1 1368response_latency=1 1369snoop_filter=Null 1370snoop_response_latency=1 1371system=system 1372use_default_range=false 1373width=32 1374master=system.l2c.cpu_side 1375slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1376 1377[system.tsunami] 1378type=Tsunami 1379children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1380eventq_index=0 1381intrctrl=system.intrctrl 1382system=system 1383 1384[system.tsunami.backdoor] 1385type=AlphaBackdoor 1386clk_domain=system.clk_domain 1387cpu=system.cpu0 1388disk=system.simple_disk 1389eventq_index=0 1390pio_addr=8804682956800 1391pio_latency=100000 1392platform=system.tsunami 1393system=system 1394terminal=system.terminal 1395pio=system.iobus.master[24] 1396 1397[system.tsunami.cchip] 1398type=TsunamiCChip 1399clk_domain=system.clk_domain 1400eventq_index=0 1401pio_addr=8803072344064 1402pio_latency=100000 1403system=system 1404tsunami=system.tsunami 1405pio=system.iobus.master[0] 1406 1407[system.tsunami.ethernet] 1408type=NSGigE 1409BAR0=1 1410BAR0LegacyIO=false 1411BAR0Size=256 1412BAR1=0 1413BAR1LegacyIO=false 1414BAR1Size=4096 1415BAR2=0 1416BAR2LegacyIO=false 1417BAR2Size=0 1418BAR3=0 1419BAR3LegacyIO=false 1420BAR3Size=0 1421BAR4=0 1422BAR4LegacyIO=false 1423BAR4Size=0 1424BAR5=0 1425BAR5LegacyIO=false 1426BAR5Size=0 1427BIST=0 1428CacheLineSize=0 1429CapabilityPtr=0 1430CardbusCIS=0 1431ClassCode=2 1432Command=0 1433DeviceID=34 1434ExpansionROM=0 1435HeaderType=0 1436InterruptLine=30 1437InterruptPin=1 1438LatencyTimer=0 1439LegacyIOBase=0 1440MSICAPBaseOffset=0 1441MSICAPCapId=0 1442MSICAPMaskBits=0 1443MSICAPMsgAddr=0 1444MSICAPMsgCtrl=0 1445MSICAPMsgData=0 1446MSICAPMsgUpperAddr=0 1447MSICAPNextCapability=0 1448MSICAPPendingBits=0 1449MSIXCAPBaseOffset=0 1450MSIXCAPCapId=0 1451MSIXCAPNextCapability=0 1452MSIXMsgCtrl=0 1453MSIXPbaOffset=0 1454MSIXTableOffset=0 1455MaximumLatency=52 1456MinimumGrant=176 1457PMCAPBaseOffset=0 1458PMCAPCapId=0 1459PMCAPCapabilities=0 1460PMCAPCtrlStatus=0 1461PMCAPNextCapability=0 1462PXCAPBaseOffset=0 1463PXCAPCapId=0 1464PXCAPCapabilities=0 1465PXCAPDevCap2=0 1466PXCAPDevCapabilities=0 1467PXCAPDevCtrl=0 1468PXCAPDevCtrl2=0 1469PXCAPDevStatus=0 1470PXCAPLinkCap=0 1471PXCAPLinkCtrl=0 1472PXCAPLinkStatus=0 1473PXCAPNextCapability=0 1474ProgIF=0 1475Revision=0 1476Status=656 1477SubClassCode=0 1478SubsystemID=0 1479SubsystemVendorID=0 1480VendorID=4107 1481clk_domain=system.clk_domain 1482config_latency=20000 1483dma_data_free=false 1484dma_desc_free=false 1485dma_no_allocate=true 1486dma_read_delay=0 1487dma_read_factor=0 1488dma_write_delay=0 1489dma_write_factor=0 1490eventq_index=0 1491hardware_address=00:90:00:00:00:01 1492intr_delay=10000000 1493pci_bus=0 1494pci_dev=1 1495pci_func=0 1496pio_latency=30000 1497platform=system.tsunami 1498rss=false 1499rx_delay=1000000 1500rx_fifo_size=524288 1501rx_filter=true 1502rx_thread=false 1503system=system 1504tx_delay=1000000 1505tx_fifo_size=524288 1506tx_thread=false 1507config=system.iobus.master[28] 1508dma=system.iobus.slave[2] 1509pio=system.iobus.master[27] 1510 1511[system.tsunami.fake_OROM] 1512type=IsaFake 1513clk_domain=system.clk_domain 1514eventq_index=0 1515fake_mem=false 1516pio_addr=8796093677568 1517pio_latency=100000 1518pio_size=393216 1519ret_bad_addr=false 1520ret_data16=65535 1521ret_data32=4294967295 1522ret_data64=18446744073709551615 1523ret_data8=255 1524system=system 1525update_data=false 1526warn_access= 1527pio=system.iobus.master[8] 1528 1529[system.tsunami.fake_ata0] 1530type=IsaFake 1531clk_domain=system.clk_domain 1532eventq_index=0 1533fake_mem=false 1534pio_addr=8804615848432 1535pio_latency=100000 1536pio_size=8 1537ret_bad_addr=false 1538ret_data16=65535 1539ret_data32=4294967295 1540ret_data64=18446744073709551615 1541ret_data8=255 1542system=system 1543update_data=false 1544warn_access= 1545pio=system.iobus.master[19] 1546 1547[system.tsunami.fake_ata1] 1548type=IsaFake 1549clk_domain=system.clk_domain 1550eventq_index=0 1551fake_mem=false 1552pio_addr=8804615848304 1553pio_latency=100000 1554pio_size=8 1555ret_bad_addr=false 1556ret_data16=65535 1557ret_data32=4294967295 1558ret_data64=18446744073709551615 1559ret_data8=255 1560system=system 1561update_data=false 1562warn_access= 1563pio=system.iobus.master[20] 1564 1565[system.tsunami.fake_pnp_addr] 1566type=IsaFake 1567clk_domain=system.clk_domain 1568eventq_index=0 1569fake_mem=false 1570pio_addr=8804615848569 1571pio_latency=100000 1572pio_size=8 1573ret_bad_addr=false 1574ret_data16=65535 1575ret_data32=4294967295 1576ret_data64=18446744073709551615 1577ret_data8=255 1578system=system 1579update_data=false 1580warn_access= 1581pio=system.iobus.master[9] 1582 1583[system.tsunami.fake_pnp_read0] 1584type=IsaFake 1585clk_domain=system.clk_domain 1586eventq_index=0 1587fake_mem=false 1588pio_addr=8804615848451 1589pio_latency=100000 1590pio_size=8 1591ret_bad_addr=false 1592ret_data16=65535 1593ret_data32=4294967295 1594ret_data64=18446744073709551615 1595ret_data8=255 1596system=system 1597update_data=false 1598warn_access= 1599pio=system.iobus.master[11] 1600 1601[system.tsunami.fake_pnp_read1] 1602type=IsaFake 1603clk_domain=system.clk_domain 1604eventq_index=0 1605fake_mem=false 1606pio_addr=8804615848515 1607pio_latency=100000 1608pio_size=8 1609ret_bad_addr=false 1610ret_data16=65535 1611ret_data32=4294967295 1612ret_data64=18446744073709551615 1613ret_data8=255 1614system=system 1615update_data=false 1616warn_access= 1617pio=system.iobus.master[12] 1618 1619[system.tsunami.fake_pnp_read2] 1620type=IsaFake 1621clk_domain=system.clk_domain 1622eventq_index=0 1623fake_mem=false 1624pio_addr=8804615848579 1625pio_latency=100000 1626pio_size=8 1627ret_bad_addr=false 1628ret_data16=65535 1629ret_data32=4294967295 1630ret_data64=18446744073709551615 1631ret_data8=255 1632system=system 1633update_data=false 1634warn_access= 1635pio=system.iobus.master[13] 1636 1637[system.tsunami.fake_pnp_read3] 1638type=IsaFake 1639clk_domain=system.clk_domain 1640eventq_index=0 1641fake_mem=false 1642pio_addr=8804615848643 1643pio_latency=100000 1644pio_size=8 1645ret_bad_addr=false 1646ret_data16=65535 1647ret_data32=4294967295 1648ret_data64=18446744073709551615 1649ret_data8=255 1650system=system 1651update_data=false 1652warn_access= 1653pio=system.iobus.master[14] 1654 1655[system.tsunami.fake_pnp_read4] 1656type=IsaFake 1657clk_domain=system.clk_domain 1658eventq_index=0 1659fake_mem=false 1660pio_addr=8804615848707 1661pio_latency=100000 1662pio_size=8 1663ret_bad_addr=false 1664ret_data16=65535 1665ret_data32=4294967295 1666ret_data64=18446744073709551615 1667ret_data8=255 1668system=system 1669update_data=false 1670warn_access= 1671pio=system.iobus.master[15] 1672 1673[system.tsunami.fake_pnp_read5] 1674type=IsaFake 1675clk_domain=system.clk_domain 1676eventq_index=0 1677fake_mem=false 1678pio_addr=8804615848771 1679pio_latency=100000 1680pio_size=8 1681ret_bad_addr=false 1682ret_data16=65535 1683ret_data32=4294967295 1684ret_data64=18446744073709551615 1685ret_data8=255 1686system=system 1687update_data=false 1688warn_access= 1689pio=system.iobus.master[16] 1690 1691[system.tsunami.fake_pnp_read6] 1692type=IsaFake 1693clk_domain=system.clk_domain 1694eventq_index=0 1695fake_mem=false 1696pio_addr=8804615848835 1697pio_latency=100000 1698pio_size=8 1699ret_bad_addr=false 1700ret_data16=65535 1701ret_data32=4294967295 1702ret_data64=18446744073709551615 1703ret_data8=255 1704system=system 1705update_data=false 1706warn_access= 1707pio=system.iobus.master[17] 1708 1709[system.tsunami.fake_pnp_read7] 1710type=IsaFake 1711clk_domain=system.clk_domain 1712eventq_index=0 1713fake_mem=false 1714pio_addr=8804615848899 1715pio_latency=100000 1716pio_size=8 1717ret_bad_addr=false 1718ret_data16=65535 1719ret_data32=4294967295 1720ret_data64=18446744073709551615 1721ret_data8=255 1722system=system 1723update_data=false 1724warn_access= 1725pio=system.iobus.master[18] 1726 1727[system.tsunami.fake_pnp_write] 1728type=IsaFake 1729clk_domain=system.clk_domain 1730eventq_index=0 1731fake_mem=false 1732pio_addr=8804615850617 1733pio_latency=100000 1734pio_size=8 1735ret_bad_addr=false 1736ret_data16=65535 1737ret_data32=4294967295 1738ret_data64=18446744073709551615 1739ret_data8=255 1740system=system 1741update_data=false 1742warn_access= 1743pio=system.iobus.master[10] 1744 1745[system.tsunami.fake_ppc] 1746type=IsaFake 1747clk_domain=system.clk_domain 1748eventq_index=0 1749fake_mem=false 1750pio_addr=8804615848891 1751pio_latency=100000 1752pio_size=8 1753ret_bad_addr=false 1754ret_data16=65535 1755ret_data32=4294967295 1756ret_data64=18446744073709551615 1757ret_data8=255 1758system=system 1759update_data=false 1760warn_access= 1761pio=system.iobus.master[7] 1762 1763[system.tsunami.fake_sm_chip] 1764type=IsaFake 1765clk_domain=system.clk_domain 1766eventq_index=0 1767fake_mem=false 1768pio_addr=8804615848816 1769pio_latency=100000 1770pio_size=8 1771ret_bad_addr=false 1772ret_data16=65535 1773ret_data32=4294967295 1774ret_data64=18446744073709551615 1775ret_data8=255 1776system=system 1777update_data=false 1778warn_access= 1779pio=system.iobus.master[2] 1780 1781[system.tsunami.fake_uart1] 1782type=IsaFake 1783clk_domain=system.clk_domain 1784eventq_index=0 1785fake_mem=false 1786pio_addr=8804615848696 1787pio_latency=100000 1788pio_size=8 1789ret_bad_addr=false 1790ret_data16=65535 1791ret_data32=4294967295 1792ret_data64=18446744073709551615 1793ret_data8=255 1794system=system 1795update_data=false 1796warn_access= 1797pio=system.iobus.master[3] 1798 1799[system.tsunami.fake_uart2] 1800type=IsaFake 1801clk_domain=system.clk_domain 1802eventq_index=0 1803fake_mem=false 1804pio_addr=8804615848936 1805pio_latency=100000 1806pio_size=8 1807ret_bad_addr=false 1808ret_data16=65535 1809ret_data32=4294967295 1810ret_data64=18446744073709551615 1811ret_data8=255 1812system=system 1813update_data=false 1814warn_access= 1815pio=system.iobus.master[4] 1816 1817[system.tsunami.fake_uart3] 1818type=IsaFake 1819clk_domain=system.clk_domain 1820eventq_index=0 1821fake_mem=false 1822pio_addr=8804615848680 1823pio_latency=100000 1824pio_size=8 1825ret_bad_addr=false 1826ret_data16=65535 1827ret_data32=4294967295 1828ret_data64=18446744073709551615 1829ret_data8=255 1830system=system 1831update_data=false 1832warn_access= 1833pio=system.iobus.master[5] 1834 1835[system.tsunami.fake_uart4] 1836type=IsaFake 1837clk_domain=system.clk_domain 1838eventq_index=0 1839fake_mem=false 1840pio_addr=8804615848944 1841pio_latency=100000 1842pio_size=8 1843ret_bad_addr=false 1844ret_data16=65535 1845ret_data32=4294967295 1846ret_data64=18446744073709551615 1847ret_data8=255 1848system=system 1849update_data=false 1850warn_access= 1851pio=system.iobus.master[6] 1852 1853[system.tsunami.fb] 1854type=BadDevice 1855clk_domain=system.clk_domain 1856devicename=FrameBuffer 1857eventq_index=0 1858pio_addr=8804615848912 1859pio_latency=100000 1860system=system 1861pio=system.iobus.master[21] 1862 1863[system.tsunami.ide] 1864type=IdeController 1865BAR0=1 1866BAR0LegacyIO=false 1867BAR0Size=8 1868BAR1=1 1869BAR1LegacyIO=false 1870BAR1Size=4 1871BAR2=1 1872BAR2LegacyIO=false 1873BAR2Size=8 1874BAR3=1 1875BAR3LegacyIO=false 1876BAR3Size=4 1877BAR4=1 1878BAR4LegacyIO=false 1879BAR4Size=16 1880BAR5=1 1881BAR5LegacyIO=false 1882BAR5Size=0 1883BIST=0 1884CacheLineSize=0 1885CapabilityPtr=0 1886CardbusCIS=0 1887ClassCode=1 1888Command=0 1889DeviceID=28945 1890ExpansionROM=0 1891HeaderType=0 1892InterruptLine=31 1893InterruptPin=1 1894LatencyTimer=0 1895LegacyIOBase=0 1896MSICAPBaseOffset=0 1897MSICAPCapId=0 1898MSICAPMaskBits=0 1899MSICAPMsgAddr=0 1900MSICAPMsgCtrl=0 1901MSICAPMsgData=0 1902MSICAPMsgUpperAddr=0 1903MSICAPNextCapability=0 1904MSICAPPendingBits=0 1905MSIXCAPBaseOffset=0 1906MSIXCAPCapId=0 1907MSIXCAPNextCapability=0 1908MSIXMsgCtrl=0 1909MSIXPbaOffset=0 1910MSIXTableOffset=0 1911MaximumLatency=0 1912MinimumGrant=0 1913PMCAPBaseOffset=0 1914PMCAPCapId=0 1915PMCAPCapabilities=0 1916PMCAPCtrlStatus=0 1917PMCAPNextCapability=0 1918PXCAPBaseOffset=0 1919PXCAPCapId=0 1920PXCAPCapabilities=0 1921PXCAPDevCap2=0 1922PXCAPDevCapabilities=0 1923PXCAPDevCtrl=0 1924PXCAPDevCtrl2=0 1925PXCAPDevStatus=0 1926PXCAPLinkCap=0 1927PXCAPLinkCtrl=0 1928PXCAPLinkStatus=0 1929PXCAPNextCapability=0 1930ProgIF=133 1931Revision=0 1932Status=640 1933SubClassCode=1 1934SubsystemID=0 1935SubsystemVendorID=0 1936VendorID=32902 1937clk_domain=system.clk_domain 1938config_latency=20000 1939ctrl_offset=0 1940disks=system.disk0 system.disk2 1941eventq_index=0 1942io_shift=0 1943pci_bus=0 1944pci_dev=0 1945pci_func=0 1946pio_latency=30000 1947platform=system.tsunami 1948system=system 1949config=system.iobus.master[26] 1950dma=system.iobus.slave[1] 1951pio=system.iobus.master[25] 1952 1953[system.tsunami.io] 1954type=TsunamiIO 1955clk_domain=system.clk_domain 1956eventq_index=0 1957frequency=976562500 1958pio_addr=8804615847936 1959pio_latency=100000 1960system=system 1961time=Thu Jan 1 00:00:00 2009 1962tsunami=system.tsunami 1963year_is_bcd=false 1964pio=system.iobus.master[22] 1965 1966[system.tsunami.pchip] 1967type=TsunamiPChip 1968clk_domain=system.clk_domain 1969eventq_index=0 1970pio_addr=8802535473152 1971pio_latency=100000 1972system=system 1973tsunami=system.tsunami 1974pio=system.iobus.master[1] 1975 1976[system.tsunami.pciconfig] 1977type=PciConfigAll 1978bus=0 1979clk_domain=system.clk_domain 1980eventq_index=0 1981pio_addr=0 1982pio_latency=30000 1983platform=system.tsunami 1984size=16777216 1985system=system 1986pio=system.iobus.default 1987 1988[system.tsunami.uart] 1989type=Uart8250 1990clk_domain=system.clk_domain 1991eventq_index=0 1992pio_addr=8804615848952 1993pio_latency=100000 1994platform=system.tsunami 1995system=system 1996terminal=system.terminal 1997pio=system.iobus.master[23] 1998 1999[system.voltage_domain] 2000type=VoltageDomain 2001eventq_index=0 2002voltage=1.000000 2003 2004