config.ini revision 9348
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000 15console=/projects/pd/randd/dist/binaries/console 16init_param=0 17kernel=/projects/pd/randd/dist/binaries/vmlinux 18load_addr_mask=1099511627775 19mem_mode=timing 20memories=system.physmem 21num_work_ids=16 22pal=/projects/pd/randd/dist/binaries/ts_osfpal 23readfile=tests/halt.sh 24symbolfile= 25system_rev=1024 26system_type=34 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.bridge] 37type=Bridge 38clock=1000 39delay=50000 40ranges=8796093022208:18446744073709551615 41req_size=16 42resp_size=16 43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu0] 47type=DerivO3CPU 48children=dcache dtb fuPool icache interrupts isa itb tracer 49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74defer_registration=false 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu0.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu0.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu0.interrupts 96isa=system.cpu0.isa 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu0.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000 134system=system 135tracer=system.cpu0.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu0.dcache.cpu_side 141icache_port=system.cpu0.icache.cpu_side 142 143[system.cpu0.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64 148clock=500 149forward_snoops=true 150hash_delay=1 151hit_latency=2 152is_top_level=true 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null 157prioritizeRequests=false 158repl=Null 159response_latency=2 160size=32768 161subblock_size=0 162system=system 163tgts_per_mshr=20 164trace_addr=0 165two_queue=false 166write_buffers=8 167cpu_side=system.cpu0.dcache_port 168mem_side=system.toL2Bus.slave[1] 169 170[system.cpu0.dtb] 171type=AlphaTLB 172size=64 173 174[system.cpu0.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 178 179[system.cpu0.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu0.fuPool.FUList0.opList 184 185[system.cpu0.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu0.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 196 197[system.cpu0.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu0.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu0.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 214 215[system.cpu0.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu0.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu0.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu0.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 238 239[system.cpu0.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu0.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu0.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu0.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu0.fuPool.FUList4.opList 262 263[system.cpu0.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu0.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 274 275[system.cpu0.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu0.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu0.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu0.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu0.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu0.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu0.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu0.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu0.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu0.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu0.fuPool.FUList6.opList 400 401[system.cpu0.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu0.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 412 413[system.cpu0.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu0.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu0.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu0.fuPool.FUList8.opList 430 431[system.cpu0.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu0.icache] 438type=BaseCache 439addr_ranges=0:18446744073709551615 440assoc=1 441block_size=64 442clock=500 443forward_snoops=true 444hash_delay=1 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451prioritizeRequests=false 452repl=Null 453response_latency=2 454size=32768 455subblock_size=0 456system=system 457tgts_per_mshr=20 458trace_addr=0 459two_queue=false 460write_buffers=8 461cpu_side=system.cpu0.icache_port 462mem_side=system.toL2Bus.slave[0] 463 464[system.cpu0.interrupts] 465type=AlphaInterrupts 466 467[system.cpu0.isa] 468type=AlphaISA 469 470[system.cpu0.itb] 471type=AlphaTLB 472size=48 473 474[system.cpu0.tracer] 475type=ExeTracer 476 477[system.cpu1] 478type=DerivO3CPU 479children=dcache dtb fuPool icache interrupts isa itb tracer 480BTBEntries=4096 481BTBTagSize=16 482LFSTSize=1024 483LQEntries=32 484LSQCheckLoads=true 485LSQDepCheckShift=4 486RASSize=16 487SQEntries=32 488SSITSize=1024 489activity=0 490backComSize=5 491cachePorts=200 492checker=Null 493choiceCtrBits=2 494choicePredictorSize=8192 495clock=500 496commitToDecodeDelay=1 497commitToFetchDelay=1 498commitToIEWDelay=1 499commitToRenameDelay=1 500commitWidth=8 501cpu_id=1 502decodeToFetchDelay=1 503decodeToRenameDelay=1 504decodeWidth=8 505defer_registration=false 506dispatchWidth=8 507do_checkpoint_insts=true 508do_quiesce=true 509do_statistics_insts=true 510dtb=system.cpu1.dtb 511fetchToDecodeDelay=1 512fetchTrapLatency=1 513fetchWidth=8 514forwardComSize=5 515fuPool=system.cpu1.fuPool 516function_trace=false 517function_trace_start=0 518globalCtrBits=2 519globalHistoryBits=13 520globalPredictorSize=8192 521iewToCommitDelay=1 522iewToDecodeDelay=1 523iewToFetchDelay=1 524iewToRenameDelay=1 525instShiftAmt=2 526interrupts=system.cpu1.interrupts 527isa=system.cpu1.isa 528issueToExecuteDelay=1 529issueWidth=8 530itb=system.cpu1.itb 531localCtrBits=2 532localHistoryBits=11 533localHistoryTableSize=2048 534localPredictorSize=2048 535max_insts_all_threads=0 536max_insts_any_thread=0 537max_loads_all_threads=0 538max_loads_any_thread=0 539needsTSO=false 540numIQEntries=64 541numPhysFloatRegs=256 542numPhysIntRegs=256 543numROBEntries=192 544numRobs=1 545numThreads=1 546predType=tournament 547profile=0 548progress_interval=0 549renameToDecodeDelay=1 550renameToFetchDelay=1 551renameToIEWDelay=2 552renameToROBDelay=1 553renameWidth=8 554smtCommitPolicy=RoundRobin 555smtFetchPolicy=SingleThread 556smtIQPolicy=Partitioned 557smtIQThreshold=100 558smtLSQPolicy=Partitioned 559smtLSQThreshold=100 560smtNumFetchingThreads=1 561smtROBPolicy=Partitioned 562smtROBThreshold=100 563squashWidth=8 564store_set_clear_period=250000 565system=system 566tracer=system.cpu1.tracer 567trapLatency=13 568wbDepth=1 569wbWidth=8 570workload= 571dcache_port=system.cpu1.dcache.cpu_side 572icache_port=system.cpu1.icache.cpu_side 573 574[system.cpu1.dcache] 575type=BaseCache 576addr_ranges=0:18446744073709551615 577assoc=4 578block_size=64 579clock=500 580forward_snoops=true 581hash_delay=1 582hit_latency=2 583is_top_level=true 584max_miss_count=0 585mshrs=4 586prefetch_on_access=false 587prefetcher=Null 588prioritizeRequests=false 589repl=Null 590response_latency=2 591size=32768 592subblock_size=0 593system=system 594tgts_per_mshr=20 595trace_addr=0 596two_queue=false 597write_buffers=8 598cpu_side=system.cpu1.dcache_port 599mem_side=system.toL2Bus.slave[3] 600 601[system.cpu1.dtb] 602type=AlphaTLB 603size=64 604 605[system.cpu1.fuPool] 606type=FUPool 607children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 608FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 609 610[system.cpu1.fuPool.FUList0] 611type=FUDesc 612children=opList 613count=6 614opList=system.cpu1.fuPool.FUList0.opList 615 616[system.cpu1.fuPool.FUList0.opList] 617type=OpDesc 618issueLat=1 619opClass=IntAlu 620opLat=1 621 622[system.cpu1.fuPool.FUList1] 623type=FUDesc 624children=opList0 opList1 625count=2 626opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 627 628[system.cpu1.fuPool.FUList1.opList0] 629type=OpDesc 630issueLat=1 631opClass=IntMult 632opLat=3 633 634[system.cpu1.fuPool.FUList1.opList1] 635type=OpDesc 636issueLat=19 637opClass=IntDiv 638opLat=20 639 640[system.cpu1.fuPool.FUList2] 641type=FUDesc 642children=opList0 opList1 opList2 643count=4 644opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 645 646[system.cpu1.fuPool.FUList2.opList0] 647type=OpDesc 648issueLat=1 649opClass=FloatAdd 650opLat=2 651 652[system.cpu1.fuPool.FUList2.opList1] 653type=OpDesc 654issueLat=1 655opClass=FloatCmp 656opLat=2 657 658[system.cpu1.fuPool.FUList2.opList2] 659type=OpDesc 660issueLat=1 661opClass=FloatCvt 662opLat=2 663 664[system.cpu1.fuPool.FUList3] 665type=FUDesc 666children=opList0 opList1 opList2 667count=2 668opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 669 670[system.cpu1.fuPool.FUList3.opList0] 671type=OpDesc 672issueLat=1 673opClass=FloatMult 674opLat=4 675 676[system.cpu1.fuPool.FUList3.opList1] 677type=OpDesc 678issueLat=12 679opClass=FloatDiv 680opLat=12 681 682[system.cpu1.fuPool.FUList3.opList2] 683type=OpDesc 684issueLat=24 685opClass=FloatSqrt 686opLat=24 687 688[system.cpu1.fuPool.FUList4] 689type=FUDesc 690children=opList 691count=0 692opList=system.cpu1.fuPool.FUList4.opList 693 694[system.cpu1.fuPool.FUList4.opList] 695type=OpDesc 696issueLat=1 697opClass=MemRead 698opLat=1 699 700[system.cpu1.fuPool.FUList5] 701type=FUDesc 702children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 703count=4 704opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 705 706[system.cpu1.fuPool.FUList5.opList00] 707type=OpDesc 708issueLat=1 709opClass=SimdAdd 710opLat=1 711 712[system.cpu1.fuPool.FUList5.opList01] 713type=OpDesc 714issueLat=1 715opClass=SimdAddAcc 716opLat=1 717 718[system.cpu1.fuPool.FUList5.opList02] 719type=OpDesc 720issueLat=1 721opClass=SimdAlu 722opLat=1 723 724[system.cpu1.fuPool.FUList5.opList03] 725type=OpDesc 726issueLat=1 727opClass=SimdCmp 728opLat=1 729 730[system.cpu1.fuPool.FUList5.opList04] 731type=OpDesc 732issueLat=1 733opClass=SimdCvt 734opLat=1 735 736[system.cpu1.fuPool.FUList5.opList05] 737type=OpDesc 738issueLat=1 739opClass=SimdMisc 740opLat=1 741 742[system.cpu1.fuPool.FUList5.opList06] 743type=OpDesc 744issueLat=1 745opClass=SimdMult 746opLat=1 747 748[system.cpu1.fuPool.FUList5.opList07] 749type=OpDesc 750issueLat=1 751opClass=SimdMultAcc 752opLat=1 753 754[system.cpu1.fuPool.FUList5.opList08] 755type=OpDesc 756issueLat=1 757opClass=SimdShift 758opLat=1 759 760[system.cpu1.fuPool.FUList5.opList09] 761type=OpDesc 762issueLat=1 763opClass=SimdShiftAcc 764opLat=1 765 766[system.cpu1.fuPool.FUList5.opList10] 767type=OpDesc 768issueLat=1 769opClass=SimdSqrt 770opLat=1 771 772[system.cpu1.fuPool.FUList5.opList11] 773type=OpDesc 774issueLat=1 775opClass=SimdFloatAdd 776opLat=1 777 778[system.cpu1.fuPool.FUList5.opList12] 779type=OpDesc 780issueLat=1 781opClass=SimdFloatAlu 782opLat=1 783 784[system.cpu1.fuPool.FUList5.opList13] 785type=OpDesc 786issueLat=1 787opClass=SimdFloatCmp 788opLat=1 789 790[system.cpu1.fuPool.FUList5.opList14] 791type=OpDesc 792issueLat=1 793opClass=SimdFloatCvt 794opLat=1 795 796[system.cpu1.fuPool.FUList5.opList15] 797type=OpDesc 798issueLat=1 799opClass=SimdFloatDiv 800opLat=1 801 802[system.cpu1.fuPool.FUList5.opList16] 803type=OpDesc 804issueLat=1 805opClass=SimdFloatMisc 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList17] 809type=OpDesc 810issueLat=1 811opClass=SimdFloatMult 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList18] 815type=OpDesc 816issueLat=1 817opClass=SimdFloatMultAcc 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList19] 821type=OpDesc 822issueLat=1 823opClass=SimdFloatSqrt 824opLat=1 825 826[system.cpu1.fuPool.FUList6] 827type=FUDesc 828children=opList 829count=0 830opList=system.cpu1.fuPool.FUList6.opList 831 832[system.cpu1.fuPool.FUList6.opList] 833type=OpDesc 834issueLat=1 835opClass=MemWrite 836opLat=1 837 838[system.cpu1.fuPool.FUList7] 839type=FUDesc 840children=opList0 opList1 841count=4 842opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 843 844[system.cpu1.fuPool.FUList7.opList0] 845type=OpDesc 846issueLat=1 847opClass=MemRead 848opLat=1 849 850[system.cpu1.fuPool.FUList7.opList1] 851type=OpDesc 852issueLat=1 853opClass=MemWrite 854opLat=1 855 856[system.cpu1.fuPool.FUList8] 857type=FUDesc 858children=opList 859count=1 860opList=system.cpu1.fuPool.FUList8.opList 861 862[system.cpu1.fuPool.FUList8.opList] 863type=OpDesc 864issueLat=3 865opClass=IprAccess 866opLat=3 867 868[system.cpu1.icache] 869type=BaseCache 870addr_ranges=0:18446744073709551615 871assoc=1 872block_size=64 873clock=500 874forward_snoops=true 875hash_delay=1 876hit_latency=2 877is_top_level=true 878max_miss_count=0 879mshrs=4 880prefetch_on_access=false 881prefetcher=Null 882prioritizeRequests=false 883repl=Null 884response_latency=2 885size=32768 886subblock_size=0 887system=system 888tgts_per_mshr=20 889trace_addr=0 890two_queue=false 891write_buffers=8 892cpu_side=system.cpu1.icache_port 893mem_side=system.toL2Bus.slave[2] 894 895[system.cpu1.interrupts] 896type=AlphaInterrupts 897 898[system.cpu1.isa] 899type=AlphaISA 900 901[system.cpu1.itb] 902type=AlphaTLB 903size=48 904 905[system.cpu1.tracer] 906type=ExeTracer 907 908[system.disk0] 909type=IdeDisk 910children=image 911delay=1000000 912driveID=master 913image=system.disk0.image 914 915[system.disk0.image] 916type=CowDiskImage 917children=child 918child=system.disk0.image.child 919image_file= 920read_only=false 921table_size=65536 922 923[system.disk0.image.child] 924type=RawDiskImage 925image_file=/projects/pd/randd/dist/disks/linux-latest.img 926read_only=true 927 928[system.disk2] 929type=IdeDisk 930children=image 931delay=1000000 932driveID=master 933image=system.disk2.image 934 935[system.disk2.image] 936type=CowDiskImage 937children=child 938child=system.disk2.image.child 939image_file= 940read_only=false 941table_size=65536 942 943[system.disk2.image.child] 944type=RawDiskImage 945image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img 946read_only=true 947 948[system.intrctrl] 949type=IntrControl 950sys=system 951 952[system.iobus] 953type=NoncoherentBus 954block_size=64 955clock=1000 956header_cycles=1 957use_default_range=true 958width=8 959default=system.tsunami.pciconfig.pio 960master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 961slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 962 963[system.iocache] 964type=BaseCache 965addr_ranges=0:8589934591 966assoc=8 967block_size=64 968clock=1000 969forward_snoops=false 970hash_delay=1 971hit_latency=50 972is_top_level=true 973max_miss_count=0 974mshrs=20 975prefetch_on_access=false 976prefetcher=Null 977prioritizeRequests=false 978repl=Null 979response_latency=50 980size=1024 981subblock_size=0 982system=system 983tgts_per_mshr=12 984trace_addr=0 985two_queue=false 986write_buffers=8 987cpu_side=system.iobus.master[29] 988mem_side=system.membus.slave[1] 989 990[system.l2c] 991type=BaseCache 992addr_ranges=0:18446744073709551615 993assoc=8 994block_size=64 995clock=500 996forward_snoops=true 997hash_delay=1 998hit_latency=20 999is_top_level=false 1000max_miss_count=0 1001mshrs=20 1002prefetch_on_access=false 1003prefetcher=Null 1004prioritizeRequests=false 1005repl=Null 1006response_latency=20 1007size=4194304 1008subblock_size=0 1009system=system 1010tgts_per_mshr=12 1011trace_addr=0 1012two_queue=false 1013write_buffers=8 1014cpu_side=system.toL2Bus.master[0] 1015mem_side=system.membus.slave[2] 1016 1017[system.membus] 1018type=CoherentBus 1019children=badaddr_responder 1020block_size=64 1021clock=1000 1022header_cycles=1 1023use_default_range=false 1024width=8 1025default=system.membus.badaddr_responder.pio 1026master=system.bridge.slave system.physmem.port 1027slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1028 1029[system.membus.badaddr_responder] 1030type=IsaFake 1031clock=1000 1032fake_mem=false 1033pio_addr=0 1034pio_latency=100000 1035pio_size=8 1036ret_bad_addr=true 1037ret_data16=65535 1038ret_data32=4294967295 1039ret_data64=18446744073709551615 1040ret_data8=255 1041system=system 1042update_data=false 1043warn_access= 1044pio=system.membus.default 1045 1046[system.physmem] 1047type=SimpleDRAM 1048addr_mapping=openmap 1049banks_per_rank=8 1050clock=1000 1051conf_table_reported=false 1052in_addr_map=true 1053lines_per_rowbuffer=64 1054mem_sched_policy=fcfs 1055null=false 1056page_policy=open 1057range=0:134217727 1058ranks_per_channel=2 1059read_buffer_size=32 1060tBURST=4000 1061tCL=14000 1062tRCD=14000 1063tREFI=7800000 1064tRFC=300000 1065tRP=14000 1066tWTR=1000 1067write_buffer_size=32 1068write_thresh_perc=70 1069zero=false 1070port=system.membus.master[1] 1071 1072[system.simple_disk] 1073type=SimpleDisk 1074children=disk 1075disk=system.simple_disk.disk 1076system=system 1077 1078[system.simple_disk.disk] 1079type=RawDiskImage 1080image_file=/projects/pd/randd/dist/disks/linux-latest.img 1081read_only=true 1082 1083[system.terminal] 1084type=Terminal 1085intr_control=system.intrctrl 1086number=0 1087output=true 1088port=3456 1089 1090[system.toL2Bus] 1091type=CoherentBus 1092block_size=64 1093clock=500 1094header_cycles=1 1095use_default_range=false 1096width=8 1097master=system.l2c.cpu_side 1098slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1099 1100[system.tsunami] 1101type=Tsunami 1102children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1103intrctrl=system.intrctrl 1104system=system 1105 1106[system.tsunami.backdoor] 1107type=AlphaBackdoor 1108clock=1000 1109cpu=system.cpu0 1110disk=system.simple_disk 1111pio_addr=8804682956800 1112pio_latency=100000 1113platform=system.tsunami 1114system=system 1115terminal=system.terminal 1116pio=system.iobus.master[24] 1117 1118[system.tsunami.cchip] 1119type=TsunamiCChip 1120clock=1000 1121pio_addr=8803072344064 1122pio_latency=100000 1123system=system 1124tsunami=system.tsunami 1125pio=system.iobus.master[0] 1126 1127[system.tsunami.ethernet] 1128type=NSGigE 1129BAR0=1 1130BAR0LegacyIO=false 1131BAR0Size=256 1132BAR1=0 1133BAR1LegacyIO=false 1134BAR1Size=4096 1135BAR2=0 1136BAR2LegacyIO=false 1137BAR2Size=0 1138BAR3=0 1139BAR3LegacyIO=false 1140BAR3Size=0 1141BAR4=0 1142BAR4LegacyIO=false 1143BAR4Size=0 1144BAR5=0 1145BAR5LegacyIO=false 1146BAR5Size=0 1147BIST=0 1148CacheLineSize=0 1149CardbusCIS=0 1150ClassCode=2 1151Command=0 1152DeviceID=34 1153ExpansionROM=0 1154HeaderType=0 1155InterruptLine=30 1156InterruptPin=1 1157LatencyTimer=0 1158MaximumLatency=52 1159MinimumGrant=176 1160ProgIF=0 1161Revision=0 1162Status=656 1163SubClassCode=0 1164SubsystemID=0 1165SubsystemVendorID=0 1166VendorID=4107 1167clock=0 1168config_latency=20000 1169dma_data_free=false 1170dma_desc_free=false 1171dma_no_allocate=true 1172dma_read_delay=0 1173dma_read_factor=0 1174dma_write_delay=0 1175dma_write_factor=0 1176hardware_address=00:90:00:00:00:01 1177intr_delay=10000000 1178pci_bus=0 1179pci_dev=1 1180pci_func=0 1181pio_latency=30000 1182platform=system.tsunami 1183rss=false 1184rx_delay=1000000 1185rx_fifo_size=524288 1186rx_filter=true 1187rx_thread=false 1188system=system 1189tx_delay=1000000 1190tx_fifo_size=524288 1191tx_thread=false 1192config=system.iobus.master[28] 1193dma=system.iobus.slave[2] 1194pio=system.iobus.master[27] 1195 1196[system.tsunami.fake_OROM] 1197type=IsaFake 1198clock=1000 1199fake_mem=false 1200pio_addr=8796093677568 1201pio_latency=100000 1202pio_size=393216 1203ret_bad_addr=false 1204ret_data16=65535 1205ret_data32=4294967295 1206ret_data64=18446744073709551615 1207ret_data8=255 1208system=system 1209update_data=false 1210warn_access= 1211pio=system.iobus.master[8] 1212 1213[system.tsunami.fake_ata0] 1214type=IsaFake 1215clock=1000 1216fake_mem=false 1217pio_addr=8804615848432 1218pio_latency=100000 1219pio_size=8 1220ret_bad_addr=false 1221ret_data16=65535 1222ret_data32=4294967295 1223ret_data64=18446744073709551615 1224ret_data8=255 1225system=system 1226update_data=false 1227warn_access= 1228pio=system.iobus.master[19] 1229 1230[system.tsunami.fake_ata1] 1231type=IsaFake 1232clock=1000 1233fake_mem=false 1234pio_addr=8804615848304 1235pio_latency=100000 1236pio_size=8 1237ret_bad_addr=false 1238ret_data16=65535 1239ret_data32=4294967295 1240ret_data64=18446744073709551615 1241ret_data8=255 1242system=system 1243update_data=false 1244warn_access= 1245pio=system.iobus.master[20] 1246 1247[system.tsunami.fake_pnp_addr] 1248type=IsaFake 1249clock=1000 1250fake_mem=false 1251pio_addr=8804615848569 1252pio_latency=100000 1253pio_size=8 1254ret_bad_addr=false 1255ret_data16=65535 1256ret_data32=4294967295 1257ret_data64=18446744073709551615 1258ret_data8=255 1259system=system 1260update_data=false 1261warn_access= 1262pio=system.iobus.master[9] 1263 1264[system.tsunami.fake_pnp_read0] 1265type=IsaFake 1266clock=1000 1267fake_mem=false 1268pio_addr=8804615848451 1269pio_latency=100000 1270pio_size=8 1271ret_bad_addr=false 1272ret_data16=65535 1273ret_data32=4294967295 1274ret_data64=18446744073709551615 1275ret_data8=255 1276system=system 1277update_data=false 1278warn_access= 1279pio=system.iobus.master[11] 1280 1281[system.tsunami.fake_pnp_read1] 1282type=IsaFake 1283clock=1000 1284fake_mem=false 1285pio_addr=8804615848515 1286pio_latency=100000 1287pio_size=8 1288ret_bad_addr=false 1289ret_data16=65535 1290ret_data32=4294967295 1291ret_data64=18446744073709551615 1292ret_data8=255 1293system=system 1294update_data=false 1295warn_access= 1296pio=system.iobus.master[12] 1297 1298[system.tsunami.fake_pnp_read2] 1299type=IsaFake 1300clock=1000 1301fake_mem=false 1302pio_addr=8804615848579 1303pio_latency=100000 1304pio_size=8 1305ret_bad_addr=false 1306ret_data16=65535 1307ret_data32=4294967295 1308ret_data64=18446744073709551615 1309ret_data8=255 1310system=system 1311update_data=false 1312warn_access= 1313pio=system.iobus.master[13] 1314 1315[system.tsunami.fake_pnp_read3] 1316type=IsaFake 1317clock=1000 1318fake_mem=false 1319pio_addr=8804615848643 1320pio_latency=100000 1321pio_size=8 1322ret_bad_addr=false 1323ret_data16=65535 1324ret_data32=4294967295 1325ret_data64=18446744073709551615 1326ret_data8=255 1327system=system 1328update_data=false 1329warn_access= 1330pio=system.iobus.master[14] 1331 1332[system.tsunami.fake_pnp_read4] 1333type=IsaFake 1334clock=1000 1335fake_mem=false 1336pio_addr=8804615848707 1337pio_latency=100000 1338pio_size=8 1339ret_bad_addr=false 1340ret_data16=65535 1341ret_data32=4294967295 1342ret_data64=18446744073709551615 1343ret_data8=255 1344system=system 1345update_data=false 1346warn_access= 1347pio=system.iobus.master[15] 1348 1349[system.tsunami.fake_pnp_read5] 1350type=IsaFake 1351clock=1000 1352fake_mem=false 1353pio_addr=8804615848771 1354pio_latency=100000 1355pio_size=8 1356ret_bad_addr=false 1357ret_data16=65535 1358ret_data32=4294967295 1359ret_data64=18446744073709551615 1360ret_data8=255 1361system=system 1362update_data=false 1363warn_access= 1364pio=system.iobus.master[16] 1365 1366[system.tsunami.fake_pnp_read6] 1367type=IsaFake 1368clock=1000 1369fake_mem=false 1370pio_addr=8804615848835 1371pio_latency=100000 1372pio_size=8 1373ret_bad_addr=false 1374ret_data16=65535 1375ret_data32=4294967295 1376ret_data64=18446744073709551615 1377ret_data8=255 1378system=system 1379update_data=false 1380warn_access= 1381pio=system.iobus.master[17] 1382 1383[system.tsunami.fake_pnp_read7] 1384type=IsaFake 1385clock=1000 1386fake_mem=false 1387pio_addr=8804615848899 1388pio_latency=100000 1389pio_size=8 1390ret_bad_addr=false 1391ret_data16=65535 1392ret_data32=4294967295 1393ret_data64=18446744073709551615 1394ret_data8=255 1395system=system 1396update_data=false 1397warn_access= 1398pio=system.iobus.master[18] 1399 1400[system.tsunami.fake_pnp_write] 1401type=IsaFake 1402clock=1000 1403fake_mem=false 1404pio_addr=8804615850617 1405pio_latency=100000 1406pio_size=8 1407ret_bad_addr=false 1408ret_data16=65535 1409ret_data32=4294967295 1410ret_data64=18446744073709551615 1411ret_data8=255 1412system=system 1413update_data=false 1414warn_access= 1415pio=system.iobus.master[10] 1416 1417[system.tsunami.fake_ppc] 1418type=IsaFake 1419clock=1000 1420fake_mem=false 1421pio_addr=8804615848891 1422pio_latency=100000 1423pio_size=8 1424ret_bad_addr=false 1425ret_data16=65535 1426ret_data32=4294967295 1427ret_data64=18446744073709551615 1428ret_data8=255 1429system=system 1430update_data=false 1431warn_access= 1432pio=system.iobus.master[7] 1433 1434[system.tsunami.fake_sm_chip] 1435type=IsaFake 1436clock=1000 1437fake_mem=false 1438pio_addr=8804615848816 1439pio_latency=100000 1440pio_size=8 1441ret_bad_addr=false 1442ret_data16=65535 1443ret_data32=4294967295 1444ret_data64=18446744073709551615 1445ret_data8=255 1446system=system 1447update_data=false 1448warn_access= 1449pio=system.iobus.master[2] 1450 1451[system.tsunami.fake_uart1] 1452type=IsaFake 1453clock=1000 1454fake_mem=false 1455pio_addr=8804615848696 1456pio_latency=100000 1457pio_size=8 1458ret_bad_addr=false 1459ret_data16=65535 1460ret_data32=4294967295 1461ret_data64=18446744073709551615 1462ret_data8=255 1463system=system 1464update_data=false 1465warn_access= 1466pio=system.iobus.master[3] 1467 1468[system.tsunami.fake_uart2] 1469type=IsaFake 1470clock=1000 1471fake_mem=false 1472pio_addr=8804615848936 1473pio_latency=100000 1474pio_size=8 1475ret_bad_addr=false 1476ret_data16=65535 1477ret_data32=4294967295 1478ret_data64=18446744073709551615 1479ret_data8=255 1480system=system 1481update_data=false 1482warn_access= 1483pio=system.iobus.master[4] 1484 1485[system.tsunami.fake_uart3] 1486type=IsaFake 1487clock=1000 1488fake_mem=false 1489pio_addr=8804615848680 1490pio_latency=100000 1491pio_size=8 1492ret_bad_addr=false 1493ret_data16=65535 1494ret_data32=4294967295 1495ret_data64=18446744073709551615 1496ret_data8=255 1497system=system 1498update_data=false 1499warn_access= 1500pio=system.iobus.master[5] 1501 1502[system.tsunami.fake_uart4] 1503type=IsaFake 1504clock=1000 1505fake_mem=false 1506pio_addr=8804615848944 1507pio_latency=100000 1508pio_size=8 1509ret_bad_addr=false 1510ret_data16=65535 1511ret_data32=4294967295 1512ret_data64=18446744073709551615 1513ret_data8=255 1514system=system 1515update_data=false 1516warn_access= 1517pio=system.iobus.master[6] 1518 1519[system.tsunami.fb] 1520type=BadDevice 1521clock=1000 1522devicename=FrameBuffer 1523pio_addr=8804615848912 1524pio_latency=100000 1525system=system 1526pio=system.iobus.master[21] 1527 1528[system.tsunami.ide] 1529type=IdeController 1530BAR0=1 1531BAR0LegacyIO=false 1532BAR0Size=8 1533BAR1=1 1534BAR1LegacyIO=false 1535BAR1Size=4 1536BAR2=1 1537BAR2LegacyIO=false 1538BAR2Size=8 1539BAR3=1 1540BAR3LegacyIO=false 1541BAR3Size=4 1542BAR4=1 1543BAR4LegacyIO=false 1544BAR4Size=16 1545BAR5=1 1546BAR5LegacyIO=false 1547BAR5Size=0 1548BIST=0 1549CacheLineSize=0 1550CardbusCIS=0 1551ClassCode=1 1552Command=0 1553DeviceID=28945 1554ExpansionROM=0 1555HeaderType=0 1556InterruptLine=31 1557InterruptPin=1 1558LatencyTimer=0 1559MaximumLatency=0 1560MinimumGrant=0 1561ProgIF=133 1562Revision=0 1563Status=640 1564SubClassCode=1 1565SubsystemID=0 1566SubsystemVendorID=0 1567VendorID=32902 1568clock=1000 1569config_latency=20000 1570ctrl_offset=0 1571disks=system.disk0 system.disk2 1572io_shift=0 1573pci_bus=0 1574pci_dev=0 1575pci_func=0 1576pio_latency=30000 1577platform=system.tsunami 1578system=system 1579config=system.iobus.master[26] 1580dma=system.iobus.slave[1] 1581pio=system.iobus.master[25] 1582 1583[system.tsunami.io] 1584type=TsunamiIO 1585clock=1000 1586frequency=976562500 1587pio_addr=8804615847936 1588pio_latency=100000 1589system=system 1590time=Thu Jan 1 00:00:00 2009 1591tsunami=system.tsunami 1592year_is_bcd=false 1593pio=system.iobus.master[22] 1594 1595[system.tsunami.pchip] 1596type=TsunamiPChip 1597clock=1000 1598pio_addr=8802535473152 1599pio_latency=100000 1600system=system 1601tsunami=system.tsunami 1602pio=system.iobus.master[1] 1603 1604[system.tsunami.pciconfig] 1605type=PciConfigAll 1606bus=0 1607clock=1000 1608pio_latency=30000 1609platform=system.tsunami 1610size=16777216 1611system=system 1612pio=system.iobus.default 1613 1614[system.tsunami.uart] 1615type=Uart8250 1616clock=1000 1617pio_addr=8804615848952 1618pio_latency=100000 1619platform=system.tsunami 1620system=system 1621terminal=system.terminal 1622pio=system.iobus.master[23] 1623 1624