stats.txt revision 10636:9ac724889705
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.884236 # Number of seconds simulated 4sim_ticks 1884235597000 # Number of ticks simulated 5final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 167027 # Simulator instruction rate (inst/s) 8host_op_rate 167027 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5607682389 # Simulator tick rate (ticks/s) 10host_mem_usage 359752 # Number of bytes of host memory used 11host_seconds 336.01 # Real time elapsed on the host 12sim_insts 56122640 # Number of instructions simulated 13sim_ops 56122640 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1053184 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24861632 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 16456 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388463 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 558945 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13194545 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 558945 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13194545 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 404934 # Number of read requests accepted 44system.physmem.writeReqs 159706 # Number of write requests accepted 45system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue 49system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25481 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25742 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25839 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25784 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25228 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24953 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24817 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24560 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25102 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25274 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25530 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24856 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24523 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25574 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25845 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25739 # Per bank write bursts 71system.physmem.perBankWrBursts::0 10323 # Per bank write bursts 72system.physmem.perBankWrBursts::1 10094 # Per bank write bursts 73system.physmem.perBankWrBursts::2 10597 # Per bank write bursts 74system.physmem.perBankWrBursts::3 9998 # Per bank write bursts 75system.physmem.perBankWrBursts::4 9794 # Per bank write bursts 76system.physmem.perBankWrBursts::5 9430 # Per bank write bursts 77system.physmem.perBankWrBursts::6 9122 # Per bank write bursts 78system.physmem.perBankWrBursts::7 8746 # Per bank write bursts 79system.physmem.perBankWrBursts::8 9866 # Per bank write bursts 80system.physmem.perBankWrBursts::9 8965 # Per bank write bursts 81system.physmem.perBankWrBursts::10 9841 # Per bank write bursts 82system.physmem.perBankWrBursts::11 9391 # Per bank write bursts 83system.physmem.perBankWrBursts::12 9895 # Per bank write bursts 84system.physmem.perBankWrBursts::13 10602 # Per bank write bursts 85system.physmem.perBankWrBursts::14 10396 # Per bank write bursts 86system.physmem.perBankWrBursts::15 10461 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 1884226862500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 404934 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 159706 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads 258system.physmem.totQLat 2143675250 # Total ticks spent queuing 259system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM 260system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers 261system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst 262system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 263system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst 264system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s 265system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s 266system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s 267system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s 268system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 269system.physmem.busUtil 0.15 # Data bus utilization in percentage 270system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 271system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes 272system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 273system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing 274system.physmem.readRowHits 364210 # Number of row buffer hits during reads 275system.physmem.writeRowHits 132411 # Number of row buffer hits during writes 276system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads 277system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes 278system.physmem.avgGap 3337041.06 # Average gap between requests 279system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined 280system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) 281system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) 282system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) 283system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) 284system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) 285system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) 286system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) 287system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) 288system.physmem_0.averagePower 670.517914 # Core power per rank (mW) 289system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states 290system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states 291system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 292system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states 293system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 294system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) 295system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) 296system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) 297system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) 298system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) 299system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) 300system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) 301system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) 302system.physmem_1.averagePower 670.585024 # Core power per rank (mW) 303system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states 304system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states 305system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 306system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states 307system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 308system.cpu.branchPred.lookups 15006303 # Number of BP lookups 309system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted 310system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect 311system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups 312system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits 313system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 314system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage 315system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. 316system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. 317system.cpu_clk_domain.clock 500 # Clock period in ticks 318system.cpu.dtb.fetch_hits 0 # ITB hits 319system.cpu.dtb.fetch_misses 0 # ITB misses 320system.cpu.dtb.fetch_acv 0 # ITB acv 321system.cpu.dtb.fetch_accesses 0 # ITB accesses 322system.cpu.dtb.read_hits 9241313 # DTB read hits 323system.cpu.dtb.read_misses 17796 # DTB read misses 324system.cpu.dtb.read_acv 211 # DTB read access violations 325system.cpu.dtb.read_accesses 766310 # DTB read accesses 326system.cpu.dtb.write_hits 6385986 # DTB write hits 327system.cpu.dtb.write_misses 2327 # DTB write misses 328system.cpu.dtb.write_acv 160 # DTB write access violations 329system.cpu.dtb.write_accesses 298447 # DTB write accesses 330system.cpu.dtb.data_hits 15627299 # DTB hits 331system.cpu.dtb.data_misses 20123 # DTB misses 332system.cpu.dtb.data_acv 371 # DTB access violations 333system.cpu.dtb.data_accesses 1064757 # DTB accesses 334system.cpu.itb.fetch_hits 4016976 # ITB hits 335system.cpu.itb.fetch_misses 6883 # ITB misses 336system.cpu.itb.fetch_acv 674 # ITB acv 337system.cpu.itb.fetch_accesses 4023859 # ITB accesses 338system.cpu.itb.read_hits 0 # DTB read hits 339system.cpu.itb.read_misses 0 # DTB read misses 340system.cpu.itb.read_acv 0 # DTB read access violations 341system.cpu.itb.read_accesses 0 # DTB read accesses 342system.cpu.itb.write_hits 0 # DTB write hits 343system.cpu.itb.write_misses 0 # DTB write misses 344system.cpu.itb.write_acv 0 # DTB write access violations 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.data_hits 0 # DTB hits 347system.cpu.itb.data_misses 0 # DTB misses 348system.cpu.itb.data_acv 0 # DTB access violations 349system.cpu.itb.data_accesses 0 # DTB accesses 350system.cpu.numCycles 175257245 # number of cpu cycles simulated 351system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 352system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 353system.cpu.committedInsts 56122640 # Number of instructions committed 354system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed 355system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit 356system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching 357system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 358system.cpu.cpi 3.122755 # CPI: cycles per instruction 359system.cpu.ipc 0.320230 # IPC: instructions per cycle 360system.cpu.kern.inst.arm 0 # number of arm instructions executed 361system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed 362system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed 363system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl 364system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 365system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl 366system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl 367system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl 368system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl 369system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 370system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl 371system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl 372system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl 373system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl 374system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl 375system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl 376system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl 377system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl 378system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl 379system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 380system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 381system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl 382system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl 383system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 384system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 385system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 386system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 387system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 388system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 389system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 390system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 391system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 392system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 393system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 394system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 395system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 396system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 397system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 398system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 399system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 400system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 401system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 402system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 403system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 404system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 405system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 406system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 407system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 408system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 409system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 410system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 411system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 412system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 413system.cpu.kern.syscall::total 326 # number of syscalls executed 414system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 415system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 416system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 417system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 418system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 419system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 420system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 421system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed 422system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed 423system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 424system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 425system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 426system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 427system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed 428system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 429system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 430system.cpu.kern.callpal::total 192413 # number of callpals executed 431system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches 432system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 433system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 434system.cpu.kern.mode_good::kernel 1910 435system.cpu.kern.mode_good::user 1740 436system.cpu.kern.mode_good::idle 170 437system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches 438system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 439system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches 440system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches 441system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode 442system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode 443system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode 444system.cpu.kern.swap_context 4177 # number of times the context was actually changed 445system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked 446system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped 447system.cpu.dcache.tags.replacements 1395383 # number of replacements 448system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use 449system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. 450system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. 451system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. 452system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. 453system.cpu.dcache.tags.occ_blocks::cpu.data 511.982334 # Average occupied blocks per requestor 454system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy 455system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 456system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 457system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 458system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 459system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 460system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 461system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses 462system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses 463system.cpu.dcache.ReadReq_hits::cpu.data 7814297 # number of ReadReq hits 464system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits 465system.cpu.dcache.WriteReq_hits::cpu.data 5576378 # number of WriteReq hits 466system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits 467system.cpu.dcache.LoadLockedReq_hits::cpu.data 182732 # number of LoadLockedReq hits 468system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits 469system.cpu.dcache.StoreCondReq_hits::cpu.data 198999 # number of StoreCondReq hits 470system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits 471system.cpu.dcache.demand_hits::cpu.data 13390675 # number of demand (read+write) hits 472system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits 473system.cpu.dcache.overall_hits::cpu.data 13390675 # number of overall hits 474system.cpu.dcache.overall_hits::total 13390675 # number of overall hits 475system.cpu.dcache.ReadReq_misses::cpu.data 1201640 # number of ReadReq misses 476system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses 477system.cpu.dcache.WriteReq_misses::cpu.data 573763 # number of WriteReq misses 478system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses 479system.cpu.dcache.LoadLockedReq_misses::cpu.data 17288 # number of LoadLockedReq misses 480system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses 481system.cpu.dcache.demand_misses::cpu.data 1775403 # number of demand (read+write) misses 482system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses 483system.cpu.dcache.overall_misses::cpu.data 1775403 # number of overall misses 484system.cpu.dcache.overall_misses::total 1775403 # number of overall misses 485system.cpu.dcache.ReadReq_miss_latency::cpu.data 31034654250 # number of ReadReq miss cycles 486system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles 487system.cpu.dcache.WriteReq_miss_latency::cpu.data 20679395543 # number of WriteReq miss cycles 488system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles 489system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231275750 # number of LoadLockedReq miss cycles 490system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles 491system.cpu.dcache.demand_miss_latency::cpu.data 51714049793 # number of demand (read+write) miss cycles 492system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles 493system.cpu.dcache.overall_miss_latency::cpu.data 51714049793 # number of overall miss cycles 494system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles 495system.cpu.dcache.ReadReq_accesses::cpu.data 9015937 # number of ReadReq accesses(hits+misses) 496system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) 497system.cpu.dcache.WriteReq_accesses::cpu.data 6150141 # number of WriteReq accesses(hits+misses) 498system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) 499system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200020 # number of LoadLockedReq accesses(hits+misses) 500system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) 501system.cpu.dcache.StoreCondReq_accesses::cpu.data 198999 # number of StoreCondReq accesses(hits+misses) 502system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) 503system.cpu.dcache.demand_accesses::cpu.data 15166078 # number of demand (read+write) accesses 504system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses 505system.cpu.dcache.overall_accesses::cpu.data 15166078 # number of overall (read+write) accesses 506system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses 507system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133280 # miss rate for ReadReq accesses 508system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses 509system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093293 # miss rate for WriteReq accesses 510system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses 511system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086431 # miss rate for LoadLockedReq accesses 512system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses 513system.cpu.dcache.demand_miss_rate::cpu.data 0.117064 # miss rate for demand accesses 514system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses 515system.cpu.dcache.overall_miss_rate::cpu.data 0.117064 # miss rate for overall accesses 516system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses 517system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25826.915091 # average ReadReq miss latency 518system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency 519system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36041.702834 # average WriteReq miss latency 520system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency 521system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13377.819875 # average LoadLockedReq miss latency 522system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency 523system.cpu.dcache.demand_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency 524system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency 525system.cpu.dcache.overall_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency 526system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency 527system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 528system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 529system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 530system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 531system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 532system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 533system.cpu.dcache.fast_writes 0 # number of fast writes performed 534system.cpu.dcache.cache_copies 0 # number of cache copies performed 535system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks 536system.cpu.dcache.writebacks::total 838265 # number of writebacks 537system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127268 # number of ReadReq MSHR hits 538system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits 539system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269487 # number of WriteReq MSHR hits 540system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits 541system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 542system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 543system.cpu.dcache.demand_mshr_hits::cpu.data 396755 # number of demand (read+write) MSHR hits 544system.cpu.dcache.demand_mshr_hits::total 396755 # number of demand (read+write) MSHR hits 545system.cpu.dcache.overall_mshr_hits::cpu.data 396755 # number of overall MSHR hits 546system.cpu.dcache.overall_mshr_hits::total 396755 # number of overall MSHR hits 547system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074372 # number of ReadReq MSHR misses 548system.cpu.dcache.ReadReq_mshr_misses::total 1074372 # number of ReadReq MSHR misses 549system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304276 # number of WriteReq MSHR misses 550system.cpu.dcache.WriteReq_mshr_misses::total 304276 # number of WriteReq MSHR misses 551system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17285 # number of LoadLockedReq MSHR misses 552system.cpu.dcache.LoadLockedReq_mshr_misses::total 17285 # number of LoadLockedReq MSHR misses 553system.cpu.dcache.demand_mshr_misses::cpu.data 1378648 # number of demand (read+write) MSHR misses 554system.cpu.dcache.demand_mshr_misses::total 1378648 # number of demand (read+write) MSHR misses 555system.cpu.dcache.overall_mshr_misses::cpu.data 1378648 # number of overall MSHR misses 556system.cpu.dcache.overall_mshr_misses::total 1378648 # number of overall MSHR misses 557system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26917637000 # number of ReadReq MSHR miss cycles 558system.cpu.dcache.ReadReq_mshr_miss_latency::total 26917637000 # number of ReadReq MSHR miss cycles 559system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10249005096 # number of WriteReq MSHR miss cycles 560system.cpu.dcache.WriteReq_mshr_miss_latency::total 10249005096 # number of WriteReq MSHR miss cycles 561system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196537750 # number of LoadLockedReq MSHR miss cycles 562system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles 563system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37166642096 # number of demand (read+write) MSHR miss cycles 564system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles 565system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37166642096 # number of overall MSHR miss cycles 566system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles 567system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423897500 # number of ReadReq MSHR uncacheable cycles 568system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles 569system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002909000 # number of WriteReq MSHR uncacheable cycles 570system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles 571system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3426806500 # number of overall MSHR uncacheable cycles 572system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles 573system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119164 # mshr miss rate for ReadReq accesses 574system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses 575system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049475 # mshr miss rate for WriteReq accesses 576system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses 577system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086416 # mshr miss rate for LoadLockedReq accesses 578system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # mshr miss rate for LoadLockedReq accesses 579system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for demand accesses 580system.cpu.dcache.demand_mshr_miss_rate::total 0.090903 # mshr miss rate for demand accesses 581system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for overall accesses 582system.cpu.dcache.overall_mshr_miss_rate::total 0.090903 # mshr miss rate for overall accesses 583system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25054.298697 # average ReadReq mshr miss latency 584system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25054.298697 # average ReadReq mshr miss latency 585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33683.251706 # average WriteReq mshr miss latency 586system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33683.251706 # average WriteReq mshr miss latency 587system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11370.422332 # average LoadLockedReq mshr miss latency 588system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.422332 # average LoadLockedReq mshr miss latency 589system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency 590system.cpu.dcache.demand_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency 591system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency 592system.cpu.dcache.overall_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency 593system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 594system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 595system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 596system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 597system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 598system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 599system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 600system.cpu.icache.tags.replacements 1459474 # number of replacements 601system.cpu.icache.tags.tagsinuse 509.626385 # Cycle average of tags in use 602system.cpu.icache.tags.total_refs 18964719 # Total number of references to valid blocks. 603system.cpu.icache.tags.sampled_refs 1459985 # Sample count of references to valid blocks. 604system.cpu.icache.tags.avg_refs 12.989667 # Average number of references to valid blocks. 605system.cpu.icache.tags.warmup_cycle 31607466250 # Cycle when the warmup percentage was hit. 606system.cpu.icache.tags.occ_blocks::cpu.inst 509.626385 # Average occupied blocks per requestor 607system.cpu.icache.tags.occ_percent::cpu.inst 0.995364 # Average percentage of cache occupancy 608system.cpu.icache.tags.occ_percent::total 0.995364 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 613system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 614system.cpu.icache.tags.tag_accesses 21885040 # Number of tag accesses 615system.cpu.icache.tags.data_accesses 21885040 # Number of data accesses 616system.cpu.icache.ReadReq_hits::cpu.inst 18964722 # number of ReadReq hits 617system.cpu.icache.ReadReq_hits::total 18964722 # number of ReadReq hits 618system.cpu.icache.demand_hits::cpu.inst 18964722 # number of demand (read+write) hits 619system.cpu.icache.demand_hits::total 18964722 # number of demand (read+write) hits 620system.cpu.icache.overall_hits::cpu.inst 18964722 # number of overall hits 621system.cpu.icache.overall_hits::total 18964722 # number of overall hits 622system.cpu.icache.ReadReq_misses::cpu.inst 1460159 # number of ReadReq misses 623system.cpu.icache.ReadReq_misses::total 1460159 # number of ReadReq misses 624system.cpu.icache.demand_misses::cpu.inst 1460159 # number of demand (read+write) misses 625system.cpu.icache.demand_misses::total 1460159 # number of demand (read+write) misses 626system.cpu.icache.overall_misses::cpu.inst 1460159 # number of overall misses 627system.cpu.icache.overall_misses::total 1460159 # number of overall misses 628system.cpu.icache.ReadReq_miss_latency::cpu.inst 20038728384 # number of ReadReq miss cycles 629system.cpu.icache.ReadReq_miss_latency::total 20038728384 # number of ReadReq miss cycles 630system.cpu.icache.demand_miss_latency::cpu.inst 20038728384 # number of demand (read+write) miss cycles 631system.cpu.icache.demand_miss_latency::total 20038728384 # number of demand (read+write) miss cycles 632system.cpu.icache.overall_miss_latency::cpu.inst 20038728384 # number of overall miss cycles 633system.cpu.icache.overall_miss_latency::total 20038728384 # number of overall miss cycles 634system.cpu.icache.ReadReq_accesses::cpu.inst 20424881 # number of ReadReq accesses(hits+misses) 635system.cpu.icache.ReadReq_accesses::total 20424881 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.demand_accesses::cpu.inst 20424881 # number of demand (read+write) accesses 637system.cpu.icache.demand_accesses::total 20424881 # number of demand (read+write) accesses 638system.cpu.icache.overall_accesses::cpu.inst 20424881 # number of overall (read+write) accesses 639system.cpu.icache.overall_accesses::total 20424881 # number of overall (read+write) accesses 640system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071489 # miss rate for ReadReq accesses 641system.cpu.icache.ReadReq_miss_rate::total 0.071489 # miss rate for ReadReq accesses 642system.cpu.icache.demand_miss_rate::cpu.inst 0.071489 # miss rate for demand accesses 643system.cpu.icache.demand_miss_rate::total 0.071489 # miss rate for demand accesses 644system.cpu.icache.overall_miss_rate::cpu.inst 0.071489 # miss rate for overall accesses 645system.cpu.icache.overall_miss_rate::total 0.071489 # miss rate for overall accesses 646system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13723.661864 # average ReadReq miss latency 647system.cpu.icache.ReadReq_avg_miss_latency::total 13723.661864 # average ReadReq miss latency 648system.cpu.icache.demand_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency 649system.cpu.icache.demand_avg_miss_latency::total 13723.661864 # average overall miss latency 650system.cpu.icache.overall_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::total 13723.661864 # average overall miss latency 652system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.icache.fast_writes 0 # number of fast writes performed 659system.cpu.icache.cache_copies 0 # number of cache copies performed 660system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1460159 # number of ReadReq MSHR misses 661system.cpu.icache.ReadReq_mshr_misses::total 1460159 # number of ReadReq MSHR misses 662system.cpu.icache.demand_mshr_misses::cpu.inst 1460159 # number of demand (read+write) MSHR misses 663system.cpu.icache.demand_mshr_misses::total 1460159 # number of demand (read+write) MSHR misses 664system.cpu.icache.overall_mshr_misses::cpu.inst 1460159 # number of overall MSHR misses 665system.cpu.icache.overall_mshr_misses::total 1460159 # number of overall MSHR misses 666system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17111152616 # number of ReadReq MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_miss_latency::total 17111152616 # number of ReadReq MSHR miss cycles 668system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17111152616 # number of demand (read+write) MSHR miss cycles 669system.cpu.icache.demand_mshr_miss_latency::total 17111152616 # number of demand (read+write) MSHR miss cycles 670system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17111152616 # number of overall MSHR miss cycles 671system.cpu.icache.overall_mshr_miss_latency::total 17111152616 # number of overall MSHR miss cycles 672system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for ReadReq accesses 673system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071489 # mshr miss rate for ReadReq accesses 674system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for demand accesses 675system.cpu.icache.demand_mshr_miss_rate::total 0.071489 # mshr miss rate for demand accesses 676system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for overall accesses 677system.cpu.icache.overall_mshr_miss_rate::total 0.071489 # mshr miss rate for overall accesses 678system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332 # average ReadReq mshr miss latency 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11718.691332 # average ReadReq mshr miss latency 680system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency 682system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency 684system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 685system.cpu.l2cache.tags.replacements 339433 # number of replacements 686system.cpu.l2cache.tags.tagsinuse 65325.334655 # Cycle average of tags in use 687system.cpu.l2cache.tags.total_refs 2983211 # Total number of references to valid blocks. 688system.cpu.l2cache.tags.sampled_refs 404595 # Sample count of references to valid blocks. 689system.cpu.l2cache.tags.avg_refs 7.373326 # Average number of references to valid blocks. 690system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit. 691system.cpu.l2cache.tags.occ_blocks::writebacks 54499.677348 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 5826.101052 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.data 4999.556256 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_percent::writebacks 0.831599 # Average percentage of cache occupancy 695system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088899 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.data 0.076287 # Average percentage of cache occupancy 697system.cpu.l2cache.tags.occ_percent::total 0.996786 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 699system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 700system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id 701system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5137 # Occupied blocks per task id 702system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id 704system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 705system.cpu.l2cache.tags.tag_accesses 30263477 # Number of tag accesses 706system.cpu.l2cache.tags.data_accesses 30263477 # Number of data accesses 707system.cpu.l2cache.ReadReq_hits::cpu.inst 1443639 # number of ReadReq hits 708system.cpu.l2cache.ReadReq_hits::cpu.data 819413 # number of ReadReq hits 709system.cpu.l2cache.ReadReq_hits::total 2263052 # number of ReadReq hits 710system.cpu.l2cache.Writeback_hits::writebacks 838265 # number of Writeback hits 711system.cpu.l2cache.Writeback_hits::total 838265 # number of Writeback hits 712system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 713system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 714system.cpu.l2cache.ReadExReq_hits::cpu.data 187609 # number of ReadExReq hits 715system.cpu.l2cache.ReadExReq_hits::total 187609 # number of ReadExReq hits 716system.cpu.l2cache.demand_hits::cpu.inst 1443639 # number of demand (read+write) hits 717system.cpu.l2cache.demand_hits::cpu.data 1007022 # number of demand (read+write) hits 718system.cpu.l2cache.demand_hits::total 2450661 # number of demand (read+write) hits 719system.cpu.l2cache.overall_hits::cpu.inst 1443639 # number of overall hits 720system.cpu.l2cache.overall_hits::cpu.data 1007022 # number of overall hits 721system.cpu.l2cache.overall_hits::total 2450661 # number of overall hits 722system.cpu.l2cache.ReadReq_misses::cpu.inst 16457 # number of ReadReq misses 723system.cpu.l2cache.ReadReq_misses::cpu.data 272214 # number of ReadReq misses 724system.cpu.l2cache.ReadReq_misses::total 288671 # number of ReadReq misses 725system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses 726system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses 727system.cpu.l2cache.ReadExReq_misses::cpu.data 116676 # number of ReadExReq misses 728system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses 729system.cpu.l2cache.demand_misses::cpu.inst 16457 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::cpu.data 388890 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::total 405347 # number of demand (read+write) misses 732system.cpu.l2cache.overall_misses::cpu.inst 16457 # number of overall misses 733system.cpu.l2cache.overall_misses::cpu.data 388890 # number of overall misses 734system.cpu.l2cache.overall_misses::total 405347 # number of overall misses 735system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1197673500 # number of ReadReq miss cycles 736system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17722888500 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::total 18920562000 # number of ReadReq miss cycles 738system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 214497 # number of UpgradeReq miss cycles 739system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles 740system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8064568611 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::total 8064568611 # number of ReadExReq miss cycles 742system.cpu.l2cache.demand_miss_latency::cpu.inst 1197673500 # number of demand (read+write) miss cycles 743system.cpu.l2cache.demand_miss_latency::cpu.data 25787457111 # number of demand (read+write) miss cycles 744system.cpu.l2cache.demand_miss_latency::total 26985130611 # number of demand (read+write) miss cycles 745system.cpu.l2cache.overall_miss_latency::cpu.inst 1197673500 # number of overall miss cycles 746system.cpu.l2cache.overall_miss_latency::cpu.data 25787457111 # number of overall miss cycles 747system.cpu.l2cache.overall_miss_latency::total 26985130611 # number of overall miss cycles 748system.cpu.l2cache.ReadReq_accesses::cpu.inst 1460096 # number of ReadReq accesses(hits+misses) 749system.cpu.l2cache.ReadReq_accesses::cpu.data 1091627 # number of ReadReq accesses(hits+misses) 750system.cpu.l2cache.ReadReq_accesses::total 2551723 # number of ReadReq accesses(hits+misses) 751system.cpu.l2cache.Writeback_accesses::writebacks 838265 # number of Writeback accesses(hits+misses) 752system.cpu.l2cache.Writeback_accesses::total 838265 # number of Writeback accesses(hits+misses) 753system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) 754system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 755system.cpu.l2cache.ReadExReq_accesses::cpu.data 304285 # number of ReadExReq accesses(hits+misses) 756system.cpu.l2cache.ReadExReq_accesses::total 304285 # number of ReadExReq accesses(hits+misses) 757system.cpu.l2cache.demand_accesses::cpu.inst 1460096 # number of demand (read+write) accesses 758system.cpu.l2cache.demand_accesses::cpu.data 1395912 # number of demand (read+write) accesses 759system.cpu.l2cache.demand_accesses::total 2856008 # number of demand (read+write) accesses 760system.cpu.l2cache.overall_accesses::cpu.inst 1460096 # number of overall (read+write) accesses 761system.cpu.l2cache.overall_accesses::cpu.data 1395912 # number of overall (read+write) accesses 762system.cpu.l2cache.overall_accesses::total 2856008 # number of overall (read+write) accesses 763system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011271 # miss rate for ReadReq accesses 764system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249365 # miss rate for ReadReq accesses 765system.cpu.l2cache.ReadReq_miss_rate::total 0.113128 # miss rate for ReadReq accesses 766system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses 767system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses 768system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383443 # miss rate for ReadExReq accesses 769system.cpu.l2cache.ReadExReq_miss_rate::total 0.383443 # miss rate for ReadExReq accesses 770system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011271 # miss rate for demand accesses 771system.cpu.l2cache.demand_miss_rate::cpu.data 0.278592 # miss rate for demand accesses 772system.cpu.l2cache.demand_miss_rate::total 0.141928 # miss rate for demand accesses 773system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011271 # miss rate for overall accesses 774system.cpu.l2cache.overall_miss_rate::cpu.data 0.278592 # miss rate for overall accesses 775system.cpu.l2cache.overall_miss_rate::total 0.141928 # miss rate for overall accesses 776system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72775.931215 # average ReadReq miss latency 777system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65106.454848 # average ReadReq miss latency 778system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143 # average ReadReq miss latency 779system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12617.470588 # average UpgradeReq miss latency 780system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency 781system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.344261 # average ReadExReq miss latency 782system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency 783system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72775.931215 # average overall miss latency 784system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66310.414541 # average overall miss latency 785system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111 # average overall miss latency 786system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72775.931215 # average overall miss latency 787system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66310.414541 # average overall miss latency 788system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111 # average overall miss latency 789system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 790system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 793system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 794system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 795system.cpu.l2cache.fast_writes 0 # number of fast writes performed 796system.cpu.l2cache.cache_copies 0 # number of cache copies performed 797system.cpu.l2cache.writebacks::writebacks 76642 # number of writebacks 798system.cpu.l2cache.writebacks::total 76642 # number of writebacks 799system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16457 # number of ReadReq MSHR misses 800system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272214 # number of ReadReq MSHR misses 801system.cpu.l2cache.ReadReq_mshr_misses::total 288671 # number of ReadReq MSHR misses 802system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses 803system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses 804system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116676 # number of ReadExReq MSHR misses 805system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses 806system.cpu.l2cache.demand_mshr_misses::cpu.inst 16457 # number of demand (read+write) MSHR misses 807system.cpu.l2cache.demand_mshr_misses::cpu.data 388890 # number of demand (read+write) MSHR misses 808system.cpu.l2cache.demand_mshr_misses::total 405347 # number of demand (read+write) MSHR misses 809system.cpu.l2cache.overall_mshr_misses::cpu.inst 16457 # number of overall MSHR misses 810system.cpu.l2cache.overall_mshr_misses::cpu.data 388890 # number of overall MSHR misses 811system.cpu.l2cache.overall_mshr_misses::total 405347 # number of overall MSHR misses 812system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 990967000 # number of ReadReq MSHR miss cycles 813system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14320677500 # number of ReadReq MSHR miss cycles 814system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15311644500 # number of ReadReq MSHR miss cycles 815system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271014 # number of UpgradeReq MSHR miss cycles 816system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles 817system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6596786889 # number of ReadExReq MSHR miss cycles 818system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6596786889 # number of ReadExReq MSHR miss cycles 819system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 990967000 # number of demand (read+write) MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20917464389 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::total 21908431389 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 990967000 # number of overall MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20917464389 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::total 21908431389 # number of overall MSHR miss cycles 825system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333789500 # number of ReadReq MSHR uncacheable cycles 826system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333789500 # number of ReadReq MSHR uncacheable cycles 827system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887480500 # number of WriteReq MSHR uncacheable cycles 828system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles 829system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3221270000 # number of overall MSHR uncacheable cycles 830system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles 831system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for ReadReq accesses 832system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249365 # mshr miss rate for ReadReq accesses 833system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses 834system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses 835system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses 836system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383443 # mshr miss rate for ReadExReq accesses 837system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses 838system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for demand accesses 839system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for demand accesses 840system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses 841system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for overall accesses 842system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for overall accesses 843system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses 844system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60215.531385 # average ReadReq mshr miss latency 845system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52608.159389 # average ReadReq mshr miss latency 846system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency 847system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15942 # average UpgradeReq mshr miss latency 848system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency 849system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56539.364471 # average ReadExReq mshr miss latency 850system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency 851system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency 853system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 858system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 859system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 860system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 861system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 862system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 863system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 864system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 875system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) 876system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) 877system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) 879system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) 881system.cpu.toL2Bus.snoops 41944 # Total snoops (count) 882system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 886system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 890system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram 893system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) 894system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 895system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 896system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 897system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) 898system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 899system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) 900system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 901system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 902system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 903system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 904system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 905system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 906system.disk0.dma_write_txs 395 # Number of DMA write transactions. 907system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 908system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 909system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 910system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 911system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 912system.disk2.dma_write_txs 1 # Number of DMA write transactions. 913system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 914system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 915system.iobus.trans_dist::WriteReq 51171 # Transaction distribution 916system.iobus.trans_dist::WriteResp 9619 # Transaction distribution 917system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 918system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) 919system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 921system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 922system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 923system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 924system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 925system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 926system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 927system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 928system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 929system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 930system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) 931system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 932system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 933system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) 934system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) 935system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 936system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 937system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 938system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 939system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 940system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 941system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 944system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) 947system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 948system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 949system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) 950system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) 951system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 952system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 953system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 954system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 955system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 956system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 957system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 958system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 959system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 960system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 961system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 962system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 963system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 964system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 965system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 966system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 967system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 968system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 969system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 970system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 971system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 972system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) 973system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 974system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 975system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 976system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 977system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 978system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) 979system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 980system.iocache.tags.replacements 41685 # number of replacements 981system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use 982system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 983system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 984system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 985system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. 986system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor 987system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy 988system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy 989system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 990system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 991system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 992system.iocache.tags.tag_accesses 375525 # Number of tag accesses 993system.iocache.tags.data_accesses 375525 # Number of data accesses 994system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 995system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 996system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 997system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 998system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 999system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1000system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1001system.iocache.overall_misses::total 173 # number of overall misses 1002system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 1003system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 1004system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles 1005system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles 1006system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 1007system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 1008system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 1009system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 1010system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1011system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1012system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1013system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 1014system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1015system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1016system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1017system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1018system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1019system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1020system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1021system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1022system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1023system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1024system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1025system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1026system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 1027system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 1028system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency 1029system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency 1030system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1031system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 1032system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1033system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 1034system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked 1035system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1036system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked 1037system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1038system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked 1039system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1040system.iocache.fast_writes 0 # number of fast writes performed 1041system.iocache.cache_copies 0 # number of cache copies performed 1042system.iocache.writebacks::writebacks 41512 # number of writebacks 1043system.iocache.writebacks::total 41512 # number of writebacks 1044system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1045system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1046system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1047system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1048system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1049system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1050system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1051system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1052system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 1053system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 1054system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles 1055system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles 1056system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 1057system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 1058system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 1059system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 1060system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1061system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1062system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1063system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1064system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1065system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1066system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1067system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1068system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 1069system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 1070system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency 1071system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency 1072system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1073system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1074system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1075system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1076system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1077system.membus.trans_dist::ReadReq 295774 # Transaction distribution 1078system.membus.trans_dist::ReadResp 295758 # Transaction distribution 1079system.membus.trans_dist::WriteReq 9619 # Transaction distribution 1080system.membus.trans_dist::WriteResp 9619 # Transaction distribution 1081system.membus.trans_dist::Writeback 118154 # Transaction distribution 1082system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1083system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 1084system.membus.trans_dist::UpgradeReq 156 # Transaction distribution 1085system.membus.trans_dist::UpgradeResp 156 # Transaction distribution 1086system.membus.trans_dist::ReadExReq 116537 # Transaction distribution 1087system.membus.trans_dist::ReadExResp 116537 # Transaction distribution 1088system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1089system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) 1090system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) 1091system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) 1092system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) 1093system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1094system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) 1095system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) 1096system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) 1097system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) 1098system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) 1099system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1100system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1101system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) 1102system.membus.snoops 433 # Total snoops (count) 1103system.membus.snoop_fanout::samples 565243 # Request fanout histogram 1104system.membus.snoop_fanout::mean 1 # Request fanout histogram 1105system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1106system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1107system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1108system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram 1109system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1110system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1111system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1112system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1113system.membus.snoop_fanout::total 565243 # Request fanout histogram 1114system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) 1115system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1116system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) 1117system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1118system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) 1119system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1120system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) 1121system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1122system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) 1123system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1124system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1125system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1126system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1127system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1128system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1129system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1130system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1131system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1132system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1133system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1134system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1135system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1136system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1137system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1138system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1139system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1140system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1141system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1142system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1143system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1144system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1145system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1146system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1147system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1148system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1149system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1150system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1151system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1152system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1153system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1154system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1155 1156---------- End Simulation Statistics ---------- 1157