twosys-tsunami-simple-atomic.py revision 9246:ab0f995552fc 
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from FSConfig import *
33from Benchmarks import *
34
35test_sys = makeLinuxAlphaSystem('atomic',
36                                 SysConfig('netperf-stream-client.rcS'))
37test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
38# create the interrupt controller
39test_sys.cpu.createInterruptController()
40test_sys.cpu.connectAllPorts(test_sys.membus)
41test_sys.cpu.clock = '2GHz'
42# In contrast to the other (one-system) Tsunami configurations we do
43# not have an IO cache but instead rely on an IO bridge for accesses
44# from masters on the IO bus to the memory bus
45test_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
46test_sys.iobridge.slave = test_sys.iobus.master
47test_sys.iobridge.master = test_sys.membus.slave
48
49drive_sys = makeLinuxAlphaSystem('atomic',
50                                 SysConfig('netperf-server.rcS'))
51drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
52# create the interrupt controller
53drive_sys.cpu.createInterruptController()
54drive_sys.cpu.connectAllPorts(drive_sys.membus)
55drive_sys.cpu.clock = '4GHz'
56drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
57drive_sys.iobridge.slave = drive_sys.iobus.master
58drive_sys.iobridge.master = drive_sys.membus.slave
59
60root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
61
62maxtick = 199999999
63