tsunami-simple-timing.py revision 4444:0648bdc8d1c9 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32import FSConfig
33
34
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40    latency = '1ns'
41    block_size = 64
42    mshrs = 4
43    tgts_per_mshr = 8
44    protocol = CoherenceProtocol(protocol='moesi')
45
46# ----------------------
47# Base L2 Cache
48# ----------------------
49
50class L2(BaseCache):
51    block_size = 64
52    latency = '10ns'
53    mshrs = 92
54    tgts_per_mshr = 16
55    write_buffers = 8
56
57#cpu
58cpu = TimingSimpleCPU(cpu_id=0)
59#the system
60system = FSConfig.makeLinuxAlphaSystem('timing')
61
62system.cpu = cpu
63#create the l1/l2 bus
64system.toL2Bus = Bus()
65
66#connect up the l2 cache
67system.l2c = L2(size='4MB', assoc=8)
68system.l2c.cpu_side = system.toL2Bus.port
69system.l2c.mem_side = system.membus.port
70
71#connect up the cpu and l1s
72cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
73                            L1(size = '32kB', assoc = 4))
74# connect cpu level-1 caches to shared level-2 cache
75cpu.connectMemPorts(system.toL2Bus)
76cpu.clock = '2GHz'
77
78root = Root(system=system)
79m5.ticks.setGlobalFrequency('1THz')
80
81