tsunami-simple-timing.py revision 4444
14167Sbinkertn@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 23005Sstever@eecs.umich.edu# All rights reserved. 33005Sstever@eecs.umich.edu# 43005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133005Sstever@eecs.umich.edu# this software without specific prior written permission. 143005Sstever@eecs.umich.edu# 153005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 283005Sstever@eecs.umich.edu 293005Sstever@eecs.umich.eduimport m5 303005Sstever@eecs.umich.edufrom m5.objects import * 313005Sstever@eecs.umich.edum5.AddToPath('../configs/common') 323005Sstever@eecs.umich.eduimport FSConfig 333005Sstever@eecs.umich.edu 344444Ssaidi@eecs.umich.edu 354444Ssaidi@eecs.umich.edu# -------------------- 364444Ssaidi@eecs.umich.edu# Base L1 Cache 374444Ssaidi@eecs.umich.edu# ==================== 384444Ssaidi@eecs.umich.edu 394444Ssaidi@eecs.umich.educlass L1(BaseCache): 404444Ssaidi@eecs.umich.edu latency = '1ns' 414444Ssaidi@eecs.umich.edu block_size = 64 424444Ssaidi@eecs.umich.edu mshrs = 4 434444Ssaidi@eecs.umich.edu tgts_per_mshr = 8 444444Ssaidi@eecs.umich.edu protocol = CoherenceProtocol(protocol='moesi') 454444Ssaidi@eecs.umich.edu 464444Ssaidi@eecs.umich.edu# ---------------------- 474444Ssaidi@eecs.umich.edu# Base L2 Cache 484444Ssaidi@eecs.umich.edu# ---------------------- 494444Ssaidi@eecs.umich.edu 504444Ssaidi@eecs.umich.educlass L2(BaseCache): 514444Ssaidi@eecs.umich.edu block_size = 64 524444Ssaidi@eecs.umich.edu latency = '10ns' 534444Ssaidi@eecs.umich.edu mshrs = 92 544444Ssaidi@eecs.umich.edu tgts_per_mshr = 16 554444Ssaidi@eecs.umich.edu write_buffers = 8 564444Ssaidi@eecs.umich.edu 574444Ssaidi@eecs.umich.edu#cpu 583170Sstever@eecs.umich.educpu = TimingSimpleCPU(cpu_id=0) 594444Ssaidi@eecs.umich.edu#the system 603005Sstever@eecs.umich.edusystem = FSConfig.makeLinuxAlphaSystem('timing') 614444Ssaidi@eecs.umich.edu 623005Sstever@eecs.umich.edusystem.cpu = cpu 634444Ssaidi@eecs.umich.edu#create the l1/l2 bus 644444Ssaidi@eecs.umich.edusystem.toL2Bus = Bus() 654444Ssaidi@eecs.umich.edu 664444Ssaidi@eecs.umich.edu#connect up the l2 cache 674444Ssaidi@eecs.umich.edusystem.l2c = L2(size='4MB', assoc=8) 684444Ssaidi@eecs.umich.edusystem.l2c.cpu_side = system.toL2Bus.port 694444Ssaidi@eecs.umich.edusystem.l2c.mem_side = system.membus.port 704444Ssaidi@eecs.umich.edu 714444Ssaidi@eecs.umich.edu#connect up the cpu and l1s 724444Ssaidi@eecs.umich.educpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 734444Ssaidi@eecs.umich.edu L1(size = '32kB', assoc = 4)) 744444Ssaidi@eecs.umich.edu# connect cpu level-1 caches to shared level-2 cache 754444Ssaidi@eecs.umich.educpu.connectMemPorts(system.toL2Bus) 764444Ssaidi@eecs.umich.educpu.clock = '2GHz' 773005Sstever@eecs.umich.edu 784167Sbinkertn@umich.eduroot = Root(system=system) 794444Ssaidi@eecs.umich.edum5.ticks.setGlobalFrequency('1THz') 804444Ssaidi@eecs.umich.edu 81