tsunami-simple-timing-dual.py revision 4444
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.AddToPath('../configs/common') 32import FSConfig 33 34# -------------------- 35# Base L1 Cache 36# ==================== 37 38class L1(BaseCache): 39 latency = '1ns' 40 block_size = 64 41 mshrs = 4 42 tgts_per_mshr = 8 43 protocol = CoherenceProtocol(protocol='moesi') 44 45# ---------------------- 46# Base L2 Cache 47# ---------------------- 48 49class L2(BaseCache): 50 block_size = 64 51 latency = '10ns' 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56#cpu 57cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] 58#the system 59system = FSConfig.makeLinuxAlphaSystem('timing') 60 61system.cpu = cpus 62#create the l1/l2 bus 63system.toL2Bus = Bus() 64 65#connect up the l2 cache 66system.l2c = L2(size='4MB', assoc=8) 67system.l2c.cpu_side = system.toL2Bus.port 68system.l2c.mem_side = system.membus.port 69 70#connect up the cpu and l1s 71for c in cpus: 72 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) 74 # connect cpu level-1 caches to shared level-2 cache 75 c.connectMemPorts(system.toL2Bus) 76 c.clock = '2GHz' 77 78root = Root(system=system) 79m5.ticks.setGlobalFrequency('1THz') 80 81 82