tsunami-simple-atomic.py revision 8801:1a84c6a81299 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39    latency = '1ns'
40    block_size = 64
41    mshrs = 4
42    tgts_per_mshr = 8
43    is_top_level = True
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50    block_size = 64
51    latency = '10ns'
52    mshrs = 92
53    tgts_per_mshr = 16
54    write_buffers = 8
55
56# ---------------------
57# I/O Cache
58# ---------------------
59class IOCache(BaseCache):
60    assoc = 8
61    block_size = 64
62    latency = '50ns'
63    mshrs = 20
64    size = '1kB'
65    tgts_per_mshr = 12
66    addr_range=AddrRange(0, size='8GB')
67    forward_snoops = False
68    is_top_level = True
69
70#cpu
71cpu = AtomicSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeLinuxAlphaSystem('atomic')
74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.port
76system.iocache.mem_side = system.membus.port
77
78system.cpu = cpu
79#create the l1/l2 bus
80system.toL2Bus = Bus()
81
82#connect up the l2 cache
83system.l2c = L2(size='4MB', assoc=8)
84system.l2c.cpu_side = system.toL2Bus.port
85system.l2c.mem_side = system.membus.port
86
87#connect up the cpu and l1s
88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
89                            L1(size = '32kB', assoc = 4))
90# connect cpu level-1 caches to shared level-2 cache
91cpu.connectAllPorts(system.toL2Bus, system.membus)
92cpu.clock = '2GHz'
93
94root = Root(full_system=True, system=system)
95m5.ticks.setGlobalFrequency('1THz')
96
97