tsunami-simple-atomic.py revision 8801:1a84c6a81299
110037SARM gem5 Developers# Copyright (c) 2006-2007 The Regents of The University of Michigan
210037SARM gem5 Developers# All rights reserved.
310346Smitch.hayenga@arm.com#
410037SARM gem5 Developers# Redistribution and use in source and binary forms, with or without
510037SARM gem5 Developers# modification, are permitted provided that the following conditions are
610037SARM gem5 Developers# met: redistributions of source code must retain the above copyright
710037SARM gem5 Developers# notice, this list of conditions and the following disclaimer;
810037SARM gem5 Developers# redistributions in binary form must reproduce the above copyright
910037SARM gem5 Developers# notice, this list of conditions and the following disclaimer in the
1010037SARM gem5 Developers# documentation and/or other materials provided with the distribution;
1110037SARM gem5 Developers# neither the name of the copyright holders nor the names of its
1210037SARM gem5 Developers# contributors may be used to endorse or promote products derived from
1310037SARM gem5 Developers# this software without specific prior written permission.
1410037SARM gem5 Developers#
1510037SARM gem5 Developers# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1610037SARM gem5 Developers# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1710037SARM gem5 Developers# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1810037SARM gem5 Developers# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
1910037SARM gem5 Developers# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2010037SARM gem5 Developers# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2110037SARM gem5 Developers# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2210037SARM gem5 Developers# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2310037SARM gem5 Developers# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2410037SARM gem5 Developers# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2510037SARM gem5 Developers# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2610037SARM gem5 Developers#
2710037SARM gem5 Developers# Authors: Steve Reinhardt
2810037SARM gem5 Developers
2910037SARM gem5 Developersimport m5
3010037SARM gem5 Developersfrom m5.objects import *
3110037SARM gem5 Developersm5.util.addToPath('../configs/common')
3210037SARM gem5 Developersimport FSConfig
3310037SARM gem5 Developers
3410037SARM gem5 Developers# --------------------
3510037SARM gem5 Developers# Base L1 Cache
3610037SARM gem5 Developers# ====================
3710037SARM gem5 Developers
3810037SARM gem5 Developersclass L1(BaseCache):
3910037SARM gem5 Developers    latency = '1ns'
4010037SARM gem5 Developers    block_size = 64
4110037SARM gem5 Developers    mshrs = 4
4210037SARM gem5 Developers    tgts_per_mshr = 8
4310037SARM gem5 Developers    is_top_level = True
4410037SARM gem5 Developers
4510037SARM gem5 Developers# ----------------------
4610037SARM gem5 Developers# Base L2 Cache
4710037SARM gem5 Developers# ----------------------
4810037SARM gem5 Developers
4910037SARM gem5 Developersclass L2(BaseCache):
5010037SARM gem5 Developers    block_size = 64
5110037SARM gem5 Developers    latency = '10ns'
5210037SARM gem5 Developers    mshrs = 92
5310037SARM gem5 Developers    tgts_per_mshr = 16
5410037SARM gem5 Developers    write_buffers = 8
5510037SARM gem5 Developers
5610037SARM gem5 Developers# ---------------------
5710037SARM gem5 Developers# I/O Cache
5810037SARM gem5 Developers# ---------------------
5910037SARM gem5 Developersclass IOCache(BaseCache):
6010037SARM gem5 Developers    assoc = 8
6110037SARM gem5 Developers    block_size = 64
6210037SARM gem5 Developers    latency = '50ns'
6310037SARM gem5 Developers    mshrs = 20
6410037SARM gem5 Developers    size = '1kB'
6510037SARM gem5 Developers    tgts_per_mshr = 12
6610037SARM gem5 Developers    addr_range=AddrRange(0, size='8GB')
6710037SARM gem5 Developers    forward_snoops = False
6810037SARM gem5 Developers    is_top_level = True
6910037SARM gem5 Developers
7010037SARM gem5 Developers#cpu
7110037SARM gem5 Developerscpu = AtomicSimpleCPU(cpu_id=0)
7210037SARM gem5 Developers#the system
7310037SARM gem5 Developerssystem = FSConfig.makeLinuxAlphaSystem('atomic')
7410037SARM gem5 Developerssystem.iocache = IOCache()
7510037SARM gem5 Developerssystem.iocache.cpu_side = system.iobus.port
7610037SARM gem5 Developerssystem.iocache.mem_side = system.membus.port
7710037SARM gem5 Developers
7810037SARM gem5 Developerssystem.cpu = cpu
7910037SARM gem5 Developers#create the l1/l2 bus
8010037SARM gem5 Developerssystem.toL2Bus = Bus()
8110037SARM gem5 Developers
8210037SARM gem5 Developers#connect up the l2 cache
8310037SARM gem5 Developerssystem.l2c = L2(size='4MB', assoc=8)
8410037SARM gem5 Developerssystem.l2c.cpu_side = system.toL2Bus.port
8510037SARM gem5 Developerssystem.l2c.mem_side = system.membus.port
8610037SARM gem5 Developers
8710037SARM gem5 Developers#connect up the cpu and l1s
8810037SARM gem5 Developerscpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
8910037SARM gem5 Developers                            L1(size = '32kB', assoc = 4))
9010037SARM gem5 Developers# connect cpu level-1 caches to shared level-2 cache
9110037SARM gem5 Developerscpu.connectAllPorts(system.toL2Bus, system.membus)
9210037SARM gem5 Developerscpu.clock = '2GHz'
9310037SARM gem5 Developers
9410037SARM gem5 Developersroot = Root(full_system=True, system=system)
9510037SARM gem5 Developersm5.ticks.setGlobalFrequency('1THz')
9610037SARM gem5 Developers
9710037SARM gem5 Developers